Low-resistance super junction structure and manufacturing method thereof

Abstract

The invention discloses a low-resistance super junction structure and a manufacturing method thereof, the low-resistance super junction structure comprises a plurality of MOS cells which are connected in parallel, each MOS cell comprises a drain electrode, an upper metal source electrode, a grid electrode, a semiconductor epitaxial layer and a substrate layer, the semiconductor epitaxial layer is located on the surface of the substrate layer and is also called as a diffusion layer, and a P well layer and an N well layer are formed through ion implantation; the P-well layer comprises a lightly doped P-well layer I and a heavily doped P-well layer I, a groove is etched between adjacent MOS cells and in the middle of the heavily doped P-well layer I, an oxide layer is deposited at the bottom of the groove, a side metal source electrode is arranged on the surface of the oxide layer, and the top of the side metal source electrode is in contact with the upper metal source electrode. According to the invention, the injection depth of the heavily doped P well layer I is increased through the groove, and the source ohmic contact is buried in the epitaxial layer in the vertical direction, so that the transverse cell size occupied by the source contact is greatly reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a low-resistance super junction structure and a manufacturing method thereof. Background Art

[0002] SiC MOSFET devices have the significant advantages of high frequency and low loss, and are widely used in electric vehicles, photovoltaic inverters, charging piles and other fields. With the gradual development of SiC MOSFET devices, the voltage requirements of the devices at the application end are gradually increasing. For SiC MOSFET, higher voltage resistance means thicker epitaxial layer, and the increase of epitaxial layer means a sharp increase in the on-resistance of the device. For devices with the same on-resistance, the epitaxial thickness and device area of ​​high-voltage devices will be much higher than those of low-voltage devices. The superjunction structure solves the above problems due to its special structure.

[0003] However, the manufacture of super junction structures usually requires very deep P+ implantation to improve voltage resistance and reduce on-resistance. The implantation depth of P+ ions is limited by the implantation capacity of the implantation machine. Currently, implantation machines in the industry can usually only achieve an implantation depth of 2 to 3 μm. If you want to manufacture a heavily doped P well layer with a thickness of more than 5 μm, it is actually impossible. Even with more advanced implantation machines, silicon carbide substrates cannot withstand such a high concentration of impurity ions, resulting in material damage. Limited by process manufacturing, super junction structures are greatly limited in actual device production and cannot be widely used. Summary of the invention

[0004] The purpose of the present invention is to provide a low-resistance super junction structure and a method for manufacturing the same, which not only solves the problem in the prior art that P+ injection is limited by the injection capacity of the implanter, improves the feasibility of the process, but also further reduces the cell size, reduces the specific on-resistance, and improves the device performance and power density.

[0005] The technical solution adopted by the present invention is:

[0006] A low-resistance superjunction structure, comprising a plurality of mutually parallel MOS cells, wherein a single MOS cell comprises a drain, an upper metal source, a gate, a semiconductor epitaxial layer, and a substrate layer, wherein a dielectric layer is provided on the surface of the gate; the semiconductor epitaxial layer is located on the surface of the substrate layer, also known as a diffusion layer, and is formed with a P-well layer and an N-well layer by ion implantation; the P-well layer comprises a lightly doped P-well layer 1 and a heavily doped P-well layer 1, wherein the heavily doped P-well layer 1 extends to the bottom of the semiconductor epitaxial layer and contacts the substrate layer;

[0007] The gate is arranged inside the upper metal source and is isolated from the upper metal source by a dielectric layer;

[0008] Between adjacent MOS cells, a groove is etched in the middle of the heavily doped P-well layer 1, the bottom of the groove extends or does not extend to the substrate layer, an oxide layer is deposited at the bottom of the groove, a side metal source is provided on the surface of the oxide layer and the top of the groove, the top of the side metal source is in contact with the upper metal source; the side of the side metal source is in ohmic contact with the N-well layer, the lightly doped P-well layer 1 and the heavily doped P-well layer 1.

[0009] Further, the substrate layer is arranged on the drain surface, the heavily doped P well layer 1 and the diffusion layer are arranged on the substrate layer surface, and the heavily doped P well layer 1 is respectively arranged on both sides of a single MOS cell, the diffusion layer is located in the middle of the heavily doped P well layer 1 located on both sides of the single MOS cell, the lightly doped P well layer 1 is arranged on the surfaces of the diffusion layer and the heavily doped P well layer 1, and are respectively connected to the diffusion layer and the heavily doped P well layer 1, the N well layer is located on the surface of the lightly doped P well layer 1, and is connected to the lightly doped P well layer 1, and the gate is isolated and connected to the upper surface of the N well layer, the lightly doped P well layer 1 and the surface of the diffusion layer through a dielectric layer;

[0010] Furthermore, the N well layer includes a lightly doped N well layer 1 and a heavily doped N well layer 1, wherein the heavily doped N well layer 1 is located on the upper layer of the lightly doped N well layer 1; the lightly doped N well layer 1 is located on the surface of the lightly doped P well layer 1, the side of the side metal source is in ohmic contact with the lightly doped N well layer 1, the heavily doped N well layer 1, the lightly doped P well layer 1 and the heavily doped P well layer 1, and the gate is connected to the upper surface of the heavily doped N well layer 1, the lightly doped P well layer 1 and the surface of the diffusion layer through isolation of a dielectric layer.

[0011] Furthermore, the height of the oxide layer filled in the trench is lower than the bottom cross-sectional height of the lightly-doped P-well layer 1, so that the side metal source can contact the heavily-doped P-well layer 1.

[0012] More preferably, the groove is perpendicular to the substrate layer.

[0013] Furthermore, the gate is isolated from the upper metal source by a dielectric layer; the gate with the dielectric layer on its surface is arranged inside the upper metal source, and adjacent gates are isolated by the upper metal source to form a lateral gate-source alternating structure.

[0014] When the low-resistance super junction structure is in a blocking state, the oxide layer bears pressure together with the device. This will not cause the device's withstand voltage characteristics to decrease. During the device manufacturing process, the provision of the oxide layer can greatly reduce the requirements for ion implanters during the super junction structure manufacturing process. The present invention designs the source ohmic contact in the vertical direction within the epitaxial layer, which can greatly reduce the cell size occupied by the source contact.

[0015] The present invention also provides a method for manufacturing the low-resistance super junction structure, the method comprising the following steps:

[0016] S1. Select epitaxial wafers that meet the specifications, insert wafers, mark them, and clean them;

[0017] S2, forming a P-well layer and an N-well layer on the surface of the epitaxial layer by ion implantation;

[0018] S3. Between adjacent MOS cells, a reserved heavily doped P-well layer is etched to form a groove. The depth and width of the groove can be set according to the specific device design.

[0019] S4, performing multiple implantations at multiple angles to obtain a heavily doped P-well layer 1 that meets the specifications;

[0020] S5, depositing an oxide layer in the trench, filling the trench to a height lower than the bottom cross-sectional height of the lightly doped P-well layer 1, and then depositing metal into the trench to prepare a side metal source electrode, so that the top of the side metal source electrode fills the trench;

[0021] S6. Complete the remaining parts of the device according to the normal process.

[0022] In the step S6, the gate electrode, the dielectric layer and the upper metal source electrode are generally manufactured according to normal processes.

[0023] In the step S5, the oxide layer may be deposited using an oxide layer deposition device.

[0024] Furthermore, in step S3, by inspecting the average width of the trench in the substrate epitaxial layer, the verticality of the trench sidewalls, and the amount of cracks on the inner surface of the trench, it is determined whether the substrate epitaxial layer trench etching process is qualified, and:

[0025]

[0026] In the formula, C represents the yield rate of the trench etched on the surface of the substrate epitaxial layer, d represents the average width of the etched trench, d0 represents the target width of the etched trench, h represents the vertical coefficient of the inner wall of the etched trench, and g represents the existence rate of cracks in the inner surface of the trench;

[0027] When C≥80%, it means that the process of performing trench etching on the surface of the substrate epitaxial layer meets the requirements of good products.

[0028] Furthermore, in step S3, the verticality of the groove sidewall is determined by checking the ratio of the groove bottom cross-sectional width to the top cross-sectional width and the maximum inclination angle of the groove sidewall after heating.

[0029]

[0030] In the formula, h represents the vertical coefficient of the inner wall of the etched groove, where the larger h is, the worse the verticality of the groove is; m represents the ratio of the cross-sectional width at the bottom of the groove to the cross-sectional width at the top; u represents the maximum inclination angle of the groove side wall after heating.

[0031] The beneficial effects of the present invention are:

[0032] The present invention solves for the first time the problem of the difficulty of the super junction device manufacturing process. By increasing the groove etching, the injection port of the implanter can penetrate deep into the groove, so that when the maximum injection depth of the implanter remains unchanged, the injection depth of the heavily doped P-well layer 1 is increased through the groove, making it possible to manufacture the heavily doped P-well layer 1 with an injection depth greater than the maximum injection depth of the implanter. This greatly reduces the requirements of the super junction device for the implanter, significantly reduces the difficulty of manufacturing super junction devices, lowers the threshold for manufacturing super junction devices, and lays a solid foundation for the industrial application of super junction devices.

[0033] Furthermore, the present invention utilizes the trench to perform impurity injection and then fills the trench with oxide, which can reduce the difficulty of deep trench filling in the industrial manufacturing process without losing the withstand voltage characteristics of the device.

[0034] The present invention buries the source ohmic contact in the vertical direction of the epitaxial layer, and the adjacent N-well layer, lightly doped P-well layer 1 and heavily doped P-well layer 1 can directly contact the side metal source, so that adjacent MOS cells do not need to be isolated by the heavily doped P-well layer 1, which greatly reduces the lateral cell size occupied by the source contact. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 It is a cross-sectional schematic diagram of the super junction structure in Example 1 in which the oxide layer fills the trench.

[0036] Figure 2 Schematic diagram of the cross-section of the low-resistance super junction structure of the present invention in Example 2.

[0037] Figure 3 It is a cross-sectional comparison diagram of Example 1 and Example 2.

[0038] In the figure: 1. drain; 2. upper metal source; 3. dielectric layer; 4. gate; 5. side metal source; 6. oxide layer; 61. trench; 7. lightly doped P-well layer 1; 8. heavily doped P-well layer 1; 9. diffusion layer; 10. lightly doped N-well layer 1; 11. heavily doped N-well layer 1; 12. substrate layer. DETAILED DESCRIPTION

[0039] The technical solution of the present invention is further described below in conjunction with the accompanying drawings and embodiments, but the protection scope of the present invention is not limited thereto. It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other without conflict.

[0040] Example 1

[0041] The schematic diagram of the super junction structure with the oxide layer filling the trench is as follows Figure 1As shown, it includes several MOS cells connected in parallel, and a single MOS cell includes a drain 1, an upper metal source 2, a gate 4, a semiconductor epitaxial layer, and a substrate layer 12. The surface of the gate 4 is provided with a dielectric layer 3; the semiconductor epitaxial layer is located on the surface of the substrate layer 12, also known as the diffusion layer 9, and is formed with a P well layer and an N well layer by ion implantation; the P well layer includes a lightly doped P well layer 7 and a heavily doped P well layer 8, wherein the heavily doped P well layer 8 extends to the bottom of the diffusion layer 9 and contacts with the substrate layer 12.

[0042] The gate 4 is arranged inside the upper metal source 2 and is isolated from the upper metal source 2 by a dielectric layer 3;

[0043] The substrate layer 12 is located on the surface of the drain 1, the heavily doped P well layer 8 and the diffusion layer 9 are located on the surface of the substrate layer 12, and the heavily doped P well layer 8 is respectively arranged on both sides of a single MOS cell, the diffusion layer 9 is located in the middle of the heavily doped P well layer 8 located on both sides of the single MOS cell, the lightly doped P well layer 7 is located on the surface of the diffusion layer 9 and the heavily doped P well layer 8, and is respectively connected to the diffusion layer 9 and the heavily doped P well layer 8, the N well layer is located on the surface of the lightly doped P well layer 7, Figure 1 In the embodiment of the present invention, the N well layer includes a lightly doped N well layer 10 and a heavily doped N well layer 11, wherein the heavily doped N well layer 11 is located on the upper layer of the lightly doped N well layer 10; the lightly doped N well layer 10 is located on the surface of the lightly doped P well layer 7, and is connected to the lightly doped P well layer 7 and the heavily doped P well layer 8 respectively; the heavily doped N well layer 11 is connected to the heavily doped P well layer 8, and the gate 4 is isolated and connected to the upper surface of the heavily doped N well layer 11, the lightly doped P well layer 7 and the surface of the diffusion layer 9 through the dielectric layer 3;

[0044] The upper metal source 2 is connected to the upper surface of the heavily doped N-well layer 11 and the upper surface of the heavily doped P-well layer 8;

[0045] Between adjacent MOS cells, a groove 61 is etched in the middle of the heavily doped P-well layer 8, the bottom of the groove 61 extends to the substrate layer 12, and the top of the groove 61 contacts the upper metal source 2; an oxide layer 6 is deposited inside the groove, the oxide layer 6 fills the groove 61, and when the super junction structure is in a blocking state, the oxide layer 6 is under pressure together with the device.

[0046] Figure 1 The bottom of the groove 61 shown extends to the substrate layer 12, but the groove 61 may not extend to the substrate layer 12, because considering the implantation depth that the implanter can reach, the depth of the groove only needs to ensure that the impurities injected by the implanter can reach the bottom of the diffusion layer and the surface of the substrate layer. That is, the depth of the groove 61 can be greater than or equal to the target implantation depth minus the maximum implantation depth of the implanter.

[0047] The super junction structure is prepared by the following method:

[0048] S1. Select epitaxial wafers that meet the specifications, insert wafers, mark them, and clean them;

[0049] S2, forming a P-well layer and an N-well layer on the surface of the epitaxial layer by ion implantation;

[0050] S3. Between adjacent MOS cells, a groove is etched in the middle of the reserved heavily doped P well layer 1 to form a groove. In the diffusion layer 9, the etching depth reaches the groove 61 of the substrate layer. The groove is located between adjacent MOS cells and in the middle of the reserved heavily doped P well layer 8.

[0051] The depth and width of the trench can be set according to the specific device design.

[0052] S4, performing multiple implantations at multiple angles to obtain a heavily doped P-well layer 1 that meets the specifications;

[0053] S5, depositing an oxide layer in the trench to fill the trench, so that the oxide layer fills the trench;

[0054] S6. Complete the production of the gate, dielectric layer and upper metal source according to normal process.

[0055] This structure has further room for improvement, as shown in Example 2.

[0056] Example 2

[0057] This embodiment provides a low-resistance super junction structure, the cross-sectional structure diagram is as follows Figure 2 As shown, it includes several MOS cells connected in parallel, and a single MOS cell includes a drain 1, an upper metal source 2, a gate 4, a semiconductor epitaxial layer, and a substrate layer 12. The surface of the gate 4 is provided with a dielectric layer 3; the semiconductor epitaxial layer is located on the surface of the substrate layer 12, also known as the diffusion layer 9, and is formed with a P well layer and an N well layer by ion implantation; the P well layer includes a lightly doped P well layer 7 and a heavily doped P well layer 8, wherein the heavily doped P well layer 8 extends to the bottom of the diffusion layer 9 and contacts with the substrate layer 12.

[0058] The gate 4 is arranged inside the upper metal source 2 and is isolated from the upper metal source 2 by a dielectric layer 3;

[0059] Between adjacent MOS cells, a groove 61 is etched in the middle of the heavily doped P-well layer 8, and the bottom of the groove 61 extends or does not extend to the substrate layer 12. In this embodiment, the groove 61 does not extend to the substrate layer 12, and an oxide layer 6 is deposited at the bottom of the groove 61. A side metal source 5 is provided on the surface of the oxide layer 6 and the top of the groove 61, and the top of the side metal source 5 is in contact with the upper metal source 2; the side of the side metal source 5 is in ohmic contact with the N-well layer, the lightly doped P-well layer 7 and the heavily doped P-well layer 8.

[0060] Further, the substrate layer 12 is arranged on the surface of the drain 1, the heavily doped P well layer 8 and the diffusion layer 9 are arranged on the surface of the substrate layer 12, and the heavily doped P well layer 8 is respectively arranged on both sides of a single MOS cell, the diffusion layer 9 is located in the middle of the heavily doped P well layer 8 located on both sides of the single MOS cell, the lightly doped P well layer 7 is arranged on the surface of the diffusion layer 9 and the heavily doped P well layer 8, and is respectively connected to the diffusion layer 9 and the heavily doped P well layer 8, the N well layer is located on the surface of the lightly doped P well layer 7, Figure 2 In the embodiment of the present invention, the N well layer includes a lightly doped N well layer 10 and a heavily doped N well layer 11, wherein the heavily doped N well layer 11 is located on the upper layer of the lightly doped N well layer 10; the lightly doped N well layer 10 is located on the surface of the lightly doped P well layer 7; the side surface of the side metal source 5 is in ohmic contact with the lightly doped N well layer 10 and the heavily doped N well layer 11, the lightly doped P well layer 7 and the heavily doped P well layer 8, and the gate 4 is isolated and connected with the upper surface of the heavily doped N well layer 11, the lightly doped P well layer 7 and the surface of the diffusion layer 9 through the dielectric layer 3;

[0061] Furthermore, the height of the oxide layer 6 filled in the trench 61 is lower than the bottom cross-sectional height of the lightly-doped P-well layer 7 , so that the side metal source 5 can contact the heavily-doped P-well layer 8 .

[0062] More preferably, the groove 61 is perpendicular to the substrate layer 12 .

[0063] The gate 4 is isolated from the upper metal source 2 by a dielectric layer 3; the gate 4 with the dielectric layer 3 on the surface is arranged inside the upper metal source 2, and adjacent gates 4 are isolated by the upper metal source 2 to form a lateral gate-source alternating structure.

[0064] When the super junction structure is in a blocking state, the oxide layer bears pressure together with the device.

[0065] The low-resistance super junction structure is prepared by the following method:

[0066] S1. Select epitaxial wafers that meet the specifications, insert wafers, mark them, and clean them;

[0067] S2, forming a P-well layer and an N-well layer on the surface of the epitaxial layer by ion implantation;

[0068] S3. Between adjacent MOS cells, a reserved heavily doped P-well layer is etched to form a groove. The depth and width of the groove can be set according to the specific device design.

[0069] In step S3, the verticality of the groove sidewall is determined by checking the ratio of the groove bottom cross-sectional width to the top cross-sectional width and the maximum inclination angle of the groove sidewall after heating, and:

[0070]

[0071] In the formula, h represents the vertical coefficient of the inner wall of the etched groove, where the larger h is, the worse the verticality of the groove is; m represents the ratio of the cross-sectional width at the bottom of the groove to the cross-sectional width at the top; u represents the maximum inclination angle of the groove side wall after heating.

[0072] Among them, for the semiconductor substrate layer, the ratio of the cross-sectional width at the bottom of the trench to the cross-sectional width at the top is m=1.5, and the maximum inclination angle of the trench sidewall after heating is u=4.2 (degrees), then:

[0073]

[0074] From the above calculation, it can be known that the vertical coefficient of the inner wall of the trench etched by the semiconductor substrate layer is h=1.8.

[0075] The average width of the trench in the substrate epitaxial layer, the verticality of the trench sidewalls, and the amount of cracks on the inner surface of the trench are inspected to determine whether the substrate epitaxial layer trench etching process is qualified.

[0076]

[0077] In the formula, C represents the yield rate of the trench etched on the surface of the substrate epitaxial layer, d represents the average width of the etched trench, d0 represents the target width of the etched trench, h represents the vertical coefficient of the inner wall of the etched trench, and g represents the existence rate of cracks in the inner surface of the trench;

[0078] When C≥80%, it means that the process of performing trench etching on the surface of the substrate epitaxial layer meets the requirements of good products.

[0079] Among them, the average width of the trench etched for the substrate epitaxial layer is d=3.4 (micrometers), the target width of the etched trench is d0=2 (micrometers), and the existence rate of cracks in the inner surface of the trench is g=35% (the existence rate of cracks = the number of substrate epitaxial layers with more than 10 cracks in the trench ÷ the number of sampled substrate epitaxial layers), then:

[0080]

[0081] From the above calculations, it can be known that the process of trench etching on the surface of the substrate epitaxial layer meets the requirements of good products.

[0082] S4, perform multiple injections at multiple angles to obtain a heavily doped P-well layer that meets the specifications; multiple injections at multiple angles can be performed by rotating the wafer and tilting the wafer.

[0083] S5, depositing an oxide layer in the trench, filling the trench to a height lower than the bottom cross-sectional height of the lightly doped P-well layer 1, and then depositing metal in the trench to prepare a side metal source electrode, so that the side metal source electrode fills the trench. In this embodiment, the top of the side metal source electrode can contact the upper metal source electrode; the oxide layer can be deposited using an oxide layer deposition device.

[0084] S6. Complete the production of the gate, dielectric layer and upper metal source according to normal process.

[0085] In this embodiment, a side metal source is designed, and the source ohmic contact is designed in the vertical direction within the epitaxial layer. The adjacent N-well layer, lightly doped P-well layer 1 and heavily doped P-well layer 1 can directly contact the side metal source, so that adjacent MOS cells do not need to be isolated by the heavily doped P-well layer 1. The design structure is more compact and the cell size occupied by the source contact is greatly reduced.

[0086] The design comparison diagram of the two structures of Example 1 and Example 2 is as follows Figure 3 As shown, it can be seen that when the gate width is the same, the distance between adjacent MOS cells is significantly reduced, and the cell size is also reduced.

Claims

1. A low-resistance superjunction structure, comprising a plurality of MOS cells connected in parallel, characterized in that A single MOS cell comprises a drain, an upper metal source, a gate, a semiconductor epitaxial layer, and a substrate layer, wherein a dielectric layer is provided on the surface of the gate; the semiconductor epitaxial layer is located on the surface of the substrate layer, also known as a diffusion layer, and is formed with a P-well layer and an N-well layer by ion implantation; the P-well layer comprises a lightly doped P-well layer 1 and a heavily doped P-well layer 1, wherein the heavily doped P-well layer 1 extends to the bottom of the semiconductor epitaxial layer and contacts the substrate layer; The gate is arranged inside the upper metal source and is isolated from the upper metal source by a dielectric layer; Between adjacent MOS cells, a groove is etched in the middle of the heavily doped P-well layer 1, the bottom of the groove extends or does not extend to the substrate layer, an oxide layer is deposited at the bottom of the groove, a side metal source is provided on the surface of the oxide layer and the top of the groove, the top of the side metal source is in contact with the upper metal source; the side of the side metal source is in ohmic contact with the N-well layer, the lightly doped P-well layer 1 and the heavily doped P-well layer 1.

2. The low-resistance superjunction structure according to claim 1, characterized in that The substrate layer is arranged on the drain surface, the heavily doped P-well layer 1 and the diffusion layer are arranged on the substrate layer surface, and the heavily doped P-well layer 1 is respectively arranged on both sides of a single MOS cell, the diffusion layer is located in the middle of the heavily doped P-well layer 1 located on both sides of the single MOS cell, the lightly doped P-well layer 1 is arranged on the surfaces of the diffusion layer and the heavily doped P-well layer 1, and are respectively connected to the diffusion layer and the heavily doped P-well layer 1, the N-well layer is located on the surface of the lightly doped P-well layer 1, and is connected to the lightly doped P-well layer 1, and the gate is isolated and connected to the upper surface of the N-well layer, the lightly doped P-well layer 1 and the surface of the diffusion layer through a dielectric layer.

3. The low-resistance superjunction structure according to claim 2, characterized in that The N-well layer includes a lightly doped N-well layer 1 and a heavily doped N-well layer 1, wherein the heavily doped N-well layer 1 is located on the upper layer of the lightly doped N-well layer 1; the lightly doped N-well layer 1 is located on the surface of the lightly doped P-well layer 1, the side of the side metal source is in ohmic contact with the lightly doped N-well layer 1, the heavily doped N-well layer 1, the lightly doped P-well layer 1 and the heavily doped P-well layer 1, and the gate is connected to the upper surface of the heavily doped N-well layer 1, the lightly doped P-well layer 1 and the surface of the diffusion layer through isolation of a dielectric layer.

4. The low-resistance super junction structure according to claim 1, characterized in that The height of the oxide layer filled in the trench is lower than the bottom cross-sectional height of the lightly doped P-well layer 1, so that the side metal source is in contact with the heavily doped P-well layer 1.

5. The low-resistance super junction structure according to claim 1, characterized in that When the super junction structure is in a blocking state, the oxide layer bears pressure together with the device.

6. The low-resistance super junction structure according to claim 1, characterized in that The trench is perpendicular to the substrate layer.

7. The method for manufacturing a low-resistance super junction structure according to any one of claims 1 to 6, characterized in that The method comprises the following steps: S1. Select epitaxial wafers that meet the specifications, insert wafers, mark them, and clean them; S2, forming a P-well layer and an N-well layer on the surface of the epitaxial layer by ion implantation; S3, between adjacent MOS cells, a reserved heavily doped P-well layer is etched to form a groove; S4, performing multiple implantations at multiple angles to obtain a heavily doped P-well layer 1 that meets the specifications; S5, depositing an oxide layer in the trench, filling the trench to a height lower than the bottom cross-sectional height of the lightly doped P-well layer 1, and then depositing metal into the trench to prepare a side metal source electrode, so that the side metal source electrode fills the trench; S6. Complete the remaining parts of the device according to the normal process.

8. The method according to claim 7, characterized in that In step S3, by inspecting the average width of the trench in the substrate epitaxial layer, the verticality of the trench sidewalls, and the amount of cracks on the inner surface of the trench, it is determined whether the substrate epitaxial layer trench etching process is qualified, as follows: In the formula, C represents the yield rate of the trench etched on the surface of the substrate epitaxial layer, d represents the average width of the etched trench, d0 represents the target width of the etched trench, h represents the vertical coefficient of the inner wall of the etched trench, and g represents the existence rate of cracks in the inner surface of the trench; When C≥80%, it means that the process of performing trench etching on the surface of the substrate epitaxial layer meets the requirements of good products.

9. The method according to claim 8, characterized in that In step S3, the verticality of the groove sidewall is determined by checking the ratio of the groove bottom cross-sectional width to the top cross-sectional width and the maximum inclination angle of the groove sidewall after heating. In the formula, h represents the vertical coefficient of the inner wall of the etched groove, where the larger h is, the worse the verticality of the groove is; m represents the ratio of the cross-sectional width at the bottom of the groove to the cross-sectional width at the top; u represents the maximum inclination angle of the groove side wall after heating.

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