A light-load current detection circuit

Abstract

The present invention provides a light-load current detection circuit, which is used to obtain the output current of a DC-DC conversion circuit. The output current is the average value of the inductor current, and it includes a first counter, a second counter, and an output current determination module. The first counter is set to count the upper transistor turn-off trigger signal. The second counter is set to count the number of periods of a periodic signal, and the period of the periodic signal is proportional to the sum of the upper transistor conduction time and the lower transistor conduction time. The output current determination module determines the output current according to the count value of the first counter and the count value of the second counter. In the light-load current detection circuit of the present invention, the first counter is set to count the upper transistor turn-off trigger signal, and the second counter is set to count the number of periods of the periodic signal. Therefore, the obtained ratio can be used to obtain the output current.

Description

Technical Field

[0001] The present invention relates to the field of voltage conversion circuits, and particularly to a light-load current detection circuit. Background Art

[0002] A step-down DC-DC converter (i.e., a buck conversion circuit) will enter the discontinuous conduction mode (DCM mode) of the switching current in the light-load mode, which is beneficial to reducing the switching loss and improving the working efficiency. The switch will work for a period of time and then stop for a period of time until the upper transistor needs to be turned on again next time to charge the inductor. In this working state, the working cycle of the buck conversion circuit is very long, and it is difficult to sample the magnitude of the output current. The traditional current sampling method is to sample and average the output current. In this way, the sampled voltage is very low, and the requirement for the circuit accuracy is very high; the non-sampling time is very long, and a large sampling capacitor is required, which is not conducive to circuit design. Summary of the Invention

[0003] The purpose of the present invention is to provide a light-load current detection circuit to obtain the output current of the DC-DC conversion circuit when the DC-DC converter works in the DCM mode.

[0004] To achieve the above purpose, the present invention provides a light-load current detection circuit, which is used to obtain the output current of the DC-DC conversion circuit. The output current is the average value of the inductor current. The circuit includes a first counter, a second counter, and an output current determination module; the first counter is set to count the turn-off trigger signal of the upper transistor; the second counter is set to count the number of cycles of a periodic signal, and the period of the periodic signal is proportional to the sum of the conduction time of the upper transistor and the conduction time of the lower transistor; the output current determination module determines the output current according to the count value of the first counter and the count value of the second counter.

[0005] The second counter is connected to the output end of a periodic signal generation device, and the periodic signal generation device is set to generate a periodic signal with a period equal to the sum of the conduction time of the upper transistor and the conduction time of the lower transistor.

[0006] The periodic signal generation device includes a first capacitor and a second capacitor. The low-voltage sides of the first capacitor and the second capacitor are both grounded. The high-voltage sides of the first capacitor and the second capacitor are respectively connected to a first charging current and a second charging current and are respectively connected to two input ends of a first voltage comparator. The output end of the first voltage comparator is the output end of the periodic signal generation device; the first charging current charges the first capacitor only when the upper transistor or the lower transistor is conducting; the high-voltage side of the second capacitor is connected to a second voltage zero-clearing switch transistor, and the gate of the second voltage zero-clearing switch transistor is connected to the output end of the first voltage comparator to clear the second capacitor through the second voltage zero-clearing switch transistor when the periodic signal output by the periodic signal generation device becomes high.

[0007] The first capacitor is also connected to a first voltage clearing switch transistor, and the gate of the first voltage clearing switch transistor is connected to the upper transistor conduction start signal output by the driving circuit, so that each time the upper transistor starts to conduct or after a fixed time, when the upper transistor starts to conduct again, the first voltage clearing switch transistor clears the voltage of the first capacitor.

[0008] The output current determination module includes a division register and a current value calculation module. The division register is set to continuously calculate and update the ratio n / m of the count value of the first counter to the count value of the second counter and store it in the DCM mode; and the current value calculation module is set to continuously calculate the output current according to the ratio n / m in the DCM mode.

[0009] The first charging current is equal to the second charging current, and the period of the periodic signal is equal to the sum of the upper transistor conduction time and the lower transistor conduction time.

[0010] For the buck conversion circuit, the output current calculated by the current value calculation module is:

[0011] ,

[0012] For the boost conversion circuit, the output current calculated by the current value calculation module is:

[0013] ,

[0014] where, is the internal reference current, n is the count value of the first counter, and m is the count value of the second counter.

[0015] The DC-DC conversion circuit includes an error amplifier, a driving circuit, a pair of parallel switch transistors and a filtering circuit connected in sequence, and an inductor current comparator and a zero-crossing detection module connected to the driving circuit.

[0016] The positive input terminal and the negative input terminal of the error amplifier are respectively connected to the feedback voltage and the reference voltage, and the output terminal of the error amplifier is connected to the input terminal of the driving circuit; when the feedback voltage is lower than or equal to the reference voltage, the error amplifier outputs an upper transistor start trigger signal to the driving circuit, so that the upper transistor is turned on;

[0017] The inductor current comparator is used to compare the inductor detection current and the internal reference current. When the inductor detection current is greater than or equal to the internal reference current, the inductor current comparator outputs an upper transistor turn-off trigger signal to the driving circuit, and the driving circuit outputs a signal to turn off the upper transistor and turn on the lower transistor;

[0018] When the zero-crossing detection module detects that the inductor current is 0, the zero-crossing detection module outputs a trigger signal for turning off the lower transistor, and the drive circuit outputs a signal for turning off the lower transistor.

[0019] The parallel-connected switching transistors include an upper transistor and a lower transistor. The two output terminals of the drive circuit are respectively connected to the gates of the upper transistor and the lower transistor, and the drains of the upper transistor and the lower transistor are connected. The source of the lower transistor is grounded;

[0020] The filter circuit includes an inductor with one end connected to the drains of the upper transistor and the lower transistor and a grounded capacitor connected to the other end of the inductor. The connection point of the inductor and the grounded capacitor is used as the voltage output terminal, and the source of the upper transistor is used as the voltage input terminal; or, the filter circuit includes an inductor with one end connected to the drains of the upper transistor and the lower transistor and a grounded capacitor connected to the source of the upper transistor. The source of the upper transistor is used as the voltage output terminal, and the other end of the inductor is used as the voltage input terminal.

[0021] The first counter of the light-load current detection circuit of the present invention is set to count the trigger signal for turning off the upper transistor, and the second counter is set to count the number of cycles of the periodic signal. Therefore, the obtained ratio can be used to obtain the output current. Description of the Drawings

[0022] Figure 1 FIG. is a circuit block diagram of a light-load current detection circuit according to an embodiment of the present invention, which shows an application scenario of the light-load current detection circuit of the present invention.

[0023] Figure 2 FIG. is an output current waveform diagram of a buck conversion circuit using the light-load current detection circuit of the present invention operating in the DCM mode.

[0024] Figure 3 FIG. is another application scenario diagram of the light-load current detection circuit of the present invention. Detailed Embodiments

[0025] As Figure 1 FIG. shows a circuit block diagram of a light-load current detection circuit according to an embodiment of the present invention, which is used to obtain the output current iout of a DC-DC conversion circuit. Among them, the output current iout is the average value of the inductor current isw, and the output current iout can be used for other functional modules of the circuit. Among them, a light-load current detection circuit of the present invention is applicable to a DC-DC conversion circuit, and is particularly applicable to all DC-DC conversion circuits that can operate in the discontinuous switching current mode (DCM mode), including buck conversion circuits and boost conversion circuits.

[0026] The control principle of the light-load current detection circuit of the present invention is:

[0027] AsFigure 1 As shown, the existing DC-DC conversion circuit includes an error amplifier 100, a drive circuit 200, a pair of parallel switch tubes 300, and a filter circuit 400 connected in sequence.

[0028] The positive input terminal and the negative input terminal of the error amplifier 100 are respectively connected to the feedback voltage Vfb and the reference voltage Vref, and the output terminal of the error amplifier 100 is connected to the input terminal of the drive circuit 200. The feedback voltage Vfb is a feedback signal of the output voltage Vout, usually obtained by resistor voltage division, and Vref is an internal or external reference signal. The error amplifier 100 is set to compare the feedback voltage Vfb and the reference voltage Vref. When the feedback voltage Vfb is lower than or equal to the reference voltage Vref, the error amplifier outputs an upper transistor start trigger signal hs_on to the drive circuit 200 to turn on the upper transistor.

[0029] In addition, the DC-DC conversion circuit further includes an inductor current comparator 600 connected to the drive circuit 200, which is used to compare the inductor detection current isense and the internal reference current ipeak. When the inductor detection current isense reaches the internal reference current ipeak, the inductor current comparator outputs an upper transistor turn-off trigger signal hs_off to the drive circuit 200 to turn off the upper transistor and turn on the lower transistor. The inductor detection current isense is obtained by sampling the inductor current isw by an output current sampling module, usually isense = 1 / N × isw, where N is the sampling ratio. There are many classic forms of the output current sampling module, which will not be elaborated here. The magnitude of the internal reference current ipeak is adjustable.

[0030] In this embodiment, the inductor current comparator 600 is implemented by a current mirror formed by a pair of common-gate NMOS switch tubes. The two NMOS switch tubes are respectively connected to the inductor detection current isense and the internal reference current ipeak, and the gate of the NMOS switch tube connected to the internal reference current ipeak is connected to an inverter, and the output terminal of the inverter is the output signal of the inductor current comparator 600. Thus, when the inductor detection current isense is less than the internal reference current ipeak, the output level of the inductor current comparator 600 is low, that is, no upper transistor turn-off trigger signal hs_off is generated. When the inductor detection current isense is greater than or equal to the internal reference current ipeak, the output level of the inductor current comparator 600 is high, that is, the inductor current comparator 600 outputs an upper transistor turn-off trigger signal hs_off. In other embodiments, the inductor current comparator 600 can be implemented in other ways.

[0031] The DC-DC conversion circuit further includes a zero-crossing detection module 500 connected to the driving circuit 200. When the zero-crossing detection module 500 detects that the inductor current is 0, the zero-crossing detection module 500 outputs a lower transistor turn-off trigger signal ls_off, so that the lower transistor conduction signal gls output by the driving circuit 200 switches to a low level, that is, the driving circuit 200 outputs a signal to turn off the lower transistor.

[0032] The parallel switch transistors 300 include an upper transistor and a lower transistor. Two output terminals of the driving circuit 200 are respectively connected to the gates of the upper transistor and the lower transistor, and the drains of the upper transistor and the lower transistor are connected, and the source of the lower transistor is grounded.

[0033] In one embodiment, since the DC-DC conversion circuit is a buck-type conversion circuit, therefore, the filtering circuit 400 includes an inductor with one end connected to the drains of the upper transistor and the lower transistor and a grounding capacitor connected to the other end of the inductor, and the connection point of the inductor and the grounding capacitor is used as the voltage output terminal, and the source of the upper transistor is used as the voltage input terminal.

[0034] Thus, as Figure 1 and Figure 2 shown, when the feedback voltage Vfb is lower than the reference voltage Vref, the error amplifier 100 outputs an upper transistor start trigger signal hs_on to the driving circuit 200, so that the upper transistor conduction signal ghs output by the driving circuit 200 switches to a high level, that is, the driving circuit 200 outputs a signal to turn on the upper transistor, and the inductor current isw starts to increase from 0.

[0035] When the inductor detection current isense corresponding to the inductor current isw reaches the internal reference current ipeak (a set value, adjustable), the inductor current comparator outputs an upper transistor turn-off trigger signal hs_off to the driving circuit 200, so that the upper transistor conduction signal ghs output by the driving circuit 200 switches to a low level, and at the same time the lower transistor conduction signal gls switches to a high level, that is, the driving circuit 200 outputs a signal to turn off the upper transistor and turn on the lower transistor. The upper transistor conduction time is ton.

[0036] After the lower transistor is turned on, the inductor current starts to decrease from the internal reference current ipeak. When the zero-crossing detection module 500 detects that the inductor current is 0, the zero-crossing detection module 500 outputs a lower transistor turn-off trigger signal ls_off, so that the lower transistor conduction signal gls output by the driving circuit 200 switches to a low level, that is, the driving circuit 200 outputs a signal to turn off the lower transistor. The lower transistor conduction time is toff. Thus, a triangular output waveform is formed.

[0037] It should be noted that, in this embodiment, as Figure 2As shown, the waveforms of the high-side switch conduction signal ghs and the low-side switch conduction signal gls output by the drive circuit 200 are merely illustrative for the case where the corresponding switching transistors are turned on when the signal is at a high level and turned off when the signal is at a low level. In other embodiments, the high-side switch conduction signal ghs and the low-side switch conduction signal gls do not necessarily turn on the corresponding switching transistors when at a high level, and thus the corresponding waveforms will also change, as long as the on and off times of the switching transistors remain unchanged.

[0038] Subsequently, when the voltage at the vfb terminal of the error amplifier is lower than the vref voltage, the high-side switch conducts again. It can be seen that the waveform of the inductor current is discontinuous and has no pattern, and in this case, current sampling becomes very difficult.

[0039] Please refer again to Figure 1 , based on the control principle of the present invention, the implemented light-load current detection circuit includes a first counter 10, a second counter 20, and an output current determination module.

[0040] Among them, the first counter 10 is set to count the high-side switch turn-off trigger signal hs_off. Thus, the first counter 10 accumulates the number of times the high-side switch is turned off and the low-side switch is turned on during the time of the discontinuous switching current mode (such as within the mT time), and each time it encounters such a situation, the count value of the first counter 10 increases by 1. Among them, the count value of the first counter 10 is n.

[0041] The second counter 20 is set to count the number of cycles of a periodic signal, and the period of the periodic signal is equal to the sum of the high-side switch conduction time ton and the low-side switch conduction time toff. Among them, the count value of the second counter 20 is m.

[0042] The second counter 20 is connected to the output terminal of a periodic signal generating device 50, and the periodic signal generating device 50 is set to generate a periodic signal with a period equal to the sum of the high-side switch conduction time ton and the low-side switch conduction time toff. In this embodiment, the periodic signal generating device 50 includes a first capacitor c1 and a second capacitor c2. The low-voltage sides of the first capacitor c1 and the second capacitor c2 are both grounded. The high-voltage sides of the first capacitor c1 and the second capacitor c2 are respectively connected to a first charging current i1 and a second charging current i2 and are respectively connected to the two input terminals (i.e., the negative input terminal and the positive input terminal) of a first voltage comparator cp1. The output terminal of the first voltage comparator cp1 is the output terminal of the periodic signal generating device 50.

[0043] The first charging current i1 is connected to a first driving switch K1, and the first driving switch K1 is closed only when the upper transistor is conducting or the lower transistor is conducting. Therefore, the first charging current i1 charges the first capacitor c1 only when the upper transistor is conducting or the lower transistor is conducting, and the total charging duration is equal to the sum of the conduction time ton of the upper transistor and the conduction time toff of the lower transistor (i.e., equal to ton + toff). Therefore, at the end of the charging for the duration of ton + toff, the following is satisfied:

[0044] i1(ton + toff) = c1 × Vc1,

[0045] where i1 is the first charging current, ton is the conduction time of the upper transistor, toff is the conduction time of the lower transistor, c1 is the first capacitor, and Vc1 is the voltage of the first capacitor.

[0046] Then Vc1 = i1(ton + toff) / c1.

[0047] Since there is no discharge path, the voltage on the first capacitor c1 will always maintain the first capacitor voltage Vc1.

[0048] In some embodiments, the first capacitor c1 is also connected to a first voltage clearing switch transistor, and the gate of the first voltage clearing switch transistor is connected to the upper transistor conduction start signal output by the driving circuit 200, so that each time the upper transistor starts to conduct or after a fixed time the upper transistor starts to conduct again, the first voltage clearing switch transistor quickly clears the first capacitor voltage Vc1 (i.e., the second charging current charging ends). The duration of the upper transistor conduction start signal is very short, generally on the order of a few ns. In other embodiments, the shorter the duration, the better. Therefore, after the first capacitor voltage Vc1 is quickly cleared, the first capacitor c1 immediately starts to charge through the first charging current i1. In some other embodiments, if there is no leakage in the entire circuit (ideally), the first voltage clearing switch transistor can also be omitted, so as not to clear the first capacitor voltage Vc1 and always maintain the first capacitor voltage Vc1.

[0049] The high-voltage side of the second capacitor c2 is connected to a second voltage clearing switch transistor, and the gate of the second voltage clearing switch transistor is connected to the output end of the first voltage comparator cp1, so as to clear the second capacitor c2 through the second voltage clearing switch transistor when the periodic signal output by the periodic signal generating device 50 becomes high, so that the periodic signal changes back to low level and starts the timing of the next cycle. Thus, the period T of the periodic signal is the charging duration of the second capacitor c2. In this embodiment, the second voltage clearing switch transistor is an NMOS transistor. In other embodiments, the second voltage clearing switch transistor can be a PMOS transistor, as long as it satisfies that when the periodic signal output by the periodic signal generating device 50 becomes high, the second capacitor c2 is cleared through the second voltage clearing switch transistor.

[0050] The first voltage comparator CP1 is set to make the periodic signal become high when the second capacitor voltage Vc2 is greater than or equal to the first capacitor voltage Vc1. At this time, the second capacitor C2 is discharged and cleared through the second voltage clearing switch transistor.

[0051] The second capacitor voltage Vc2 satisfies the formula: i2 × t = C2 × Vc2,

[0052] where, i2 is the second charging current, C2 is the resistance value of the second capacitor, t is the charging duration, and Vc2 is the second capacitor voltage.

[0053] Since whenever Vc2 = Vc1, that is, whenever the charging duration t reaches the total single - charge duration of the second capacitor C2, at this time the first voltage comparator CP1 will output a high level, and then the second capacitor voltage Vc2 starts to charge again (that is, the charging duration t returns to 0). Therefore, the high levels output by the first voltage comparator CP1 every time the charging duration t reaches the total charging duration of the second capacitor C2 form a periodic signal pulse, and the period T of the periodic signal pulse is the total single - charge duration of the second capacitor C2.

[0054] In this embodiment, the first charging current i1 is equal to the second charging current i2. After calculation, the period T of the periodic signal = ton + toff. Thus, the second counter 20 can count the number of periods of the periodic signal, and the period of the periodic signal is equal to the sum of the on - time ton of the upper transistor and the off - time toff of the lower transistor.

[0055] In other embodiments, the values of the first charging current i1 and the second charging current i2 are different, and the period of the periodic signal is proportional to the sum of the on - time of the upper transistor and the off - time of the lower transistor.

[0056] In some embodiments, the second charging current i2 is connected to a second drive switch K2. In DCM, the output stage sometimes works and sometimes does not work. The second drive switch K2 is set to remain closed when both the upper and lower transistors are off, so that the result of the second counter can be obtained. When one of the upper and lower transistors conducts (i.e., ton or toff), the second drive switch K2 is turned off, causing the second counter to pause working.

[0057] Since in DCM mode, the output current all satisfy the following formula:

[0058] ,

[0059] Therefore, the output current is:

[0060] ,

[0061] wherein, is the internal reference current, n is the count value of the first counter, and m is the count value of the second counter.

[0062] The output current determination module is configured to determine the output current according to the count value n of the first counter 10 and the count value m of the second counter 20 . In this embodiment, the output current determination module includes a division register 30 and a current value calculation module 40.

[0063] wherein, the division register 30 is set to continuously calculate and update the ratio n / m of the count value of the first counter 10 to the count value of the second counter 20 and store it in the DCM mode, and the current value calculation module 40 is set to continuously calculate the output current according to the ratio n / m in the DCM mode.

[0064] wherein, the division register 30 uses 12-bit data. The current value calculation module 40 can be a digital circuit. Due to the above formula, therefore, the output current calculated by the current value calculation module 40 is:

[0065] ,

[0066] wherein, is the internal reference current, n is the count value of the first counter, and m is the count value of the second counter.

[0067] In this embodiment, in the DCM mode, the count values of the first counter ct1 and the second counter ct2 continuously increase (without being cleared), and the ratio n / m calculated by the division register 30 is continuously updated. This is because for a load of a fixed size, the output current is a fixed value. Therefore, the ratio n / m obtained from the starting formula will be unstable, but as the counting duration becomes longer, the ratio n / m will become stable. The circuit is always in dynamic adjustment, so the ratio n / m will be calculated continuously.

[0068] Considering that the buck DC-DC converter does not need to calculate the output current when exiting the DCM mode, therefore, in this embodiment, the first counter ct1 and the second counter ct2 are set to end their operations and be cleared when exiting the DCM mode, and the output current determination module ends its operation.

[0069] It can be combined with a digital circuit, so that the value of the output current can be obtained conveniently.

[0070] In another embodiment, as Figure 3As shown, since the DC-DC conversion circuit is a boost-type conversion circuit (i.e., a boost circuit), the filtering circuit 400 includes an inductor connected at one end to the drains of the upper transistor and the lower transistor, and a grounding capacitor connected to the source of the upper transistor. The source of the upper transistor serves as the voltage output terminal, and the other end of the inductor serves as the voltage input terminal.

[0071] For Figure 3 the DC-DC conversion circuit shown, the implemented light-load current detection circuit also includes a first counter, a second counter, and an output current determination module connected to the output terminals of both the first counter and the second counter.

[0072] The first counter is set to count the number of times the upper transistor is turned off and the lower transistor is turned on. The second counter is set to count the number of cycles of a periodic signal, where the period of the periodic signal is equal to the sum of the on-time ton of the upper transistor and the on-time toff of the lower transistor, and the counted value of the second counter is m. The output current determination module is used to determine the output current based on the counted value n of the first counter and the counted value m of the second counter. .

[0073] Among them, the specific structures of the first counter and the second counter can be the same as those of the first counter 10 and the second counter 20 in the embodiment described above and as Figure 1 shown.

[0074] For a boost circuit, the output current satisfies the following formula:

[0075] ,

[0076] Therefore, the output current is:

[0077] ,

[0078] Among them, is the internal reference current, n is the counted value of the first counter, and m is the counted value of the second counter.

[0079] Therefore, in this embodiment, the output current determination module includes a division register and a current value calculation module. The division register 30 is set to continuously calculate and update the ratio n / m of the counted value of the first counter 10 to the counted value of the second counter 20 and store it in the DCM mode; and the current value calculation module 40 is set to continuously calculate the output current based on the ratio n / m in the DCM mode. Among them, the output current has the following calculation formula: .

[0080] The above are only the preferred embodiments of the present invention and are not intended to limit the scope of the present invention. Various changes can be made to the above embodiments of the present invention. All simple, equivalent changes and modifications made in accordance with the claims and the content of the specification of the present invention application fall within the scope of protection of the claims of the present invention patent. Those not described in detail in the present invention are all conventional technical contents.

Claims

1. A light-load current detection circuit, which is used to obtain the output current of a DC-DC conversion circuit, wherein the DC-DC conversion circuit comprises an error amplifier, a drive circuit, a pair of parallel switch tubes and a filter circuit connected in sequence, and an inductor current comparator and a zero-crossing detection module connected to the drive circuit; The parallel switch tubes include an upper tube and a lower tube, the two output ends of the driving circuit are respectively connected to the gates of the upper tube and the lower tube, the drains of the upper tube and the lower tube are connected, and the source of the lower tube is grounded; The filter circuit includes an inductor connected to the drains of the upper tube and the lower tube at one end and a grounded capacitor connected to the other end of the inductor, and the connection point of the inductor and the grounded capacitor serves as a voltage output terminal, and the source of the upper tube serves as a voltage input terminal; or, the filter circuit includes an inductor connected to the drains of the upper tube and the lower tube at one end and a grounded capacitor connected to the source of the upper tube, and the source of the upper tube serves as a voltage output terminal, and the other end of the inductor serves as a voltage input terminal; The output current is the average value of the inductor current, characterized by: It includes a first counter, a second counter and an output current determination module; the first counter is configured to count the upper tube shutdown trigger signal; the second counter is configured to count the number of cycles of the periodic signal, and the cycle of the periodic signal is proportional to the sum of the upper tube conduction time and the lower tube conduction time; the output current determination module determines the output current according to the count value of the first counter and the count value of the second counter; The output current determination module includes a division register and a current value calculation module. The division register is configured to continuously calculate and update the ratio n / m of the count value of the first counter to the count value of the second counter in the DCM mode and store it; and the current value calculation module is configured to continuously calculate the output current according to the ratio n / m in the DCM mode.

2. The light load current detection circuit according to claim 1, characterized in that: The second counter is connected to an output end of a periodic signal generating device, and the periodic signal generating device is configured to generate a periodic signal having a period equal to the sum of an upper tube conduction time and a lower tube conduction time.

3. The light load current detection circuit according to claim 2, characterized in that: The periodic signal generating device comprises a first capacitor and a second capacitor, the low voltage sides of the first capacitor and the second capacitor are both grounded, the high voltage sides of the first capacitor and the second capacitor are respectively connected to a first charging current and a second charging current and are respectively connected to two input ends of a first voltage comparator, and the output end of the first voltage comparator is the output end of the periodic signal generating device; The first charging current charges the first capacitor only when the upper tube is turned on or the lower tube is turned on; The high voltage side of the second capacitor is connected to a second voltage clearing switch tube, and the gate of the second voltage clearing switch tube is connected to the output end of the first voltage comparator, so that when the periodic signal output by the periodic signal generating device becomes a high level, the second capacitor is cleared through the second voltage clearing switch tube.

4. The light load current detection circuit according to claim 3, characterized in that: The first capacitor is also connected to a first voltage clearing switch tube. The DC-DC conversion circuit includes a driving circuit. The gate of the first voltage clearing switch tube is connected to the upper tube conduction start signal output by the driving circuit, so that each time the upper tube starts to turn on or when the upper tube starts to turn on again after a fixed time, the first voltage clearing switch tube clears the voltage of the first capacitor.

5. The light load current detection circuit according to claim 3, characterized in that: The first charging current is equal to the second charging current, and the period of the periodic signal is equal to the sum of the upper tube conduction time and the lower tube conduction time.

6. The light load current detection circuit according to claim 1, characterized in that: For the step-down converter circuit, the output current calculated by the current value calculation module for: ， For the boost converter circuit, the output current calculated by the current value calculation module for: ， in, is the internal reference current, n is the count value of the first counter, and m is the count value of the second counter.

7. The light load current detection circuit according to claim 1, characterized in that: The positive input terminal and the negative input terminal of the error amplifier are connected to the feedback voltage and the reference voltage respectively, and the output terminal of the error amplifier is connected to the input terminal of the driving circuit; when the feedback voltage is lower than or equal to the reference voltage, the error amplifier outputs an upper tube start trigger signal to the driving circuit, so that the upper tube is turned on; The inductor current comparator is used to compare the inductor detection current with the internal reference current. When the inductor detection current is greater than or equal to the internal reference current, the inductor current comparator outputs an upper tube shutdown trigger signal to the drive circuit, and the drive circuit outputs a signal to shut down the upper tube and turn on the lower tube; When the zero-crossing detection module detects that the inductor current is 0, the zero-crossing detection module outputs a lower tube shutdown trigger signal, and the drive circuit outputs a signal to shut down the lower tube.

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