Channel degradation monitoring circuit, chip degradation monitoring circuit and chip

Abstract

The present invention relates to the field of integrated circuits and chip technologies, and provides a channel degradation monitoring circuit, a chip degradation monitoring circuit, and a chip. The channel degradation monitoring circuit includes a degraded inverter, and the degraded inverter includes a first high-voltage transistor, a first resistor, a second resistor, and a third resistor. The gate of the first high-voltage transistor is connected to the input end of the degraded inverter through the first resistor and grounded through the second resistor. The drain of the first high-voltage transistor is connected to the power supply terminal of the chip through the third resistor, and the node between the drain of the first high-voltage transistor and the third resistor serves as the output end of the degraded inverter. The present invention respectively designs corresponding monitoring circuits for the channel degradation, gate oxide degradation, and substrate degradation of high-voltage devices and integrates them, which can support the degradation monitoring and early warning of high-voltage devices and circuits, and can be embedded into the power supply and isolation driver chips, overcoming the defect that the existing monitoring circuits are only applicable to monitoring low-voltage SOC chips and cannot monitor high-voltage circuits and chips.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits and chip technologies, and particularly to a channel degradation monitoring circuit, a chip degradation monitoring circuit, and a chip. Background Art

[0002] Industrial chips applied in fields such as power, rail transit, and automobiles are usually mounted outdoors with the terminal, and are very susceptible to strong transient electromagnetic interference generated by the operation of surrounding power devices such as IGBTs, and are also affected by environmental factors such as high temperature and high humidity. Industrial chips need to operate stably for 7×24 hours in environments such as high / low temperature, high humidity, and strong electromagnetic fields, and have a service life of more than 15 years, which poses a huge challenge to the reliability of chip pins that are vulnerable to environmental interference.

[0003] With the rapid development of ultra-large-scale integrated circuit manufacturing technology towards deep sub-micron, while the channel length, junction depth, gate oxide thickness, etc. of the device are scaled down proportionally and the substrate concentration increases, the power supply voltage does not scale down proportionally, resulting in a significant increase in the lateral and longitudinal electric fields in the channel region. Hot carriers obtain sufficient energy under high electric fields and cross the interface potential barrier (3.2 eV for electron injection and 4.5 eV for hole injection) and are injected into the oxide layer, generating oxide layer trap charges or interface trap charges, causing the oxide layer charge to increase or fluctuate unstably. When the energy of hot electrons is higher than the Si-SiO2 interface potential barrier, it may cross the interface potential barrier and be injected into the gate oxide layer. Part of the carriers finally reach the gate electrode and form part of the gate current. During the process of hot carriers reaching the gate electrode through the gate oxide layer, the hot carriers will use their energy to break the bonds such as Si-H and Si-OH bonds at the interface, generating acceptor-type interface states at the Si-SiO2 interface, or being captured by traps in the gate oxide layer to form trap charges. These generated interface states and trap charges will cause local electric field changes in the device, resulting in the degradation of device characteristics, causing the circuit performance to gradually degrade over time, and ultimately leading to the functional failure of the device and the circuit where it is located. The degradation of the device includes channel degradation, gate oxide degradation, and substrate degradation.

[0004] Power supply chips and isolation driver chips usually use high-voltage MOS devices to support power supplies of 12V (typically 40V commonly used) and above. Traditional degradation monitoring circuits only support low-voltage devices of 5V, and are only for SOC chips, and cannot support the monitoring of devices and circuit systems with voltages above 12V, and are not applicable to power supply chips and isolation driver chips containing chips. Summary of the Invention

[0005] In order to solve the above technical defects, the present invention provides a channel degradation monitoring circuit and a chip degradation monitoring circuit.

[0006] The channel degradation monitoring circuit provided by the embodiment of the present invention includes: a degradation ring oscillator;

[0007] The degenerated ring oscillator includes an odd number of degenerated inverters connected in series;

[0008] The degenerated inverter includes: a first high-voltage transistor, a first resistor, a second resistor, and a third resistor. The gate of the first high-voltage transistor is connected to the input terminal of the degenerated inverter through the first resistor and grounded through the second resistor. The source of the first high-voltage transistor is grounded, and the drain of the first high-voltage transistor is connected to the power supply terminal of the chip through the third resistor. The node between the drain of the first high-voltage transistor and the third resistor serves as the output terminal of the degenerated inverter;

[0009] The channel degradation monitoring circuit monitors the channel degradation of the first high-voltage transistor of the degenerated inverter by detecting the frequency attenuation amount of the degenerated ring oscillator over time.

[0010] In an embodiment of the present invention, the channel degradation monitoring circuit further includes: a non-degenerated ring oscillator;

[0011] The non-degenerated ring oscillator includes an odd number of non-degenerated inverters connected in series;

[0012] The non-degenerated inverter includes: a second high-voltage transistor, a third high-voltage transistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, and an eighth resistor;

[0013] The gate of the second high-voltage transistor is connected to the input terminal of the non-degenerated inverter through the eighth resistor and grounded through the fourth resistor. The source of the second high-voltage transistor is grounded, and the drain of the second high-voltage transistor is connected to the source of the third high-voltage transistor;

[0014] The gate of the third high-voltage transistor is connected to the power supply terminal of the chip through the fifth resistor and grounded through the sixth resistor. The drain of the third high-voltage transistor is connected to the power supply terminal of the chip through the seventh resistor. The node between the drain of the third high-voltage transistor and the seventh resistor serves as the output terminal of the non-degenerated inverter.

[0015] In an embodiment of the present invention, the first high-voltage transistor, the second high-voltage transistor, and the third high-voltage transistor are one of LDMOS, VDMOS, and BJT, and the source-drain voltage of the first high-voltage transistor, the second high-voltage transistor, and the third high-voltage transistor is 12V to 750V.

[0016] In an embodiment of the present invention, the channel degradation monitoring circuit further includes: a non-degenerated level conversion circuit, a degenerated level conversion circuit, and a frequency attenuation detection circuit;

[0017] The non-degenerated ring oscillator is connected to the frequency attenuation detection circuit through the non-degenerated level conversion circuit, and the degenerated ring oscillator is connected to the frequency attenuation detection circuit through the degenerated level conversion circuit;

[0018] The non-degenerate level conversion circuit is used to convert the high-voltage oscillation signal output by the non-degenerate ring oscillator into a low-voltage oscillation signal;

[0019] The degenerate level conversion circuit is used to convert the high-voltage oscillation signal output by the degenerate ring oscillator into a low-voltage oscillation signal;

[0020] The frequency decay detection circuit is used to detect the frequency decay amount of the degenerate ring oscillator over time, and count the number of cycles of the non-degenerate ring oscillator in the period corresponding to the degenerated ring oscillator, so as to realize the monitoring and early warning of the channel degradation of the first high-voltage transistor of the degenerate inverter.

[0021] In the embodiment of the present invention, the degenerate level conversion circuit includes: a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor and a seventh MOS transistor;

[0022] The gate of the fourth MOS transistor is connected to the gate of the fifth MOS transistor and connected to the output end of the degenerate ring oscillator, and the drain of the fourth MOS transistor is connected to the drain of the fifth MOS transistor;

[0023] The gate of the sixth MOS transistor is connected to the gate of the seventh MOS transistor, and connected to the common end where the drain of the fourth MOS transistor is connected to the drain of the fifth MOS transistor. The common end where the drain of the sixth MOS transistor is connected to the drain of the seventh MOS transistor is used as the output end of the degenerate level conversion circuit;

[0024] The source of the fourth MOS transistor and the source of the sixth MOS transistor are connected to the low-voltage power supply, and the source of the fifth MOS transistor and the source of the seventh MOS transistor are grounded.

[0025] In the embodiment of the present invention, the non-degenerate level conversion circuit includes: an eighth MOS transistor, a ninth MOS transistor, a tenth MOS transistor, an eleventh MOS transistor, a twelfth MOS transistor and a thirteenth MOS transistor;

[0026] The common terminal where the gate of the eighth MOS transistor is connected to the gates of the ninth MOS transistor and the tenth MOS transistor is connected to the output end of the non-degenerate ring oscillator. The source of the eighth MOS transistor is connected to the low-voltage power supply. The drain of the eighth MOS transistor is connected to the drain of the ninth MOS transistor, and the source of the ninth MOS transistor is connected to the drain of the tenth MOS transistor;

[0027] The common terminal where the gate of the eleventh MOS transistor is connected to the gate of the thirteenth MOS transistor is connected to the common terminal where the drain of the eighth MOS transistor is connected to the drain of the ninth MOS transistor. The source of the eleventh MOS transistor and the gate of the twelfth MOS transistor are connected to the low-voltage power supply. The common terminal where the drain of the eleventh MOS transistor is connected to the drain of the twelfth MOS transistor is used as the output end of the non-degenerate level conversion circuit;

[0028] The source electrode of the twelfth MOS transistor is connected to the drain electrode of the thirteenth MOS transistor, and the source electrodes of the tenth MOS transistor and the thirteenth MOS transistor are grounded.

[0029] In the embodiment of the present invention, the fourth MOS transistor, the sixth MOS transistor, the eighth MOS transistor, and the eleventh MOS transistor are enhancement-type PMOS transistors; the fifth MOS transistor, the seventh MOS transistor, the ninth MOS transistor, the tenth MOS transistor, the twelfth MOS transistor, and the thirteenth MOS transistor are enhancement-type NMOS transistors.

[0030] In the embodiment of the present invention, the frequency attenuation detection circuit includes: a frequency divider, a counter, a discriminator, and a latch;

[0031] The high-voltage oscillation signal output by the non-degenerate ring oscillator is converted into a low-voltage oscillation signal through a non-degenerate level conversion circuit and then output to the counter as the reference clock of the counter;

[0032] The high-voltage oscillation signal output by the degenerate ring oscillator is converted into a low-voltage oscillation signal through a degenerate level conversion circuit and then output to the frequency divider for frequency division to obtain the counting signal of the counter and the latching signal of the latch;

[0033] The counter counts the reference clock according to the counting signal and outputs the counting result to the discriminator;

[0034] The discriminator determines whether the counting result is greater than the threshold value to obtain a discrimination result;

[0035] The latch latches the discrimination result according to the latching signal and then outputs an early warning signal.

[0036] The chip degradation monitoring circuit provided by the embodiment of the present invention includes: the above-mentioned channel degradation monitoring circuit, gate oxide degradation monitoring circuit, and data serial output circuit;

[0037] The channel degradation monitoring circuit and the gate oxide degradation monitoring circuit output multiple monitoring signals in parallel to the data serial output circuit;

[0038] The data serial output circuit serially outputs the multiple monitoring signals.

[0039] In an embodiment of the present invention, the gate oxide degradation monitoring circuit includes a first branch and a second branch, and the first branch and the second branch are connected by a current mirror; the first branch includes a MOS capacitor bank, and the second branch includes an inverter; the MOS capacitor bank includes a plurality of high-voltage MOS transistors connected in parallel, and the source and drain of each high-voltage MOS transistor are short-circuited to be equivalent to a capacitor; the common terminal connected to the gate of each high-voltage MOS transistor serves as the first end of the MOS capacitor bank, and the common terminal where the source and drain of each high-voltage MOS transistor are short-circuited serves as the second end of the MOS capacitor bank; the second end of the MOS capacitor bank is grounded, and the first end of the MOS capacitor bank is connected to a stress voltage, and the stress voltage is greater than the operating voltage of the high-voltage MOS transistor to accelerate the gate oxide degradation of the high-voltage MOS transistor;

[0040] The current mirror is used to copy the current of the first branch to the input terminal of the inverter in the second branch, and the level signal output by the inverter is used as the gate oxide degradation monitoring signal.

[0041] In an embodiment of the present invention, the current mirror includes: a first resistor, a second resistor, a first MOS transistor, and a second MOS transistor; the gate of the first MOS transistor is connected to the gate of the second MOS transistor; the source of the first MOS transistor is connected to the stress voltage through the first resistor, and the drain of the first MOS transistor is connected to the first end of the MOS capacitor bank; the source of the second MOS transistor is connected to the stress voltage through the second resistor and is connected to the first resistor, and the drain of the second MOS transistor is connected to the input terminal of the inverter.

[0042] The common terminal where the gate of the first MOS transistor is connected to the gate of the second MOS transistor is connected to the first end of the MOS capacitor bank.

[0043] In an embodiment of the present invention, the second branch further includes a third resistor, the first end of the third resistor is connected to the input terminal of the inverter and is connected to the drain of the second MOS transistor, and the second end of the third resistor is grounded.

[0044] The second branch further includes a Zener diode, the negative electrode of the Zener diode is connected to the input terminal of the inverter and is connected to the drain of the second MOS transistor, and the positive electrode of the Zener diode is grounded.

[0045] In an embodiment of the present invention, when the gate oxide of the high-voltage MOS transistor in the MOS capacitor bank degrades under the action of the stress voltage and the gate oxide of the high-voltage MOS transistor is not broken down, there is no current in the first branch, there is no mirrored current in the second branch, the third resistor pulls down the voltage at the input terminal of the inverter, and the inverter outputs a high level;

[0046] When the high-voltage MOS transistor in the MOS capacitor bank undergoes gate oxide degradation under the action of the stress voltage, when the gate oxide of the high-voltage MOS transistor is broken down, a large current is generated in the first branch, and a mirrored large current is generated in the second branch. The mirrored large current generates a voltage through the third resistor, the input end of the inverter is at a high level, and the inverter outputs a low level.

[0047] In the embodiment of the present invention, the chip degradation monitoring circuit further includes: a substrate degradation monitoring circuit for monitoring the substrate degradation of the high-voltage power device;

[0048] The substrate degradation monitoring circuit is connected in parallel with the channel degradation monitoring circuit and the gate oxide degradation monitoring circuit;

[0049] The channel degradation monitoring circuit, the gate oxide degradation monitoring circuit, and the substrate degradation monitoring circuit output multiple monitoring signals in parallel to the data serial output circuit.

[0050] In the embodiment of the invention, the substrate degradation monitoring circuit includes a plurality of monitoring branches connected in parallel. Each monitoring branch includes: a high-voltage MOS device, a comparator, and a selector. The selector includes a first selector, a second selector, and a third selector;

[0051] The drain of the high-voltage MOS device is connected to the stress voltage through the first selector and connected to the first input end of the comparator;

[0052] The gate of the high-voltage MOS device is connected to the test voltage through the second selector. The test voltage is used to apply a negative bias voltage to the gate-drain terminal of the high-voltage MOS device;

[0053] The source of the high-voltage MOS device is connected to the reverse test voltage through the third selector;

[0054] The reference voltage is input to the second input end of the comparator of each monitoring branch, and the reference voltages input to the second input ends of the comparators of each monitoring branch are all different.

[0055] In the embodiment of the invention, the substrate degradation monitoring circuit further includes: a channel degradation compensation circuit, a gate oxide degradation compensation circuit, and a substrate degradation compensation circuit;

[0056] The channel degradation compensation circuit is connected in parallel with the channel degradation monitoring circuit, the gate oxide degradation compensation circuit is connected in parallel with the gate oxide degradation monitoring circuit, and the substrate degradation compensation circuit is connected in parallel with the substrate degradation monitoring circuit.

[0057] The present invention also provides a power supply chip, and the power supply chip includes the above-mentioned chip degradation monitoring circuit.

[0058] The present invention also provides an isolation drive chip, and the isolation drive chip includes the above-mentioned chip degradation monitoring circuit.

[0059] The present invention designs a corresponding channel degradation monitoring circuit for the channel degradation of high-voltage devices to achieve the monitoring and early warning of the channel degradation of high-voltage devices. The present invention also designs corresponding monitoring circuits for the channel degradation, gate oxide degradation, and substrate degradation of high-voltage devices in the chip and integrates them, which can support the degradation monitoring and early warning of high-voltage devices and circuits in the chip, overcoming the defect that the existing monitoring circuits are only applicable to monitoring low-voltage SOC chips and cannot monitor high-voltage circuits and chips; the degradation monitoring circuit of the present invention can be embedded into the power supply and isolation driver chip to form a power supply and isolation driver chip with the function of monitoring high-voltage device failures.

[0060] Other features and advantages of the technical solution of the present invention will be described in detail in the following specific implementation part. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] The drawings described herein are used to provide a further understanding of the present invention and form a part of the present invention. The schematic embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0062] Figure 1 is a schematic structural diagram of the channel degradation monitoring circuit provided by an embodiment of the present invention;

[0063] Figure 2 is a schematic circuit diagram of the degraded inverter provided by an embodiment of the present invention;

[0064] Figure 3 is a schematic circuit diagram of the non-degraded inverter provided by an embodiment of the present invention;

[0065] Figure 4 is a schematic diagram of the degraded level conversion circuit provided by an embodiment of the present invention;

[0066] Figure 5 is a schematic diagram of the non-degraded level conversion circuit provided by an embodiment of the present invention;

[0067] Figure 6 is a schematic diagram of the frequency attenuation detection circuit provided by an embodiment of the present invention;

[0068] Figure 7 is a schematic structural diagram of the chip degradation monitoring circuit provided by an embodiment of the present invention;

[0069] Figure 8 is a schematic diagram of the gate oxide degradation monitoring circuit provided by an embodiment of the present invention;

[0070] Figure 9 is a schematic structural diagram of the chip degradation monitoring circuit provided by another embodiment of the present invention;

[0071] Figure 10It is a schematic diagram of the substrate degradation monitoring circuit provided by an embodiment of the present invention;

[0072] Figure 11 It is a schematic diagram of the data serial output circuit provided by an embodiment of the present invention;

[0073] Figure 12 It is a schematic circuit diagram of the serial shift register in the data serial output circuit provided by an embodiment of the present invention;

[0074] Figure 13 It is a schematic circuit diagram of the frequency divider in the data serial output circuit provided by an embodiment of the present invention;

[0075] Figure 14 It is a schematic diagram of the data serial output circuit embedded with a ring oscillator provided by an embodiment of the present invention;

[0076] Figure 15 It is a schematic structural diagram of the chip degradation monitoring circuit with redundancy compensation provided by an embodiment of the present invention;

[0077] Figure 16 It is a schematic diagram of the channel degradation compensation circuit provided by an embodiment of the present invention;

[0078] Figure 17 It is a schematic diagram of the gate oxide degradation compensation circuit provided by an embodiment of the present invention;

[0079] Figure 18 It is a schematic diagram of the substrate degradation compensation circuit provided by an embodiment of the present invention. Detailed implementation manners

[0080] In order to make the technical solutions and advantages in the embodiments of the present invention clearer and more understandable, the following further describes the exemplary embodiments of the present invention in detail with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than an exhaustive list of all embodiments. It should be noted that, without conflict, the embodiments in the present invention and the features in the embodiments can be combined with each other.

[0081] In the description of the present invention, the terms "first", "second", and "third" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first", "second", and "third" may explicitly or implicitly include one or more of such features. In the description of the present invention, the meaning of "a plurality" is at least two, such as two, three, etc., unless otherwise specifically defined.

[0082] In the present invention, unless otherwise clearly defined and limited, terms such as "connected" and "linked" shall be understood in a broad sense. For example, it may be an electrical connection or may communicate with each other, may be directly connected, or may be indirectly connected through an intermediate medium, and may be the internal communication of two components or the interaction relationship between two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0083] In the process of implementing the present invention, the inventors found that the traditional device degradation monitoring circuit is only applicable to SOC chips and is not suitable for power chips and isolation driver chips. Moreover, the traditional device degradation monitoring solution only monitors low-voltage process defects and only supports low-voltage devices of 5V, and cannot support the monitoring of high-voltage devices and circuit systems of 12V to 750V.

[0084] In view of the above problems, an embodiment of the present invention provides a high-voltage device degradation monitoring circuit applicable to power chips and isolation driver chips, which integrates a channel degradation monitoring circuit, a gate oxide degradation monitoring circuit, and a substrate degradation monitoring circuit. The channel degradation monitoring circuit is used to monitor the channel degradation of high-voltage devices in the circuit under test; the gate oxide degradation monitoring circuit is used to monitor the gate oxide degradation of high-voltage devices in the circuit under test; the substrate degradation monitoring circuit is used to monitor the substrate degradation of high-voltage devices in the circuit under test. The channel degradation monitoring circuit, the gate oxide degradation monitoring circuit, and the substrate degradation monitoring circuit output multiple monitoring signals in parallel, and the multiple monitoring signals are serially output through a data serial output circuit. The present invention designs corresponding monitoring circuits for the channel degradation, gate oxide degradation, and substrate degradation of high-voltage devices and integrates them, which can support the degradation monitoring and failure warning of high-voltage devices and circuits; the degradation monitoring circuit of the present invention can be embedded in power and isolation driver chips to form power and isolation driver chips with the function of monitoring high-voltage MOS device failures.

[0085] Figure 1 is a schematic structural diagram of the channel degradation monitoring circuit provided by an embodiment of the present invention. As Figure 1As shown, the channel degradation monitoring circuit includes: a non-degraded ring oscillator, a degraded ring oscillator, a non-degraded level conversion circuit, a degraded level conversion circuit, and a frequency attenuation detection circuit. The degraded ring oscillator includes an odd number of serially connected degraded inverters, and the non-degraded ring oscillator includes an odd number of serially connected non-degraded inverters. Both the degraded inverter and the non-degraded inverter have high-voltage transistors. The high-voltage transistors in the degraded inverter are subjected to voltage stress to cause channel degradation, so that the frequency of the degraded ring oscillator decays over time. The frequency of the degraded ring oscillator degrades (attenuates) over time, and the frequency of the non-degraded ring oscillator only degrades very slightly over time. The frequency degradation of the non-degraded ring oscillator is negligible compared to that of the degraded ring oscillator. The channel degradation monitoring and warning circuit monitors and warns of the channel degradation of the high-voltage devices in the degraded inverter by detecting the amount of frequency attenuation of the degraded ring oscillator over time.

[0086] The non-degraded ring oscillator is connected to the frequency attenuation detection circuit through the non-degraded level conversion circuit, and the degraded ring oscillator is connected to the frequency attenuation detection circuit through the degraded level conversion circuit; the non-degraded level conversion circuit is used to convert the high-voltage oscillation signal CLK_REF_40V output by the non-degraded ring oscillator into a low-voltage oscillation signal CLK_REF; the degraded level conversion circuit is used to convert the high-voltage oscillation signal CLK_DEG_40V output by the degraded ring oscillator into a low-voltage oscillation signal CLK_DEG; the frequency attenuation detection circuit is used to detect the amount of frequency attenuation of the oscillation signal CLK_REF converted by the degraded level conversion circuit relative to the oscillation signal CLK_REF converted by the non-degraded level conversion circuit.

[0087] In this embodiment, the degraded ring oscillator includes an odd number of serially connected degraded inverters, and the circuit structure of the degraded inverter is as Figure 2As shown in the figure. The degenerative inverter includes: a first high-voltage transistor M1, a first resistor R1, a second resistor R2, and a third resistor R3. The gate of the first high-voltage transistor M1 is connected to the input terminal IN (corresponding to the output terminal of the previous degenerative inverter) of the degenerative inverter through the first resistor R1, and is grounded to GND through the second resistor R2. The source of the first high-voltage transistor M1 is grounded to GND. The drain of the first high-voltage transistor M1 is connected to the power supply terminal VDD of the chip through the third resistor R3. The node between the drain of the first high-voltage transistor M1 and the third resistor R3 is used as the output terminal OUT of the degenerative inverter. The first high-voltage transistor M1 is one of high-voltage-resistant devices such as LDMOS (Laterally Diffused Metal Oxide Semiconductor), VDMOS (Vertical Double-diffused Metal-Oxide-Semiconductor device), and BJT (Bipolar Junction Transistor), and its source-drain voltage (maximum withstand voltage) ranges from 12V to 750V. The first high-voltage transistor M1 undergoes channel degradation when a stress voltage is applied, and the frequency of the degenerative ring oscillator composed of the degenerative inverter decays over time. In a typical power supply chip, the source-drain voltage of high-voltage devices such as LDMOS is 40V, supporting a 40V power supply.

[0088] In a specific embodiment, taking the design of an inverter that can support a 40V power supply as an example, different from the existing inverter using NMOS + PMOS, since this embodiment needs to support a 40V power supply input, voltage division is performed through rphripoly type resistors R1 and R2 that can withstand high voltage to obtain the gate voltage of the LDMOS that can withstand 40V withstand voltage, thereby realizing the reverse function. Since when the IN signal is at a low level, the OUT signal outputs a high voltage, and the 40V device M1 is an LDMOS, its drain-source voltage VDS reaches a high voltage of 40V, constituting a high-voltage channel degradation inverter.

[0089] In this embodiment, the non-degenerative ring oscillator includes an odd number of serially connected non-degenerative inverters, and the circuit structure of the non-degenerative inverter is as Figure 3As shown in the figure. The non-degenerate inverter includes: a second high-voltage transistor M2, a third high-voltage transistor M3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, and an eighth resistor R8. The gate of the second high-voltage transistor M2 is connected to the input terminal IN (corresponding to the output terminal of the previous non-degenerate inverter) of the non-degenerate inverter through the eighth resistor R8, and is grounded to GND through the fourth resistor R4. The source of the second high-voltage transistor M2 is grounded to GND, and the drain of the second high-voltage transistor M2 is connected to the source of the third high-voltage transistor M3. The gate of the third high-voltage transistor M3 is connected to the power supply terminal VDD of the chip through the fifth resistor R5, and is grounded to GND through the sixth resistor R6. The drain of the third high-voltage transistor M3 is connected to the power supply terminal VDD of the chip through the seventh resistor R7. The node between the drain of the third high-voltage transistor M3 and the seventh resistor R7 serves as the output terminal OUT of the non-degenerate inverter. The second high-voltage transistor M2 and the third high-voltage transistor M3 are one of high-voltage devices such as LDMOS, VDMOS, and BJT, and their source-drain voltage (maximum breakdown voltage) ranges from 12V to 750V. The second high-voltage transistor M2 and the third high-voltage transistor M3 are not applied with a stress voltage, and their channel degradation is very slow and negligible. The frequency decay of the degenerate ring oscillator composed of non-degenerate inverters is also negligible.

[0090] In a specific embodiment, taking the design of an inverter that can support a 40V power supply as an example, different from the existing inverter using NMOS + PMOS, since this embodiment needs to support a 40V power supply input, voltage division is performed through rphripoly type resistors R3, R4, R5, and R6 that can withstand high voltage to obtain the gate voltage of the LDMOS that can withstand 40V breakdown voltage, thereby realizing the reverse function. When the IN signal is at a low level, the OUT signal outputs a high voltage. Different from the degenerate inverter circuit, the non-degenerate inverter provides a biasing effect by adding a 40V LDMOS transistor M3. Since the Gate voltage of M3 is a fixed value, the source voltage of M3 is a fixed value, which is much less than 40V, so that the drain-source voltage (source-drain voltage) VDS of the 40V LDMOS transistor M2 does not reach the 40V high voltage, and it only bears a low voltage, so it is a high-voltage channel non-degenerate inverter.

[0091] After obtaining the above two types of inverters, a ring oscillator can be obtained by designing an odd number of inverters connected in series. By designing a corresponding ring oscillator and embedding it in the system under test, the purpose of testing the degradation of the system under test can be achieved by measuring the frequency and its degradation of the ring oscillator in real-time online without affecting the operation of the circuit under test. The present invention is designed based on this principle, using a ring oscillator as a test circuit, and measuring its degradation degree by monitoring the attenuation amount of its frequency.

[0092] Due to the complexity of the internal logic circuit of the chip, if a 40V voltage domain is used for all designs, it will be very wasteful in terms of power consumption and area. Therefore, a "high voltage 40V to low voltage 5V" conversion circuit is designed.

[0093] As Figure 4 shown, the degraded level conversion circuit includes: the fourth MOS transistor M4, the fifth MOS transistor M5, the sixth MOS transistor M6, and the seventh MOS transistor M7. The gate of the fourth MOS transistor M4 is connected to the gate of the fifth MOS transistor M5 and connected to the output terminal of the degraded ring oscillator. The drain of the fourth MOS transistor M4 is connected to the drain of the fifth MOS transistor M5. The gate of the sixth MOS transistor M6 is connected to the gate of the seventh MOS transistor M7 and connected to the common terminal where the drain of the fourth MOS transistor M4 is connected to the drain of the fifth MOS transistor M5. The common terminal where the drain of the sixth MOS transistor M6 is connected to the drain of the seventh MOS transistor M7 serves as the output terminal of the degraded level conversion circuit. The source of the fourth MOS transistor M4 and the source of the sixth MOS transistor M6 are connected to the 5V power supply. The source of the fifth MOS transistor M5 and the source of the seventh MOS transistor M7 are grounded. Among them, the fourth MOS transistor M4 and the sixth MOS transistor M6 are enhancement-mode PMOS transistors, and the fifth MOS transistor M5 and the seventh MOS transistor M7 are enhancement-mode NMOS transistors.

[0094] As Figure 5 shown, the non-degraded level conversion circuit includes: the eighth MOS transistor M8, the ninth MOS transistor M9, the tenth MOS transistor M10, the eleventh MOS transistor M11, the twelfth MOS transistor M12, and the thirteenth MOS transistor M13. The common terminal where the gate of the eighth MOS transistor M8 is connected to the gate of the ninth MOS transistor M9 and the gate of the tenth MOS transistor M10 is connected to the output terminal of the non-degraded ring oscillator. The source of the eighth MOS transistor M8 is connected to the 5V low-voltage power supply. The drain of the eighth MOS transistor M8 is connected to the drain of the ninth MOS transistor M9. The source of the ninth MOS transistor M9 is connected to the drain of the tenth MOS transistor M10. The common terminal where the gate of the eleventh MOS transistor M11 is connected to the gate of the thirteenth MOS transistor M13 is connected to the common terminal where the drain of the eighth MOS transistor M8 is connected to the drain of the ninth MOS transistor M9. The source of the eleventh MOS transistor M11 and the gate of the twelfth MOS transistor M12 are connected to the 5V low-voltage power supply. The common terminal where the drain of the eleventh MOS transistor M11 is connected to the drain of the twelfth MOS transistor M12 serves as the output terminal of the non-degraded level conversion circuit. The source of the twelfth MOS transistor M12 is connected to the drain of the thirteenth MOS transistor M13. The source of the tenth MOS transistor M10 and the source of the thirteenth MOS transistor M13 are grounded. Among them, the eighth MOS transistor M8 and the eleventh MOS transistor M11 are enhancement-mode PMOS transistors, and the ninth MOS transistor M9, the tenth MOS transistor M10, the twelfth MOS transistor M12, and the thirteenth MOS transistor M13 are enhancement-mode NMOS transistors.

[0095] In this embodiment, the frequency decay detection circuit monitors and gives an early warning of the channel degradation of the first high-voltage transistor of the degraded inverter by detecting the frequency decay amount of the degraded ring oscillator over time and counting the number of cycles of the non-degraded ring oscillator in the corresponding period after degradation. Figure 6 shows the structure of the frequency decay detection circuit, which includes a frequency divider, a counter, a discriminator, and a latch. Refer to Figure 6 and Figure 1 , the non-degraded level conversion circuit converts the high-voltage oscillation signal CLK_REF_40V output by the non-degraded ring oscillator into a low-voltage oscillation signal CLK_REF and then outputs it to the counter as the reference clock of the counter; the degraded level conversion circuit converts the high-voltage oscillation signal CLK_DEG_40V output by the degraded ring oscillator into a low-voltage oscillation signal CLK_DEG and then outputs it to the frequency divider for frequency division to obtain the counting signal of the counter and the latching signal of the latch. The counter counts the reference clock according to the counting signal and outputs the counting result to the discriminator; the discriminator determines whether the counting result is greater than the threshold to obtain the discrimination result; the latch latches the discrimination result according to the latching signal (the rising edge of the CLK_DEG signal) and then outputs it. Among them, the frequency of CLK_DEG degrades over time, and the frequency of CLK_REF does not degrade over time. As the degraded ring oscillator degrades, the period of the oscillation signal CLK_DEG becomes longer and the frequency becomes smaller (frequency decay). After frequency division, the period is even longer. The frequency-divided signal is used as the counting signal to count the number of the reference clock (non-degraded oscillation signal). As the degraded ring oscillator degrades, the number of counts becomes more. If the counting result is greater than the threshold, it indicates that the frequency of the CLK_DEG signal decays and the degraded ring oscillator reaches a certain degree of degradation, and the latch outputs a channel degradation warning signal.

[0096] Figure 7 is a schematic structural diagram of a chip degradation monitoring circuit provided by an embodiment of the present invention. As Figure 7 shown, the chip degradation monitoring circuit provided in this embodiment includes a channel degradation monitoring circuit and a gate oxide degradation monitoring circuit. The channel degradation monitoring circuit and the gate oxide degradation monitoring circuit output multiple monitoring signals in parallel, and the multiple monitoring signals are serially output through a data serial output circuit. The data serial output circuit outputs a clock signal CLK or a digital signal DOUT.

[0097] In a MOS device, hot carriers obtain sufficient energy under a high electric field and overcome the interface barrier to be injected into the oxide layer, generating oxide layer trap charges or interface trap charges, which increases or makes the oxide layer charge fluctuate unstably, leading to channel degradation, gate oxide degradation or substrate degradation of the device. The channel degradation mechanism is as follows: When the energy of hot electrons is higher than the Si-SiO2 interface barrier, they may overcome the interface barrier and be injected into the gate oxide layer. Some carriers finally reach the gate electrode and form part of the gate current. During the process of hot carriers reaching the gate electrode through the gate oxide layer, the hot carriers will use their energy to break the bonds such as Si-H and Si-OH bonds at the interface, generating acceptor-type interface states at the Si-SiO2 interface, or being trapped by the traps in the gate oxide layer to form trap charges. These generated interface states and trap charges will cause local electric field changes in the device, resulting in the degradation of device characteristics, the gradual degradation of circuit performance over time, and ultimately the functional failure of the device and the circuit it belongs to, that is, the channel degradation effect occurs.

[0098] In the embodiment of the present invention, a corresponding monitoring circuit is designed for the gate oxide degradation of the chip. The gate oxides of the gate oxide breakdown monitoring circuit and the host circuit (the circuit under test) have the same gate oxide thickness and work in the same temperature environment, only the gate oxide area and voltage stress are different. A voltage stress greater than its operating condition is applied to the gate dielectric of the monitoring circuit to cause the gate dielectric of the monitoring circuit to fail earlier than the circuit under test. When the life of the circuit under test (chip) is still a preset "forecast advance" away from the wear-out failure region, the monitoring circuit subjected to a larger voltage stress enters the wear-out failure region in advance, thus achieving the purpose of early warning of gate oxide degradation failure.

[0099] Such as Figure 8As shown, the gate oxide degradation monitoring circuit provided in this embodiment includes a first branch (left branch) and a second branch (right branch). The first branch and the second branch are connected by a current mirror. The first branch includes a MOS capacitor bank, and the second branch includes an inverter. The MOS capacitor bank includes multiple high-voltage MOS transistors connected in parallel. The source and drain of each high-voltage MOS transistor are shorted to be equivalent to a capacitor. The common terminal connected to the gate of each high-voltage MOS transistor serves as the first terminal of the MOS capacitor bank, and the common terminal where the source and drain of each high-voltage MOS transistor are shorted serves as the second terminal of the MOS capacitor bank. The second terminal of the MOS capacitor bank is grounded, and the first terminal of the MOS capacitor bank is connected to a stress voltage, which is greater than the operating voltage of the high-voltage MOS transistor to accelerate the gate oxide degradation of the high-voltage MOS transistor. The current mirror copies the current image of the first branch to the input terminal of the inverter in the second branch, and determines the degree of gate oxide degradation of the high-voltage MOS transistor according to the level signal output by the inverter. This gate oxide degradation monitoring circuit can perform real-time dynamic internal monitoring of PA (picoampere)-level current. The stress voltage is adjustable, and the degradation time is controllable, enabling dynamic monitoring of the time-dependent reliability faults of the power supply and the isolation drive circuit. The high-voltage MOS transistors in the MOS capacitor bank can be one of high-voltage-resistant devices such as LDMOS (Laterally Diffused Metal Oxide Semiconductor), VDMOS (Vertical Double-diffused Metal-Oxide-Semiconductor device), and DEMOS (Drain-Extended MOS). In the embodiment of the present invention, the breakdown voltage of the high-voltage MOS transistor ranges from 12V to 750V.

[0100] The first branch and the second branch are connected by a current mirror. The current mirror copies the current image of the first branch to the input terminal of the inverter in the second branch, and determines the degree of gate oxide degradation of the high-voltage MOS transistor according to the level of the level signal output by the inverter, achieving the purpose of early warning.

[0101] In this embodiment, the current mirror includes a first resistor R1, a second resistor R2, a first MOS transistor PM1, and a second MOS transistor PM2. The first MOS transistor PM1 and the second MOS transistor PM2 are PMOS transistors. The gate of the first MOS transistor PM1 is connected to the gate of the second MOS transistor PM2; the source of the first MOS transistor PM1 is connected to the stress voltage through the first resistor R1, and the drain of the first MOS transistor PM1 is connected to the first end of the MOS capacitor bank. The common terminal where the gate of the first MOS transistor PM1 is connected to the gate of the second MOS transistor PM2 is connected to the first end of the MOS capacitor bank. The source of the second MOS transistor PM2 is connected to the stress voltage through the second resistor R2 and is connected to the first resistor R1, and the drain of the second MOS transistor PM2 is connected to the input terminal of the inverter.

[0102] In this embodiment, the second branch further includes a third resistor R3 and a Zener diode D1. The first end of the third resistor R3 is connected to the input terminal of the inverter and is connected to the drain of the second MOS transistor PM2, and the second end of the third resistor R3 is grounded to GND. The negative electrode of the Zener diode D1 is connected to the input terminal of the inverter and is connected to the drain of the second MOS transistor PM2, and the positive electrode of the Zener diode D1 is grounded to GND.

[0103] For the chip gate oxide degradation monitoring circuit provided in this embodiment, when the high-voltage MOS transistor in the MOS capacitor bank undergoes gate oxide degradation under the action of the stress voltage and the gate oxide of the high-voltage MOS transistor is not broken down, there is no current in the first branch, no mirror current in the second branch, and the third resistor R3 pulls down the input voltage of the inverter, and the inverter outputs a high level. When the high-voltage MOS transistor in the MOS capacitor bank undergoes gate oxide degradation under the action of the stress voltage and the gate oxide of the high-voltage MOS transistor is broken down, a large current is generated in the first branch, there is a mirror large current in the second branch, the mirror large current generates a voltage through the third resistor R3, the input of the inverter is at a high level, and the inverter outputs a low level. Specifically, when the high-voltage MOS transistor serving as the MOS capacitor does not degrade, the capacitor bank can be equivalent to an open circuit. At this time, there is no current in the branch where the first resistor R1 on the left side of the current mirror is located, so there is no current in the branch where the second resistor R2 on the right side is located either. At this time, the third resistor R3 pulls down the input voltage of the inverter, and the output of the inverter is at a high level. When the high-voltage MOS transistor serving as the MOS capacitor degrades and breaks down, it can be equivalent to a short circuit. At this time, a current appears in the branch where the first resistor R1 on the left side of the current mirror is located, and the magnitude of the current is determined by the size of R1 and the PMOS transistor below R1. The magnitude of the current in the left branch is limited by the first resistor R1 and will not exceed the safe operating range of the circuit. At the same time, due to the characteristics of the proportional current mirror, a current also appears in the branch where the second resistor R2 on the right side of the current mirror is located. This current generates a voltage through the third resistor R3, and the Zener diode D1 limits this voltage within the safe operating range to protect the inverter from being damaged by high voltage. At this time, the input of the inverter is at a high level and the output is at a low level. The degradation degree of the MOS capacitor is judged according to the level of the output of the inverter.

[0104] In a specific embodiment, the high-voltage MOS transistor in the gate oxide degradation monitoring circuit uses an LDMOS with a breakdown voltage of 12V to 750V for monitoring the gate oxide degradation of the LDMOS in the circuit under test. The source and drain of the LDMOS are shorted together to form a capacitor. Since in actual power chips and isolation driver chips, the LDMOS is designed with an even number of fingers, the embodiments of the present invention design an even number of LDMOSs.

[0105] In another specific embodiment, the high-voltage MOS transistor in the gate oxide degradation monitoring circuit can also use a DEMOS (Drain-Extended MOS) with a breakdown voltage of 40V to 750V to monitor the gate oxide degradation of the DEMOS in the circuit under test. The drain terminal of the DEMOS has an extended layer of a lightly doped region, which increases the breakdown voltage at the drain terminal by maintaining charge balance, using an appropriate vertical profile, and increasing the length of the lightly doped region. The lightly doped region forms a high resistance that can withstand a higher voltage, and most of the high drain terminal voltage will drop across this lightly doped region. Therefore, the lightly doped extended layer can improve the breakdown voltage at the drain terminal. As a high-voltage device, the DEMOS is applied in high-voltage power supplies and isolation driver chips. The source and drain of the DEMOS are shorted together to form a capacitor.

[0106] It should be noted that the number of high-voltage MOS transistors in the MOS capacitor bank can be an even number or an odd number. The more the number of high-voltage MOS transistors in the MOS capacitor bank, the more accurate the monitoring. By adjusting the magnitude of the stress voltage applied to the MOS capacitor bank, the degradation time of the MOS capacitor can be controlled, and PA (picoampere)-level current dynamic internal monitoring can be performed in real time.

[0107] Figure 9 is a schematic structural diagram of the chip degradation monitoring circuit provided by another embodiment of the present invention. As Figure 9 shown, the chip degradation monitoring circuit provided in this embodiment includes: a channel degradation monitoring circuit, a gate oxide degradation monitoring circuit, and a substrate degradation monitoring circuit. The channel degradation monitoring circuit is used to monitor the channel degradation of high-voltage power devices; the gate oxide degradation monitoring circuit is used to monitor the gate oxide degradation of high-voltage power devices; the substrate degradation monitoring circuit is used to monitor the substrate degradation of high-voltage power devices. The substrate degradation monitoring circuit is connected in parallel with the channel degradation monitoring circuit and the gate oxide degradation monitoring circuit, and outputs multiple monitoring signals in parallel to the data serial output circuit. The multiple monitoring signals are serially output through the data serial output circuit, and the data serial output circuit outputs a clock signal CLK or a digital signal DOUT.

[0108] As Figure 10As shown, the substrate degradation monitoring circuit provided in this embodiment includes a plurality of monitoring branches connected in parallel. Each monitoring branch includes a high-voltage MOS device, a comparator, and a selector. The selector includes a first selector, a second selector, and a third selector. The drain of the high-voltage MOS device is connected to the stress voltage through the first selector and is connected to the first input terminal of the comparator. The gate of the high-voltage MOS device is connected to the test voltage through the second selector, and this test voltage is used to apply a negative bias voltage to the gate-drain terminal of the high-voltage MOS device. The source of the high-voltage MOS device is connected to the reverse test voltage through the third selector. The second input terminal of the comparator of each monitoring branch inputs a reference voltage, and the reference voltages input by the second input terminals of the comparators of different monitoring branches are different. In a specific embodiment, the high-voltage MOS devices in each monitoring branch can be one of high-voltage-resistant devices such as DEMOS (Drain-Extended MOS), LDMOS (Laterally Diffused Metal Oxide Semiconductor), VDMOS (Vertical Double-diffused Metal-Oxide-Semiconductor device), BJT (Bipolar Junction Transistor), etc., and their source-drain voltages (maximum breakdown voltages) range from 12V to 750V.

[0109] In this embodiment, the high-voltage MOS transistors in each monitoring branch are DEMOS devices, and the source-drain voltages vds of the DEMOS devices in each monitoring branch are the same. As Figure 10As shown, taking a 40V pedmos device as an example, the high-voltage device substrate degradation monitoring circuit includes multiple monitoring branches connected in parallel. Each monitoring branch includes: a pedmos 40V device, a comparator AMP, and a selector sel. Each monitoring branch has three selectors sel. For ease of description, the selectors from top to bottom are defined as the first selector sel, the second selector sel, and the third selector sel in sequence. In each monitoring branch, the drain of the pedmos 40V device is connected to the stress voltage Stress through the first selector sel and is connected to the first input terminal (inverting input terminal) of the comparator AMP; the gate of the pedmos 40V device is connected to the test voltage press through the second selector sel, and this test voltage press applies a negative bias voltage to the gate-drain terminal of the pedmos 40V device; the source of the pedmos 40V device is connected to the inverted test voltage press through the third selector sel. The gate of the pedmos 40V device is connected to the source of this pedmos 40V device through the second selector sel and the third selector sel. Different reference voltages Vref are input to the second input terminal (non-inverting input terminal) of the comparator AMP in each monitoring branch.

[0110] The power supply voltage range in the monitoring circuit is 0 - 5V, which is a monitoring circuit composed of ordinary low-voltage devices; in the circuit to be monitored, the power supply voltage range is 0 - 40V, which is a circuit structure composed of high-voltage pedmos 40V devices. In the fault monitoring circuit composed of 5V low-voltage devices, there are multiple pedmos 40V tubes for monitoring substrate degradation. These pedmos 40V tubes are applied with the same or different stress voltages Stress during the degradation stage. At the same time, during the stage of detecting the degradation degree, a comparator is connected to the output terminal of each pedmos 40V tube, and the reference voltage Vref of each comparator is different. Press is the negative bias stress applied to the gate-drain terminal of the tested pedmos 40V device. Generally, a negative bias voltage of 0 - 5V is applied to the gate-drain terminal. The source-drain voltage vds of the pedmos40V device is 40V, which is a high-voltage MOS tube capable of meeting the 40V power supply. The negative bias stress (i.e., the test voltage) press applied to the gate-drain terminal of the pedmos 40V device is 0 - 5V, and the threshold voltage vth of the pedmos 40V device is 0.92V. By applying a constant voltage stress to the source terminal of the pedmos, when press = 0V, vgs > vth, making the pedmos in the saturation region, thus causing it to degrade. When the stress voltage Stress is 5V, 5.5V, 6V, a difference can be generated with the 5V voltage at the drain, thereby simulating the degradation of high-voltage devices and analyzing the influence of substrate degradation on the life of the pedmos 40V device.

[0111] Figure 10The substrate degradation monitoring circuit shown is essentially a circuit that monitors the drift of the threshold voltage. The circuit formed by connecting ABCDEF in each monitoring branch is a circuit that applies voltage stress and monitors the degree of degradation, and the output is sent to one input terminal of the comparator AMP, and the reference voltage Vref is input to the other input terminal of the comparator AMP. The power supply terminal provides a stress voltage Stress, and the stress voltage Stress of each monitoring branch can be fixed and the same, or it can be different. When the threshold voltage of the pedmos 40v device drifts under the effect of substrate degradation, the threshold voltage output at the B terminal of the monitoring circuit becomes larger. When the degraded threshold voltage is greater than a certain set value, the comparator AMP outputs a high level to issue a warning to the subsequent circuit.

[0112] In the embodiment of the present invention, the working state of the monitoring branch can be selected / switched to be a stress application state or a degradation monitoring state through three selectors Sel. When the first selector Sel selects the drain of the pedmos device to be connected to the stress voltage Stress, the second selector Sel selects the gate of the pedmos device to be connected to the test voltage Press, and the third selector Sel selects the source of the pedmos device to be connected to the reverse test voltage, the working state of the monitoring branch is the stress application state; when the first selector Sel selects the drain of the pedmos device to be connected to the first input terminal of the comparator, and the second selector Sel and the third selector Sel select the gate and source of the pedmos device to be connected, the working state of the monitoring branch is the degradation monitoring state.

[0113] In a specific embodiment, the stress voltages Stress connected to the drains of the pedmos devices in each monitoring branch are the same, and the source-drain voltages vds of the pedmos devices in each monitoring branch are all the same, being 40V. The reference voltages Vref input to the comparators AMP in each monitoring branch increase sequentially, for example: 0.95V, 0.96V, 0.97V, etc. The circuit state can be switched by the selector Sel: when the circuit is in the stress application state, the selector Sel selects the A-C-E path to apply overvoltage stress to the pedmos 40v device; when the circuit is in the monitoring circuit state, the Sel selector will select the B-D-F path. For example, when the substrate of a certain pedmos40v device degrades and its maximum threshold voltage vth increases to above 0.95V and below 0.96V, during the monitoring stage, this threshold voltage vth is compared with the reference voltage Vref 0.95V of the comparator. Since the degraded threshold voltage is higher than the reference voltage, the output terminal of the comparator outputs a low level, sending a warning to the subsequent circuit, and it can be known that the substrate of the pedmos 40v device in this monitoring branch has degraded. The reference voltages Vref of the comparators in other monitoring branches are higher than 0.96V, and the comparators do not issue warnings and can continue to work. As the circuit operation time extends, the substrates of the pedmos 40v devices in other monitoring branches continue to degrade, and the maximum threshold voltage vth of the pedmos 40v device grows to above 0.96V and below 0.97V. During the monitoring stage, this threshold voltage vth is compared with the reference voltage Vref of the comparator. The degraded threshold voltage is higher than the reference voltages Vref 0.95V and 0.96V of the comparators, and the output terminals of these two comparators both output low levels, sending warnings to the subsequent circuit, and it can be known that the substrates of the pedmos 40v devices in these two monitoring branches have both degraded. The remaining comparators with Vref higher than 0.97V do not issue warnings and can continue to work, and so on. Through the warnings issued by the comparators with different reference voltages Vref, the greater the degraded threshold voltage, the more comparators issue early warnings, indicating a higher degree of degradation. Thus, the degradation degree of the threshold voltage of the substrate at this time can be judged, and the visualization of the threshold voltage vth of the monitored circuit is realized. Since the reference voltage Vref of the comparator is an external input, a circuit structure with an adjustable monitoring degradation threshold is formed simultaneously, playing a role in the fault monitoring and early warning of high-voltage pedmos devices.

[0114] In another specific embodiment, the stress voltages Stress connected to the drains of the pedmos 40V devices in each monitoring branch are different. For example, the stress voltages Stress in the monitoring branches are 5V, 5.5V, 6V, etc. respectively. Different stress voltages Stress will result in different degradation times of the pedmos 40V devices. Increasing the stress voltage Stress will advance the degradation time, while decreasing the stress voltage Stress will delay the degradation time. Assume that when the maximum threshold voltage vth of the pedmos 40v device degrades to above 0.95V, the degradation degree is regarded as 20%, and when the threshold voltage vth degrades to above 0.96V, the degradation degree is regarded as 30%, and so on. Then, by increasing the stress voltage Stress, the pedmos 40V device can be degraded in advance, the degradation time is controllable, the waiting time for monitoring the degradation degree is saved, and thus the current degradation degree of the pedmos 40V device can be known.

[0115] It should be noted that the reference voltage Vref of the comparator includes but is not limited to 0.95V, 0.96V, 0.97V, and can be specifically set according to requirements. The stress voltages Stress in each monitoring branch include but are not limited to 5V, 5.5V, 6V, and can be specifically set according to requirements.

[0116] In the embodiment of the present invention, the channel degradation monitoring circuit, the gate oxide degradation monitoring circuit, and the substrate degradation monitoring circuit output multiple monitoring signals in parallel. Since the number of pins of general analog chips, especially power supply and isolation chips, is limited, the parallel multiple monitoring signals are converted into a serial single output through a data serial output circuit.

[0117] Figure 11 is a schematic diagram of the data serial output circuit provided by the embodiment of the present invention. As Figure 11 shown, the data serial output circuit includes: a serial shift register, a frequency divider, and a multiplexer. The serial shift register serially outputs the parallel monitoring signals; the output signal of the frequency divider is a control signal, and its function is to refresh the monitoring signals to be output and the selection signals of the multiplexer; the function of the multiplexer is to select whether to output a clock signal or a serial data signal.

[0118] As Figure 12As shown in the figure, the core devices of the serial shift register include multiple D flip-flops and multiple selectors. The output terminals of the multiple selectors are respectively connected to the D input terminals of the multiple D flip-flops, and the control terminals of the multiple selectors are connected to the control signal sel output by the frequency divider. The control signal sel controls the update of each round of data, and serializes and outputs the parallel input data data[0], data[1], data[2], and data[3] under the action of the clock CLK. Among them, when the triggering edge arrives, the D flip-flop stores the value at the input terminal, which is independent of the currently stored value. Between two valid pulse edges, the jump of D does not affect the value stored in the flip-flop, but before the pulse edge arrives, the input terminal D must have sufficient setup time to ensure signal stability.

[0119] As Figure 13 shown in the figure, the clock signal is input to the CLK terminal of the frequency divider, and the out output terminal generates a clock signal divided by 64. When the divided signal is at a high level, it controls the multiplexer to output the non-divided clock signal to generate the frame header of each round of serial data; at the same time, it also controls the sel signal in the serial shift register circuit. When this clock signal is at a high level, the parallel data is stored in the register. When the divided signal is at a low level, it controls the multiplexer to output the serial data signal.

[0120] To improve the convenience of the module, a ring oscillator is embedded in the data serial output circuit, and the clock signal is provided by the ring oscillator inside the data serial output circuit without the need for an external clock input. Figure 14 is a schematic diagram of the data serial output circuit with an embedded ring oscillator provided by an embodiment of the present invention. Specifically, the structure of the ring oscillator is a closed-loop formed by a series connection of an odd number of inverters (Invertor) (the last output is the initial input). If the initial trigger is "1", then the final output is "0", then the input is also "0", and then the output becomes "1" again, thus realizing the fixed-frequency alternating oscillation output of "0" and "1". In a specific embodiment, an existing push-pull inverter can be used to form the ring oscillator, and this ring oscillator can generate a stable clock signal.

[0121] The embodiment of the present invention also provides a chip degradation monitoring circuit with redundancy compensation. As Figure 15As shown in the figure, the chip degradation monitoring circuit with redundancy compensation according to the embodiment of the present invention includes: a channel degradation monitoring circuit, a gate oxide degradation monitoring circuit, a substrate degradation monitoring circuit, a channel degradation compensation circuit, a gate oxide degradation compensation circuit, and a substrate degradation compensation circuit. The channel degradation compensation circuit is connected in parallel with the channel degradation monitoring circuit, the gate oxide degradation compensation circuit is connected in parallel with the gate oxide degradation monitoring circuit, and the substrate degradation compensation circuit is connected in parallel with the substrate degradation monitoring circuit. When the channel degradation monitoring signal output by the channel degradation monitoring circuit reaches the warning value, it can be switched to the channel degradation compensation circuit; when the gate oxide degradation monitoring signal output by the gate oxide degradation monitoring circuit reaches the warning value, it can be switched to the gate oxide degradation compensation circuit; when the substrate degradation monitoring signal output by the substrate degradation monitoring circuit reaches the warning value, it can be switched to the substrate degradation compensation circuit.

[0122] After the channel degradation monitoring circuit, the gate oxide degradation monitoring circuit, and the substrate degradation monitoring circuit give warning signals, the chip will automatically switch to the redundancy compensation circuit to compensate for the chip reliability. For example, for channel degradation, the sensitive critical path is strengthened; for gate oxide degradation, it is obtained by compensating the MOS capacitor; and for substrate degradation, it is switched to the Dummy transistor. Since the process defect monitoring and compensation include multiple outputs, and for general analog chips, especially power supply and isolation chips, the number of pins is limited, so it is necessary to convert the multiple parallel results into a serial single-channel output. For the power supply chip, only one pin is added; for the isolation chip, only one pin is added to each side of the primary and secondary sides.

[0123] As Figure 16 shown, the channel degradation compensation circuit includes a first MOS transistor M1 and a second MOS transistor M2. The gate of the first MOS transistor M1 is connected to a 40V power supply, the gate of the second MOS transistor M2 is connected to the input signal IN, the source of the first MOS transistor M1 is connected to the drain of the second MOS transistor M2, the source of the second MOS transistor M2 is grounded, and the drain of the first MOS transistor M1 is used as the output terminal OUT.

[0124] As Figure 17 shown, the gate oxide degradation compensation circuit includes a third MOS transistor M3, a fourth MOS transistor M4, and a first switch T1. The gates of the third MOS transistor M3 and the fourth MOS transistor M4 are connected to the first switch T1. The drain of the third MOS transistor M3 is connected to the source of the fourth MOS transistor M4, and the source of the third MOS transistor M3 is connected to the drain of the fourth MOS transistor M4 and grounded. The third MOS transistor M3 and the fourth MOS transistor M4 are used as redundancy compensation devices. One end 1 of the first switch T1 is connected to the normal operating circuit of the chip, and the other end 2 of the first switch T1 is connected to the redundancy compensation control signal. When the chip is operating normally, the first switch T1 is connected to the normal operating circuit of the chip. When the redundancy compensation control signal is "1", the redundancy compensation device circuit is started.

[0125] As shown Figure 18 in the figure, the substrate degradation compensation circuit includes a fifth MOS transistor M5, a sixth MOS transistor M6, a second switch T2, and a third switch T3. The fifth MOS transistor M5 and the sixth MOS transistor M6 serve as redundant compensation devices. The gate of the fifth MOS transistor M5 is connected to the common terminal 2 through the second switch T2, and the gate of the sixth MOS transistor M6 is connected to the common terminal 2 through the third switch T3. The common terminal 2 is connected to the normal working circuit of the chip. The sources of the fifth MOS transistor M5 and the sixth MOS transistor M6 are connected to the power supply terminal VDD of the chip, and the common terminal 3 where the drains of the fifth MOS transistor M5 and the sixth MOS transistor M6 are connected is connected to the normal working circuit of the chip. The common terminal 1 where the third switch T3 is connected to the second switch T2 is connected to the redundant compensation control signal.

[0126] The present invention designs corresponding monitoring circuits for channel degradation, gate oxide degradation, and substrate degradation of high-voltage devices, and can support the degradation monitoring and early warning of high-voltage devices and circuits. The degradation monitoring circuit for high-voltage devices of the present invention can be embedded into a power supply and isolation driver chip to form a power supply and isolation driver chip with the function of monitoring and early warning of high-voltage MOS device failures. The present invention fills the gap that the current process monitoring module only monitors low-voltage processes and does not monitor high-voltage processes; it overcomes the problem that only the initial aging reliability prediction of the chip is performed at the time of initial factory shipment, and it is impossible to early warn of the real-time dynamic aging monitoring of high-voltage power supplies and isolation chips over time.

[0127] The embodiment of the present invention also provides a power supply chip, and the power supply chip embeds the above-mentioned degradation monitoring circuit for high-voltage devices. The degradation monitoring circuit for high-voltage devices in the above embodiment is embedded into the power supply chip to integrate a power supply chip with the function of monitoring the degradation faults of high-voltage devices from 12V to 750V.

[0128] The embodiment of the present invention also provides an isolation driver chip, and the isolation driver chip embeds the above-mentioned degradation monitoring circuit for high-voltage devices. The degradation monitoring circuit for high-voltage devices in the above embodiment is embedded into the isolation driver chip to integrate an isolation driver chip with the function of monitoring the degradation faults of high-voltage devices from 12V to 750V.

[0129] The manufacturing process of the above power supply chip or isolation driver chip can adopt the ultra-high-voltage bipolar CMOS-DMOS (BCD) process technology. Using the ultra-high-voltage BCD process without epitaxial technology, MOS devices with a breakdown voltage of up to 750V can be realized, and these devices have higher reliability. The high-voltage device substrate degradation monitoring and early warning circuit in the above embodiment is compatible with the ultra-high-voltage BCD process.

[0130] The optional embodiments of the present invention have been described in detail above in conjunction with the accompanying drawings. However, the embodiments of the present invention are not limited to the specific details in the above embodiments. Within the scope of the technical concept of the embodiments of the present invention, various simple modifications can be made to the technical solutions of the embodiments of the present invention, and these simple modifications all fall within the protection scope of the embodiments of the present invention. Additionally, it should be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without conflict, as long as such combination does not violate the idea of the embodiments of the present invention, and it should equally be regarded as the content disclosed by the embodiments of the present invention.

Claims

1. A channel degradation monitoring circuit, characterized in that, Including: A degenerated ring oscillator, a non-degenerated ring oscillator, and a frequency attenuation detection circuit; The degenerated ring oscillator includes an odd number of degenerated inverters connected in series; The degenerated inverter includes: a first high-voltage transistor, a first resistor, a second resistor, and a third resistor. The gate of the first high-voltage transistor is connected to the input end of the degenerated inverter through the first resistor and grounded through the second resistor. The source of the first high-voltage transistor is grounded. The drain of the first high-voltage transistor is connected to the power supply terminal of the chip through the third resistor. The node between the drain of the first high-voltage transistor and the third resistor serves as the output end of the degenerated inverter; The non-degenerated ring oscillator includes an odd number of non-degenerated inverters connected in series; The non-degenerated inverter includes: a second high-voltage transistor, a third high-voltage transistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, and an eighth resistor. The gate of the second high-voltage transistor is connected to the input end of the non-degenerated inverter through the eighth resistor and grounded through the fourth resistor. The source of the second high-voltage transistor is grounded. The drain of the second high-voltage transistor is connected to the source of the third high-voltage transistor. The gate of the third high-voltage transistor is connected to the power supply terminal of the chip through the fifth resistor and grounded through the sixth resistor. The drain of the third high-voltage transistor is connected to the power supply terminal of the chip through the seventh resistor. The node between the drain of the third high-voltage transistor and the seventh resistor serves as the output end of the non-degenerated inverter; The frequency attenuation detection circuit is used to detect the frequency attenuation amount of the degenerated ring oscillator over time, and count the number of cycles of the non-degenerated ring oscillator in the corresponding period of the degenerated ring oscillator, so as to realize the monitoring of the channel degradation of the first high-voltage transistor of the degenerated inverter.

2. The channel degradation monitoring circuit according to claim 1, wherein The first high-voltage transistor, the second high-voltage transistor, and the third high-voltage transistor are one of LDMOS, VDMOS, and BJT; The source-drain voltage of the first high-voltage transistor, the second high-voltage transistor, and the third high-voltage transistor is 12V to 750V.

3. The channel degradation monitoring circuit according to claim 1, wherein It also includes: A non-degenerated level conversion circuit and a degenerated level conversion circuit; The non-degenerated ring oscillator is connected to the frequency attenuation detection circuit through the non-degenerated level conversion circuit, and the degenerated ring oscillator is connected to the frequency attenuation detection circuit through the degenerated level conversion circuit; The non-degenerated level conversion circuit is used to convert the high-voltage oscillation signal output by the non-degenerated ring oscillator into a low-voltage oscillation signal; The degenerated level conversion circuit is used to convert the high-voltage oscillation signal output by the degenerated ring oscillator into a low-voltage oscillation signal.

4. The channel degradation monitoring circuit according to claim 3, wherein The degenerated level conversion circuit includes: a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, and a seventh MOS transistor; The gate of the fourth MOS transistor is connected to the gate of the fifth MOS transistor and connected to the output end of the degenerated ring oscillator. The drain of the fourth MOS transistor is connected to the drain of the fifth MOS transistor; The gate of the sixth MOS transistor is connected to the gate of the seventh MOS transistor and connected to the common end where the drain of the fourth MOS transistor is connected to the drain of the fifth MOS transistor. The common end where the drain of the sixth MOS transistor is connected to the drain of the seventh MOS transistor serves as the output end of the degenerated level conversion circuit; The source electrodes of the fourth MOS transistor and the sixth MOS transistor are connected to the low-voltage power supply, and the source electrodes of the fifth MOS transistor and the seventh MOS transistor are grounded.

5. The channel degradation monitoring circuit according to claim 4, characterized in that The non-degenerate level conversion circuit includes: an eighth MOS transistor, a ninth MOS transistor, a tenth MOS transistor, an eleventh MOS transistor, a twelfth MOS transistor, and a thirteenth MOS transistor; The common terminal where the gates of the eighth MOS transistor, the ninth MOS transistor, and the tenth MOS transistor are connected is connected to the output terminal of the non-degenerate ring oscillator. The source electrode of the eighth MOS transistor is connected to the low-voltage power supply, the drain electrode of the eighth MOS transistor is connected to the drain electrode of the ninth MOS transistor, and the source electrode of the ninth MOS transistor is connected to the drain electrode of the tenth MOS transistor; The common terminal where the gates of the eleventh MOS transistor and the thirteenth MOS transistor are connected is connected to the common terminal where the drain electrodes of the eighth MOS transistor and the ninth MOS transistor are connected. The source electrodes of the eleventh MOS transistor and the twelfth MOS transistor are connected to the low-voltage power supply, and the common terminal where the drain electrodes of the eleventh MOS transistor and the twelfth MOS transistor are connected serves as the output terminal of the non-degenerate level conversion circuit; The source electrode of the twelfth MOS transistor is connected to the drain electrode of the thirteenth MOS transistor, and the source electrodes of the tenth MOS transistor and the thirteenth MOS transistor are grounded.

6. The channel degradation monitoring circuit according to claim 5, wherein, The fourth MOS transistor, the sixth MOS transistor, the eighth MOS transistor, and the eleventh MOS transistor are enhancement-mode PMOS transistors; The fifth MOS transistor, the seventh MOS transistor, the ninth MOS transistor, the tenth MOS transistor, the twelfth MOS transistor, and the thirteenth MOS transistor are enhancement-mode NMOS transistors.

7. The channel degradation monitoring circuit according to claim 3, wherein The frequency attenuation detection circuit includes: a frequency divider, a counter, a discriminator, and a latch; The high-voltage oscillation signal output by the non-degenerate ring oscillator is converted into a low-voltage oscillation signal by the non-degenerate level conversion circuit and then output to the counter as the reference clock of the counter; The high-voltage oscillation signal output by the degenerate ring oscillator is converted into a low-voltage oscillation signal by the degenerate level conversion circuit and then output to the frequency divider for frequency division to obtain the counting signal of the counter and the latching signal of the latch; The counter counts the reference clock according to the counting signal and outputs the counting result to the discriminator; The discriminator determines whether the counting result is greater than the threshold to obtain a discrimination result; The latch latches the discrimination result according to the latching signal and then outputs an early warning signal.

8. A chip degradation monitoring circuit, characterized in that, Including: The channel degradation monitoring circuit, the gate oxide degradation monitoring circuit, and the data serial output circuit according to any one of claims 1-7; The channel degradation monitoring circuit and the gate oxide degradation monitoring circuit output multiple monitoring signals in parallel to the data serial output circuit; The data serial output circuit serially outputs the multiple monitoring signals.

9. The chip degradation monitoring circuit according to claim 8, wherein The gate oxide degradation monitoring circuit includes a first branch and a second branch, and the first branch and the second branch are connected by a current mirror; The first branch includes a MOS capacitor bank, and the second branch includes an inverter; The MOS capacitor bank includes a plurality of high-voltage MOS transistors connected in parallel, and the source and drain electrodes of each high-voltage MOS transistor are short-circuited to be equivalent to a capacitor; The common terminal connected to the gate of each high-voltage MOS transistor serves as the first terminal of the MOS capacitor bank, and the common terminal where the source and drain of each high-voltage MOS transistor are short-circuited serves as the second terminal of the MOS capacitor bank; The second terminal of the MOS capacitor bank is grounded, and the first terminal of the MOS capacitor bank is connected to a stress voltage, which is greater than the operating voltage of the high-voltage MOS transistor to accelerate the gate oxide degradation of the high-voltage MOS transistor; A current mirror is used to mirror-copy the current of the first branch to the input terminal of the inverter in the second branch, and the level signal output by the inverter serves as the gate oxide degradation monitoring signal.

10. The chip degradation monitoring circuit according to claim 9, characterized in that, The current mirror includes: a first resistor, a second resistor, a first MOS transistor, and a second MOS transistor; The gate of the first MOS transistor is connected to the gate of the second MOS transistor; The source of the first MOS transistor is connected to the stress voltage through the first resistor, and the drain of the first MOS transistor is connected to the first terminal of the MOS capacitor bank; The source of the second MOS transistor is connected to the stress voltage through the second resistor and is connected to the first resistor, and the drain of the second MOS transistor is connected to the input terminal of the inverter.

11. The chip degradation monitoring circuit according to claim 10, characterized in that, The common terminal where the gate of the first MOS transistor is connected to the gate of the second MOS transistor is connected to the first terminal of the MOS capacitor bank.

12. The chip degradation monitoring circuit according to claim 10, wherein, The second branch further includes a third resistor, the first end of the third resistor is connected to the input terminal of the inverter and is connected to the drain of the second MOS transistor, and the second end of the third resistor is grounded.

13. The chip degradation monitoring circuit according to claim 12, wherein The second branch further includes a Zener diode, the negative electrode of the Zener diode is connected to the input terminal of the inverter and is connected to the drain of the second MOS transistor, and the positive electrode of the Zener diode is grounded.

14. The chip degradation monitoring circuit according to claim 12, wherein, When the high-voltage MOS transistor in the MOS capacitor bank undergoes gate oxide degradation under the action of the stress voltage and the gate oxide of the high-voltage MOS transistor is not broken down, there is no current in the first branch, no mirrored current in the second branch, and the third resistor pulls down the voltage at the input terminal of the inverter, and the inverter outputs a high level; When the high-voltage MOS transistor in the MOS capacitor bank undergoes gate oxide degradation under the action of the stress voltage and the gate oxide of the high-voltage MOS transistor is broken down, a current is generated in the first branch, there is a large mirrored current in the second branch, the mirrored current generates a voltage through the third resistor, the input terminal of the inverter is at a high level, and the inverter outputs a low level.

15. The chip degradation monitoring circuit according to claim 9, wherein The high-voltage MOS transistor in the MOS capacitor bank is one of LDMOS, VDMOS, and DEMOS.

16. The chip degradation monitoring circuit according to claim 8, wherein It further includes: A substrate degradation monitoring circuit for monitoring the substrate degradation of high-voltage power devices; The substrate degradation monitoring circuit is connected in parallel with the channel degradation monitoring circuit and the gate oxide degradation monitoring circuit; The channel degradation monitoring circuit, the gate oxide degradation monitoring circuit, and the substrate degradation monitoring circuit output multiple monitoring signals in parallel to the data serial output circuit.

17. The chip degradation monitoring circuit according to claim 16, wherein The substrate degradation monitoring circuit includes a plurality of monitoring branches connected in parallel, and each monitoring branch includes: a high-voltage MOS device, a comparator, and a selector, and the selector includes a first selector, a second selector, and a third selector; The drain of the high-voltage MOS device is connected to the stress voltage through the first selector and is connected to the first input terminal of the comparator; The gate of the high-voltage MOS device is connected to the test voltage through the second selector, and the test voltage is used to apply a negative bias voltage to the gate-drain terminal of the high-voltage MOS device; The source of the high-voltage MOS device is connected to a reverse test voltage through a third selector; A reference voltage is input to the second input terminal of the comparator in each monitoring branch, and the reference voltages input to the second input terminals of the comparators in each monitoring branch are all different.

18. The chip degradation monitoring circuit according to claim 17, wherein The gate of the high-voltage MOS device is connected to the source of the high-voltage MOS device through a second selector and a third selector.

19. The chip degradation monitoring circuit according to claim 17, characterized in that, The substrate degradation monitoring circuit selects the working state of each monitoring branch as the stress application state or the degradation monitoring state through a first selector, a second selector, and a third selector.

20. The chip degradation monitoring circuit according to claim 19, wherein When the first selector selects the drain of the high-voltage MOS device to be connected to the stress voltage, the second selector selects the gate of the high-voltage MOS device to be connected to the test voltage, and the third selector selects the source of the high-voltage MOS device to be connected to the reverse test voltage, the working state of the monitoring branch is the stress application state; When the first selector selects the drain of the high-voltage MOS device to be connected to the first input terminal of the comparator, and the second selector and the third selector select the gate and the source of the high-voltage MOS device to be connected, the working state of the monitoring branch is the degradation monitoring state.

21. The chip degradation monitoring circuit according to claim 17, characterized in that, The stress voltages connected to the drains of the high-voltage MOS devices in each monitoring branch are the same; The reference voltages input to the second input terminals of the comparators in each monitoring branch increase sequentially.

22. The chip degradation monitoring circuit according to claim 17, wherein The stress voltages connected to the drains of the high-voltage MOS devices in each monitoring branch are all different; The reference voltages input to the second input terminals of the comparators in each monitoring branch increase sequentially.

23. The chip degradation monitoring circuit according to claim 21 or 22, characterized in that, The source-drain voltages of the high-voltage MOS devices in each monitoring branch are the same.

24. The chip degradation monitoring circuit according to claim 17, wherein The high-voltage MOS devices in each monitoring branch are one of DEMOS, LDMOS, VDMOS, and BJT, and the source-drain voltage of the high-voltage MOS device is 12V to 750V.

25. The chip degradation monitoring circuit according to claim 16, wherein It further includes: A channel degradation compensation circuit, a gate oxide degradation compensation circuit, and a substrate degradation compensation circuit; The channel degradation compensation circuit is connected in parallel with the channel degradation monitoring circuit, the gate oxide degradation compensation circuit is connected in parallel with the gate oxide degradation monitoring circuit, and the substrate degradation compensation circuit is connected in parallel with the substrate degradation monitoring circuit.

26. The chip degradation monitoring circuit according to claim 25, wherein, The gate oxide degradation compensation circuit includes: a third MOS transistor, a fourth MOS transistor, and a first switch, and the third MOS transistor and the fourth MOS transistor are used as redundant compensation devices; The gate of the third MOS transistor and the gate of the fourth MOS transistor are connected to the first switch, the drain of the third MOS transistor is connected to the source of the fourth MOS transistor, and the source of the third MOS transistor is connected to the drain of the fourth MOS transistor and grounded; One end of the first switch is connected to the normal working circuit of the chip, and the other end of the first switch is connected to the redundant compensation control signal.

27. The chip degradation monitoring circuit according to claim 25, wherein The substrate degradation compensation circuit includes: a fifth MOS transistor, a sixth MOS transistor, a second switch, and a third switch, and the fifth MOS transistor and the sixth MOS transistor are used as redundant compensation devices; The gate of the fifth MOS transistor is connected to the common terminal through the second switch, the gate of the sixth MOS transistor is connected to the common terminal through the third switch, and the common terminal is connected to the normal working circuit of the chip; The source electrode of the fifth MOS transistor and the source electrode of the sixth MOS transistor are connected to the power supply terminal of the chip, and the common terminal where the drain electrode of the fifth MOS transistor is connected to the drain electrode of the sixth MOS transistor is connected to the normal working circuit of the chip; The common terminal where the third switch is connected to the second switch is connected to the redundant compensation control signal.

28. A power chip, characterized in that, It includes the chip degradation monitoring circuit described in any one of claims 8-27.

29. An isolation driving chip, characterized in that, It includes the chip degradation monitoring circuit described in any one of claims 8-27.

Images