Method for detecting integrity of full-link simulation signal of backboard combined with daughter board and bottom board

Abstract

The invention relates to the technical field of signal integrity detection, in particular to a backboard and daughter board and bottom board combined full-link simulation signal integrity detection method, which comprises the following steps of: connecting all circuit boards to obtain a connected circuit board; performing electrical performance evaluation on the connection circuit board by using a network analyzer; analyzing the topology of the connection circuit board, and confirming the worst condition of the connection circuit board; according to the method, high-speed channel modeling is carried out on a connection circuit board, and eye pattern simulation after cascading is carried out, signal detection can be carried out on a backboard and daughter board and bottom board all-link, the signal condition of each link is detected, meanwhile, the whole signal is analyzed through modeling, simulation signals are rapidly detected, and the detection efficiency is improved. Meanwhile, the IBIS model is used for analyzing signal sending and receiving, so that data are more accurate, efficiency is higher, and the problem that it cannot be determined that a circuit board can have complete operation signals when an existing backboard is combined with a daughter board and a bottom board to be delivered is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of signal integrity detection, and in particular to a method for detecting the full-link simulation signal integrity of a backplane combined with a daughterboard and baseboard. Background Art

[0002] With the rapid development of digital circuits, the transmission rate of signals continues to increase, the transmission frequency of signals continues to increase, and the transmission line delay of signals has an increasingly greater impact on the overall performance of digital circuits, gradually becoming a key factor in determining signal quality. Specifically, it mainly includes the reflection of the signal itself, crosstalk between signals, and the delay of signal transmission. Therefore, analog detection of signal link faults is particularly important.

[0003] The integrity of the full-link signal of the backplane combined with the daughterboard baseplane is the key to the operation of the circuit board. However, when the existing backplane combined with the daughterboard baseplane is delivered, it is impossible to ensure that the circuit board can have complete operating signals. Therefore, it is urgent to design a full-link simulation signal integrity detection method for the backplane combined with the daughterboard baseplane. Summary of the invention

[0004] The purpose of the present invention is to provide a full-link simulation signal integrity detection method for a backplane combined with a daughterboard baseboard, aiming to solve the problem that when the existing backplane combined with a daughterboard baseboard is delivered, it is impossible to determine whether the circuit board can have a complete operating signal.

[0005] To achieve the above object, the present invention provides a backplane combined with a daughterboard and a baseboard full-link simulation signal integrity detection method, comprising the following steps:

[0006] Connect all circuit boards to obtain a connected circuit board;

[0007] Using a network analyzer to evaluate the electrical performance of the connection circuit board;

[0008] Analyze the topology of the connection circuit board to determine the worst case of the connection circuit board;

[0009] High-speed channel modeling is performed on the connection circuit board, and eye diagram simulation after cascading is performed.

[0010] Among them, the circuit board includes a backplane, a motherboard, a daughterboard and a cross-board. The motherboard is connected to the daughterboard using a buckle board connector infinX. The motherboard, the daughterboard and the cross-board are all connected to the backplane through a backplane connector GF3A and GF3B.

[0011] The specific method in which the network analyzer evaluates the electrical performance of the connection circuit board is as follows:

[0012] Perform open, short, and load calibration on the network analyzer, prepare test fixtures, measure performance parameters, analyze performance parameters, view amplitude and phase response, check the trend of electrical performance parameters over frequency, identify whether there are resonance points or abnormal behavior, convert electrical performance parameters to impedance form using Smith chart and display on Smith chart, save raw data, and generate electrical performance reports.

[0013] The topological analysis of the connection circuit board is performed to determine the worst case of the connection circuit board:

[0014] Identify the network that needs to be analyzed, determine the clock line and data line in the network, analyze the routing length, width and stacking structure of the network, create an electrical model of the connector through simulation software, and determine the dielectric constant and conductor resistivity, set the driver model and receiver model, configure boundary conditions, set the simulation frequency range or time domain window, run electrical performance parameter extraction, time domain reflection and eye diagram analysis, analyze electrical performance indicators, identify the location with the worst signal quality, and determine which factors will lead to the worst results through sensitivity analysis of different parameters, and then analyze the factors.

[0015] The specific method of performing high-speed channel modeling on the connection circuit board and performing eye diagram simulation after cascading is as follows:

[0016] Use the IBIS model to describe the behavior of the transmitter and the characteristics of the receiver. According to the established electrical model, cascade all the blocks in the order of connection in the actual circuit to ensure that the coupling relationship between the components is correctly reflected in the model. Select the simulation tool for simulation, set the corresponding data rate and waveform as the excitation signal, and set the simulation frequency range and time step. Obtain the signal waveform through time domain reflection or time domain transmission analysis. Based on the time domain waveform, superimpose the waveforms of several bit periods to form an eye diagram, and observe the eye opening size, degree of closure, and whether there is obvious inter-symbol interference.

[0017] The backplane combined with daughter board bottom plate full-link simulation signal integrity detection method of the present invention connects all circuit boards to obtain a connected circuit board; uses a network analyzer to evaluate the electrical performance of the connected circuit board; performs topological analysis on the connected circuit board to confirm the worst case of the connected circuit board; performs high-speed channel modeling on the connected circuit board, and performs eye diagram simulation after cascading. The method can detect signals in the full link of the backplane combined with daughter board bottom plate, detect the signal status of each link, and analyze the overall signal through modeling to achieve rapid detection of simulated signals. At the same time, the IBIS model is used to analyze signal sending and receiving, so that the data is more accurate and the efficiency is higher, which solves the problem that the existing backplane combined with daughter board bottom plate cannot determine whether the circuit board can have a complete operating signal when it is delivered. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0019] Figure 1 It is a flow chart of the full-link simulation signal integrity detection method of the backplane combined with the daughterboard and baseboard provided by the present invention.

[0020] Figure 2 It is a schematic diagram of the connection structure of the backplane and the sub-board bottom plate of the present invention.

[0021] Figure 3 This is a signal connection diagram of the backplane and daughterboard bottom plate of the present invention.

[0022] Figure 4 This is a diagram of the insertion loss results of the infinX sub-plate connector of the present invention.

[0023] Figure 5 It is a diagram of the crosstalk results of the infinX sub-board connector of the present invention.

[0024] Figure 6 This is a diagram showing the insertion loss results of the backplane connector GF3A and GF3B of the present invention.

[0025] Figure 7 This is a graph showing the return loss results of the backplane connector GF3A and GF3B of the present invention.

[0026] Figure 8 This is a diagram showing the crosstalk results of the backplane connector GF3A and GF3B of the present invention.

[0027] Fig. 9 This is a diagram showing the result of link topology segmentation modeling in the present invention.

[0028] Fig.10 It is a signal strength diagram of the link modeled by topology segmentation in the present invention. DETAILED DESCRIPTION

[0029] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and should not be construed as limiting the present invention.

[0030] See also Figures 1 to 10The present invention provides a method for detecting the integrity of a full-link simulation signal of a backplane combined with a daughterboard and a baseboard, comprising the following steps:

[0031] S1 connects all circuit boards to obtain a connected circuit board;

[0032] In the embodiment of the present invention, Figure 2-3 As shown, the circuit board includes a backplane, a motherboard, a daughterboard and a cross-board. The motherboard is connected to the daughterboard using the infinX buckle connector. The motherboard, the daughterboard and the cross-board are all connected to the backplane through the backplane connectors GF3A and GF3B. The longest link is the signal through three pairs of connectors + backplane.

[0033] S2 uses a network analyzer to evaluate the electrical performance of the connection circuit board;

[0034] In an embodiment of the present invention, the performance evaluation includes electrical performance evaluation, mechanical performance evaluation, environmental adaptability performance evaluation, electromagnetic compatibility performance evaluation, and thermal management performance evaluation. The electrical performance evaluation includes insertion loss, return loss, crosstalk, and differential impedance, which are measured using a network analyzer. The specific process is: a vector network analyzer that can cover the corresponding frequency band, before starting the measurement, the network analyzer is calibrated for open circuit, short circuit, and load to eliminate system errors, prepare a test fixture, and the test fixture has the performance of no additional loss or reflection, measure performance parameters, analyze performance parameters, view amplitude and phase response, check the trend graph of electrical performance parameters changing with frequency, identify whether there is a resonance point or abnormal behavior, and use the Smith chart to convert electrical performance parameters into impedance form and display them on the Smith chart, so that the impedance characteristics of the connector can be intuitively understood, the original data can be saved, and an electrical performance report can be generated.

[0035] according to Figure 4-5 It can be seen that the infinX sub-board connector meets the requirements of 12.5G signal transmission with a large margin. Figure 6-8 It can be seen that the backplane connector GF3A combined with GF3B meets the requirements of 12.5G signal transmission with a large margin.

[0036] S3 performs topological analysis on the connection circuit board to determine the worst case of the connection circuit board;

[0037] In the embodiment of the present invention, Figure 2-3As shown, determine the network that needs to be analyzed, determine the clock line and data line in the network, analyze the routing length, width, and stacking structure of the network, create an electrical model of the connector through simulation software, and determine the dielectric constant and conductor resistivity, set the driver model and receiver model, configure boundary conditions, set the simulation frequency range or time domain window, run electrical performance parameter extraction, time domain reflection and eye diagram analysis, analyze electrical performance indicators, identify the location with the worst signal quality, and determine which factors will lead to the worst results through sensitivity analysis of different parameters, and then analyze the factors.

[0038] S4 performs high-speed channel modeling on the connection circuit board and performs eye diagram simulation after cascading.

[0039] In an embodiment of the present invention, an IBIS model is used to describe the behavior of the transmitter and the characteristics of the receiver. According to the established electrical model, all the blocks are cascaded in the order of connection in the actual circuit to ensure that the coupling relationship between the components is correctly reflected in the model. A simulation tool is selected for simulation, and the corresponding data rate and waveform are set as the excitation signal. The frequency range and time step of the simulation are set. The signal waveform is obtained through time domain reflection or time domain transmission analysis. Based on the time domain waveform, the waveforms of several bit periods are superimposed to form an eye diagram. The eye diagram can intuitively display the signal quality, including the factors of amplitude, jitter, and noise, and observe the size of the eye opening, the degree of closure, and whether there is obvious inter-symbol interference.

[0040] like Figure 9-10 As shown in the figure, after the link is modeled by topology segmentation, the performance of the cascaded full link is as follows: It meets the ILKN protocol. Active eye diagram simulation: From M21036 to CTC7132, the receiving end is adaptive and the margin is sufficient. The high-speed design of the daughterboard, backplane, and cross disk meets the 12.5G transmission requirements. The passive performance of the longest link meets the ILKN protocol requirements, and the active simulation shows that the eye diagram margin is sufficient and meets the requirements. The whole equipment design meets the 12.5G requirements.

[0041] What is disclosed above is only a preferred embodiment of the backplane combined with daughterboard bottom board full-link simulation signal integrity detection method of the present invention. Of course, this cannot be used to limit the scope of rights of the present invention. Ordinary technicians in this field can understand that all or part of the processes of the above embodiments are implemented, and equivalent changes made according to the claims of the present invention still fall within the scope covered by the invention.

Claims

1. A method for detecting the full-link simulation signal integrity of a backplane and a daughterboard and a baseboard, characterized in that: The following steps are involved: Connect all circuit boards to obtain a connected circuit board; Using a network analyzer to evaluate the electrical performance of the connection circuit board; Analyze the topology of the connection circuit board to determine the worst case of the connection circuit board; High-speed channel modeling is performed on the connection circuit board, and eye diagram simulation after cascading is performed.

2. The backplane combined with the daughterboard bottom board full link simulation signal integrity detection method as described in claim 1 is characterized in that ； The circuit board includes a backplane, a motherboard, a daughterboard and a cross-board. The motherboard is connected to the daughterboard using a buckle board connector infinX. The motherboard, the daughterboard and the cross-board are all connected to the backplane through a backplane connector GF3A and GF3B.

3. The backplane combined with the daughterboard bottom board full link simulation signal integrity detection method as claimed in claim 1, characterized in that; The specific method of the network analyzer to evaluate the electrical performance of the connection circuit board is as follows: Perform open, short, and load calibration on the network analyzer, prepare test fixtures, measure performance parameters, analyze performance parameters, view amplitude and phase response, check the trend of electrical performance parameters over frequency, identify whether there are resonance points or abnormal behavior, convert electrical performance parameters to impedance form using Smith chart and display on Smith chart, save raw data, and generate electrical performance reports.

4. The backplane combined with the daughterboard bottom board full link simulation signal integrity detection method as claimed in claim 1, characterized in that; The topological analysis of the connection circuit board determines the specific manner of the worst case of the connection circuit board: Identify the network that needs to be analyzed, determine the clock line and data line in the network, analyze the routing length, width and stacking structure of the network, create an electrical model of the connector through simulation software, and determine the dielectric constant and conductor resistivity, set the driver model and receiver model, configure boundary conditions, set the simulation frequency range or time domain window, run electrical performance parameter extraction, time domain reflection and eye diagram analysis, analyze electrical performance indicators, identify the location with the worst signal quality, and determine which factors will lead to the worst results through sensitivity analysis of different parameters, and then analyze the factors.

5. The backplane combined with the daughterboard bottom board full link simulation signal integrity detection method as claimed in claim 1, characterized in that; The specific method of performing high-speed channel modeling on the connection circuit board and performing eye diagram simulation after cascading is: Use the IBIS model to describe the behavior of the transmitter and the characteristics of the receiver. According to the established electrical model, cascade all the blocks in the order of connection in the actual circuit to ensure that the coupling relationship between the components is correctly reflected in the model. Select the simulation tool for simulation, set the corresponding data rate and waveform as the excitation signal, and set the simulation frequency range and time step. Obtain the signal waveform through time domain reflection or time domain transmission analysis. Based on the time domain waveform, superimpose the waveforms of several bit periods to form an eye diagram, and observe the eye opening size, degree of closure, and whether there is obvious inter-symbol interference.

Images