SOC + FPGA-based flight control, any control and timing system three-in-one system and method for unmanned aerial vehicle

Abstract

The invention relates to an SOC + FPGA-based flight control, any control and timing system three-in-one system and method for an unmanned aerial vehicle. The system comprises an SOC unit, an FPGA unit, a timing system unit and a power management unit, according to the invention, three functions of flight control, task control and high-precision time service of the unmanned aerial vehicle can be realized at the same time.

Description

Technical Field

[0001] The present invention belongs to the technical field of unmanned aerial vehicles, and relates to a three-in-one system and method for unmanned aerial vehicle flight control, mission control, and time integration, and in particular to a three-in-one system and method for unmanned aerial vehicle flight control, mission control, and time integration based on SOC+FPGA. Background Art

[0002] The flight control system (FC) is the core component of the UAV. The quality of the FC largely determines the performance of the UAV. Currently, open source FCs (such as APM) are widely used in fixed-wing, multi-rotor, helicopter and other UAVs due to their low cost and rich functions. This type of FC has the following functional limitations: first, it does not have advanced applications such as networking, formation, and target recognition, and often relies on an external independent mission control module; second, the time synchronization accuracy with the UAV payload is low or not synchronized, which affects the efficiency of mission execution.

[0003] At present, among the existing drone products on the market, flight control, mission control, and time synchronization are all independent module products, and communication is completed through external cables. The disadvantages of this type of design are: first, it increases the take-off weight of the drone, affecting the flight endurance; second, multiple modules occupy a large volume, affecting the deployment of other drone payloads; third, there are many external connection solder points, low integration, and reduced product reliability.

[0004] Therefore, in order to solve the above problems, the present invention proposes a three-in-one system and method for UAV flight control, mission control and time integration based on SOC+FPGA.

[0005] After searching, no public documents of the prior art identical or similar to the present invention were found. Summary of the invention

[0006] The purpose of the present invention is to overcome the shortcomings of the prior art and propose a three-in-one system and method for UAV flight control, mission control and time synchronization based on SOC+FPGA, which can simultaneously realize three functions of UAV flight control, mission control and high-precision timing.

[0007] The present invention solves the practical problem by adopting the following technical solutions:

[0008] A three-in-one system of UAV flight control, mission control and time control based on SOC+FPGA, including: SOC unit, FPGA unit, time control unit and power management unit;

[0009] Among them, the SOC unit is a domestic SOC chip with video encoding and decoding and AI functions. The SOC unit is connected to the FPGA unit. The FPGA unit provides the SOC unit with system clock and time information. The SOC unit controls the time calibration through the PCIE bus;

[0010] The FPGA unit is a domestic FPGA that can implement the Microblaze soft core. It is used to collect data from the external gyroscope and receive time information from the time system unit for time calibration of the SOC unit and external load.

[0011] The timing unit includes an RTK satellite timing circuit, a constant temperature crystal oscillator circuit and a taming circuit. The timing unit is connected to the FPGA unit to generate a standard 10MHz signal as the working reference clock of the FPGA.

[0012] The power management unit includes a SOC dedicated switch power chip, and the FPGA unit, the SOC unit and the timing unit share a set of power management circuits.

[0013] Moreover, the FPGA unit includes: a Microblaze soft core, a clock synchronization and frequency multiplication circuit, a PCIE hard core, and a COM forwarding circuit;

[0014] Among them, the Microblaze soft core is responsible for implementing flight control functions and running the RT-tread embedded system;

[0015] The clock synchronization and frequency multiplication circuit, together with the time synchronization unit, is responsible for realizing the time synchronization function. The circuit outputs the synchronized system time to the SOC unit, Microblaze soft core and external payload to ensure that the working clocks of the UAV flight control, mission control and payload are the same source;

[0016] The PCIE hard core is responsible for realizing the high-speed data exchange channel between the SOC unit and Microblaze. The PCIE hard core is configured in EP mode, that is, the flight control unit acts as a PCIE slave device of the SOC unit;

[0017] The COM forwarding circuit is implemented through FPGA logic instantiation and is used to transmit second pulses and time information to the SOC and external loads. It can also be used as an auxiliary communication interface between the flight control and the mission control.

[0018] Moreover, the SOC unit includes: a SOC controller and its peripheral circuits, and the peripheral circuits include: DDR, SPIflash, XTAL / RTC, PCIE and COM interfaces; the SOC unit realizes the control function, communicates with the external load through its own integrated network, serial port, video interface, etc., and interacts with the flight control through PCIE and COM ports.

[0019] Among them, XTAL / RTC is the clock circuit of the SOC unit, which is implemented through the crystal oscillator design; the XTAL / RTC is implemented by the FPGA clock synchronization and frequency multiplication circuit to ensure that the flight control and mission control clocks are of the same source; at the same time, the PCIE reference clock is also implemented by the FPGA clock synchronization and frequency multiplication circuit, with a frequency of 100Mhz; the COM port can be configured with a level interface according to requirements, supports RS232 / 422 / 485 configurable, and the maximum baud rate is 2Mbps.

[0020] Moreover, the power management unit includes a set of power management chip circuits PMIC and switching power supply circuits that are compatible with the SOC unit; the power management unit adopts a two-level voltage conditioning method and supports wide voltage input. The input voltage is first regulated to 4V through a first-level switching power supply circuit, and then the 4V voltage is output through the PMIC to the small voltage required by the SOC unit and its peripheral system; and then the working voltage required by the FPGA is regulated through an independent switching power supply circuit.

[0021] Moreover, the timing unit comprises three parts: a 10Mhz constant temperature crystal oscillator, a voltage control circuit and an RTK timing circuit;

[0022] Among them, the 10Mhz constant temperature crystal oscillator provides the working clock of the FPGA circuit. The 10Mhz constant temperature crystal oscillator can generate local second pulses after frequency division to synchronize the standard reference time;

[0023] The voltage control circuit includes: a DA converter, which is responsible for converting the digital signal output by the FPGA into an analog signal, which is used to tame and adjust the frequency deviation of the constant temperature crystal oscillator;

[0024] The RTK timing circuit is a GNSS timing component that outputs navigation and time information by receiving satellite system signals and is the time reference of this system. The RTK outputs second pulse PPS and time information to the FPGA unit to provide a reference for its clock synchronization and frequency multiplication circuits.

[0025] An application method of a flight control, mission control, and time synchronization three-in-one system based on SOC+FPGA, comprising the following steps:

[0026] Step 1: After the system is powered on, the SOC unit waits for the FPGA unit to output the system clock, runs the bootloader and loads the system image; after the operating system runs normally, it periodically receives PPS interrupts and reads the time information sent by the FPGA for local time synchronization; at the same time, it periodically sends heartbeat messages to the FPGA through the COM port, and notifies the FPGA through the PCIE interrupt when a control instruction needs to be sent;

[0027] Step 2: After the system is powered on, the FPGA unit simultaneously loads the Microblaze soft core, clock synchronization and frequency multiplication circuit, PCIE hard core, and COM forwarding circuit. After loading is completed, each circuit works in parallel according to the designed process.

[0028] Moreover, the working process of the clock synchronization and frequency multiplication circuit in step 2 is:

[0029] For the clock synchronization and frequency multiplication circuit, after detecting the 10Mhz clock provided by the constant temperature crystal oscillator, the clock required for the SOC, payload and Microblaze soft core is output through the PLL phase-locked loop method; then the working status of the RTK receiver is monitored in real time. After determining that the RTK is normal, the RTK time is compared with the local time. If they are inconsistent, the time calibration is performed; at the same time, the PPS second pulse is sent by RTK and compared with the 10Mmz clock. If the error exceeds 10 microseconds, the constant temperature crystal oscillator voltage is adjusted through the DA controller to achieve the effect of adjusting the frequency.

[0030] Moreover, the working process of the Microblaze soft core in step 2 is:

[0031] For the Microblze soft core, the domestic RT-thread system is run after initialization, and the main flight control tasks are all integrated in the loop function. In the loop, the heartbeat message is periodically sent to the Soc through the COM port, and the PCIE interface is monitored in real time to see if an interrupt occurs. If so, it indicates that the control message sent by the SOC has been received, and the message is parsed and the corresponding action is performed after entering the interrupt response function; if no interrupt occurs, it continues to run in the loop function, monitors the IMU, and completes the attitude solution and other functions.

[0032] Moreover, the clock synchronization and frequency multiplication circuit is implemented by the state machine in the FPGA, which judges the RTK output status and monitors the valid identification of its time message to identify whether the RTK time information is valid, thereby calibrating with the local time; the Microblze soft core is implemented by the HLS code in the FPGA to complete the RT-thread and message communication.

[0033] Advantages and beneficial effects of the present invention:

[0034] The present invention proposes a flight control, mission control, and time synchronization three-in-one system based on SOC+FPGA, which can simultaneously realize three functions of UAV flight control, mission control, and high-precision timing. At the same time, in view of specific application conditions such as homologous clock output, time calibration, and execution of mission control messages, the present invention proposes an application method of the flight control, mission control, and time synchronization three-in-one system based on SOC+FPGA. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 It is a system composition diagram of the present invention;

[0036] Figure 2 is a process flow chart of the present invention;

[0037] Figure 3 This is a typical exploded view of the whole machine of the present invention;

[0038] Figure 4 It is a schematic diagram of the three-layer structure of the printing plate assembly of the present invention. DETAILED DESCRIPTION

[0039] The embodiments of the present invention are further described in detail below with reference to the accompanying drawings:

[0040] A three-in-one system of UAV flight control, mission control and time synchronization based on SOC+FPGA, such as Figure 1 As shown, it includes: SOC unit, FPGA unit, timing unit and power management unit;

[0041] Among them, the SOC unit is a domestic SOC chip with video encoding and decoding and AI functions. The SOC unit is connected to the FPGA unit. The FPGA unit provides the SOC unit with system clock and time information. The SOC unit controls the time calibration through the PCIE bus;

[0042] The FPGA unit is a domestic FPGA that can implement the Microblaze soft core. It is used to collect data from the external gyroscope and receive time information from the time system unit for time calibration of the SOC unit and external load.

[0043] The timing unit includes an RTK satellite timing circuit, a constant temperature crystal oscillator circuit and a taming circuit. The timing unit is connected to the FPGA unit to generate a standard 10MHz signal as the working reference clock of the FPGA.

[0044] The power management unit includes a SOC dedicated switch power chip, and the FPGA unit, the SOC unit and the timing unit share a set of power management circuits.

[0045] In this embodiment, the power management unit includes a power management chip circuit PMIC and a switching power supply circuit that are compatible with the SOC unit; the power management unit adopts a two-level voltage conditioning method and supports wide voltage input. The input voltage is first regulated to 4V through a first-level switching power supply circuit, and then the 4V voltage is output through the PMIC to the small voltage required by the SOC unit and its peripheral system; and then the working voltage required by the FPGA is regulated through an independent switching power supply circuit.

[0046] In this embodiment, the timing unit includes three parts: a 10Mhz constant temperature crystal oscillator, a voltage control circuit and an RTK timing circuit;

[0047] Among them, the 10Mhz constant temperature crystal oscillator provides the working clock of the FPGA circuit. The 10Mhz constant temperature crystal oscillator can generate local second pulses after frequency division to synchronize the standard reference time;

[0048] The voltage control circuit includes: a DA converter, which is responsible for converting the digital signal output by the FPGA into an analog signal, which is used to tame and adjust the frequency deviation of the constant temperature crystal oscillator;

[0049] The RTK timing circuit is a GNSS timing component that outputs navigation and time information by receiving satellite system signals and is the time reference of this system. The RTK outputs second pulse PPS and time information to the FPGA unit to provide a reference for its clock synchronization and frequency multiplication circuits.

[0050] In this embodiment, the FPGA unit includes: a Microblaze soft core, a clock synchronization and frequency multiplication circuit, a PCIE hard core, and a COM forwarding circuit;

[0051] Among them, the Microblaze soft core is responsible for implementing flight control functions and running the RT-tread embedded system;

[0052] The clock synchronization and frequency multiplication circuit, together with the time synchronization unit, is responsible for realizing the time synchronization function. The circuit outputs the synchronized system time to the SOC unit, Microblaze soft core and external payload to ensure that the working clocks of the UAV flight control, mission control and payload are the same source;

[0053] The PCIE hard core is responsible for realizing the high-speed data exchange channel between the SOC unit and Microblaze. The PCIE hard core is configured in EP mode, that is, the flight control unit acts as a PCIE slave device of the SOC unit;

[0054] The COM forwarding circuit is implemented through FPGA logic instantiation and is used to transmit second pulses and time information to the SOC and external loads. It can also be used as an auxiliary communication interface between the flight control and the mission control.

[0055] In this embodiment, the SOC unit includes: a SOC controller and its peripheral circuits, and the peripheral circuits include: DDR, SPI flash, XTAL / RTC, PCIE and COM interface; the SOC unit implements the control function, communicates with the external load through its own integrated network, serial port, video interface, etc., and interacts with the flight control through PCIE and COM ports.

[0056] Among them, XTAL / RTC is the clock circuit of the SOC unit, which is implemented through the crystal oscillator design; the XTAL / RTC is implemented by the FPGA clock synchronization and frequency multiplication circuit to ensure that the flight control and mission control clocks are of the same source; at the same time, the PCIE reference clock is also implemented by the FPGA clock synchronization and frequency multiplication circuit, with a frequency of 100Mhz; the COM port can be configured with a level interface according to requirements, supports RS232 / 422 / 485 configurable, and the maximum baud rate is 2Mbps.

[0057] In this embodiment, the functions and effects of each component in the system are further described below:

[0058] According to the present invention, a flight control, mission control, and time synchronization three-in-one system based on SOC+FPGA is provided, comprising:

[0059] The FPGA unit is a domestic FPGA that can realize the Microblaze soft core, and its resources should be no less than Fudan Micro's JFMK50T2. The timing unit contains RTK satellite timing circuit, constant temperature crystal oscillator circuit and taming circuit to generate a standard 10MHz signal as the working reference clock of FPGA; the power management unit contains a dedicated switching power supply chip for SOC, and FPGA and SOC share a set of power management circuits, eliminating the heat dissipation problems caused by using independent power supply chips.

[0060] Power management unit: It includes a power management chip circuit (PMIC) and a switching power supply circuit that are compatible with the SOC. The power management unit uses a two-level voltage conditioning method to support wide voltage input (such as 6-50V). The input voltage is first regulated to 4V through a first-level switching power supply circuit, and then the 4V voltage is output through the PMIC to the small voltage required by the SOC and its peripheral systems (DDR, network), etc.; and then the operating voltage required by the FPGA is regulated through an independent switching power supply circuit, such as 3.3V, 1.8V, etc.

[0061] Timing unit: It includes 10Mhz constant temperature crystal oscillator, voltage control circuit and RTK timing circuit. The constant temperature crystal oscillator provides the working clock of the FPGA circuit, which can generate local second pulses after frequency division to synchronize the standard reference time; the voltage control circuit mainly includes a DA converter, which is responsible for converting the digital signal output by the FPGA into an analog signal, which is used to tame and adjust the frequency offset of the constant temperature crystal oscillator; the RTK timing circuit is a GNSS timing component, which outputs navigation and time information by receiving satellite system signals, and is the time base of this system; the RTK outputs second pulses PPS and time information to the FPGA unit, providing a base for its clock synchronization and frequency multiplication circuit.

[0062] FPGA unit: It includes Microblaze soft core, clock synchronization and frequency multiplication circuit, PCIE hard core, and COM forwarding circuit. Among them, Microblaze soft core is responsible for realizing flight control functions and running RT-tread embedded system; clock synchronization and frequency multiplication circuit, together with the previous time synchronization unit, is responsible for realizing time synchronization functions. This circuit outputs the synchronized system time to SOC unit, Microblaze soft core and external load, ensuring that the working clocks of UAV flight control, mission control and load are homologous, laying the foundation for high-precision time synchronization; PCIE hard core is responsible for realizing the high-speed data interaction channel between SOC and Microblaze, and PCIE hard core is configured as end point (EP) mode, that is, flight control is the PCIE slave device of SOC; COM forwarding circuit is realized through FPGA logic instantiation, which is used to transmit second pulses and time information to SOC and external load, and can also be used as an auxiliary communication interface between flight control and mission control.

[0063] SOC unit: includes SOC controller and its peripheral circuits, such as DDR, SPI flash, XTAL / RTC, PCIE and COM interface. Among them, XTAL / RTC is the clock circuit of SOC, which is generally implemented by crystal oscillator design; in this system, this circuit is implemented by FPGA clock synchronization and frequency multiplication circuit, ensuring the same source of flight control and mission control clocks; at the same time, PCIE reference clock is also implemented by FPGA clock synchronization and frequency multiplication circuit, with a frequency of 100Mhz; COM port can be configured with level interface according to requirements, supports RS232 / 422 / 485 configurable, and the maximum baud rate is 2Mbps. SOC unit is responsible for realizing mission control function, communicating with external loads through its own integrated network, serial port, video interface, etc., and interacting with flight control through PCIE and COM port.

[0064] An application method of a flight control, mission control, and time synchronization three-in-one system based on SOC+FPGA, such as Figure 2 As shown, the following steps are included:

[0065] Step 1: After the system is powered on, the SOC unit waits for the FPGA unit to output the system clock, runs the bootloader and loads the system image; after the operating system runs normally, it periodically receives PPS interrupts and reads the time information sent by the FPGA for local time synchronization; at the same time, it periodically sends heartbeat messages to the FPGA through the COM port, and notifies the FPGA through the PCIE interrupt when a control instruction needs to be sent;

[0066] Step 2: After the system is powered on, the FPGA unit simultaneously loads the Microblaze soft core, clock synchronization and frequency multiplication circuit, PCIE hard core, and COM forwarding circuit. After loading is completed, each circuit works in parallel according to the designed process.

[0067] The application method after the FPGA unit is powered on is divided into the following two steps.

[0068] In this embodiment, the working process of the clock synchronization and frequency multiplication circuit in step 2 is as follows:

[0069] For the clock synchronization and frequency multiplication circuit, after detecting the 10Mhz clock provided by the constant temperature crystal oscillator, the clock required for the SOC, payload and Microblaze soft core is output through the PLL phase-locked loop method; then the working status of the RTK receiver is monitored in real time. After determining that the RTK is normal, the RTK time is compared with the local time. If they are inconsistent, the time calibration is performed; at the same time, the PPS second pulse is sent by RTK and compared with the 10Mmz clock. If the error exceeds 10 microseconds, the constant temperature crystal oscillator voltage is adjusted through the DA controller to achieve the effect of adjusting the frequency.

[0070] In this embodiment, the working process of the Microblaze soft core in step 2 is:

[0071] For the Microblze soft core, the domestic RT-thread system is run after initialization, and the main flight control tasks are all integrated in the loop function. In the loop, the heartbeat message is periodically sent to the Soc through the COM port, and the PCIE interface is monitored in real time to see if an interrupt occurs. If so, it indicates that the control message sent by the SOC has been received, and the message is parsed and the corresponding action is performed after entering the interrupt response function; if no interrupt occurs, it continues to run in the loop function, monitors the IMU, and completes the attitude solution and other functions.

[0072] In this embodiment, the clock synchronization and frequency multiplication circuit is implemented by a state machine in the FPGA, which judges the RTK output status and monitors the valid identification of its time message to identify whether the RTK time information is valid, thereby calibrating it with the local time; the Microblze soft core is implemented by the HLS code in the FPGA, completes the RT-thread and message communication, and improves the integration of the flight control.

[0073] Typical whole machine explosion decomposition of the present invention is as follows Figure 3As shown. The dimensions of the UAV flight control, mission control, and time synchronization three-in-one system based on SOC+FPGA are 90×50×25mm (excluding external interfaces and installation angle pieces), and the weight is 200g. The structural parts of the equipment are made of magnesium alloy materials, so that the overall structure has high strength and lightweight performance. The equipment is mainly composed of an upper cover, a main frame, a printed circuit board assembly, a radio frequency interface, an airspeed interface, and a lower cover. The printed circuit board assembly is effectively connected to the flight control module housing through structural reinforcement, and the upper and lower covers are connected to the main frame by screws, so that each independent part is connected as an effectively connected whole, which strengthens the rigidity and strength of the overall structure and meets the performance requirements of the equipment under special environmental conditions.

[0074] like Figure 4 As shown in the figure, the circuit design of the device is a three-layer structure of "core board + baseboard + GNSS RTK board". Among them, the core board is a SOC unit, which is Rockchip RK3588 in this typical application, configured with 8GB LDDR4 and 64GB EMMC, and the size is 55X45mm.

[0075] Among them, the bottom board is the FPGA unit, timing unit and power management unit, which communicate with the outside through the J30J100PIN connector. For the antenna of the RTK board and the output 10MHZ clock, all use SMA RF interface, which is located just above the J30J connector; the FPGA uses Fudan Micro JFMK50T2, which has an internal integrated PROM, the size is 1X1mm, and has a PCIE hard core, which can realize all flight control functions; the constant temperature crystal oscillator is located in the middle of the bottom board, away from sensors such as IMU and pitot tube, to reduce the temperature drift caused by their temperature;

[0076] Among them, the RTK module adopts Shanghai Sinan's K827 board, which supports positioning, orientation and timing functions, and its dual antenna interface is brought out through the SMA RF interface.

[0077] The innovation of the present invention lies in:

[0078] (1) For the first time, we designed and implemented a three-in-one system for UAV flight control, mission control, and time synchronization based on SOC+FPGA, integrating the three essential functions of a UAV into one physical space, reducing the size and power consumption, and greatly improving the UAV's flight time and maximum payload weight;

[0079] (2) For the first time, a three-in-one system application method for UAV flight control, mission control, and time synchronization based on SOC+FPGA was proposed. A Microblze soft core was designed in the FPGA as the implementation carrier of the flight control function. At the same time, clock synchronization and frequency multiplication circuit logic were designed to cooperate with the time synchronization unit to complete the time synchronization function.

[0080] (3) The three-in-one system of UAV flight control, mission control and time synchronization all uses the same source clock, which comes from a 10MHz constant temperature crystal oscillator, ensuring the time synchronization accuracy of each unit in the system. At the same time, it can output a 10Mhz clock to the outside, which can be used for payload time synchronization;

[0081] (4) By designing the clock synchronization and frequency multiplication circuit logic in FPGA, the constant temperature crystal oscillator can be tamed according to the PPS output by RTK, thus ensuring the time accuracy of the system again;

[0082] (5) A PCIE hard core and COM port are designed in the FPGA, which can be used for communication between the flight control and the mission control, and can also be used as a PCIE slave device of the mission control to expand the interface, such as expanding multiple COM ports to facilitate communication with multiple payloads.

[0083] It should be emphasized that the embodiments of the present invention are illustrative rather than restrictive. Therefore, the present invention includes but is not limited to the embodiments described in the specific implementation modes. Any other implementation modes derived by those skilled in the art based on the technical solutions of the present invention also fall within the scope of protection of the present invention.

Claims

1. A three-in-one system of UAV flight control, mission control and time synchronization based on SOC+FPGA, characterized by: include: SOC unit, FPGA unit, timing unit and power management unit; Among them, the SOC unit is a domestic SOC chip with video encoding and decoding and AI functions. The SOC unit is connected to the FPGA unit. The FPGA unit provides the SOC unit with system clock and time information. The SOC unit controls the time calibration through the PCIE bus; The FPGA unit is a domestic FPGA that can implement the Microblaze soft core. It is used to collect data from the external gyroscope and receive time information from the time system unit for time calibration of the SOC unit and external load. The timing unit includes an RTK satellite timing circuit, a constant temperature crystal oscillator circuit and a taming circuit. The timing unit is connected to the FPGA unit to generate a standard 10MHz signal as the working reference clock of the FPGA. The power management unit includes a SOC dedicated switch power chip, and the FPGA unit, the SOC unit and the timing unit share a set of power management circuits.

2. The three-in-one system of UAV flight control, mission control and time integration based on SOC+FPGA according to claim 1, characterized in that: The FPGA unit includes: Microblaze soft core, clock synchronization and frequency multiplication circuit, PCIE hard core, COM forwarding circuit; Among them, the Microblaze soft core is responsible for implementing flight control functions and running the RT-tread embedded system; The clock synchronization and frequency multiplication circuit, together with the time synchronization unit, is responsible for realizing the time synchronization function. The circuit outputs the synchronized system time to the SOC unit, Microblaze soft core and external payload to ensure that the working clocks of the UAV flight control, mission control and payload are the same source; The PCIE hard core is responsible for realizing the high-speed data exchange channel between the SOC unit and Microblaze. The PCIE hard core is configured in EP mode, that is, the flight control unit acts as a PCIE slave device of the SOC unit; The COM forwarding circuit is implemented through FPGA logic instantiation and is used to transmit second pulses and time information to the SOC and external loads. It can also be used as an auxiliary communication interface between the flight control and the mission control.

3. The UAV flight control, mission control and time integration three-in-one system based on SOC+FPGA according to claim 1 is characterized by: The SOC unit includes: a SOC controller and its peripheral circuits, wherein the peripheral circuits include: DDR, SPIflash, XTAL / RTC, PCIE and COM interfaces; the SOC unit realizes the control function, communicates with the external load through its own integrated network, serial port, video interface, etc., and interacts with the flight control through PCIE and COM ports; Among them, XTAL / RTC is the clock circuit of the SOC unit, which is implemented through the crystal oscillator design; the XTAL / RTC is implemented by the FPGA clock synchronization and frequency multiplication circuit to ensure that the flight control and mission control clocks are of the same source; at the same time, the PCIE reference clock is also implemented by the FPGA clock synchronization and frequency multiplication circuit, with a frequency of 100Mhz; the COM port can be configured with a level interface according to requirements, supports RS232 / 422 / 485 configurable, and the maximum baud rate is 2Mbps.

4. The UAV flight control, mission control and time integration three-in-one system based on SOC+FPGA according to claim 1 is characterized by: The power management unit includes a set of power management chip circuits PMIC and switching power supply circuits that are compatible with the SOC unit; the power management unit adopts a two-level voltage conditioning method and supports wide voltage input. The input voltage is first regulated to 4V through a first-level switching power supply circuit, and then the 4V voltage is output through the PMIC to the small voltage required by the SOC unit and its peripheral system; and then the working voltage required by the FPGA is regulated through an independent switching power supply circuit.

5. The UAV flight control, mission control and time integration three-in-one system based on SOC+FPGA according to claim 1 is characterized by: The timing unit includes three parts: a 10Mhz constant temperature crystal oscillator, a voltage control circuit and an RTK timing circuit; Among them, the 10Mhz constant temperature crystal oscillator provides the working clock of the FPGA circuit. The 10Mhz constant temperature crystal oscillator can generate local second pulses after frequency division to synchronize the standard reference time; The voltage control circuit includes: a DA converter, which is responsible for converting the digital signal output by the FPGA into an analog signal, which is used to tame and adjust the frequency deviation of the constant temperature crystal oscillator; The RTK timing circuit is a GNSS timing component that outputs navigation and time information by receiving satellite system signals and is the time reference of this system. The RTK outputs second pulse PPS and time information to the FPGA unit to provide a reference for its clock synchronization and frequency multiplication circuits.

6. An application method of a flight control, mission control, and time synchronization three-in-one system based on SOC+FPGA, characterized in that: The following steps are involved: Step 1: After the system is powered on, the SOC unit waits for the FPGA unit to output the system clock, then runs the bootloader and loads the system image; After the operating system runs normally, it periodically receives PPS interrupts and reads the time information sent by FPGA for local time synchronization. At the same time, it periodically sends heartbeat messages to FPGA through the COM port. When control instructions need to be sent, it notifies FPGA through PCIE interrupts. Step 2: After the system is powered on, the FPGA unit simultaneously loads the Microblaze soft core, clock synchronization and frequency multiplication circuit, PCIE hard core, and COM forwarding circuit. After loading is completed, each circuit works in parallel according to the designed process.

7. The application method of the flight control, mission control and time synchronization three-in-one system based on SOC+FPGA according to claim 6, characterized in that: The working process of the clock synchronization and frequency multiplication circuit in step 2 is as follows: For the clock synchronization and frequency multiplication circuit, after detecting the 10Mhz clock provided by the constant temperature crystal oscillator, the clock required for the SOC, payload and Microblaze soft core is output through the PLL phase-locked loop method; then the working status of the RTK receiver is monitored in real time. After determining that the RTK is normal, the RTK time is compared with the local time. If they are inconsistent, the time calibration is performed; at the same time, the PPS second pulse is sent by RTK and compared with the 10Mmz clock. If the error exceeds 10 microseconds, the constant temperature crystal oscillator voltage is adjusted through the DA controller to achieve the effect of adjusting the frequency.

8. The application method of the flight control, mission control and time synchronization three-in-one system based on SOC+FPGA according to claim 6, characterized in that: The working process of the Microblaze soft core in step 2 is as follows: For the Microblze soft core, the domestic RT-thread system is run after initialization, and the main flight control tasks are all integrated in the loop function; in the loop, heartbeat messages are periodically sent to the Soc through the COM port, and the PCIE interface is monitored in real time to see if an interrupt occurs. If so, it indicates that the control message sent by the SOC has been received, and the message is parsed and the corresponding action is performed after entering the interrupt response function; if no interrupt occurs, it continues to run in the loop function, monitors the IMU, and completes functions such as attitude solution.

9. The application method of the flight control, mission control and time synchronization three-in-one system based on SOC+FPGA according to claim 6, characterized in that: The clock synchronization and frequency multiplication circuit is implemented by the state machine in the FPGA, which judges the RTK output status and monitors the valid identification of its time message to identify whether the RTK time information is valid, thereby calibrating with the local time; the Microblze soft core is implemented by the HLS code in the FPGA to complete the RT-thread and message communication.

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