Signal transmission equipment, server mainboard and server signal transmission system

Abstract

The embodiment of the invention provides a signal transmission device, a server mainboard and a server signal transmission system.The device comprises a first processor and a second processor; the first processor is used for generating target state information according to the first signal acquired by the first signal pin; the second processor is used for determining a third signal pin corresponding to a target information type to which the target state information belongs in the plurality of second signal pins; and sending an indication signal corresponding to the operation state indicated by the target state information to data center safety control equipment through a third signal pin. According to the invention, the problem of low signal transmission efficiency between the host processor and the data center safety control equipment is solved, and the effect of improving the signal transmission efficiency between the host processor and the data center safety control equipment is achieved.

Description

Technical Field

[0001] The embodiments of the present application relate to the computer field, and in particular, to a signal transmission device, a server motherboard, and a server signal transmission system. Background Art

[0002] With the rise of fields such as big data and AI (Artificial Intelligence), the market demand for servers with high computing performance is increasing. The scale of data centers is also increasing. At the same time, the call for standardization of data center management is also increasing. Therefore, using standardized module design to be compatible with the security management requirements of different platforms, reduce the duplication of R&D resources, and speed up product iteration has become an important development trend for data centers to change and upgrade continuously. The DC-SCM (Data Center-ready Secure Control Module) project came from this. By configuring the DC-SCM circuit board, common management, security and control functions can be separated from the mainboard and transferred to a smaller DC-SCM circuit board, which is connected to the mainboard through the DC-SCM circuit board connector. The DC-SCM circuit board can contain all the firmware states previously contained on the mainboard (BMC (Baseboard Management Controller), TPM (Trusted Platform Module), Boot Flash, ROT (Root Of Trust), etc.). At the moment of promoting modular design, DC-SCM is facing incompatibility with traditional design, which brings great challenges to the smooth upgrade of software and hardware design. In traditional design, the devices that realize management, security and control functions have sufficient GPIO (General Purpose Input Output) resources on the motherboard. In hardware design, the status is usually directly connected to the devices with management, security and control functions on the motherboard through GPIO. Therefore, the devices deployed on the motherboard can directly read the GPIO status to determine the current hardware status. The status of the motherboard is directly transmitted to these devices through GPIO, so the current motherboard status can be obtained safely and reliably. After adopting the DC-SCM design, due to the limitation of the number of DC-SCM pins, the devices with management, security and control functions cannot allocate too many pin resources on the DC-SCM circuit board, so that the device cannot meet the needs of the device to obtain the motherboard status information, resulting in the failure of normal transmission of some device signals. Summary of the invention

[0003] The embodiments of the present application provide a signal transmission device, a server mainboard and a server signal transmission system to at least solve the problem of low signal transmission efficiency between a host processor and a data center security control device in the related art.

[0004] According to an embodiment of the present application, a signal transmission device is provided, including:

[0005] A first processor and a second processor, the first processor is configured with a plurality of first signal pins and a first transmission port, the second processor is configured with a plurality of second signal pins and a second transmission port, the server comprises: an external socket for a host processor and a data center security control device, a plurality of the first signal pins are used to be connected to the signal pins of the host processor in a one-to-one correspondence, the first transmission port is used to be connected to a target pin of the external socket, the second transmission port is used to be connected to a signal pin corresponding to the target pin on the external socket, and a plurality of the second signal pins are used to be connected to the signal pins of the data center security control device in a one-to-one correspondence;

[0006] The first processor is configured to generate target state information according to the first signal collected by the first signal pin, wherein the target state information is used to indicate the current operating state of the host processor; and transmit the target state information to the second processor through the first transmission port;

[0007] The second processor is used to determine a third signal pin corresponding to the target information type to which the target status information belongs among multiple second signal pins; and send an indication signal corresponding to the operating status indicated by the target status information to the data center security control device through the third signal pin.

[0008] Optionally, the first processor is further used to: detect level change information of each of the first signal pins among the multiple first signal pins; when the level change information is used to indicate that the level value of a fourth signal pin among the multiple first signal pins has changed, detect the current first level value on the fourth signal pin, wherein the first signal includes the first level value; obtain the first pin identifier of the fourth signal pin among the multiple first signal pins; generate a first status message according to the first pin identifier and the first level value, wherein the first status message is used to indicate the level output state of the host processor on the fourth signal pin, and the target status information includes the first status message.

[0009] Optionally, the first processor is further used to: add the first pin identifier to the first field position in the initial status message corresponding to the host processor to obtain a second status message, wherein the first field position is the field position in the initial status message for storing the pin identifier of the pin that has undergone a level change; add the first level value to the second field position in the second status message to obtain a third status message, wherein the second field position is the field position in the second status message for storing the level value of the pin after a level change occurs; add a state change field to the message header position of the third status message to obtain the first status message, wherein the state change field is used to indicate that a level change has occurred on the signal pin of the host processor.

[0010] Optionally, the second processor is further used to: detect a field carried in a message header of an initial message received in the second transmission port; and when the field carried in the message header is a state change field, determine the initial message as a first state message sent by the host processor, wherein the target state information includes the first state message, the state change field is used to indicate that a level change has occurred on a signal pin of the host processor, and the first state message carries information on a level value on a signal pin indicating a level change among a plurality of the first signal pins.

[0011] Optionally, the second processor is further used to extract the first pin identifier carried by the first status message from the first field position in the first status message, and to extract the first level value carried by the first status message from the second field position in the first status message, wherein the first status message carries information for indicating the level value on a signal pin whose level value changes among multiple first signal pins, and the target status information includes the first status message, the first pin identifier is used to indicate the signal pin whose level value changes among multiple first signal pins, and the first level value is the current level value of the signal pin whose level value changes among multiple first signal pins; determine the target information type of the information transmitted on the first signal pin indicated by the first pin identifier; determine the third signal pin corresponding to the target information type from the information type and multiple second signal pins having a corresponding relationship; and control the third signal pin to output the indication signal corresponding to the first level value.

[0012] Optionally, the first processor is configured with a third transmission port, the second processor is configured with a fourth transmission port, the third transmission port is used to connect to a reference pin of the external socket, and the fourth transmission port is used to connect to a signal pin corresponding to the reference pin on the external socket;

[0013] The second processor is used to generate target control information according to the second signals collected from the plurality of second signal pins, wherein the second signal is a signal output by the data center security control device for controlling the operating state of the host processor, and the target control information is used to characterize the operating state of the host processor to be converted; and transmit the target control information to the first processor through the second transmission port;

[0014] The first processor is used to determine a fifth signal pin corresponding to the target state type controlled by the target control information from the multiple first signal pins; and send a state control instruction corresponding to the operating state indicated by the target control information to the host processor through the fifth signal pin.

[0015] Optionally, the second processor is further used to locate a sixth signal pin that collects the second signal from multiple second signal pins; add the second pin identifier of the sixth signal pin to the third field position of the reference status message corresponding to the data center security control device, and add the second level value of the second signal to the fourth field position of the reference status message to obtain a fourth status message, wherein the third field position is the field position in the reference status message for storing the pin identifier of the pin that generates the signal, and the fourth field position is the field position in the reference status message for storing the pin level value; add an identification field to the message header position of the fourth status message to obtain a fifth status message, wherein the identification field is used to indicate that the data center security control device has issued a control instruction to the host processor, and the target control information includes the fifth status message.

[0016] Optionally, the first processor is further used to extract the second pin identifier carried in the fifth status message and the second level value of the second signal from the fifth status message, wherein the target control information includes the fifth status message, and the second pin identifier is used to indicate the pin at which the second signal is detected among multiple second signal pins; determine the fifth signal pin corresponding to the target status type from the status types and multiple first signal pins having a corresponding relationship; and control the fifth signal pin to output the status control instruction corresponding to the second level value.

[0017] According to another embodiment of the present application, a server mainboard is provided, including:

[0018] The server motherboard is provided with: a signal transmission device, a host processor, and an external socket of a data center security control device, the signal transmission device includes a first processor and a second processor, the first processor is provided with a plurality of first signal pins and a first transmission port, the second processor is provided with a plurality of second signal pins and a second transmission port, the plurality of first signal pins are used to be connected to the signal pins of the host processor in a one-to-one correspondence, the first transmission port is connected to a target pin of the external socket, the second transmission port is used to be connected to the signal pin corresponding to the target pin on the external socket, and the plurality of second signal pins are used to be connected to the signal pins of the data center security control device in a one-to-one correspondence;

[0019] The first processor is configured to generate target state information according to the first signal collected by the first signal pin, wherein the target state information is used to indicate the current operating state of the host processor; and transmit the target state information to the second processor through the first transmission port;

[0020] The second processor is used to determine a third signal pin corresponding to the target information type to which the target status information belongs among multiple second signal pins; and send an indication signal corresponding to the operating status indicated by the target status information to the data center security control device through the third signal pin.

[0021] According to another embodiment of the present application, a server signal transmission system is provided, including:

[0022] The server is equipped with: a signal transmission device, a host processor, a data center security control device, and an external socket for the data center security control device. The signal transmission device includes a first processor and a second processor. The first processor is provided with a plurality of first signal pins and a first transmission port. The second processor is provided with a plurality of second signal pins and a second transmission port. The plurality of first signal pins are used to be connected to the signal pins of the host processor in a one-to-one correspondence. The first transmission port is connected to a target pin of the external socket. The second transmission port is used to be connected to the signal pin corresponding to the target pin on the external socket. The plurality of second signal pins are used to be connected to the signal pins of the data center security control device in a one-to-one correspondence.

[0023] The first processor is configured to generate target state information according to the first signal collected by the first signal pin, wherein the target state information is used to indicate the current operating state of the host processor; and transmit the target state information to the second processor through the first transmission port;

[0024] The second processor is used to determine a third signal pin corresponding to the target information type to which the target status information belongs among multiple second signal pins; and send an indication signal corresponding to the operating status indicated by the target status information to the data center security control device through the third signal pin.

[0025] Through the present application, by configuring the first processor and the second processor, and then configuring the first signal pin of the first processor to be connected one-to-one with the signal pin of the host processor, the first transmission port of the first processor is used to connect to a target pin on the external socket of the data center security controller, the second transmission port on the second processor is used to connect to the signal pin corresponding to the target pin on the external socket, and the multiple second pins on the second processor are used to be connected one-to-one with the signal pins of the data center security controller, thereby realizing that the multiple signal pins of the host processor and the multiple signal pins on the data center security control device are connected through a data transmission line through the first processor and the second processor, and then the first processor generates target status information and The target status information is transmitted to the second processor, which determines a third signal pin corresponding to the target information type to which the target status information belongs from multiple second signal pins, and sends an indication signal corresponding to the operating status indicated by the target status information to the data center security processor through the third signal pin, thereby realizing that the status signals of multiple signal pins on the host processor are transmitted to the data center security control device through a transmission link. This process only requires occupying one signal pin on the external socket of the data center security control device, avoiding the influence of insufficient signal pin configuration on signal transmission. Therefore, the problem of low signal transmission efficiency between the host processor and the data center security control device can be solved, thereby achieving the effect of improving the signal transmission efficiency between the host processor and the data center security control device. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 is a schematic diagram of a signal transmission device according to an embodiment of the present application;

[0027] Figure 2 This is a schematic diagram of an optional status message according to an embodiment of the present application;

[0028] Figure 3 is a schematic diagram of an optional processor according to an embodiment of the present application;

[0029] Figure 4 This is a schematic diagram of an optional two-way transparent transmission of signals according to an embodiment of the present application. DETAILED DESCRIPTION

[0030] The embodiments of the present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0031] It should be noted that the terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0032] In this embodiment, a signal transmission device is provided. Figure 1 is a schematic diagram of a signal transmission device according to an embodiment of the present application, such as Figure 1 As shown, the device includes:

[0033] A first processor and a second processor, the first processor is configured with a plurality of first signal pins and a first transmission port, the second processor is configured with a plurality of second signal pins and a second transmission port, the server comprises: an external socket for a host processor and a data center security control device, a plurality of the first signal pins are used to be connected to the signal pins of the host processor in a one-to-one correspondence, the first transmission port is used to be connected to a target pin of the external socket, the second transmission port is used to be connected to a signal pin corresponding to the target pin on the external socket, and a plurality of the second signal pins are used to be connected to the signal pins of the data center security control device in a one-to-one correspondence;

[0034] The first processor is configured to generate target state information according to the first signal collected by the first signal pin, wherein the target state information is used to indicate the current operating state of the host processor; and transmit the target state information to the second processor through the first transmission port;

[0035] The second processor is used to determine a third signal pin corresponding to the target information type to which the target status information belongs among multiple second signal pins; and send an indication signal corresponding to the operating status indicated by the target status information to the data center security control device through the third signal pin.

[0036] Through the above content, by configuring the first processor and the second processor, and then configuring the first signal pin of the first processor to be connected one-to-one with the signal pin of the host processor, the first transmission port of the first processor is used to connect to a target pin on the external socket of the data center security controller, the second transmission port on the second processor is used to connect to the signal pin corresponding to the target pin on the external socket, and the multiple second pins on the second processor are used to be connected one-to-one with the signal pins of the data center security controller, thereby realizing that the multiple signal pins of the host processor and the multiple signal pins on the data center security control device are connected through a data transmission line through the first processor and the second processor, and then the first processor generates target status information and The target status information is transmitted to the second processor, which determines a third signal pin corresponding to the target information type to which the target status information belongs from multiple second signal pins, and sends an indication signal corresponding to the operating status indicated by the target status information to the data center security processor through the third signal pin, thereby realizing that the status signals of multiple signal pins on the host processor are transmitted to the data center security control device through a transmission link. This process only requires occupying one signal pin on the external socket of the data center security control device, avoiding the influence of insufficient signal pin configuration on signal transmission. Therefore, the problem of low signal transmission efficiency between the host processor and the data center security control device can be solved, thereby achieving the effect of improving the signal transmission efficiency between the host processor and the data center security control device.

[0037] Optionally, in an embodiment of the present application, a device with functions of realizing management, security and control of the server (including but not limited to BMC, TPM, Boot Flash, ROT, etc.) is deployed in the data center security control device. In order to ensure the simplified design of the server motherboard and the security of the server, these devices originally configured on the server motherboard are transferred to a smaller universal appearance module, thereby encapsulating it into a data center security control device, so that only an external socket needs to be configured on the server motherboard, so that the data center security control device can be connected to the server through the external socket. In an embodiment of the present application, the data center security control device can be a DC-SCM (DatacenterSecure Control Module) circuit board, and the external socket can be a DC-SCM socket.

[0038] Optionally, in the embodiment of the present application, the host processor may be, but is not limited to, the HOST of a server.

[0039] Optionally, in an embodiment of the present application, the first processor is a device for converting processor signals collected from multiple signal pins of a host processor connected to multiple first signal pins, and realizes converting the signals on multiple signal pins into state information recognizable by the second processor, thereby realizing the transmission of the state of the host processor to the second processor through a transmission link for transmitting state information. This reduces the amount of socket pins occupied by the state signal of the host processor on the external socket of the data center security control device.

[0040] Optionally, in an embodiment of the present application, the second processor is a processor for identifying target status information and performing signal translation, that is, the second processor can identify the signal condition indicated by the target status information sent by the first processor, and convert the status signal output by the host processor carried by the target status information into an indication signal that can be recognized by the data center security control device, thereby realizing the transmission of the status signal output by the host processor to the data center security control device through the first processor and the second processor.

[0041] Optionally, in an embodiment of the present application, the first processor can determine the first signal pin of the collected first signal, and then generate indication information carrying the pin identifier of the signal pin that generates the first signal and the signal value of the first signal on the pin, wherein the target state information includes the indication information, and then the second processor identifies the indication information after receiving the indication information, thereby enabling the second processor to know the status signal output status of the host processor.

[0042] Optionally, in an embodiment of the present application, in actual application, the number of host processors deployed on the server motherboard may be multiple. In order to further optimize the problem of the amount of pins occupied by the external socket when the server host processor sends a synchronization signal to the data center security control device, multiple first sub-level processors can be expanded on the first processor, and each first sub-level processor includes a first sub-level transmission port and multiple first sub-level signal pins. The N signal pins on the first processor can be connected to the first sub-level transmission ports of the N first sub-level processors. The multiple first sub-level signal pins of each first sub-level processor are connected to the signal pins of the corresponding host processor in a one-to-one correspondence. The first sub-level processor is used to generate target state information according to the first sub-level signal collected by the first sub-level signal pin, wherein the target state information is used to indicate the current operating state of the host processor; the target state information is transmitted to the first processor through the first sub-level transmission port, and the first processor recognizes that it is the target state information transmitted by the first sub-level transmission port, and transmits the target state information to the second processor through the first transmission port.

[0043] Optionally, in an embodiment of the present application, in actual applications, multiple data center security control devices may be deployed on the server, such as different data center security control devices used to perform corresponding management and control functions on the server. In order to further optimize the problem of the occupancy of external socket pins when the host processor of the server synchronizes signals to the data center security control device, multiple second sub-level processors can be expanded on the second processor, each second sub-level processor includes a second sub-level transmission port and multiple second sub-level signal pins, the N signal pins on the second processor can be connected to the second sub-level transmission ports of the N second sub-level processors, and the multiple second sub-level signal pins of each second sub-level processor are connected one-to-one with the signal pins of the corresponding data center security control device. The second processor receives the target status information transmitted from the second transmission port, and identifies the target status information to determine the data center security control device corresponding to the status signal of the host processor indicated by the target status information, and then sends the target status information to the second sub-level processor through a second signal pin connected to the second sub-level processor. The second sub-level processor is used to determine a third signal pin corresponding to the target information type to which the target status information belongs among multiple second sub-level signal pins; and sends an indication signal corresponding to the operating status indicated by the target status information to the data center security control device through the third signal pin.

[0044] As an optional embodiment, the first processor is also used to: detect level change information of each of the first signal pins among the multiple first signal pins; when the level change information is used to indicate that the level value of a fourth signal pin among the multiple first signal pins has changed, detect the current first level value on the fourth signal pin, wherein the first signal includes the first level value; obtain the first pin identifier of the fourth signal pin among the multiple first signal pins; generate a first status message according to the first pin identifier and the first level value, wherein the first status message is used to indicate the level output state of the host processor on the fourth signal pin, and the target status information includes the first status message.

[0045] Optionally, in an embodiment of the present application, the first processor is a component used to connect the DC-SCM socket and the host processor, used to transmit the change state of the host processor to the DC-SCM circuit board, and is an intermediary component for signal transmission.

[0046] Optionally, in an embodiment of the present application, the first signal pin is connected to the signal pin of the host processor one by one, and the first processor is used to detect the level change of each first signal pin connected to the host processor. When the state of the host processor changes, that is, when the level of the first signal pin changes, the first processor will detect the first signal pin whose level has changed, wherein the fourth signal pin is the first signal pin whose level has changed, and the first processor will detect and obtain the current first level value (the changed level value) and the first pin identifier on the fourth signal pin, wherein the first pin identifier is the position identifier of the fourth pin among the multiple first signal pins, and the first pin identifier determines which pin has changed in level. The first processor generates a first status message according to the above-mentioned first pin identifier and the first level value. The first status message is used to indicate the level output state of the host processor on the fourth signal pin, that is, the first status message contains the position identifier information and level change information of the pin whose level has changed.

[0047] Through the above content, the first processor collects the level signals on each first signal pin, and then after collecting the change of the level signal, it converts it into a status message by using the pin identifier of the pin that collected the first signal and the level value of the first signal, thereby ensuring the accuracy of the signal during the transmission process and avoiding the second processor from misrecognizing the signal.

[0048] As an optional embodiment, the first processor is also used to: add the first pin identifier to the first field position in the initial status message corresponding to the host processor to obtain a second status message, wherein the first field position is the field position in the initial status message for storing the pin identifier of the pin that has undergone a level change; add the first level value to the second field position in the second status message to obtain a third status message, wherein the second field position is the field position in the second status message for storing the level value of the pin after a level change occurs; add a state change field to the message header position of the third status message to obtain the first status message, wherein the state change field is used to indicate that a level change has occurred on the signal pin of the host processor.

[0049] Optionally, in an embodiment of the present application, after the first processor obtains the first level value and the first pin identifier, it will add the first pin identifier to the first field position in the initial state message to obtain a second state message, wherein the initial state message is the initial state message corresponding to the host processor, and is used to indicate the initial state information corresponding to the host processor. After obtaining the second message, the first processor will add the first level value to the second field position in the second message to obtain a third position message, wherein the second field position is the field position in the second state message used to store the level value of the pin after the level change occurs, and then the first processor will add a state change field to the third message header position to obtain a first state message, wherein the state change field is used to indicate that the level on the signal pin of the host processor has changed, and the state change field here includes but is not limited to using field 0 to indicate a change from a high level to a low level, and using field 1 to indicate a change from a low level to a high level. The first state message can be encrypted by encryption, including but not limited to symmetric encryption and asymmetric encryption for more secure and reliable transmission.

[0050] Optionally, in the embodiment of the present application, the status message may be in the form of, but not limited to, a continuous string. Figure 2 is a schematic diagram of an optional status message according to an embodiment of the present application, such as Figure 2 As shown, the status message is a genetically continuous string, and each character bit in the string has a different field meaning. For example, the first character bit is the SYNC character bit, that is, the signal enable status character. When the host processor GPIO TX default level is high, it is represented by the logical number 1. When the GPIO changes, the SYNC bit will become 0; the second character bit to the second to last character bit are pin identification character bits. In this embodiment, 8 pins are taken as an example, namely P0, P1, P2, P3, P4, P5, P6, P7, and P8. When the character bit is 0, it indicates that there is no change in the level signal of the pin. When the character bit is 1, it indicates that there is a change in the level signal on the pin; the last bit of the string is the level value identification bit, and the character value corresponding to VALUE represents the corresponding GPIO logic level value.

[0051] Through the above configuration, the first processor processes the information of pin level changes and forms a state transmission message format, which can safely convert multiple complex level state change information into a more secure, flexible and compatible message format, thereby improving the security of information transmission; the message can be flexibly configured and the transmitted information can be adjusted as needed, thereby improving the flexibility of information transmission; the message can expand more state information, record more state information fields, and improve the scalability of information transmission.

[0052] As an optional embodiment, the second processor is also used to: detect a field carried in a message header of an initial message received in the second transmission port; and when the field carried in the message header is a state change field, determine the initial message as a first state message sent by the host processor, wherein the target state information includes the first state message, the state change field is used to indicate that a level change has occurred on a signal pin of the host processor, and the first state message carries information on a level value on a signal pin indicating a level change among multiple first signal pins.

[0053] Optionally, in an embodiment of the present application, the second processor is a component used to connect the DC-SCM socket and the data center security control device, used to obtain and parse the first status message, obtain target status information from the first status message, and send the target status information to the corresponding data center security control device.

[0054] Optionally, in an embodiment of the present application, the second processor receives the initial message transmitted by the first processor and detects a field carried in the header of the initial message. If it is detected that the field carried in the header is a state change field, it can be determined that the received initial message is a first state message sent by the host processor, and it can be detected that a level change has occurred on the signal pin corresponding to the host processor. On the contrary, if it is detected that the field carried in the header does not contain a state change field, it indicates that no level change has occurred on the signal pin corresponding to the host processor.

[0055] Through the above-mentioned processing means, the second processor is used to parse the fields carried in the header of the initial message to determine whether the signal pin level corresponding to the host processor has changed. It is not necessary to perform identification processing on each field of each received initial message. Only when the message header carries status change information, the message is further processed. The message that does not carry the status change field is not processed, which can improve the processing and transmission speed of the message, and further improve the response speed of the corresponding data center security control equipment.

[0056] As an optional embodiment, the second processor is also used to extract the first pin identifier carried by the first status message from the first field position in the first status message, and to extract the first level value carried by the first status message from the second field position in the first status message, wherein the first status message carries information for indicating the level value on the signal pin whose level value changes among the multiple first signal pins, and the target status information includes the first status message, the first pin identifier is used to indicate the signal pin whose level value changes among the multiple first signal pins, and the first level value is the current level value of the signal pin whose level value changes among the multiple first signal pins; determine the target information type of the information transmitted on the first signal pin indicated by the first pin identifier; determine the third signal pin corresponding to the target information type from the information type and multiple second signal pins with a corresponding relationship; and control the third signal pin to output the indication signal corresponding to the first level value.

[0057] Optionally, in an embodiment of the present application, when the second processor determines that the field carried in the message header of the received initial message is a state change field, that is, the received initial message is the first state message sent by the host processor, it will extract the first pin identifier from the first field position in the first state message, and extract the first level value carried by the first state message from the second field position in the first state message, wherein the first pin identifier is the position identifier of the signal pin corresponding to the host processor that has undergone a level change, through this first pin identifier, the second controller can parse out which parts of the host processor have changed in state; the first level value is the level value of the signal pin corresponding to the host processor that has undergone a level change, through the first level value, the second controller can parse out how the corresponding part of the host processor has changed in state. Wherein the second signal pin is connected to the data center security control device, after the second processor parses out the first pin identifier, it can determine the second signal pin corresponding to the first pin identifier in the second signal pin connected to multiple data center security control devices, that is, the third signal pin, and the second processor will control the third signal pin to output an indication signal corresponding to the parsed first level value, and the device processes and responds to the corresponding signal. Here, the parsing process of the message field by the second processor includes but is not limited to the decryption process.

[0058] Through the above means, the processing signal in a message can be parsed into indication signals of multiple corresponding devices, which not only improves the quality and speed of signal transmission, but also further improves the response speed of multiple corresponding devices, greatly improving the transmission efficiency.

[0059] As an optional embodiment, the first processor is configured with a third transmission port, the second processor is configured with a fourth transmission port, the third transmission port is used to connect to a reference pin of the external socket, and the fourth transmission port is used to connect to a signal pin corresponding to the reference pin on the external socket;

[0060] The second processor is used to generate target control information according to the second signals collected from the plurality of second signal pins, wherein the second signal is a signal output by the data center security control device for controlling the operating state of the host processor, and the target control information is used to characterize the operating state of the host processor to be converted; and transmit the target control information to the first processor through the second transmission port;

[0061] The first processor is used to determine a fifth signal pin corresponding to the target state type controlled by the target control information from the multiple first signal pins; and send a state control instruction corresponding to the operating state indicated by the target control information to the host processor through the fifth signal pin.

[0062] Optionally, in an embodiment of the present application, the fourth transmission port may be the same as the second transmission port, and the dual-line transmission form may be changed to a single-line transmission form, occupying fewer PIN pins.

[0063] Optionally, in an embodiment of the present application, the third transmission port is configured on the first processor, and the fourth transmission port is configured on the second processor. The third transmission port is used to connect to a reference pin of the DC-SCM socket, and the fourth transmission port is used to connect to a signal pin corresponding to the reference pin on the DC-SCM socket. When the data center security control device is about to transmit a signal to the host processor, the second processor will collect control information of the corresponding host processor of the data center security control device connected to it, and transmit the control information to the first processor through the fourth transmission port. The first processor receives the control information transmitted by the second processor, and determines the corresponding host signal pin (that is, the fifth signal pin) in the control information from the signal pin of the host processor connected to it, and parses the control information to obtain the status instruction corresponding to the device control, and sends it to the corresponding host processor part through the fifth signal pin. The host processor can understand the operating status of the device and can control and change the operating status of the device. For example, a device connected to the second processor is a fan. At this time, the fan is in a stopped state. The second processor connected to the fan will collect a second signal for controlling the start and stop of the fan through the second signal pin connected. The second signal is the signal output by the fan that can control the operating state of the corresponding host processor. This signal can control the start and stop of the fan. The signal at this time indicates that the fan is stopped. The second processor will transmit the control information to the first processor. The first processor parses the signal and finds the corresponding pin of the corresponding host processor that controls the start and stop of the fan. The fan's stop state information is sent to the host processor through the corresponding pin. The host processor can control the change of the fan's operating state.

[0064] Optionally, in the embodiment of the present application, the first processor and the second processor may be, but are not limited to, processors for transmitting GPIO signals. Figure 3 is a schematic diagram of an optional processor according to an embodiment of the present application, such as Figure 3 As shown, the processor may be, but is not limited to, a functional module having the function of converting and transmitting GPIO signals. Each GPIO module has three peripheral pins: GPIO pins (i.e., signal pins, such as the first signal pin or the second signal pin) (GPIO1...GPION) / GPIO TX (i.e., the first transmission port or the fourth transmission port) / GPIO RX (i.e., the second transmission port or the third transmission port), wherein:

[0065] GPIO1...GPION are general-purpose pins that can be commonly used in peripheral circuit design;

[0066] GPIO TX is the GPIO status sending pin. When the status of GPIO1 changes, GPIO TX sends the GPIO level data to the peer module through the protocol frame.

[0067] GPIO RX is the GPIO status receiving pin. When the GPIO status of the other end changes, it receives the protocol frame and sets the corresponding GPIO status to the corresponding status.

[0068] As an optional embodiment, the second processor is also used to locate the sixth signal pin that collects the second signal from multiple second signal pins; add the second pin identifier of the sixth signal pin to the third field position of the reference status message corresponding to the data center security control device, and add the second level value of the second signal to the fourth field position of the reference status message to obtain a fourth status message, wherein the third field position is the field position in the reference status message for storing the pin identifier of the pin that generates the signal, and the fourth field position is the field position in the reference status message for storing the pin level value; add an identification field to the message header position of the fourth status message to obtain a fifth status message, wherein the identification field is used to indicate that the data center security control device has issued a control instruction to the host processor, and the target control information includes the fifth status message.

[0069] Optionally, in an embodiment of the present application, the sixth signal pin is the signal connection pin of the connected target device located and collected by the second processor, and the second processor adds the second pin identifier of the sixth signal pin (that is, the position identifier of the target device signal connection pin) to the third field position of the reference status message corresponding to the data center security control device, and adds the second level value (current level value of the device) in the link device status information (second signal) to the fourth field position of the reference status message to obtain a fourth status message, adds an identification field to the message header position of the fourth status message, and obtains a fifth status message, and the second controller transmits the fifth status message to the first controller through the fourth transmission port. The above message processing and transmission process includes but is not limited to symmetric encryption and asymmetric encryption.

[0070] In this way, the status information of multiple devices can be written into the transmission message, and the complex device status information can be converted into a simple and unified message for transmission, thereby improving the efficiency and speed of signal transmission.

[0071] As an optional embodiment, the first processor is also used to extract the second pin identifier carried in the fifth state message and the second level value of the second signal from the fifth state message, wherein the target control information includes the fifth state message, and the second pin identifier is used to indicate the pin among multiple second signal pins at which the second signal is detected; determine the fifth signal pin corresponding to the target state type from the state types and multiple first signal pins having a corresponding relationship; and control the fifth signal pin to output the state control instruction corresponding to the second level value.

[0072] Optionally, in an embodiment of the present application, the first processor receives a fifth status message transmitted by the second processor, extracts a second pin identifier and a second level value from the fifth status message, determines a signal pin corresponding to the host processor corresponding to the second pin identifier, and sends the second level value to the signal pin corresponding to the host processor. The host processor can thereby determine the status of the transmitted device and thereby change the operating status of the corresponding device through control commands.

[0073] After the above configuration and process, the information transmission process reaches a closed loop, the host processor can know the operating status of each device, and can change the operating status of the device through the device in this application; each connected device can also feedback the latest operating status to the host through the device in this application. This closed-loop and convenient transmission mode can complete efficient signal communication with very few connection resources, greatly improving the communication efficiency and speed between the device and the host.

[0074] As an optional implementation, this paper proposes a GPIO transparent transmission solution based on DC-SCM design, which realizes the smooth upgrade of traditional BMC design through the interconnection of GPIO modules, taking the power status Power Status in server design as an example. In traditional design, the Power Status status is directly connected to the BMC management chip AST2600 through GPIO. In DC-SCM design, we perform GPIO transparent transmission through GPIO A (i.e., the second processor) module and GPIO B (i.e., the first processor) module, realizing a seamless upgrade of software design.

[0075] Figure 4 is a schematic diagram of an optional two-way transparent transmission of signals according to an embodiment of the present application, such as Figure 4 As shown,

[0076] The power status of the motherboard is indicated by Power Status B. A high level indicates that the HOST is turned on, and a low level indicates that the HOST is turned off.

[0077] BMC realizes the power on and off operation of HOST by controlling Power Ctrl A. Power Ctrl A high level controls the power on of HOST, and Power Ctrl A low level controls the power off of HOST.

[0078] Step 1: HOST is in shutdown state, Power Status B is low level, indicating shutdown state, GPIO module B synchronizes Power Status B to Power Status A of GPIO module A through GPIO TX, and the BMC software running on AST2600 detects that HOST is in shutdown state through GPIO status

[0079] Step 2: BMC needs to control the HOST to power on. BMC sets Power Ctrl A to a high level. GPIO module A transmits the Power Ctrl A status to GPIO module B Power Ctrl B through GPIO TX. The HOST can detect the power control key status change and control the HOST to power on.

[0080] Step 3: After the HOST is turned on, Power Status B is set to a high level, triggering the synchronization timing. GPIO module B transmits Power Status B to GPIO module A Power Status A through GPIO TX. Similarly, BMC can directly obtain the HOST power-on status through GPIO status.

[0081] Step 4: BMC controls the HOST to power off. BMC sets Power Ctrl A to a low level. GPIO module A transmits the Power Ctrl A status to GPIO module B Power Ctrl B via GPIOTX. The HOST can detect the change in the power control key status and control the HOST to shut down.

[0082] Step 5: The HOST enters the shutdown state, and Power Status B is low, indicating the shutdown state. GPIO module B synchronizes Power Status B to Power Status A of GPIO module A through GPIO TX. The BMC software detects that the HOST is in the shutdown state through the GPIO status to complete the information closed loop.

[0083] Through the above embodiments, a GPIO transparent transmission solution based on DC-SCM design is proposed, that is, the transmission of GPIO functions is completed through a bidirectional transmission GPIO expansion module, which can simplify the BMC software design. In today's modular design, the smooth upgrade of BMC software can be achieved, the maintainability of the software is improved, the R&D cost investment is reduced, and there is objective economic benefit.

[0084] Taking the above-mentioned Power Status / Power Ctrl as an example, after adopting the DC-SCM design, due to insufficient GPIO resources, the current BMC software needs to be modified to adapt to the new hardware architecture design. After adopting this solution, the BMC software does not need to be upgraded and the previous generation product design can be directly reused, which greatly shortens the server development cycle, realizes the smooth upgrade of the server software platform, and improves the competitiveness of server products.

[0085] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail herein.

[0086] In the present embodiment, a server motherboard is provided, on which: a signal transmission device, a host processor, and an external socket of a data center security control device are deployed, the signal transmission device includes a first processor and a second processor, the first processor is configured with a plurality of first signal pins and a first transmission port, the second processor is configured with a plurality of second signal pins and a second transmission port, the plurality of first signal pins are used to be connected to the signal pins of the host processor in a one-to-one correspondence, the first transmission port is connected to a target pin of the external socket, the second transmission port is used to be connected to the signal pin corresponding to the target pin on the external socket, and the plurality of second signal pins are used to be connected to the signal pins of the data center security control device in a one-to-one correspondence;

[0087] The first processor is configured to generate target state information according to the first signal collected by the first signal pin, wherein the target state information is used to indicate the current operating state of the host processor; and transmit the target state information to the second processor through the first transmission port;

[0088] The second processor is used to determine a third signal pin corresponding to the target information type to which the target status information belongs among multiple second signal pins; and send an indication signal corresponding to the operating status indicated by the target status information to the data center security control device through the third signal pin.

[0089] Through the above content, by configuring the first processor and the second processor, and then configuring the first signal pin of the first processor to be connected one-to-one with the signal pin of the host processor, the first transmission port of the first processor is used to connect to a target pin on the external socket of the data center security controller, the second transmission port on the second processor is used to connect to the signal pin corresponding to the target pin on the external socket, and the multiple second pins on the second processor are used to be connected one-to-one with the signal pins of the data center security controller, thereby realizing that the multiple signal pins of the host processor and the multiple signal pins on the data center security control device are connected through a data transmission line through the first processor and the second processor, and then the first processor generates target status information and The target status information is transmitted to the second processor, which determines a third signal pin corresponding to the target information type to which the target status information belongs from multiple second signal pins, and sends an indication signal corresponding to the operating status indicated by the target status information to the data center security processor through the third signal pin, thereby realizing that the status signals of multiple signal pins on the host processor are transmitted to the data center security control device through a transmission link. This process only requires occupying one signal pin on the external socket of the data center security control device, avoiding the influence of insufficient signal pin configuration on signal transmission. Therefore, the problem of low signal transmission efficiency between the host processor and the data center security control device can be solved, thereby achieving the effect of improving the signal transmission efficiency between the host processor and the data center security control device.

[0090] In the present embodiment, a server signal transmission system is provided, in which: a signal transmission device, a host processor, a data center security control device, and an external socket of the data center security control device are deployed in the server, the signal transmission device includes a first processor and a second processor, the first processor is configured with a plurality of first signal pins and a first transmission port, the second processor is configured with a plurality of second signal pins and a second transmission port, the plurality of first signal pins are used to be connected to the signal pins of the host processor in a one-to-one correspondence, the first transmission port is connected to a target pin of the external socket, the second transmission port is used to be connected to the signal pin corresponding to the target pin on the external socket, and the plurality of second signal pins are used to be connected to the signal pins of the data center security control device in a one-to-one correspondence;

[0091] The first processor is configured to generate target state information according to the first signal collected by the first signal pin, wherein the target state information is used to indicate the current operating state of the host processor; and transmit the target state information to the second processor through the first transmission port;

[0092] The second processor is used to determine a third signal pin corresponding to the target information type to which the target status information belongs among multiple second signal pins; and send an indication signal corresponding to the operating status indicated by the target status information to the data center security control device through the third signal pin.

[0093] Through the above content, by configuring the first processor and the second processor, and then configuring the first signal pin of the first processor to be connected one-to-one with the signal pin of the host processor, the first transmission port of the first processor is used to connect to a target pin on the external socket of the data center security controller, the second transmission port on the second processor is used to connect to the signal pin corresponding to the target pin on the external socket, and the multiple second pins on the second processor are used to be connected one-to-one with the signal pins of the data center security controller, thereby realizing that the multiple signal pins of the host processor and the multiple signal pins on the data center security control device are connected through a data transmission line through the first processor and the second processor, and then the first processor generates target status information and The target status information is transmitted to the second processor, which determines a third signal pin corresponding to the target information type to which the target status information belongs from multiple second signal pins, and sends an indication signal corresponding to the operating status indicated by the target status information to the data center security processor through the third signal pin, thereby realizing that the status signals of multiple signal pins on the host processor are transmitted to the data center security control device through a transmission link. This process only requires occupying one signal pin on the external socket of the data center security control device, avoiding the influence of insufficient signal pin configuration on signal transmission. Therefore, the problem of low signal transmission efficiency between the host processor and the data center security control device can be solved, thereby achieving the effect of improving the signal transmission efficiency between the host processor and the data center security control device.

[0094] Obviously, those skilled in the art should understand that the above modules or steps of the present application can be implemented by a general computing device, they can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, they can be implemented by a program code executable by a computing device, so that they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be executed in a different order from that herein, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. Thus, the present application is not limited to any specific combination of hardware and software.

[0095] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the principles of the present application shall be included in the protection scope of the present application.

Claims

1. A signal transmission device, It is characterized in that The server comprises: a first processor and a second processor, wherein the first processor is provided with a plurality of first signal pins and a first transmission port, and the second processor is provided with a plurality of second signal pins and a second transmission port. The server comprises: an external socket for a host processor and a data center security control device, wherein the plurality of first signal pins are used to be connected to the signal pins of the host processor in a one-to-one correspondence, the first transmission port is used to be connected to a target pin of the external socket, the second transmission port is used to be connected to the signal pin corresponding to the target pin on the external socket, and the plurality of second signal pins are used to be connected to the signal pins of the data center security control device in a one-to-one correspondence; The first processor is configured to generate target state information according to the first signal collected by the first signal pin, wherein the target state information is used to indicate the current operating state of the host processor; and transmit the target state information to the second processor through the first transmission port; The second processor is used to determine a third signal pin corresponding to the target information type to which the target status information belongs among multiple second signal pins; and send an indication signal corresponding to the operating status indicated by the target status information to the data center security control device through the third signal pin.

2. The device according to claim 1, characterized in that The first processor is further used to: detect level change information of each of the first signal pins among the multiple first signal pins; when the level change information is used to indicate that the level value of a fourth signal pin among the multiple first signal pins has changed, detect the current first level value on the fourth signal pin, wherein the first signal includes the first level value; obtain the first pin identifier of the fourth signal pin among the multiple first signal pins; generate a first status message according to the first pin identifier and the first level value, wherein the first status message is used to indicate the level output state of the host processor on the fourth signal pin, and the target status information includes the first status message.

3. The device according to claim 2, characterized in that The first processor is further used to: add the first pin identifier at the first field position in the initial state message corresponding to the host processor to obtain a second state message, wherein the first field position is the field position in the initial state message for storing the pin identifier of the pin that has undergone a level change; add the first level value at the second field position in the second state message to obtain a third state message, wherein the second field position is the field position in the second state message for storing the level value of the pin after a level change occurs; add a state change field at the message header position of the third state message to obtain the first state message, wherein the state change field is used to indicate that a level change has occurred on the signal pin of the host processor.

4. The device according to claim 1, characterized in that The second processor is further used to: detect a field carried in a message header of an initial message received in the second transmission port; and when the field carried in the message header is a state change field, determine the initial message as a first state message sent by the host processor, wherein the target state information includes the first state message, the state change field is used to indicate that a level change has occurred on a signal pin of the host processor, and the first state message carries information on a level value on a signal pin where a level change has occurred among a plurality of the first signal pins.

5. The device according to claim 1, characterized in that The second processor is also used to extract the first pin identifier carried by the first status message from the first field position in the first status message, and to extract the first level value carried by the first status message from the second field position in the first status message, wherein the first status message carries information for indicating the level value on the signal pin whose level value changes among the multiple first signal pins, and the target status information includes the first status message, the first pin identifier is used to indicate the signal pin whose level value changes among the multiple first signal pins, and the first level value is the current level value of the signal pin whose level value changes among the multiple first signal pins; determine the target information type of the information transmitted on the first signal pin indicated by the first pin identifier; determine the third signal pin corresponding to the target information type from the information type and multiple second signal pins with a corresponding relationship; and control the third signal pin to output the indication signal corresponding to the first level value.

6. The device according to claim 1, characterized in that The first processor is provided with a third transmission port, the second processor is provided with a fourth transmission port, the third transmission port is used to connect to a reference pin of the external socket, and the fourth transmission port is used to connect to a signal pin corresponding to the reference pin on the external socket; The second processor is used to generate target control information according to the second signals collected from the plurality of second signal pins, wherein the second signal is a signal output by the data center security control device for controlling the operating state of the host processor, and the target control information is used to characterize the operating state of the host processor to be converted; and transmit the target control information to the first processor through the second transmission port; The first processor is used to determine a fifth signal pin corresponding to the target state type controlled by the target control information from the multiple first signal pins; and send a state control instruction corresponding to the operating state indicated by the target control information to the host processor through the fifth signal pin.

7. The device according to claim 6, characterized in that The second processor is also used to locate the sixth signal pin that collects the second signal from multiple second signal pins; add the second pin identifier of the sixth signal pin to the third field position of the reference status message corresponding to the data center security control device, and add the second level value of the second signal to the fourth field position of the reference status message to obtain a fourth status message, wherein the third field position is the field position in the reference status message for storing the pin identifier of the pin that generates the signal, and the fourth field position is the field position in the reference status message for storing the pin level value; add an identification field to the message header position of the fourth status message to obtain a fifth status message, wherein the identification field is used to indicate that the data center security control device has issued a control instruction to the host processor, and the target control information includes the fifth status message.

8. The device according to claim 6, characterized in that The first processor is further used to extract the second pin identifier carried in the fifth state message and the second level value of the second signal from the fifth state message, wherein the target control information includes the fifth state message, and the second pin identifier is used to indicate the pin at which the second signal is detected among multiple second signal pins; determine the fifth signal pin corresponding to the target state type from the state types and multiple first signal pins having a corresponding relationship; and control the fifth signal pin to output the state control instruction corresponding to the second level value.

9. A server motherboard, characterized in that: The server motherboard is provided with: a signal transmission device, a host processor, and an external socket of a data center security control device, the signal transmission device includes a first processor and a second processor, the first processor is provided with a plurality of first signal pins and a first transmission port, the second processor is provided with a plurality of second signal pins and a second transmission port, the plurality of first signal pins are used to be connected to the signal pins of the host processor in a one-to-one correspondence, the first transmission port is connected to a target pin of the external socket, the second transmission port is used to be connected to the signal pin corresponding to the target pin on the external socket, and the plurality of second signal pins are used to be connected to the signal pins of the data center security control device in a one-to-one correspondence; The first processor is configured to generate target state information according to the first signal collected by the first signal pin, wherein the target state information is used to indicate the current operating state of the host processor; and transmit the target state information to the second processor through the first transmission port; The second processor is used to determine a third signal pin corresponding to the target information type to which the target status information belongs among multiple second signal pins; and send an indication signal corresponding to the operating status indicated by the target status information to the data center security control device through the third signal pin.

10. A server signal transmission system, characterized in that: The server is equipped with: a signal transmission device, a host processor, a data center security control device, and an external socket of the data center security control device. The signal transmission device includes a first processor and a second processor. The first processor is provided with a plurality of first signal pins and a first transmission port. The second processor is provided with a plurality of second signal pins and a second transmission port. The plurality of first signal pins are used to be connected to the signal pins of the host processor in a one-to-one correspondence. The first transmission port is connected to a target pin of the external socket. The second transmission port is used to be connected to the signal pin corresponding to the target pin on the external socket. The plurality of second signal pins are used to be connected to the signal pins of the data center security control device in a one-to-one correspondence. The first processor is used to generate target state information according to the first signal collected by the first signal pin, wherein: The target state information is used to indicate the current operating state of the host processor; the target state information is transmitted to the second processor through the first transmission port; The second processor is used to determine a third signal pin corresponding to the target information type to which the target status information belongs among multiple second signal pins; and send an indication signal corresponding to the operating status indicated by the target status information to the data center security control device through the third signal pin.

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