SOC chip integrated with M1553B interactive interface and method

Abstract

The invention relates to an SOC chip and a method for integrating an M1553B interactive interface, and through the design that an M1553B controller and an M1553B transceiver module are integrated on an SOC, the M1553B transceiver module integrated on a chip can be flexibly accessed under the condition that the M1553B controller in the chip is slightly modified, so that the M1553B interactive interface is integrated on the SOC chip. Therefore, the problem that a transceiver needs to be externally hung when the M1553B interface is used or the problem that the M1553B interface needs to be expanded by occupying a universal interface designed and realized by the SOC is solved, and the application of the M1553B interface is simpler and more convenient. Besides, the functions of the M1553B transceiver module can be flexibly expanded through the added interactive interface, such as the configuration function of the driving capability, the swing and the transmission rate of data, so that the use efficiency of the M1553B on the SOC chip is greatly improved.

Description

Technical Field

[0001] The invention belongs to the technical field of SOC chip interface design, and relates to a SOC chip and a method integrating an M1553B interactive interface. Background Art

[0002] The M1553B protocol is a time-division multiplexing bus protocol that defines interactive commands. It is mainly used in aerospace and other scenarios. When in use, all different devices distributed on large equipment communicate through the same copper cable, and are generally equipped with an additional redundant backup line. There are special interactive commands inside the M1553B. In existing SOC (system on chip) chips, the following two solutions are usually used to design and implement the application of the M1553B interface. For example, one is to implement only the M1553B controller but not the M1553B transceiver in the SOC chip. When the M1553B interface is actually applied, the M1553B transceiver needs to be mounted outside the SOC chip; the other is not to implement the M1553B controller and the M1553B transceiver in the SOC chip, but to directly use the USB / PCI / Ethernet / UART and other universal interfaces that the SOC has designed and implemented, and directly mount the M1553B controller and transceiver integrated module under these universal interfaces. However, the aforementioned traditional technical solutions have the technical problem of low efficiency. Summary of the invention

[0003] In view of the problems existing in the above-mentioned traditional technology, the present invention proposes a SOC chip integrating an M1553B interactive interface and a processing method of the M1553B interactive interface on the SOC chip, which can greatly improve the utilization efficiency of the M1553B on the SOC chip.

[0004] In order to achieve the above objectives, the embodiments of the present invention adopt the following technical solutions: On the one hand, a SOC chip with an integrated M1553B interactive interface is provided, wherein the SOC chip is integrated with an M1553B controller, an M1553B transceiver module and an arbiter module, the M1553B controller is internally provided with a bus interface module, the M1553B transceiver module is internally provided with a bus interface module, a channel module, an extended register and a storage unit; the bus interface module supports the ahb protocol and the apb protocol; The arbiter module is respectively connected to the SOC system bus of the SOC chip, the bus interface module of the M1553B controller and the bus interface module of the M1553B transceiver module. The channel module of the M1553B transceiver module is compatible with the channels of different M1553B controller IP cores. The bus interface module of the M1553B transceiver module is connected to the extended registers and storage units. The channels of different M1553B controller IP cores include the channels ATX, ARX, BTX, BRX and the channels of the physical layer chip control signals of the M1553B controller. The extended registers and storage units are used to configure the driving capability, swing and transmission rate of the M1553B transceiver module for data. The channel module of the M1553B transceiver module is used to resample in the clock domain of bus data transmission. The arbitrator module supports the apb protocol and ahb protocol on the SOC system bus side, on the bus interface module side of the M1553B controller, and on the bus interface module side of the M1553B transceiver module. The arbitrator module is used to forward requests on the SOC system bus to the M1553B controller and the M1553B transceiver module.

[0005] On the other hand, a method for processing an M1553B interactive interface on a SOC chip is also provided, which is applied to a SOC chip with an integrated M1553B interactive interface, wherein an M1553B controller, an M1553B transceiver module and an arbiter module are integrated in the SOC chip, a bus interface module is provided inside the M1553B controller, and a bus interface module, a channel module, an extended register and a storage unit are provided inside the M1553B transceiver module; the bus interface module supports the ahb protocol and the apb protocol; The arbiter module is respectively connected to the SOC system bus of the SOC chip, the bus interface module of the M1553B controller and the bus interface module of the M1553B transceiver module. The channel module of the M1553B transceiver module is compatible with the channels of different M1553B controller IP cores. The bus interface module of the M1553B transceiver module is connected to the extended registers and storage units. The channels of different M1553B controller IP cores include the channels ATX, ARX, BTX, BRX and the channels of the physical layer chip control signals of the M1553B controller. The extended registers and storage units are used to configure the driving capability, swing and transmission rate of the M1553B transceiver module for data. The channel module of the M1553B transceiver module is used to resample in the clock domain of bus data transmission. The arbiter module supports the apb protocol and ahb protocol on the SOC system bus side, the bus interface module side of the M1553B controller, and the bus interface module side of the M1553B transceiver module. The arbiter module is used to forward requests on the SOC system bus to the M1553B controller and the M1553B transceiver module. The processing method of the M1553B interactive interface on the SOC chip comprises the following steps: After the arbiter module obtains the information of the defined address segment from the SOC system bus, it decodes and arbitrates the specific address bits in the address segment to determine whether the address segment is a controller configuration segment or a transceiver configuration segment; If the address segment is neither a controller configuration segment nor a transceiver configuration segment, the address segment is reserved and not processed.

[0006] One of the above technical solutions has the following advantages and beneficial effects: The above-mentioned SOC chip and method with integrated M1553B interactive interface, through the design of integrating M1553B controller and M1553B transceiver module on SOC, can flexibly access the M1553B transceiver module integrated on chip with a small modification of the M1553B controller on chip, thereby solving the problem of needing an external transceiver when using the M1553B interface or the problem of needing to occupy the universal interface designed and implemented by SOC to expand the M1553B interface, and also making the application of M1553B interface simpler and more convenient. In addition, the functions of M1553B transceiver module can be flexibly expanded through the added interactive interface, such as including the configuration functions of data driving capability, swing and transmission rate, thereby greatly improving the use efficiency of M1553B on SOC chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0008] Figure 1 This is a schematic diagram of the system structure in which only the M1553B controller is implemented in the SOC chip; Figure 2 The schematic diagram of the system structure of mounting the M1553B controller and transceiver integrated module on the universal interface of the SOC chip; Figure 3 It is a schematic diagram of an improved structure of a SOC chip integrating an M1553B interactive interface in one embodiment; Figure 4 A schematic diagram of the M1553B processing flow of a SOC chip integrating an M1553B interactive interface in one embodiment; Figure 5 The figure is a flowchart of a method for processing the M1553B interactive interface on a SOC chip in one embodiment. DETAILED DESCRIPTION

[0009] In order to make the purpose, technical scheme and advantages of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and Examples. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by those skilled in the art of the present invention. The terms used in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0010] It should be noted that the reference to "embodiment" in this article means that the specific features, structures or characteristics described in conjunction with the embodiment may be included in at least one embodiment of the present invention. The presentation of this phrase at various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It will be appreciated by those skilled in the art that the embodiments described herein may be combined with other embodiments. The term "and / or" used in the specification and appended claims of the present invention refers to any combination of one or more of the associated listed items and all possible combinations, and includes these combinations.

[0011] The following will describe the implementation of the present invention in detail with reference to the accompanying drawings in the embodiment diagram of the present invention.

[0012] On the one hand, if Figure 1 As shown, only the M1553B controller is implemented in the SOC chip without implementing the M1553B transceiver. When the M1553B interface is actually applied, the M1553B transceiver needs to be mounted outside the SOC chip (such as Figure 1 ). Under the existing solution, since the M1553B transceiver is not implemented on the SOC chip, when the M1553B interface is actually applied, the M1553B transceiver needs to be mounted outside the SOC chip, and the interaction between the M1553B controller and the M1553B transceiver is limited to the transmission of the data stream after Manchester encoding, which makes the SOC chip lack control over the inside of the M1553B transceiver, limiting the further enrichment of the functions of the M1553B transceiver.

[0013] On the other hand, the M1553B controller and M1553B transceiver are not implemented in the SOC chip, but the general interfaces such as USB / PCI / Ethernet / UART that have been designed and implemented in the SOC are directly used to mount the M1553B controller and transceiver integrated module directly under these general interfaces, such as Figure 2 Under this solution, users need to spend a lot of time debugging to match the SOC chip and the external integrated module, which makes the overall application device development time too long, requires the expansion interface of the device, is not conducive to the development of embedded scenarios, and is not conducive to the miniaturization of the device.

[0014] In one embodiment, Figure 3 As shown, a SOC chip with an integrated M1553B interactive interface is provided, wherein the SOC chip is integrated with an M1553B controller, an M1553B transceiver module and an arbiter module ( Figure 3 The M1553B controller is internally provided with a bus interface module, and the M1553B transceiver module is internally provided with a bus interface module, a channel module, an extended register and a storage unit; the bus interface module supports the ahb protocol and the apb protocol. The arbiter module is respectively connected to the SOC system bus of the SOC chip, the bus interface module of the M1553B controller and the bus interface module of the M1553B transceiver module. The channel module of the M1553B transceiver module is compatible with the channels connected to different M1553B controller IP cores. The bus interface module of the M1553B transceiver module connects the extended registers and storage units; the channels of different M1553B controller IP cores include the channels ATX, ARX, BTX, BRX of the M1553B controller and the channels of the physical layer chip control signals.

[0015] The extended registers and storage units are used to configure the driving capability, swing and transmission rate of the M1553B transceiver module for data. The channel module of the M1553B transceiver module is used to resample in the clock domain of bus data transmission. The arbiter module supports the apb protocol and ahb protocol on the SOC system bus side, the bus interface module side of the M1553B controller, and the bus interface module side of the M1553B transceiver module. The arbiter module is used to forward requests on the SOC system bus to the M1553B controller and the M1553B transceiver module.

[0016] It can be understood that in this embodiment, the M1553B controller and the M1553B transceiver module are designed and integrated in the SOC chip, and a bus interface module, an arbitrator module and a channel module are added to the design of the SOC chip to realize the interactive interface between the SOC system bus in the SOC chip and the integrated M1553B controller and the M1553B transceiver module.

[0017] Specifically, in the design of the SOC chip, according to the functional requirements of the existing M1553B controller and M1553B transceiver, the M1553B controller and the M1553B transceiver module are integrated into the SOC chip, and the bus interface module, channel module, extended registers and storage units are designed and implemented inside the M1553B transceiver module, and an arbiter module is added to the SOC system bus to support flexible simultaneous mounting of the M1553B controller and the M1553B transceiver module. The design and implementation of the aforementioned functional modules follow the existing chip design specifications in this field. Among them, the bus interface module designed and implemented inside the M1553B transceiver module supports the ahb protocol and the apb protocol, so that the aforementioned required registers and storage units can be extended and configured inside the M1553B transceiver module, and then the extended registers and storage units can be accessed through the bus interface module designed and implemented inside the M1553B transceiver module.

[0018] The extended registers and storage units are used to configure the M1553B transceiver module's data driving capability, swing, and transmission rate, making the M1553B interface suitable for a wider range of application scenarios. The channel module designed and implemented inside the M1553B transceiver module can be compatible with the (data transmission) channels of different M1553B controller IP (Intellectual Property) cores, thereby connecting the channel module with the M1553B controller's channel ATX, channel ARX, channel BTX, channel BRX, and the channel of the physical layer chip control signal, and resampling in the clock domain of bus data transmission to ensure compatibility with the original M1553B controller's external interface and reliability of data transmission.

[0019] The arbiter module is directly connected to the SOC system bus, the bus interface module of the M1553B controller and the bus interface module of the M1553B transceiver module respectively. The arbiter module supports the apb protocol and ahb protocol on the SOC system bus side, the bus interface module side of the M1553B controller and the bus interface module side of the M1553B transceiver module, and through decoding and judging specific address bits, it can forward requests on the SOC system bus (such as configuration information, valid data or instructions transmitted, etc.) to the M1553B controller and the M1553B transceiver module according to the user-defined address segment, thereby realizing the selection and configuration of the M1553B controller and the M1553B transceiver module.

[0020] In the implementation of the above-mentioned design integration, there is no need to modify the design of the existing M1553B controller. By directly adding an arbitrator module and a channel module, it can be used to realize the functional integration of the existing M1553B controller and the M1553B transceiver module. In the M1553B transceiver module, by adding a bus interface module, an extended register and a storage unit, it can support flexible configuration of the M1553B transceiver module according to the actual needs of the user, such as the driving capability, swing amplitude and transmission rate of the data. More functions.

[0021] The SOC chip with integrated M1553B interactive interface can flexibly access the M1553B transceiver module integrated on the chip by integrating the M1553B controller and the M1553B transceiver module on the SOC with a small modification of the M1553B controller on the chip, thereby solving the problem of needing an external transceiver when using the M1553B interface or the problem of needing to occupy the general interface designed and implemented by the SOC to expand the M1553B interface, and also making the application of the M1553B interface simpler and more convenient. In addition, the functions of the M1553B transceiver module can be flexibly expanded through the added interactive interface, such as the configuration functions of the driving capability, swing and transmission rate of the data, thereby greatly improving the use efficiency of the M1553B on the SOC chip.

[0022] It should be noted that the definition of the aforementioned address segment is freely defined by the SOC chip designer according to project requirements. For example, the internal addressing range of a SOC chip is 0x00000000~0xffffffff, and the addresses of 0x2000000~0x20003fff can be assigned to these registers and RAM. The specific address bit refers to the criterion of the address segment used for the arbitrator module to forward the request, that is, the middle bit or bits of the address used when the registers and RAM in the module are accessed by other components in the chip (such as the processor core). The decoding method is to use demux (reverse data selector) and mux (data selector) to route data, where demux has a set of data inputs, two sets of data outputs and a set of criterion inputs, and mux has a set of data outputs, two sets of data inputs and a set of criterion inputs.

[0023] In the design of this embodiment, one of the two data outputs of the demux is connected to the input of the bus interface module of the M1553B controller, and the other output is connected to the input of the bus interface module of the M1553B transceiver module. The data input of the demux is connected to the output signal of the SOC system bus. One of the two data inputs of the mux is connected to the output of the bus interface module of the M1553B controller, and the other is connected to the output of the bus interface module of the M1553B transceiver module. The data input of the mux is connected to the SOC system bus as an input signal. The demux and mux are connected to the same criterion input.

[0024] Assuming that the user defines the address segment for the M1553B controller as 0x20000000~0x20001fff (which can be called the controller configuration segment), and the address segment for the M1553B transceiver module as 0x20002000~0x20003fff (which can be called the transceiver configuration segment), then it can be obtained that the bit that distinguishes the two address segments is bit 3 (0 to 7 from right to left), that is, when the request should be sent to the M1553B controller, bit 3 should be 0 or 1, and when the request should be sent to the M1553B transceiver module, bit 3 It should be 2 or 3; the third bit can be used as a criterion input because it can distinguish the difference between the two address segments (the third bit can be used as a specific address bit); in this way, when the data of the third bit of the user-defined address segment is 0 or 1, the arbiter module determines that the demux is connected to the M1553B controller and the mux is also connected to the M1553B controller; when the data of the third bit of the user-defined address segment is 2 or 3, the arbiter module determines that the demux is connected to the M1553B transceiver module and the mux is also connected to the M1553B transceiver module, thereby achieving the purpose of decoding. The above decoding function can also be implemented in the same way using Verilog code.

[0025] In one embodiment, after the arbitrator module obtains the information of the defined address segment from the SOC system bus, it decodes and arbitrates the specific address bits in the address segment to determine whether the address segment is a controller configuration segment or a transceiver configuration segment. If it is neither a controller configuration segment nor a transceiver configuration segment, the address segment is reserved and not processed.

[0026] It is understandable that Figure 4 As shown, in actual applications, the user can define an address segment in the SOC chip with integrated M1553B interactive interface. The address segment can include configuration information for the current working configuration of the M1553B controller or the M1553B transceiver module, as well as a specific address bit. The arbitrator module obtains the information of the address segment from the SOC system bus and decodes and arbitrates the specific address bit, first determining whether the user-defined address segment is a controller configuration segment or a transceiver configuration segment. If it is neither of the two configuration segments, the address segment is retained and not processed.

[0027] In one embodiment, if it is determined that the address segment is a controller configuration segment, the arbiter module configures the registers inside the M1553B controller and the controller message stack inside the M1553B controller through the bus interface module of the M1553B controller according to the configuration information of the address segment. At the same time, the arbiter module configures the registers inside the M1553B transceiver module and the transceiver message stack inside the M1553B transceiver module through the bus interface module of the M1553B transceiver module according to the configuration information of the address segment. After the configuration is completed, the M1553B controller starts the transmission, performs Manchester encoding on the data from the SOC system bus and transmits it to the channel module of the M1553B transceiver module. After the M1553B transceiver module determines that there is a valid transmission from the channel module, it performs the corresponding level conversion on the data and transmits it to the outside of the SOC chip through the external channel.

[0028] It is understandable that Figure 4As shown, if it is determined that the user-defined address segment is a controller configuration segment, the arbiter module configures the registers inside the M1553B controller and the controller message stack (RAM storage body) inside the M1553B controller through the bus interface module of the M1553B controller according to the configuration information of the address segment, so that the M1553B controller enters a work-ready state. At the same time, the arbiter module configures the registers inside the M1553B transceiver module and the transceiver message stack (RAM storage body) inside the M1553B transceiver module through the bus interface module of the M1553B transceiver module according to the configuration information of the address segment, so that the M1553B transceiver module enters a work-ready state. After the configuration is completed, the M1553B controller starts the transmission, Manchester encodes the data from the SOC system bus and transmits it to the channel module of the M1553B transceiver module. The M1553B transceiver module determines from the channel module that there is a valid transmission and performs corresponding level conversion on the data and transmits it to the outside of the SOC chip through external channels (such as channel A and / or channel B).

[0029] In one embodiment, if it is determined that the address segment is a transceiver configuration segment, the arbiter module configures the registers inside the M1553B transceiver module and the transceiver message stack inside the M1553B transceiver module through the bus interface module of the M1553B transceiver module according to the configuration information of the address segment. At the same time, the arbiter module configures the registers inside the M1553B controller and the controller message stack inside the M1553B controller through the bus interface module of the M1553B controller according to the configuration information of the address segment. After the configuration is completed, the M1553B transceiver module determines whether there is a valid transmission from the external channel. If there is a valid transmission, the M1553B transceiver module performs corresponding level conversion on the data received from the external channel, and sends it to the M1553B controller for processing through the channel module. The M1553B controller performs Manchester decoding on the received data and sends it to the SOC system bus.

[0030] It is understandable that Figure 4As shown, if it is determined that the user-defined address segment is a transceiver configuration segment, the arbiter module configures the registers inside the M1553B transceiver module and the transceiver message stack (RAM storage body) inside the M1553B transceiver module through the bus interface module of the M1553B transceiver module according to the configuration information of the address segment, so that the M1553B transceiver module enters a work-ready state. At the same time, the arbiter module configures the registers inside the M1553B controller and the controller message stack (RAM storage body) inside the M1553B controller through the bus interface module of the M1553B controller according to the configuration information of the address segment, so that the M1553B controller enters a work-ready state. After the configuration is completed, the M1553B transceiver module determines whether there is valid transmission from the external channel (such as channel A and / or channel B). If there is valid transmission, the M1553B transceiver module performs corresponding level conversion on the data received by the channel and sends it to the M1553B controller for processing through the channel module. The M1553B controller can perform Manchester decoding on the received data and send the data to the SOC system bus.

[0031] In one embodiment, a method for processing an M1553B interactive interface on a SOC chip is also provided, which is applied to a SOC chip with an integrated M1553B interactive interface. The SOC chip is integrated with an M1553B controller, an M1553B transceiver module and an arbiter module. The M1553B controller is provided with a bus interface module, and the M1553B transceiver module is provided with a bus interface module, a channel module, an extended register and a storage unit. The bus interface module supports the ahb protocol and the apb protocol. The arbiter module is respectively connected to the SOC system bus of the SOC chip, the bus interface module of the M1553B controller and the bus interface module of the M1553B transceiver module. The channel module of the M1553B transceiver module is compatible with the channels of different M1553B controller IP cores. The bus interface module of the M1553B transceiver module is connected to the extended registers and storage units. The channels of different M1553B controller IP cores include the channels ATX, ARX, BTX, BRX and the channels of the physical layer chip control signals of the M1553B controller. The extended registers and storage units are used to configure the driving capability, swing and transmission rate of the M1553B transceiver module for data. The channel module of the M1553B transceiver module is used to resample in the clock domain of bus data transmission. The arbiter module supports the apb protocol and ahb protocol on the SOC system bus side, the bus interface module side of the M1553B controller, and the bus interface module side of the M1553B transceiver module. The arbiter module is used to forward requests on the SOC system bus to the M1553B controller and the M1553B transceiver module. Among them, Figure 5 As shown, the processing method of the M1553B interactive interface on the SOC chip may at least include the following processing steps S10 and S12: S10, after the arbiter module obtains the information of the defined address segment from the SOC system bus, it decodes and arbitrates the specific address bits in the address segment to determine whether the address segment is a controller configuration segment or a transceiver configuration segment; S12, if the address segment is neither a controller configuration segment nor a transceiver configuration segment, the address segment is reserved and not processed.

[0032] The processing method of the M1553B interactive interface on the SOC chip mentioned above, through the design of integrating the M1553B controller and the M1553B transceiver module on the SOC, can flexibly access the M1553B transceiver module integrated on the chip with a small modification of the M1553B controller on the chip, thereby solving the problem of needing an external transceiver when using the M1553B interface or the problem of occupying the general interface designed and implemented by the SOC to expand the M1553B interface, and also making the application of the M1553B interface simpler and more convenient. In addition, the functions of the M1553B transceiver module can be flexibly expanded through the added interactive interface, such as the configuration functions of the driving capability, swing and transmission rate of the data, thereby greatly improving the use efficiency of the M1553B on the SOC chip.

[0033] In one embodiment, the processing method of the M1553B interactive interface on the SOC chip may further include the following processing steps: If it is determined that the address segment is a controller configuration segment, the arbiter module configures the registers inside the M1553B controller and the controller message stack inside the M1553B controller through the bus interface module of the M1553B controller according to the configuration information of the address segment; at the same time, the arbiter module configures the registers inside the M1553B transceiver module and the transceiver message stack inside the M1553B transceiver module through the bus interface module of the M1553B transceiver module according to the configuration information of the address segment; After the configuration is completed, the M1553B controller starts the transmission, performs Manchester encoding on the data from the SOC system bus and transmits it to the channel module of the M1553B transceiver module; After the M1553B transceiver module determines that there is valid transmission from the channel module, it performs corresponding level conversion on the data and transmits it to the outside of the SOC chip through the external channel.

[0034] In one embodiment, the processing method of the M1553B interactive interface on the SOC chip may further include the following processing steps: If it is determined that the address segment is a transceiver configuration segment, the arbiter module configures the registers inside the M1553B transceiver module and the transceiver message stack inside the M1553B transceiver module through the bus interface module of the M1553B transceiver module according to the configuration information of the address segment; at the same time, the arbiter module configures the registers inside the M1553B controller and the controller message stack inside the M1553B controller through the bus interface module of the M1553B controller according to the configuration information of the address segment; After configuration is complete, the M1553B transceiver module determines whether there is valid transmission from the external channel; If there is a valid transmission, the M1553B transceiver module performs the corresponding level conversion on the data received from the external channel and sends it to the M1553B controller through the channel module; The M1553B controller performs Manchester decoding on the received data and sends it to the SOC system bus.

[0035] For the specific explanation and limitation of the processing method of the M1553B interactive interface on the above-mentioned SOC chip, please refer to the corresponding limitation of the SOC chip integrating the M1553B interactive interface mentioned above, which will not be repeated here.

[0036] It should be understood that although Figure 5 The steps in the method are shown in sequence as indicated by the arrows, but the steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of the steps, and the steps can be executed in other orders. Figure 5 At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequentially, but can be executed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.

[0037] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided by the present invention can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus dynamic random access memory (RambusDRAM, referred to as RDRAM) and interface dynamic random access memory (DRDRAM).

[0038] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0039] The above embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of protection of the invention. It should be pointed out that, for those of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present invention, which all belong to the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be subject to the attached claims.

Claims

1. A SOC chip integrating an M1553B interactive interface, characterized in that: The SOC chip is integrated with an M1553B controller, an M1553B transceiver module and an arbiter module. The M1553B controller is internally provided with a bus interface module. The M1553B transceiver module is internally provided with a bus interface module, a channel module, an extended register and a storage unit. The bus interface module supports the ahb protocol and the apb protocol. The arbiter module is respectively connected to the SOC system bus of the SOC chip, the bus interface module of the M1553B controller and the bus interface module of the M1553B transceiver module, the channel module of the M1553B transceiver module is compatible with the channels of different M1553B controller IP cores, and the bus interface module of the M1553B transceiver module is connected to the extended registers and storage units; the channels of different M1553B controller IP cores include the channels ATX, ARX, BTX, BRX and the channels of the physical layer chip control signal of the M1553B controller; The extended registers and storage units are used to configure the driving capability, swing and transmission rate of the M1553B transceiver module for data. The channel module of the M1553B transceiver module is used to resample in the clock domain of bus data transmission. The arbitrator module supports the apb protocol and ahb protocol on the SOC system bus side, on the bus interface module side of the M1553B controller, and on the bus interface module side of the M1553B transceiver module. The arbitrator module is used to forward requests on the SOC system bus to the M1553B controller and the M1553B transceiver module.

2. The SOC chip with integrated M1553B interactive interface according to claim 1, characterized in that: After the arbitrator module obtains the information of the defined address segment from the SOC system bus, it decodes and arbitrates the specific address bits in the address segment to determine whether the address segment is a controller configuration segment or a transceiver configuration segment. If it is neither a controller configuration segment nor a transceiver configuration segment, the address segment is retained and not processed.

3. The SOC chip with integrated M1553B interactive interface according to claim 2, characterized in that: If it is determined that the address segment is a controller configuration segment, the arbitrator module configures the registers inside the M1553B controller and the controller message stack inside the M1553B controller through the bus interface module of the M1553B controller according to the configuration information of the address segment. At the same time, the arbitrator module configures the registers inside the M1553B transceiver module and the transceiver message stack inside the M1553B transceiver module through the bus interface module of the M1553B transceiver module according to the configuration information of the address segment. After the configuration is completed, the M1553B controller starts the transmission, performs Manchester encoding on the data from the SOC system bus and transmits it to the channel module of the M1553B transceiver module. After the M1553B transceiver module determines that there is a valid transmission from the channel module, it performs corresponding level conversion on the data and transmits it to the outside of the SOC chip through the external channel.

4. The SOC chip with integrated M1553B interactive interface according to claim 2, characterized in that: If it is determined that the address segment is a transceiver configuration segment, the arbitrator module configures the registers inside the M1553B transceiver module and the transceiver message stack inside the M1553B transceiver module through the bus interface module of the M1553B transceiver module according to the configuration information of the address segment. At the same time, the arbitrator module configures the registers inside the M1553B controller and the controller message stack inside the M1553B controller through the bus interface module of the M1553B controller according to the configuration information of the address segment. After the configuration is completed, the M1553B transceiver module determines whether there is valid transmission from the external channel. If there is valid transmission, the M1553B transceiver module performs corresponding level conversion on the data received from the external channel, and sends it to the M1553B controller for processing through the channel module. The M1553B controller performs Manchester decoding on the received data and sends it to the SOC system bus.

5. A method for processing an M1553B interactive interface on a SOC chip, characterized in that: The invention is applied to a SOC chip integrating an M1553B interactive interface, wherein the SOC chip is integrated with an M1553B controller, an M1553B transceiver module and an arbiter module, wherein a bus interface module is arranged inside the M1553B controller, and a bus interface module, a channel module, an extended register and a storage unit are arranged inside the M1553B transceiver module; and the bus interface module supports the ahb protocol and the apb protocol; The arbiter module is respectively connected to the SOC system bus of the SOC chip, the bus interface module of the M1553B controller and the bus interface module of the M1553B transceiver module, the channel module of the M1553B transceiver module is compatible with the channels of different M1553B controller IP cores, and the bus interface module of the M1553B transceiver module is connected to the extended registers and storage units; the channels of different M1553B controller IP cores include the channels ATX, ARX, BTX, BRX and the channels of the physical layer chip control signal of the M1553B controller; The extended registers and storage units are used to configure the driving capability, swing and transmission rate of the M1553B transceiver module for data. The channel module of the M1553B transceiver module is used to resample in the clock domain of bus data transmission. The arbitrator module supports the apb protocol and ahb protocol on the SOC system bus side, the bus interface module side of the M1553B controller, and the bus interface module side of the M1553B transceiver module. The arbitrator module is used to forward requests on the SOC system bus to the M1553B controller and the M1553B transceiver module. The method for processing the M1553B interactive interface on the SOC chip comprises the following steps: After the arbitrator module obtains the information of the defined address segment from the SOC system bus, it decodes and arbitrates the specific address bits in the address segment to determine whether the address segment is a controller configuration segment or a transceiver configuration segment; If the address segment is neither a controller configuration segment nor a transceiver configuration segment, the address segment is reserved and not processed.

6. The method for processing the M1553B interactive interface on a SOC chip according to claim 5, characterized in that: Also includes the steps: If it is determined that the address segment is a controller configuration segment, the arbitrator module configures the registers inside the M1553B controller and the controller message stack inside the M1553B controller through the bus interface module of the M1553B controller according to the configuration information of the address segment; at the same time, the arbitrator module configures the registers inside the M1553B transceiver module and the transceiver message stack inside the M1553B transceiver module through the bus interface module of the M1553B transceiver module according to the configuration information of the address segment; After the configuration is completed, the M1553B controller starts the transmission, performs Manchester encoding on the data from the SOC system bus, and transmits it to the channel module of the M1553B transceiver module; The M1553B transceiver module determines from the channel module that there is valid transmission, performs corresponding level conversion on the data, and then transmits it to the outside of the SOC chip through the external channel.

7. The method for processing the M1553B interactive interface on the SOC chip according to claim 5, characterized in that: Also includes the steps: If it is determined that the address segment is a transceiver configuration segment, the arbitrator module configures the registers inside the M1553B transceiver module and the transceiver message stack inside the M1553B transceiver module through the bus interface module of the M1553B transceiver module according to the configuration information of the address segment; at the same time, the arbitrator module configures the registers inside the M1553B controller and the controller message stack inside the M1553B controller through the bus interface module of the M1553B controller according to the configuration information of the address segment; After the configuration is completed, the M1553B transceiver module determines whether there is valid transmission from the external channel; If there is a valid transmission, the M1553B transceiver module performs corresponding level conversion on the data received from the external channel and sends it to the M1553B controller through the channel module; The M1553B controller performs Manchester decoding on the received data and sends the data to the SOC system bus.

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