Universal chip clock observation logic circuit, system and method

Abstract

The invention relates to a universal chip clock observation logic circuit, system and method, which combines the technology and test of clock observation logic, selects an input clock source by configuring a pin of a clock selection module, and determines a clock frequency division coefficient by configuring a pin of a clock frequency division module according to a clock frequency. And finally, clock output control is completed through a clock control module, and an output observation port multiplexes a clock output pin of the chip to be tested to support observation of output clock frequency. The observation output clock not only can be a main frequency clock of the chip to be tested, but also can be used for observing clocks of high-speed or low-speed parts in the chip to be tested through configuration, so that independent observation of module clocks in the chip to be tested can be realized, and a problem part or configuration can be directly positioned according to an observation result; the situation that the problem cannot be checked due to clock errors existing in the chip testing process is avoided, and therefore the testing efficiency is greatly improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit design, and relates to a universal chip clock observation logic circuit, system and method. Background Art

[0002] In the design of a multi-clock chip system, the clock generation module and the configuration module provide different clock frequencies for the entire chip according to the design requirements; during the manufacturing process, the clock generation module and the configuration module may have faults or unreasonable clock configuration, resulting in the generated clock frequency not meeting the design expectations, and thus causing the chip to fail to work properly. At present, ATE (AUTOMATIC TEST EQUIPMENT) machines or boards are generally used to test the chip under test. The ATE machine compares the measured chip output signal with the expected output signal to determine or evaluate whether the circuit function and performance of the chip under test are normal. At present, the optimal clock observation frequency of the ATE machine test is within 100 megahertz (MHz), but the actual clock frequency of the chip under test is several times or even dozens of times the optimal frequency; for chip failures caused by abnormal clock frequency, it is difficult to troubleshoot and the causes are more complicated. The clock generation module and the configuration module involve more logic, and only a single clock output observation port can no longer effectively diagnose the fault. Therefore, how to avoid the chip from having clock errors during the test process and being unable to troubleshoot the problem to improve the test efficiency has become a technical problem to be solved. Summary of the invention

[0003] In response to the problems existing in the above-mentioned traditional technologies, the present invention proposes a universal chip clock observation logic circuit, an ATE machine testing system and a universal chip clock observation method, which can avoid the situation where the chip has clock errors during the testing process and the problem cannot be troubleshooted, thereby improving the testing efficiency.

[0004] In order to achieve the above objectives, the embodiments of the present invention adopt the following technical solutions: On the one hand, a universal chip clock observation logic circuit is provided, comprising a clock selection module, a clock frequency division module, a clock control module and an output observation port; The output observation port multiplexes the clock output pin of the chip under test, the output end of the clock selection module is connected to the clock frequency division module and the clock control module respectively, the output end of the clock frequency division module is connected to the clock control module, and the output end of the clock control module is connected to the output observation port; The clock selection module is used to select the input clock source inside the chip under test through configuration and output the currently selected clock. The clock division module is used to switch the clock division factor to the currently configured clock division factor through configuration, divide the clock output by the clock selection module according to the currently configured clock division factor and output the divided clock. The clock control module is used to control the clock entering the output observation port to be the clock output by the clock selection module or the divided clock output by the clock division module. The output observation port is used to observe the output clock.

[0005] On the other hand, an ATE machine test system is also provided, including an ATE machine, a chip to be tested and a universal chip clock observation logic circuit, the chip to be tested is connected to the ATE machine through the universal chip clock observation logic circuit, the universal chip clock observation logic circuit includes a clock selection module, a clock frequency division module, a clock control module and an output observation port, the output observation port multiplexes the clock output pin of the chip to be tested, the output end of the clock selection module is respectively connected to the clock frequency division module and the clock control module, the output end of the clock frequency division module is connected to the clock control module, and the output end of the clock control module is connected to the output observation port; The clock selection module is used to select the input clock source inside the chip under test through configuration and output the currently selected clock. The clock division module is used to switch the clock division coefficient to the currently configured clock division coefficient through configuration. The clock output by the clock selection module is divided according to the currently configured clock division coefficient and then the divided clock is output. The clock control module is used to control the clock entering the output observation port to be the clock output by the clock selection module or the divided clock output by the clock division module. The output observation port is connected to the ATE machine, and the ATE machine is used to observe the output clock.

[0006] On the other hand, a universal chip clock observation method is provided. Based on the universal chip clock observation logic circuit or the ATE machine test system, the universal chip clock observation method comprises the following steps: Determine the configuration bit of the clock selection pin of the clock selection module to complete the clock frequency selection of the input clock source inside the chip to be tested; The frequency division selection bit of the clock frequency division module is configured according to the selected clock frequency to determine the clock frequency division coefficient; the clock frequency division coefficient is used to divide the clock frequency output by the clock selection module to a frequency of 100 MHz or less; Confirm the output clock source through the clock control module and output it to the output observation port; confirm that the output clock source is the clock output by the clock selection module or the divided clock output by the clock division module; By measuring the clock frequency output by the output observation port and comparing it with the expected clock frequency, it is determined whether the components inside the chip under test corresponding to the currently selected input clock source are normal.

[0007] One of the above technical solutions has the following advantages and beneficial effects: The above-mentioned universal chip clock observation logic circuit, system and method combine the technology of clock observation logic with testing, select the input clock source by configuring the pins of the clock selection module, configure the pins of the clock division module according to the clock frequency to determine the clock division coefficient, and finally complete the clock output control through the clock control module, and the output observation port reuses the clock output pins of the chip under test to support the observation of the output clock frequency. The observed output clock can not only be the main frequency clock of the chip under test, but also can be configured to observe the clocks of various high-speed or low-speed components in the chip under test, which can realize the separate observation of the module clock in the chip under test, so that the problem component or configuration can be directly located according to the observation results, avoiding the situation where the chip has clock errors during the test process and cannot be troubleshooted, thereby greatly improving the test efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0009] Figure 1 It is a schematic diagram of the module structure of a universal chip clock observation logic circuit in one embodiment; Figure 2 A schematic diagram of the structure of an ATE machine test system in one embodiment; Figure 3 Schematic diagram of a flow chart of a general chip clock observation method in an embodiment. DETAILED DESCRIPTION

[0010] In order to make the purpose, technical scheme and advantages of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and Examples. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by those skilled in the art of the present invention. The terms used in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0011] It should be noted that the reference to "embodiment" in this article means that the specific features, structures or characteristics described in conjunction with the embodiment may be included in at least one embodiment of the present invention. The presentation of this phrase at various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It will be appreciated by those skilled in the art that the embodiments described herein may be combined with other embodiments. The term "and / or" used in the specification and appended claims of the present invention refers to any combination of one or more of the associated listed items and all possible combinations, and includes these combinations.

[0012] The following will describe the implementation of the present invention in detail with reference to the accompanying drawings in the embodiment diagram of the present invention.

[0013] In one embodiment, Figure 1 As shown, a general chip clock observation logic circuit is provided, including a clock selection module, a clock frequency division module, a clock control module and an output observation port. The output observation port reuses the clock output pin of the chip to be tested. The output end of the clock selection module is respectively connected to the clock frequency division module and the clock control module, the output end of the clock frequency division module is connected to the clock control module, and the output end of the clock control module is connected to the output observation port. The clock selection module is used to select the input clock source inside the chip to be tested by configuration and output the clock currently selected for use. The clock frequency division module is used to switch the clock frequency division coefficient to the currently configured clock frequency division coefficient by configuration, and divide the clock output by the clock selection module according to the currently configured clock frequency division coefficient and then output the divided clock. The clock control module is used to control the clock entering the output observation port to be the clock output by the clock selection module or the divided clock output by the clock frequency division module, and the output observation port is used to observe the output clock.

[0014] It can be understood that this embodiment combines the technology of clock observation logic with testing, and provides a general chip clock observation logic design scheme. Through the clock selection module, clock frequency division module and clock control module, clock control and output observation are completed, and the pin multiplexing design can flexibly configure the clock output frequency, so as to avoid the situation where the chip has clock errors during the test process and the problem cannot be found, thereby improving the test efficiency. For example, when the module clock frequency of the chip to be tested is 1.2GHz, the tester completes the clock selection through the clock selection module, and configures the clock frequency division coefficient to 12 by configuring the register, so as to realize clock control and observe whether the output clock is consistent with the expected clock frequency (such as 100MHz).

[0015] Specifically, the designed universal chip clock observation logic circuit includes a clock selection module (i.e., CLK_SEL), a clock division module (i.e., CLK_DIV), a clock control module (i.e., clock control) and an output observation port, wherein the output observation port multiplexes the clock output pin of the chip under test (denoted as PAD, and the clock outputted therethrough is CLK_OUT).

[0016] The clock selection module is used to select the input clock source (for example, the input clock CLKIN_n of the chip under test, where n is the number of clock sources of the chip under test), and receives clocks from some or all internal modules of the chip under test, where CLK_SEL[n:0] is the clock selection signal provided to the clock selection module, and a corresponding clock source required for the current test can be selected by inputting any clock selection signal. The clock selection module consists of a control module, a configuration module, and an output module. By configuring the register bits corresponding to the configuration modules in the clock selection module, the control module can switch the input clock source and output the switched clock from the output module. The configuration module can be a register module with more than 32 bits, and each register bit is used to configure the control module in the clock selection module to switch to each input clock source. The number of register bits can be selected according to the number of input clock sources that need to be tested in the chip under test.

[0017] The clock frequency division module is used to configure the clock frequency division coefficient, which includes a configuration module, a frequency division module and an output module. DIV_SEL[m:0] is a clock frequency division coefficient selection signal provided to the clock frequency division module, which is used to configure the register bit corresponding to the configuration module in the clock frequency division module, so that the frequency division module divides the clock output by the clock selection module according to the switched clock frequency division coefficient to obtain the divided clock, and then outputs the divided clock through the output module in the clock frequency division module. The configuration module of the clock frequency division module can also be a register module with more than 32 bits. Each register bit is used to configure the frequency division module in the clock frequency division module to switch to the currently configured clock frequency division coefficient to perform clock division. The number of register bits can be selected according to the number of clock frequency division coefficients to be configured.

[0018] The clock control module is used to control whether the clock entering the output observation port is the (full frequency) clock output by the clock selection module or the divided frequency clock output by the clock frequency division module. The clock control module is composed of a selection module and an output module, and the output module is connected to the output observation port; wherein, MODE is the mode selection signal of the clock control module, which is used to instruct the selection module of the clock control module to select the clock entering the output observation port. The output observation port can be reused with the clock output pin of the chip under test, and is used to observe the output clock frequency during testing. The design and implementation of the above modules all follow the existing integrated circuit design specifications in this field, and are designed using the hardware resources (such as circuit logic and registers) on the integrated circuit according to the functional requirements of the above modules. The hardware resources used are controllable and the test configuration is flexible. It has an observation node (i.e., an output observation port) to facilitate the observation of the output clock; the design logic of the module is simple, and there is no need to consider the timing optimization problem of the chip under test; through the observation node and specific configuration, the clock of the specific components inside the chip under test can be observed separately, which can assist the ATE machine to quickly locate clock-related faults, improve test efficiency, and reduce test costs.

[0019] The above-mentioned universal chip clock observation logic circuit combines the technology of clock observation logic with testing, selects the input clock source by configuring the pins of the clock selection module, configures the pins of the clock division module according to the clock frequency to determine the clock division coefficient, and finally completes the clock output control through the clock control module, and the output observation port reuses the clock output pins of the chip under test to support the observation of the output clock frequency. The observed output clock can not only be the main frequency clock of the chip under test, but also can be configured to observe the clocks of various high-speed or low-speed components in the chip under test, which can realize the separate observation of the module clock in the chip under test, so that the problem component or configuration can be directly located according to the observation results, avoiding the situation where the chip has clock errors during the test process and cannot be troubleshooted, thereby greatly improving the test efficiency.

[0020] In one embodiment, the configuration module of the clock selection module is a 32-bit register module.

[0021] It can be understood that when the general chip clock observation logic circuit is tested: the first step is to determine the configuration (register) bit of the CLK_SEL (clock selection) pin of the clock selection module to complete the clock frequency selection of the input clock CLKIN_n. The description of the CLK_SEL register (configuration module) of the clock selection module is shown in Table 1. After the configuration is completed, enter the second step.

[0022] Table 1

[0023] Among them, R / W means readable and writable.

[0024] In one embodiment, the configuration module used by the clock frequency division module is a 32-bit register module.

[0025] The second step is to configure the DIV_SEL (division selection) bit of the DIV_SEL register (configuration module) of the clock division module according to the selected clock frequency, and determine the clock division coefficient to divide the clock frequency to 100MHz and below. The description of the DIV_SEL register is shown in Table 2: Table 2

[0026] In the third step, the clock control module confirms the output clock source and outputs it to the output observation port (i.e., the clock output pin PAD of the multiplexed chip under test).

[0027] The fourth step, during the test, is to measure the clock frequency output by the chip under test and compare it with the expected clock frequency to determine whether the components corresponding to the currently selected clock source are normal, such as but not limited to determining whether the currently tested phase-locked loop oscillates normally, whether the module clock configuration is normal, and whether the module clock is working normally.

[0028] In one embodiment, Figure 2 As shown, an ATE machine test system 200 is also provided, including an ATE machine 25, a chip to be tested 21 and a universal chip clock observation logic circuit 23. The chip to be tested 21 is connected to the ATE machine 25 through the universal chip clock observation logic circuit 23. The universal chip clock observation logic circuit 23 includes a clock selection module, a clock frequency division module, a clock control module and an output observation port, and the output observation port multiplexes the clock output pin of the chip to be tested 21. The output end of the clock selection module is respectively connected to the clock frequency division module and the clock control module, the output end of the clock frequency division module is connected to the clock control module, and the output end of the clock control module is connected to the output observation port. The clock selection module is used to select the input clock source inside the chip to be tested 21 by configuration and output the clock currently selected for use. The clock frequency division module is used to switch the clock frequency division coefficient to the currently configured clock frequency division coefficient by configuration, and divide the clock output by the clock selection module according to the currently configured clock frequency division coefficient and output the divided clock. The clock control module is used to control the clock entering the output observation port to be the clock output by the clock selection module or the divided clock output by the clock frequency division module. The output observation port is connected to the ATE machine 25, and the ATE machine 25 is used to observe the output clock.

[0029] The above-mentioned ATE machine test system 200 combines the technology of clock observation logic with the test, selects the input clock source by configuring the pins of the clock selection module, configures the pins of the clock division module according to the clock frequency to determine the clock division coefficient, and finally completes the clock output control through the clock control module, and the output observation port reuses the clock output pins of the chip under test 21 to support the observation of the output clock frequency. The observed output clock can not only be the main frequency clock of the chip under test 21, but also can be configured to observe the clocks of various high-speed or low-speed components in the chip under test 21, so as to realize the separate observation of the module clock in the chip under test 21, so that the problem component or configuration can be directly located according to the observation results, avoiding the situation that the chip has a clock error during the test process and the problem cannot be found, thereby greatly improving the test efficiency.

[0030] In one embodiment, the configuration module used by the clock selection module is a 32-bit register module.

[0031] In one embodiment, the configuration module used by the clock frequency division module is a 32-bit register module.

[0032] In one embodiment, a general chip clock observation method is further provided, based on the general chip clock observation logic circuit of any of the above embodiments or the ATE machine test system 200 of any of the above embodiments, such as Figure 3 As shown, the universal chip clock observation method may include the following processing steps S10 and S16: S10, determining the configuration bit of the clock selection pin of the clock selection module, and completing the clock frequency selection of the input clock source inside the chip to be tested; S12, configuring the frequency division selection bit of the clock frequency division module according to the selected clock frequency, and determining the clock frequency division coefficient; the clock frequency division coefficient is used to divide the clock frequency output by the clock selection module to a frequency of 100 MHz or less; S14, confirming the output clock source through the clock control module and outputting it to the output observation port; confirming that the output clock source is the clock output by the clock selection module or the divided clock output by the clock division module; S16, by measuring the clock frequency output by the output observation port and comparing it with the expected clock frequency, it is determined whether the components inside the chip to be tested corresponding to the currently selected input clock source are normal.

[0033] The above-mentioned general chip clock observation method combines the technology of clock observation logic with testing, selects the input clock source by configuring the pins of the clock selection module, configures the pins of the clock division module according to the clock frequency to determine the clock division coefficient, and finally completes the clock output control through the clock control module, and the output observation port reuses the clock output pins of the chip under test to support the observation of the output clock frequency. The observed output clock can not only be the main frequency clock of the chip under test, but also can be configured to observe the clocks of various high-speed or low-speed components in the chip under test, which can realize the separate observation of the module clock in the chip under test, so that the problem component or configuration can be directly located according to the observation results, avoiding the situation where the chip has clock errors during the test process and cannot be troubleshooted, thereby greatly improving the test efficiency.

[0034] For the specific explanation and limitation of the above-mentioned universal chip clock observation method, please refer to the corresponding limitation of the universal chip clock observation logic circuit in the above text, which will not be repeated here.

[0035] It should be understood that although Figure 3 The steps in the method are shown in sequence as indicated by the arrows, but the steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of the steps, and the steps can be executed in other orders. Figure 3 At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequentially, but can be executed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.

[0036] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided by the present invention can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus dynamic random access memory (RambusDRAM, referred to as RDRAM) and interface dynamic random access memory (DRDRAM).

[0037] The technical features of the above embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0038] The above embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of protection of the invention. It should be pointed out that, for those of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present invention, which all belong to the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be subject to the attached claims.

Claims

1. A universal chip clock observation logic circuit, characterized in that: It includes a clock selection module, a clock frequency division module, a clock control module and an output observation port; The output observation port multiplexes the clock output pin of the chip to be tested, the output end of the clock selection module is respectively connected to the clock frequency division module and the clock control module, the output end of the clock frequency division module is connected to the clock control module, and the output end of the clock control module is connected to the output observation port; The clock selection module is used to select the input clock source inside the chip under test through configuration and output the clock currently selected for use. The clock division module is used to switch the clock division coefficient to the currently configured clock division coefficient through configuration, divide the clock output by the clock selection module according to the currently configured clock division coefficient and output the divided clock. The clock control module is used to control the clock entering the output observation port to be the clock output by the clock selection module or the divided clock output by the clock division module, and the output observation port is used to observe the output clock.

2. The universal chip clock observation logic circuit according to claim 1, characterized in that: The configuration module adopted by the clock selection module is a 32-bit register module.

3. The universal chip clock observation logic circuit according to claim 1 or 2, characterized in that: The configuration module used by the clock frequency division module is a 32-bit register module.

4. An ATE machine test system, characterized in that: It includes an ATE machine, a chip to be tested and a universal chip clock observation logic circuit, wherein the chip to be tested is connected to the ATE machine through the universal chip clock observation logic circuit, the universal chip clock observation logic circuit includes a clock selection module, a clock frequency division module, a clock control module and an output observation port, the output observation port multiplexes the clock output pin of the chip to be tested, the output end of the clock selection module is respectively connected to the clock frequency division module and the clock control module, the output end of the clock frequency division module is connected to the clock control module, and the output end of the clock control module is connected to the output observation port; The clock selection module is used to select the input clock source inside the chip to be tested through configuration and output the clock currently selected for use. The clock division module is used to switch the clock division coefficient to the currently configured clock division coefficient through configuration, and divide the clock output by the clock selection module according to the currently configured clock division coefficient and then output the divided clock. The clock control module is used to control the clock entering the output observation port to be the clock output by the clock selection module or the divided clock output by the clock division module. The output observation port is connected to the ATE machine, and the ATE machine is used to observe the output clock.

5. The ATE machine test system according to claim 4, characterized in that: The configuration module adopted by the clock selection module is a 32-bit register module.

6. The ATE machine test system according to claim 4 or 5, characterized in that: The configuration module used by the clock frequency division module is a 32-bit register module.

7. A universal chip clock observation method, characterized in that: Based on the universal chip clock observation logic circuit according to any one of claims 1 to 3 or the ATE machine test system according to any one of claims 4 to 6, the universal chip clock observation method comprises the steps of: Determine the configuration bit of the clock selection pin of the clock selection module to complete the clock frequency selection of the input clock source inside the chip under test; Configure the frequency division selection bit of the clock frequency division module according to the selected clock frequency to determine the clock frequency division coefficient; The clock division coefficient is used to divide the clock frequency output by the clock selection module to a frequency of 100MHz or less; Confirm the output clock source through the clock control module and output it to the output observation port; confirm that the output clock source is the clock output by the clock selection module or the divided clock output by the clock division module; By measuring the clock frequency outputted by the output observation port and comparing it with the expected clock frequency, it is determined whether the components inside the chip to be tested corresponding to the currently selected input clock source are normal.

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