Clock tree verification method and device, computer readable storage medium and computing equipment

Abstract

The invention provides a clock tree verification method and device, a computer readable storage medium and computing device.The clock tree verification method comprises the steps that a connection reference model is constructed, and the connection reference model comprises information of clocks in a clock tree, the connection relation between the clocks and the initial value of a control signal; the information of the clock comprises a reference period and a reference burr expected value of the clock, and each control signal is used for controlling a connection relation between at least one clock; randomly updating the value of the at least one control signal, and updating the reference period and the reference burr expected value according to the updated value of the at least one control signal; and detecting each clock according to the updated reference period and the reference burr expected value. The invention provides a scheme for improving clock tree verification convenience and accuracy.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and in particular to a clock tree verification method and apparatus, a computer-readable storage medium, and a computing device. Background Art

[0002] A clock tree is usually set up in a system on chip (SoC). The clock tree can generate clock signals with different frequencies to meet the clock signal requirements of different devices. Figure 1 As shown in the figure, it is a mesh structure built by many buffer units, with one source point and multiple endpoints. The source point of the clock tree is generally connected to the clock input of the integrated circuit. The endpoint of the clock tree is generally connected to the clock input of the register of the internal module of the integrated circuit. The source point and the endpoint of the clock tree are connected by a tree-like mesh structure built by multiple levels of buffer units.

[0003] The clock design in the system on chip is very complex. The output of one clock node may serve as the input of another or several clock nodes, thus forming a clock tree with a tree-like structure. Figure 1 A clock tree is shown, wherein the upstream clock clkin can be selectively connected to a clock switch (MUX), a frequency divider (frequency divider) or a gating unit (clock gate) component to obtain a downstream clock clkout. In the prior art, clock tree verification is an important part of SoC verification.

[0004] However, the traditional clock tree verification process needs to list the reference period and reference glitch expected value of the input clock of each module. The intermediate clock nodes of the complex clock tree are usually not tested, and the verification process is complicated and the detection efficiency is low. Summary of the invention

[0005] The present application provides a clock tree verification method and device, and provides a solution for improving the convenience and accuracy of clock tree verification.

[0006] In order to achieve the above objectives, this application provides the following technical solutions:

[0007] In a first aspect, a clock tree verification method is provided, the clock tree verification method comprising: constructing a connection reference model, the connection reference model comprising information of each clock in the clock tree, a connection relationship between each clock, and an initial value of a control signal, the clock information comprising a reference period and a reference glitch expected value of the clock, each control signal being used to control the connection relationship between at least one clock; randomly updating the value of at least one control signal, and updating the reference period and the reference glitch expected value according to the updated value of the at least one control signal; and detecting each clock according to the updated reference period and the reference glitch expected value.

[0008] Optionally, the at least one control signal includes at least one of the following: a selection signal, a frequency division control signal and an enable signal, wherein the selection signal is used to indicate the parent clock, the frequency division control signal is used to indicate the frequency division method, and the enable signal is used to indicate whether the corresponding clock is valid.

[0009] Optionally, the randomly updating the value of at least one control signal and updating the reference period and reference glitch expected value according to the at least one control signal include: randomly updating the value of at least one selection signal and / or at least one frequency division control signal; updating the reference period and the reference glitch expected value.

[0010] Optionally, the updated reference period and reference glitch expected value updated according to the at least one control signal include: determining the relevant first sub-clock according to the updated selection signal and the updated frequency division control signal, and pausing the detection of the first sub-clock; calculating the reference period and reference glitch expected value of each clock according to the reference period of the parent clock indicated by the updated selection signal and the updated frequency division control signal; and resuming the detection of all clocks.

[0011] Optionally, the clock tree verification method also includes: in response to updating the enable signal to control the gating unit to shut down, pausing the detection of the clock related to the enable signal; in response to updating the enable signal to control the gating unit to turn on, resuming the detection of the clock related to the enable signal to detect the working status of the gating unit.

[0012] Optionally, constructing a connection reference model includes: constructing an array, the array including at least one of the following: a child clock queue, a parent clock queue, a selection signal, a frequency division control signal, an enable signal, a reference cycle, and a reference glitch expected value; assigning values ​​to the array according to the structure of the clock tree and input information.

[0013] Optionally, constructing the array includes: adding information of downstream sub-clocks connected to each input clock source to a sub-clock queue of each input clock source; and adding information of a corresponding parent clock to a parent clock queue of each sub-clock.

[0014] Optionally, constructing the array includes: updating the selection signal and the division control signal according to the selector and divider components present in the upstream connection of the clock; setting the reference period and reference glitch expected values ​​corresponding to all input clock sources; for each level of sub-clock, obtaining the reference period of the corresponding parent clock from the parent clock queue according to the selection signal, and then updating the reference period and reference glitch expected value corresponding to each sub-clock according to the division control signal.

[0015] In a second aspect, a clock tree verification device is provided, which includes: a construction module for constructing a connection reference model, wherein the connection reference model includes information of each clock in the clock tree, a connection relationship between each clock, and an initial value of a control signal, wherein the clock information includes a reference period and a reference glitch expected value of the clock, and each control signal is used to control the connection relationship between at least one clock; an update module for randomly updating the value of at least one control signal, and updating the reference period and the reference glitch expected value according to the updated value of the at least one control signal; and a verification module for detecting each clock according to the updated reference period and the reference glitch expected value.

[0016] According to a third aspect, a computer-readable storage medium is provided, on which a computer program is stored. The computer program is executed by a processor to execute any one of the methods provided in the first aspect.

[0017] In a fourth aspect, a clock tree verification device is provided, comprising a memory and a processor, wherein the memory stores a computer program executable on the processor, and the processor executes the computer program to execute any one of the methods provided in the first aspect.

[0018] According to a fifth aspect, a computer program product is provided, on which a computer program is stored, and the computer program is executed by a processor to execute any one of the methods provided in the first aspect.

[0019] In a sixth aspect, an embodiment of the present application further provides a chip having a computer program stored thereon, and when the computer program is executed by the chip, the steps of the above method are implemented.

[0020] In the seventh aspect, an embodiment of the present application also provides a system chip, which is applied to a terminal, and the chip system includes at least one processor and an interface circuit, the interface circuit and the at least one processor are interconnected through lines, and the at least one processor is used to execute instructions to execute any one of the methods provided in the first aspect.

[0021] Compared with the prior art, the technical solution of this application has the following beneficial effects:

[0022] In the technical solution of the present application, a connection reference model is constructed, and the connection reference model includes the information of each clock in the clock tree, the connection relationship between each clock, and the initial value of the control signal. The clock information includes the reference period and reference glitch expected value of the clock. Each control signal is used to control the connection relationship between at least one clock; the value of at least one control signal is randomly updated, and the reference period and reference glitch expected value are updated according to the updated value of at least one control signal; and each clock is detected according to the updated reference period and reference glitch expected value. The technical solution of the present application constructs a connection reference model, takes the information of each node in the clock tree in the chip as input, and completes the automated monitoring and comparison of all clock nodes in the complex clock tree; and automatically updates information such as clock frequency and glitch expected value during the verification process to ensure that the chip clock tree meets the design intent and the verification process is simple.

[0023] Furthermore, the technical solution of the present application can timely shut down the detection of clock cycles and glitches according to the update of control signals, such as the enable signal to control the shutdown of the gating unit, the update of the selection signal or the frequency division control signal, wait for the update of the reference clock cycle and the reference glitch expected value, and then restore the clock cycle and glitch detection to ensure the correctness of the clock tree verification. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It is a schematic diagram of the structure of a clock tree in the prior art;

[0025] Figure 2 is a flowchart of a clock tree verification method provided by an embodiment of the present application;

[0026] Figure 3 It is a schematic diagram of the structure of a clock tree provided in an embodiment of the present application;

[0027] Figure 4 is a flowchart of another clock tree verification method provided by an embodiment of the present application;

[0028] Figure 5 is a flowchart of another clock tree verification method provided by an embodiment of the present application;

[0029] Figure 6 It is a structural schematic diagram of a clock tree verification device provided in an embodiment of the present application;

[0030] Figure 7 It is a schematic diagram of the hardware structure of a clock tree verification device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0031] As described in the background technology, the traditional clock tree verification process needs to list the reference period and reference glitch expected value of the input clock of each module. The intermediate clock nodes of the complex clock tree are usually not tested, and the verification process is complicated and the detection efficiency is low.

[0032] In addition, the clock tree verification process requires manual pause of detection and update of reference expected values, which further increases the complexity and tediousness of the verification process.

[0033] The technical solution of the present application constructs a connection reference model, takes the information of each node in the clock tree in the chip as input, and completes the automated monitoring and comparison of all clock nodes in the complex clock tree; and automatically updates information such as clock frequency and glitch expected value during the verification process to ensure that the chip clock tree meets the design intent and the verification process is simple.

[0034] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the specific embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0035] The embodiment of the present invention provides a clock tree verification method, referring to Figure 2 , the following is a detailed description through specific steps.

[0036] It is understandable that, in a specific implementation, the clock tree verification method can be implemented in the form of a software program, and the software program runs in a processor integrated inside a chip or a chip module. The method can also be implemented in the form of software combined with hardware, which is not limited in this application.

[0037] In step 201, a connection reference model is constructed. The connection reference model includes information of each clock in the clock tree, connection relationships between each clock, and initial values ​​of control signals. The clock information includes a reference period and a reference glitch expected value of the clock. Each control signal is used to control the connection relationship between at least one clock.

[0038] In a specific implementation, the connection reference model can be constructed to verify the period and glitch expected value of each clock in the clock tree. The information of each clock includes the reference period and reference glitch expected value of each clock, and the connection relationship between clocks can include the upstream and downstream relationship of the clocks, such as the parent clock and its child clocks.

[0039] by Figure 1 Taking the clock tree shown in the figure as an example, clkin0 is regarded as the parent clock, clkout0 is a child clock of clkin0, and the parent clock can be connected to multiple components at the same time to derive multiple child clocks, such as Figure 1As shown, clkin0 has four sub-clocks clkout0, clkout1, clkout2, and clkout3. Due to the characteristics of the clock switch MUX switching and selecting the clock, the same sub-clock can belong to multiple parent clocks, such as Figure 1 As shown, clkout0 may also belong to parent clocks clkin0, clkin1, clkin2, and clkin3.

[0040] Specifically, the clock switch MUX can input a control signal, that is, a selection signal sel, for selecting the parent clock. The period of the sub-clock can be calculated by selecting the period of the currently connected parent clock according to the selection signal sel, and then combined with the frequency division method. The enable signal can control the turn-off or turn-on of the gate control unit GATE, so as to determine whether the sub-clock is disabled, that is, whether the sub-clock is valid.

[0041] The frequency division method referred to in the embodiments of the present application may also be referred to as a frequency division coefficient, such as 2-division, 4-division, etc.

[0042] It should be noted that the specific method for calculating the period of the sub-clock according to the period of the parent clock and the frequency division method can refer to the existing technology, and this application does not limit this.

[0043] Figure 3 Another clock tree structure is shown, in which one clock source can generate multiple sub-clocks. Specifically, the input clock source (clk source0, clk source1) is regarded as a level 0 clock, which is used as a parent clock to derive level 1 sub-clocks clk1 and clk2, and the sub-clocks can further derive level 2 clk3.

[0044] In specific implementation, a complete connection reference model can be established through the multi-level connection paths between clocks in the clock tree. It only needs to configure the period information of the input clock source (such as period and glitch expected values). The connection reference model can automatically calculate the period and glitch expected values ​​of the remaining clocks, thereby realizing automatic update of the information of all clocks in the connection reference model.

[0045] In step 202, the value of at least one control signal is randomly updated, and the reference period and the reference glitch expected value are updated according to the updated value of the at least one control signal.

[0046] In a specific implementation, after the connection reference model is constructed, each clock can be detected according to the connection reference model to verify whether the actual cycle of the clock is consistent with the reference cycle and whether the actual glitch expected value is consistent with the reference glitch expected value.

[0047] Specifically, since the control signal affects the connection relationship between clocks and thus affects the clock period and glitch expected value, when verifying the clock tree, the value of the control signal can also be randomly updated, and the connection reference model can be updated based on the updated control signal, that is, the reference period and reference glitch expected value of the clock are updated for clock detection.

[0048] In step 203, each clock is detected according to the updated reference period and the reference glitch expected value.

[0049] In a specific implementation, the actual period and the actual glitch expected value of each clock in the clock tree are obtained, and it is detected whether the actual period of each clock is consistent with the reference period of the clock, and whether the actual glitch expected value of each clock is consistent with the reference glitch expected value of the clock.

[0050] The embodiment of the present application builds a universal automated clock tree verification framework, and detects the period and burrs of each clock in real time during the simulation process, without the need for additional control, and the clock tree verification process is simple and easy to implement. In addition, the present application can detect each clock in the clock tree, achieving the comprehensiveness of clock tree verification.

[0051] It should be pointed out that the serial numbers of the steps in this embodiment do not limit the execution order of the steps.

[0052] In a non-limiting embodiment, the control signal includes at least one of the following: a selection signal, a frequency division control signal, and an enable signal. Figure 1 , the clock switch MUX can input the selection signal sel to select the parent clock, for example, select the parent clock clkin3. The divider DIVIDER inputs the division control signal divide to divide the input clock, for example, 2-division, 4-division, etc. The gate control unit GATE inputs the enable signal en. When the enable signal en controls the gate control unit GATE to turn on, the sub-clock clkout0 output by the gate control unit GATE is valid; when the enable signal en controls the gate control unit GATE to turn off, the sub-clock clkout0 output by the gate control unit GATE is invalid.

[0053] In a non-limiting embodiment, the connection reference model can be constructed by constructing an array. Figure 4 , Figure 4 A process of building a connection reference model is shown.

[0054] In step 401, an array is constructed. The array includes at least one of the following: a sub-clock queue, a parent clock queue, a selection signal, a frequency division control signal, an enable signal, a reference cycle, and a reference glitch expected value;

[0055] In the specific implementation, the array created can be of type clock_object. Each clock corresponds to an element in the array, and the element type is clock_object. The array contains the following types of data:

[0056] 1. The child clock queue (child queue) is used to store the identification information of all the child clocks connected downstream of the clock tree. The type is clock_object;

[0057] 2. Parent clock queue (parent queue), which is used to store the identification information of all parent clocks that may be connected to the upstream of the clock tree. When a clock switcher is connected, the parent clocks can be saved in the parent queue in the order in which the clock switcher selects the parent clocks. The type is clock_object;

[0058] 3. Select the signal sel to save the sel signal value of the clock mux connected upstream of the clock, indicating which clock in the parent queue is currently selected as the parent clock. The default value is 0, indicating that the clock mux is not connected or the first input clock of the clock mux is selected;

[0059] 4. The frequency division control signal divide saves the signal value of the frequency divider input connected to the upstream of the clock. The default value is 1, indicating no frequency division;

[0060] 5. Enable signal en, which saves the signal value input by the gate control unit connected upstream of the clock. The default value is 1, indicating that the clock is valid;

[0061] 6. Update signal updating, indicating the state of updating the clock cycle and glitch expected value, used to suspend clock detection;

[0062] 7. Reference period period, which indicates the expected value of the current period of the clock;

[0063] 8. Reference glitch expected value glitch indicates the current glitch expected value of the clock.

[0064] Specifically, taking the clock source as the starting point, the identifier of the connected downstream sub-clock is added to the sub-clock queue of each clock source, and the identifier of the parent clock is added to the parent clock queue of the sub-clock. Starting from level 0, the sub-clock queues and parent clock queues of all clocks are updated at each level, thereby building a complete clock tree connection reference model.

[0065] by Figure 3Take the clock tree shown in the figure as an example. First, add clocks clk1 and clk2 to the sub-clock queue of clock source clk source0, and add clock clk2 to the sub-clock queue of clock source clk source1. Then, add clock source clksource0 to the parent clock queue of clock clk1, and add clock sources clk source0 and clk source1 to the parent clock queue of clock clk2. Then, add clock clk3 to the sub-clock queue of clock clk1, add clock clk3 to the sub-clock queue of clock clk2, and add clocks clk1 and clk2 to the parent clock queue of clock clk3.

[0066] In step 402, values ​​are assigned to the array according to the structure of the clock tree and input information.

[0067] In the specific implementation, according to the clock switcher and divider components existing in the upstream connection of the clock, the selection signal sel and the division control signal divide in the array are updated; the reference period period and the reference glitch expected value glitch corresponding to all input clock sources are set, and starting from level 1, the sub-clock of each level obtains the period of the corresponding parent clock from the parent clock queue according to the selection signal sel, and then the reference period period and the reference glitch expected value glitch of the sub-clock in the array are updated according to the division control signal.

[0068] by Figure 3 Take the clock tree shown in the figure as an example. First, the default value of the selection signal sel of the clock clk1 is 1, and the default value of the frequency division control signal divide is 1. The selection signal sel and the frequency division control signal divide of clk2 are updated. The selection signal sel of clk2 is updated, and the default value of the frequency division control signal divide is 1. Then, the reference period period and the reference glitch expected value glitch of the clock sources clk source0 and clk source1 are set respectively. Then, the reference period period and the reference glitch expected value glitch of the clock clk1 are updated to be the same as the reference period period and the reference glitch expected value glitch of the clock source clk source0 respectively. Then, the selection signal of the clock clk2 selects the clock source clk source0 or clk source1 as the parent clock, and the reference period period and the reference glitch expected value glitch of the clock clk2 are calculated in combination with the frequency division control signal divide of the clock clk2. Then, the selection signal of clock clk3 selects clock clk1 or clk2 as the parent clock, and updates the reference period period and reference glitch expected value glitch of clock clk3 to be the same as the reference period and reference glitch expected value of its parent clock.

[0069] At this point, a complete connection reference model can be obtained.

[0070] The embodiment of the present application establishes a connection reference model for all upstream and downstream clocks. It only needs to set the period information of all input clock sources to automatically calculate the period and glitch information of all clocks (including clock sources) in the connection reference model, avoiding the complexity of setting the period and glitch information for each clock individually and the risk of information errors.

[0071] In addition, the embodiment of the present application determines all parameters required for clock tree detection by constructing an array, and can import text update information through a script to achieve adding, deleting and updating clock items to be detected, thereby reducing the complexity of updating the verification environment.

[0072] In a non-limiting embodiment, the connection reference model can be used to verify each clock in the clock tree. Figure 5 , Figure 5 The specific process of clock tree verification is shown.

[0073] In step 501, a related first sub-clock is determined according to an updated selection signal and an updated frequency division control signal, and detection of the first sub-clock is suspended.

[0074] In a specific implementation, one or more components in the clock tree are randomly configured each time, for example, one or more connected clock switches and / or one or more frequency dividers.

[0075] Specifically, it can be to randomly update one or more selection signals sel and frequency division control signals divide. At this time, the enable signal indicates that the clock is valid, and the changed selection signal sel and frequency division control signal divide are updated to the control signal corresponding to the first sub-clock connected to the clock switcher and / or the downstream of the frequency divider, and the update signal updating = 1; at this time, the detection of the above-mentioned first sub-clock is stopped, and the sub-clock identifiers in the sub-clock queue are traversed to find the first sub-clock in which the selection signal sel points to itself, and the detection of these first sub-clocks is also suspended. Then, according to the selection signal sel, the reference period period of the parent clock is selected from the parent clock queue, and the updated reference period and reference glitch expected value are calculated with the frequency division control signal divide, and then the reference period and reference glitch expected value of the first sub-clock are updated; after the update is completed, the detection of all clocks is resumed.

[0076] In step 502, the reference period and reference glitch expected value of each clock are calculated according to the reference period of the parent clock indicated by the updated selection signal and the updated frequency division control signal.

[0077] by Figure 3Taking the clock tree shown in FIG. 1 as an example, first, the reference cycle and reference glitch expected value of the clock source clk source0 need to be updated, and the clock detection of the clock source clk source0 is stopped. The detection of the clock clk1 is stopped. When the selection signal sel of the clock clk2 selects the clock source clk source0, the detection of the clock clk2 is stopped. Determine whether to stop the detection of clk3 according to the selection signal of the clock clk3. For example, if the selection signal of the clock clk3 selects the clock clk1, then the detection of the clock clk3 is stopped. Then, update the reference cycle and reference glitch expected value of clk source0, update the reference cycle and reference glitch expected value of the clock clk1, and when the selection signal sel of the clock clk2 selects the clock source clk source0, update the reference cycle and reference glitch expected value of the clock clk2. Determine whether to update the reference cycle and reference glitch expected value according to the selection signal of the clock clk3. For example, if the selection signal of the clock clk3 selects the clock clk1, the reference cycle and reference glitch expected value of the clock clk3 are updated.

[0078] In step 503, detection of all clocks is resumed.

[0079] The embodiment of the present application can detect in real time the selection signal of the clock switch or the division mode of the divider to which each clock may be connected, update the reference period and reference glitch expected value of the clock in real time, and automatically skip the clock detection during the update process to ensure the correctness of the clock tree verification.

[0080] Furthermore, the update of the enable signal can be used to detect whether the gating unit in the clock tree can work properly. Since the gating unit can affect the validity of the clock, the detection of the enable signal and the gating unit can be independent of the update of the selection signal and the frequency division control signal.

[0081] In a specific implementation, in response to the update enable signal to control the gate control unit to turn off, the detection of the clock related to the enable signal is suspended; in response to the update enable signal to control the gate control unit to turn on, the detection of the clock related to the enable signal is resumed to detect the working state of the gate control unit.

[0082] Specifically, the gate control unit components are randomly configured (for example, turned on or off), and accordingly, the enable signal will also change. When the enable signal en=0, the detection of the corresponding sub-clock is stopped, and the sub-clocks in the sub-clock queue are traversed to find the sub-clocks that the selection signal sel points to, and the detection of these sub-clocks is also suspended; when the enable signal en=1, the detection of the sub-clock is resumed.

[0083] Further, an error is reported when the actual cycle of the clock is inconsistent with the reference cycle, or an error is reported when the actual reference glitch expected value of the clock is inconsistent with the reference glitch expected value, for example, specific information of the inconsistent clock is given.

[0084] The embodiment of the present application can detect in real time whether the clock is flipped by detecting in real time the enable signal of the gating unit to which each clock may be connected, thereby further ensuring the correctness of the clock tree verification.

[0085] Please refer to Figure 6 , Figure 6 A clock tree verification device 60 is shown, and the clock tree verification device 60 may include:

[0086] A construction module 601 is used to construct a connection reference model, where the connection reference model includes information of each clock in the clock tree, a connection relationship between each clock, and an initial value of a control signal. The clock information includes a reference period and an expected reference glitch value of the clock. Each control signal is used to control a connection relationship between at least one clock.

[0087] An updating module 602, configured to randomly update a value of at least one control signal, and update a reference period and a reference glitch expected value according to the updated value of at least one control signal;

[0088] The verification module 603 is used to detect each clock according to the updated reference cycle and the reference glitch expected value.

[0089] In a specific implementation, the above-mentioned clock tree verification device 60 can correspond to a chip with a clock tree verification function in a computing device, such as a SOC, a baseband chip, etc.; or correspond to a chip module with a clock tree verification function in a computing device; or correspond to a chip module with a data processing function chip, or correspond to a computing device.

[0090] For other related descriptions about the clock tree verification device 60 , reference may be made to the related descriptions in the aforementioned embodiments, which will not be repeated here.

[0091] Regarding the various modules / units included in the various devices and products described in the above embodiments, they can be software modules / units, or hardware modules / units, or they can be partially software modules / units and partially hardware modules / units. For example, for various devices and products applied to or integrated in a chip, the various modules / units included therein can all be implemented in the form of hardware such as circuits, or at least some of the modules / units can be implemented in the form of software programs, which run on a processor integrated inside the chip, and the remaining (if any) modules / units can be implemented in the form of hardware such as circuits; for various devices and products applied to or integrated in a chip module, the various modules / units included therein can all be implemented in the form of hardware such as circuits, and different modules / units can be located in the same component of the chip module (such as a chip, circuit module, etc.) or in different components, or at least some of the modules / units can be implemented in the form of software programs. It is implemented in the form of a software program, which runs on a processor integrated inside the chip module, and the remaining (if any) modules / units can be implemented in hardware such as circuits; for various devices and products applied to or integrated in the terminal equipment, the various modules / units contained therein can be implemented in hardware such as circuits, and different modules / units can be located in the same component (for example, chip, circuit module, etc.) or in different components in the terminal equipment, or, at least some modules / units can be implemented in the form of a software program, which runs on a processor integrated inside the terminal equipment, and the remaining (if any) modules / units can be implemented in hardware such as circuits.

[0092] The embodiment of the present application also discloses a storage medium, which is a computer-readable storage medium, on which a computer program is stored, and when the computer program is run, the steps of the method shown in the above embodiment can be executed. The storage medium may include a read-only memory (ROM), a random access memory (RAM), a disk or an optical disk, etc. The storage medium may also include a non-volatile memory (non-volatile) or a non-transitory memory, etc.

[0093] Please refer to Figure 7 The embodiment of the present application also provides a hardware structure diagram of a clock tree verification device. The device includes a processor 701, a memory 702 and a transceiver 703.

[0094] Processor 701 may be a general-purpose central processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits for controlling the execution of the program of the present application. Processor 701 may also include multiple CPUs, and processor 701 may be a single-core (single-CPU) processor or a multi-core (multi-CPU) processor. The processor here may refer to one or more devices, circuits, or processing cores for processing data (such as computer program instructions).

[0095] The memory 702 may be a ROM or other types of static storage devices that can store static information and instructions, a RAM or other types of dynamic storage devices that can store information and instructions, or an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed optical disc, laser disc, optical disc, digital versatile disc, Blu-ray disc, etc.), a disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store the desired program code in the form of an instruction or data structure and can be accessed by a computer, and the embodiments of the present application do not impose any restrictions on this. The memory 702 may exist independently (in this case, the memory 702 may be located outside the device or inside the device), or it may be integrated with the processor 701. Among them, the memory 702 may contain a computer program code. The processor 701 is used to execute the computer program code stored in the memory 702, thereby realizing the method provided in the embodiments of the present application.

[0096] The processor 701, the memory 702 and the transceiver 703 are connected via a bus. The transceiver 703 is used to communicate with other devices or communication networks. Optionally, the transceiver 703 may include a transmitter and a receiver. The device used to implement the receiving function in the transceiver 703 can be regarded as a receiver, and the receiver is used to perform the receiving step in the embodiment of the present application. The device used to implement the sending function in the transceiver 703 can be regarded as a transmitter, and the transmitter is used to perform the sending step in the embodiment of the present application.

[0097] It should be understood that the term "and / or" in this article is only a description of the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article indicates that the associated objects before and after are in an "or" relationship.

[0098] The "plurality" appearing in the embodiments of the present application refers to two or more.

[0099] The first, second, etc. descriptions appearing in the embodiments of the present application are only used for illustration and distinction of the description objects. There is no order, nor do they indicate any special limitation on the number of devices in the embodiments of the present application, and cannot constitute any limitation on the embodiments of the present application.

[0100] The "connection" that appears in the embodiments of the present application refers to various connection methods such as direct connection or indirect connection to achieve communication between devices, and the embodiments of the present application do not impose any limitations on this.

[0101] The above embodiments may be implemented in whole or in part by software, hardware, firmware or any other combination thereof. When implemented using software, the above embodiments may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer programs are loaded or executed on a computer, the processes or functions described in the embodiments of the present application are generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from one website site, computer, server or data center to another website site, computer, server or data center by wired or wireless means.

[0102] It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0103] In the several embodiments provided in the present application, it should be understood that the disclosed methods, devices and systems can be implemented in other ways. For example, the device embodiments described above are merely schematic; for example, the division of the units is only a logical function division, and there may be other division methods in actual implementation; for example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0104] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0105] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may be physically included separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of hardware plus software functional units.

[0106] The above-mentioned integrated unit implemented in the form of a software functional unit can be stored in a computer-readable storage medium. The above-mentioned software functional unit is stored in a storage medium, including a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to perform some steps of the method described in each embodiment of the present application.

[0107] Although the present application is disclosed as above, the present application is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the protection scope of the present application shall be subject to the scope defined by the claims.

Claims

1. A clock tree verification method, characterized in that: include: Constructing a connection reference model, wherein the connection reference model includes information of each clock in the clock tree, connection relationships between each clock, and initial values ​​of control signals, wherein the information of the clock includes a reference period of the clock and an expected reference glitch value, and each control signal is used to control a connection relationship between at least one clock; Randomly updating the value of at least one control signal, and updating the reference period and the reference glitch expected value according to the updated value of the at least one control signal; Each clock is detected according to the updated reference period and reference glitch expected value.

2. The clock tree verification method according to claim 1, characterized in that: The at least one control signal includes at least one of the following: a selection signal, a frequency division control signal and an enable signal, wherein the selection signal is used to indicate a parent clock, the frequency division control signal is used to indicate a frequency division method, and the enable signal is used to indicate whether the corresponding clock is valid.

3. The clock tree verification method according to claim 2, characterized in that: The randomly updating the value of at least one control signal, and updating the reference period and the reference glitch expected value according to the at least one control signal after updating, comprises: Randomly updating the value of at least one selection signal and / or at least one frequency division control signal; Updated reference cycle and reference glitch expectations.

4. The clock tree verification method according to claim 2, characterized in that: The updated reference period and the reference glitch expected value updated according to the at least one control signal include: Determine the relevant first sub-clock according to the updated selection signal and the updated frequency division control signal, and suspend the detection of the first sub-clock; Calculating the reference period and reference glitch expected value of each clock according to the reference period of the parent clock indicated by the updated selection signal and the updated frequency division control signal; Restore detection of all clocks.

5. The clock tree verification method according to claim 2, characterized in that: Also includes: In response to updating the enable signal to control the gating unit to shut down, suspending the detection of the clock related to the enable signal; In response to updating the enable signal to control the gate control unit to be turned on, the detection of the clock related to the enable signal is restored to detect the working state of the gate control unit.

6. The clock tree verification method according to claim 1, characterized in that: The construction of the connection reference model comprises: Constructing an array, the array comprising at least one of the following: a sub-clock queue, a parent clock queue, a selection signal, a frequency division control signal, an enable signal, a reference cycle, and a reference glitch expected value; The array is assigned values ​​according to the structure of the clock tree and input information.

7. The clock tree verification method according to claim 6, characterized in that: The constructing the array includes: adding information of downstream sub-clocks connected to each input clock source to the sub-clock queue of each input clock source; Add the corresponding parent clock information to the parent clock queue of each sub-clock.

8. The clock tree verification method according to claim 6, characterized in that: The constructing the array includes: updating the selection signal and the frequency division control signal according to the selector and frequency divider components present in the clock upstream connection; Set the reference period and reference glitch expected value corresponding to all input clock sources; For each level of sub-clock, the reference period of the corresponding parent clock is obtained from the parent clock queue according to the selection signal, and then the reference period and reference glitch expected value corresponding to each sub-clock are updated according to the frequency division control signal.

9. A clock tree verification device, characterized in that: include: A construction module, used to construct a connection reference model, wherein the connection reference model includes information of each clock in the clock tree, a connection relationship between each clock, and an initial value of a control signal, wherein the clock information includes a reference period of the clock and an expected reference glitch value, and each control signal is used to control a connection relationship between at least one clock; An updating module, configured to randomly update a value of at least one control signal, and update a reference period and a reference glitch expected value according to the updated value of the at least one control signal; The verification module is used to detect each clock according to the updated reference cycle and reference glitch expected value.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the clock tree verification method according to any one of claims 1 to 8 are executed.

11. A computer program product comprising a computer program / instructions, characterized in that When the computer program / instruction is executed by a processor, the steps of the clock tree verification method according to any one of claims 1 to 8 are implemented.

12. A computing device comprising a memory and a processor, wherein the memory stores a computer program executable on the processor, wherein: When the processor runs the computer program, the processor performs the steps of the clock tree verification method according to any one of claims 1 to 8.

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