Memory device

Abstract

The application discloses a memory device, which comprises a first chip and a second chip, the first chip comprises a first storage array and a second storage array, the first storage array comprises at least one first storage block, the first storage block comprises a plurality of first word lines extending along a first direction and a plurality of first bit lines extending along a second direction, and the second storage array comprises at least one second storage block. By constructing a first global bit line sub-decoder block in a first overhead projection area formed by the first storage block and a second global bit line sub-decoder block in a second overhead projection area formed by the second storage block, the occupied area of the first chip and the second chip after stacking can be reduced, thereby reducing the occupied area of the memory device, and the minimization size of the memory device is facilitated.

Description

[0001] This application is a divisional application of the invention patent with application number "2021111607662", application date "2021.09.30", and title "Storage device and preparation method thereof". Technical Field

[0002] This application relates to the field of storage technology, specifically to a storage device and its fabrication method. Background Technology

[0003] like Figure 1 As shown, the storage device in the conventional technical solution includes multiple storage blocks 510, multiple local bit-line decoders 520, multiple word-line decoders 540, multiple global bit-line decoders 530, and other circuits 550. The construction regions of the storage blocks 510, the local bit-line decoders 520, the word-line decoders 540, the global bit-line decoders 530, and the other circuits 550 do not overlap. For example, the construction region of the local bit-line decoder 520 is located on one side of the construction region of the corresponding storage block 510, the word-line decoder 540 is located on the other side of the construction region of the corresponding local bit-line decoder 520 and / or the construction region of the storage block 510, and the construction region of the global bit-line decoder 530 is located between the construction regions of the corresponding local bit-line decoders 520 and the global bit-line decoder 530.

[0004] Specifically, such as Figure 2 As shown, along a certain direction, memory blocks 510 and local bit-line decoders 520 are arranged alternately. Following the last local bit-line decoder 520 are a global bit-line decoder 530 and multiple sense amplifiers 551. A word-line decoder 540 is located on the other side of each memory block 510. Each local bit-line decoder 520 is electrically connected to its corresponding memory block 510 and global bit-line decoder 530. The output of the global bit-line decoder 530 is electrically connected to its corresponding multiple sense amplifiers 551. Similarly, Figure 2 The construction regions of each memory block 510, each local bit line decoder 520, each global bit line decoder 530, each sense amplifier 551, and each word line decoder 540 do not overlap.

[0005] Thus, the storage devices in the aforementioned traditional technical solutions require a large space to integrate the various structural components, which is not conducive to minimizing the size of the storage devices.

[0006] It should be noted that the above description of the background technology is merely for the purpose of facilitating a clear and complete understanding of the technical solutions of this application. Therefore, it should not be assumed that the technical solutions mentioned above are known to those skilled in the art simply because they appear in the background technology of this application. Summary of the Invention

[0007] This application provides a storage device and a method for manufacturing the same, in order to alleviate the technical problem that storage devices require a large area.

[0008] In a first aspect, this application provides a memory device comprising a first chip and a second chip. The first chip includes a first memory array and a second memory array. The first memory array includes at least one first memory block, and the first memory block includes multiple first word lines extending along a first direction and multiple second bit lines extending along a second direction. The second memory array includes at least one second memory block, and the second memory block includes multiple second word lines extending along the first direction and multiple second bit lines extending along the second direction. The second chip is stacked on top of the first chip along a third direction, and the second chip includes a logic control circuit, which includes a first global bit line. The second chip includes a first global bit-line decoder and a second global bit-line decoder. The first global bit-line decoder is electrically connected to at least one first memory block, and the second global bit-line decoder is electrically connected to at least one second memory block. The second chip has a first top-view projection area of ​​a first memory block and a second top-view projection area of ​​a second memory block. The first global bit-line decoder block formed by the first global bit-line decoder is located within the first top-view projection area, and the second global bit-line decoder block formed by the second global bit-line decoder is located within the second top-view projection area. Furthermore, in a second direction, the second top-view projection area and the first top-view projection area are arranged sequentially.

[0009] In some embodiments, the first top-view projection area and the second top-view projection area are adjacent in the second direction.

[0010] In some embodiments, in the first direction, the length of the first global bit line decoder block is less than or equal to the length of the first top-view projection region; in the first direction, the length of the second global bit line decoder block is less than or equal to the length of the second top-view projection region.

[0011] In some embodiments, in a first direction, the length of the first top-view projection area is equal to the length of the second top-view projection area.

[0012] In some embodiments, the logic control circuit further includes an inductive amplifier circuit, which is electrically connected to the output of the first global bit line decoder and the output of the second global bit line decoder. The inductive amplifier circuit block formed by the inductive amplifier circuit is located in the first top-view projection area and / or the second top-view projection area.

[0013] In some embodiments, the inductive amplifier circuit includes a first inductive amplifier sub-circuit and a second inductive amplifier sub-circuit. The first inductive amplifier sub-circuit is electrically connected to the output of a first global bit line decoder, and the first inductive amplifier sub-circuit block formed by the first inductive amplifier sub-circuit is located within a first top-view projection area. The second inductive amplifier sub-circuit is electrically connected to the output of a second global bit line decoder, and the second inductive amplifier sub-circuit block formed by the second inductive amplifier sub-circuit is located within a second top-view projection area.

[0014] In some embodiments, the logic control circuit further includes a first local bitline decoder, which includes a first local bitline decoding unit and a second local bitline decoding unit electrically connected to a first global bitline decoder. The first local bitline decoding unit block formed by the first local bitline decoding unit and the second local bitline decoding unit block formed by the second local bitline decoding unit are both located within a first top-view projection area. In the second direction, the first global bitline decoder block is located between the first local bitline decoding unit block and the second local bitline decoding unit block.

[0015] In some embodiments, the local bit line decoder further includes a second local bit line sub-decoder. The second local bit line sub-decoder includes a third local bit line decoding unit and a fourth local bit line decoding unit electrically connected to the second global bit line sub-decoder. The third local bit line decoding unit block formed by the third local bit line decoding unit and the fourth local bit line decoding unit block formed by the fourth local bit line decoding unit are both located within the second top-view projection area. In the second direction, the second global bit line sub-decoder block is located between the fourth local bit line decoding unit block and the third local bit line decoding unit block.

[0016] In some embodiments, in the second direction, the fourth local bit line decoding unit block, the third local bit line decoding unit block, the second local bit line decoding unit block, and the first local bit line decoding unit block are arranged sequentially; in the second direction, the distance from the first global bit line sub-decoder block to the second local bit line decoding unit block is less than the distance from the first global bit line sub-decoder block to the first local bit line decoding unit block; in the second direction, the distance from the second global bit line sub-decoder block to the third local bit line decoding unit block is less than the distance from the second global bit line sub-decoder block to the fourth local bit line decoding unit block.

[0017] In some embodiments, the logic control circuit further includes a first word line decoding unit and a second word line decoding unit. The first word line decoding unit is electrically connected to a first memory block, and the first word line decoding unit block formed by the first word line decoding unit is located within a first top-view projection area. The second word line decoding unit is electrically connected to the first memory block, and the second word line decoding unit block formed by the second word line decoding unit is located within the first top-view projection area. In a first direction, the projection of the first word line decoding unit block and the projection of the second word line decoding unit block at least partially overlap. Both the first word line decoding unit block and the second word line decoding unit block are located between the first global bit line sub-decoder block and the first local bit line decoding unit block.

[0018] In some embodiments, in a first direction, the first sensing amplifier sub-circuit block is located between the first word line decoding unit block and the second word line decoding unit block; and in a second direction, the first sensing amplifier sub-circuit block is located between the first global bit line sub-decoder block and the first local bit line decoding unit block.

[0019] In some embodiments, in a first direction, the projection of the first inductive amplifier sub-circuit block at least partially overlaps with the projection of the first word line decoding unit block and / or the projection of the second word line decoding unit block.

[0020] In some embodiments, in the second direction, the projection of the first inductive amplifier sub-circuit block does not overlap with the projection of the first word line decoding unit block and / or the projection of the second word line decoding unit block.

[0021] In some embodiments, the logic control circuit further includes a third word line decoding unit and a fourth word line decoding unit. The third word line decoding unit is electrically connected to the second memory block, and the third word line decoding unit block formed by the third word line decoding unit is located within the second top-view projection area. The fourth word line decoding unit is electrically connected to the second memory block, and the fourth word line decoding unit block formed by the fourth word line decoding unit is located within the second top-view projection area. In a first direction, the projection of the third word line decoding unit block and the projection of the fourth word line decoding unit block at least partially overlap. Both the third word line decoding unit block and the fourth word line decoding unit block are located between the second global bit line sub-decoder block and the fourth local bit line decoding unit block.

[0022] In some embodiments, the first chip includes N memory blocks arranged sequentially along a second direction, the first memory array includes M memory blocks, and the second memory array includes NM memory blocks, where M is less than N, and M and N are both positive integers; the first top-view projection area is the projection area of ​​the Mth memory block on the second chip, and the second top-view projection area is the projection area of ​​the (M+1)th memory block on the second chip; the first global bit line sub-decoder is electrically connected to at least one of the first to the 2Mth local bit line decoding units, and the second global bit line sub-decoder is electrically connected to at least one of the 2M+1 to the 2Nth local bit line decoding units.

[0023] In some embodiments, M is equal to the rounded N / 2; and the second global bit line sub-decoder block, the 2M+1 local bit line decoding unit block formed by the 2M+1 local bit line decoding unit, the 2M local bit line decoding unit block formed by the 2M local bit line decoding unit, and the first global bit line sub-decoder block are arranged adjacent to each other in the second direction.

[0024] In some embodiments, the storage device further includes a plurality of first traces and a plurality of second traces, wherein the plurality of first traces are electrically connected to a first global bit line sub-decoder and a first local bit line decoding unit to a 2Mth local bit line decoding unit; and the plurality of second traces are electrically connected to a second global bit line sub-decoder and a 2M+1th local bit line decoding unit to a 2Nth local bit line decoding unit.

[0025] In some embodiments, in the second direction, the projection of the second inductive amplifier sub-circuit block does not overlap with the projection of the third word line decoding unit block and / or the projection of the fourth word line decoding unit block.

[0026] Secondly, this application provides a method for fabricating a memory device, comprising: constructing a first memory array and a second memory array on a first chip, wherein the first memory array includes at least one first memory block, the first memory block including a plurality of first word lines extending along a first direction and a plurality of second bit lines extending along a second direction; the second memory array includes at least one second memory block, the second memory block including a plurality of second word lines extending along the first direction and a plurality of second bit lines extending along the second direction; and constructing a logic control circuit on the second chip, the logic control circuit including a first global bit line decoder and a second global bit line decoder, the first global bit line... The sub-decoder is electrically connected to at least one first memory block, and the second global bit line sub-decoder is electrically connected to at least one second memory block. The second chip has a first top-view projection area of ​​a first memory block and a second top-view projection area of ​​a second memory block. The first global bit line sub-decoder block formed by the first global bit line sub-decoder is located within the first top-view projection area, and the second global bit line sub-decoder block formed by the second global bit line sub-decoder is located within the second top-view projection area. In a second direction, the second top-view projection area and the first top-view projection area are arranged sequentially. The second chip is stacked on top of the first chip in a third direction.

[0027] In some embodiments, the fabrication method further includes: constructing an inductive amplifier circuit in a logic control circuit; electrically connecting the inductive amplifier circuit to the output terminal of a first global bit line decoder and the output terminal of a second global bit line decoder; and configuring the inductive amplifier circuit block formed by the inductive amplifier circuit to be located in a first top-view projection area and / or a second top-view projection area.

[0028] In some embodiments, the fabrication method further includes: constructing a first inductive amplifier sub-circuit and a second inductive amplifier sub-circuit in an inductive amplifier circuit; electrically connecting the first inductive amplifier sub-circuit to the output terminal of a first global bit line decoder, and electrically connecting the second inductive amplifier sub-circuit to the output terminal of a second global bit line decoder; and configuring the first inductive amplifier sub-circuit block formed by the first inductive amplifier sub-circuit to be located in a first top-view projection area, and configuring the second inductive amplifier sub-circuit block formed by the second inductive amplifier sub-circuit to be located in a second top-view projection area.

[0029] The memory device and its fabrication method provided in this application reduce the area occupied by the stacked first chip and the second chip by constructing a first global bit line decoder block located in a first top-view projection area formed by a first memory block and a second global bit line decoder block located in a second top-view projection area formed by a second memory block, thereby reducing the area occupied by the memory device and helping to achieve the minimum size of the memory device.

[0030] Based on the fact that the decoder is set entirely within the projection range and the stacked structure of the two chips, the decoder can be vertically connected to the memory array without the need for additional lateral traces. Therefore, no trace space is required between the two sub-modules, which can further reduce the area of ​​the first and second chips. Attached Figure Description

[0031] The technical solution and other beneficial effects of this application will become apparent from the following detailed description of specific embodiments in conjunction with the accompanying drawings.

[0032] Figure 1 A schematic diagram showing the distribution of various parts of a storage device provided by a conventional technical solution.

[0033] Figure 2 A schematic diagram showing another distribution of the various parts of the storage device provided by a conventional technical solution.

[0034] Figure 3 This is a schematic diagram of the structural distribution of a storage device provided in an embodiment of this application.

[0035] Figure 4 This is a schematic diagram of another structural distribution of the storage device provided in an embodiment of this application.

[0036] Figure 5 for Figure 3 A schematic diagram of the structural distribution of the first inductive amplifier sub-circuit.

[0037] Figure 6 for Figure 5 A schematic diagram of the structural distribution of the second inductive amplifier sub-circuit.

[0038] Figure 7 This is a schematic flowchart illustrating the fabrication method of the storage device provided in the embodiments of this application. Detailed Implementation

[0039] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0040] In the description of this disclosure, word line decoders are also described as X-DECs, and bit line decoders can be described as bit line selectors, bit line multiplexers, or Y-MUXs for locating a majority of memory cells in a memory array for further read and write operations on the memory cells.

[0041] In the description of this disclosure, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicating orientation or positional relationships, are based on the orientation or positional relationships shown in the accompanying drawings and are only for the purpose of simplifying the description of this disclosure. They do not indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as limiting this disclosure. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this disclosure, "a plurality of" means two or more, unless otherwise explicitly specified.

[0042] In the description of this disclosure, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0043] In this disclosure, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through a third feature other than themselves. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0044] Please see Figures 3 to 7 ,like Figure 3As shown, this embodiment provides a memory device including a first chip 100 and a second chip 200. The first chip 100 includes a first memory array 10A and a second memory array 10B. The first memory array 10A includes at least one first memory block 11, which includes multiple first word lines extending along a first direction DR1 and multiple second bit lines extending along a second direction DR2. The second memory array 10B includes at least one second memory block, which includes multiple second word lines extending along the first direction DR1 and multiple second bit lines extending along the second direction DR2. The second chip 200 includes a logic control circuit, which includes a first global bit line. The first global bitline decoder 21 is electrically connected to at least one first memory block 11, and the second global bitline decoder 22 is electrically connected to at least one second memory block. The second chip 200 has a first top-view projection area of ​​a first memory block and a second top-view projection area of ​​a second memory block. The first global bitline decoder block formed by the first global bitline decoder 21 is located within the first top-view projection area, and the second global bitline decoder block formed by the second global bitline decoder 22 is located within the second top-view projection area. Furthermore, the second top-view projection area and the first top-view projection area are arranged sequentially in the second direction DR2.

[0045] It is understood that the memory device provided in this embodiment, by constructing a first global bit line decoder block located in a first top-view projection area formed by a first memory block and a second global bit line decoder block located in a second top-view projection area formed by a second memory block, can reduce the area occupied by the first chip 100 and the second chip 200 after stacking, thereby reducing the area occupied by the memory device and helping to achieve the minimum size of the memory device.

[0046] The logic control circuit includes a global bit-line decoder 20, which includes a first global bit-line sub-decoder 21 and a second global bit-line sub-decoder 22.

[0047] It should be noted that the at least partial overlap in this application can be partial overlap or full overlap. The first storage block can be any storage block in the first storage array 10A, for example, any one of the first storage block 11 to the Mth storage block 12. Specifically, the first storage block can be the Mth storage block 12. The second storage block can be any storage block in the second storage array 10B, for example, any one of the (M+1)th storage block 13 to the Nth storage block 14. Specifically, the second storage block can be the (M+1)th storage block 13. Wherein, M and N are both positive integers, and N is greater than M.

[0048] The first direction DR1 can be the extension direction of word lines. The second direction DR2 can be the extension direction of bit lines. The third direction DR3 can be the thickness direction of the memory device.

[0049] In one embodiment, the first top-view projection area and the second top-view projection area are adjacent in the second direction DR2. Adjacent means that the edges of the two projection areas are connected or close to each other. It can be understood that, in this way, the spatial distribution among the first global bit line decoder 21, the second global bit line decoder 22, and the inductive amplifier circuit 50 can be more compact, which facilitates the first global bit line decoder 21 and the second global bit line decoder 22 sharing the same inductive amplifier circuit 50, and can also reduce the electrical transmission distance from the inductive amplifier circuit 50 to the first global bit line decoder 21 and the second global bit line decoder 22.

[0050] In one embodiment, in the first direction DR1, the length of the first global bit line decoder block is less than or equal to the length of the first top-view projection region; in the first direction DR1, the length of the second global bit line decoder block is less than or equal to the length of the second top-view projection region.

[0051] In one embodiment, in the first direction DR1, the length of the first top-view projection area is equal to the length of the second top-view projection area.

[0052] In one embodiment, the logic control circuit further includes a sensing amplifier circuit 50, which is electrically connected to the output of the first global bit line decoder 21 and the output of the second global bit line decoder 22. The sensing amplifier circuit block formed by the sensing amplifier circuit 50 is located in the first top-view projection area and / or the second top-view projection area. It is understood that the memory device provided in this embodiment, by constructing the sensing amplifier circuit block within the first top-view projection area and / or the second top-view projection area, can further reduce the area occupied by the stacked first chip 100 and second chip 200, thereby reducing the area occupied by the memory device and helping to achieve a minimized size of the memory device; and it shortens the distance between the sensing amplifier circuit 50 and the two global bit line decoders, reducing latency.

[0053] It should be noted that in this embodiment, the first storage array 10A and the second storage array 10B can share the same inductive amplifier circuit 50.

[0054] like Figure 4As shown, in one embodiment, the inductive amplifier circuit 50 includes a first inductive amplifier sub-circuit 51, a second inductive amplifier sub-circuit 52, a third inductive amplifier sub-circuit 53, and a fourth inductive amplifier sub-circuit 54. The output terminal of the first global bit line decoder 21 is electrically connected to the first inductive amplifier sub-circuit 51 and the second inductive amplifier sub-circuit 52. The first inductive amplifier sub-circuit block formed by the first inductive amplifier sub-circuit 51 and the second inductive amplifier sub-circuit block formed by the second inductive amplifier sub-circuit 52 are both located within the first top-view projection area. The output terminal of the second global bit line decoder 22 is electrically connected to the third inductive amplifier sub-circuit 53 and the fourth inductive amplifier sub-circuit 54. The third inductive amplifier sub-circuit block formed by the third inductive amplifier sub-circuit 53 and the fourth inductive amplifier sub-circuit block formed by the fourth inductive amplifier sub-circuit 54 are both located within the second top-view projection area.

[0055] It is understood that in this embodiment, the first storage array 10A is electrically connected to the first inductive amplifier sub-circuit 51 and the second inductive amplifier sub-circuit 52 through the first global bit line decoder 21, and the second storage array 10B is electrically connected to the third inductive amplifier sub-circuit 53 and the fourth inductive amplifier sub-circuit 54 through the second global bit line decoder 22. Each storage array can use a separate set of inductive amplifier sub-circuits, so that the bit line readout operation of each storage array can be implemented independently.

[0056] In one embodiment, the logic control circuit further includes a local bitline decoder 30, which includes a first local bitline sub-decoder 30A. The first local bitline sub-decoder 30A is electrically connected to a first global bitline sub-decoder 21. The first local bitline sub-decoder 30A includes a first local bitline decoding unit 31 and a second local bitline decoding unit 32. The first local bitline decoding unit block formed by the first local bitline decoding unit 31 and the second local bitline decoding unit block formed by the second local bitline decoding unit 32 are both located within the first top-view projection area. In the second direction DR2, the first global bitline sub-decoder block is located between the first local bitline decoding unit block and the second local bitline decoding unit block.

[0057] It is understood that the memory device provided in this embodiment, by constructing the first local bit line decoding unit block and the second local bit line decoding unit block located in the first top-view projection area, can further reduce the area occupied by the first chip 100 and the second chip 200 after stacking, thereby reducing the space occupied by the memory device and helping to achieve the minimum size of the memory device.

[0058] In some embodiments, the first global bitline sub-decoder block, the first local bitline decoding unit block, and / or the second local bitline decoding unit block may be located in different layers of the same chip, and the first global bitline sub-decoder block and the first local bitline decoding unit block and / or the second local bitline decoding unit block may also at least partially overlap in the third-party direction DR3.

[0059] In some embodiments, the first global bit line sub-decoder block is located between the first local bit line decoding unit block and the second local bit line decoding unit block, and the first global bit line sub-decoder block does not overlap with the first local bit line decoding unit block and / or the second local bit line decoding unit block.

[0060] It should be noted that in this embodiment, each first memory block is electrically connected to a corresponding local bitline decoder. For example, the first memory block 11 can be electrically connected to the first local bitline decoding unit 31 and the second local bitline decoding unit 32. The local bitline decoder 30 also includes the Mth local bitline decoder 30B, which includes the 2M-1th local bitline decoding unit 33 and the 2Mth local bitline decoding unit 34. The Mth memory block 12 can be electrically connected to the 2M-1th local bitline decoding unit 33 and the 2Mth local bitline decoding unit 34. The first memory block can be any one of the first memory block 11 to the Mth memory block 12. When the first memory block is the Mth memory block 12, the first local bitline decoding unit can be the 2M-1th local bitline decoding unit 33; and the second local bitline decoding unit can be the 2Mth local bitline decoding unit 34. Similarly, the second storage block can be any one of the storage blocks from the (M+1)th storage block 13 to the Nth storage block 14.

[0061] In one embodiment, the local bit line decoder 30 further includes a second local bit line sub-decoder 30C, which is electrically connected to the second global bit line sub-decoder 22. The second local bit line sub-decoder 30C includes a third local bit line decoding unit 35 and a fourth local bit line decoding unit 36. The third local bit line decoding unit block formed by the third local bit line decoding unit 35 and the fourth local bit line decoding unit block formed by the fourth local bit line decoding unit 36 ​​are both located within the second top-view projection area. In the second direction DR2, the second global bit line sub-decoder block is located between the fourth local bit line decoding unit block and the third local bit line decoding unit block.

[0062] It should be noted that in this embodiment, each second memory block is electrically connected to a corresponding local bit-line decoder. For example, the second memory block can be electrically connected to the third local bit-line decoder unit 35 and the fourth local bit-line decoder unit 36. The second local bit-line decoder 30C can be the (M+1)th local bit-line decoder 30C, which includes the (2M+1)th local bit-line decoder unit 35 and the (2M+2)th local bit-line decoder unit 36. The (M+1)th memory block 13 can be electrically connected to the (2M+1)th local bit-line decoder unit 35 and the (2M+2)th local bit-line decoder unit 36. The local bit line decoding unit 36 ​​is electrically connected. The local bit line decoder 30 also includes a fourth local bit line sub-decoder. The fourth local bit line sub-decoder can be the Nth local bit line sub-decoder 30D. The Nth local bit line sub-decoder 30D includes a 2N-1th local bit line decoding unit 37 and a 2Nth local bit line decoding unit 38. The Nth storage block 14 can be electrically connected to the 2N-1th local bit line decoding unit 37 and the 2Nth local bit line decoding unit 38.

[0063] In one embodiment, in the second direction DR2, the fourth local bit line decoding unit block, the third local bit line decoding unit block, the second local bit line decoding unit block, and the first local bit line decoding unit block are arranged sequentially; in the second direction DR2, the distance from the first global bit line sub-decoder block to the second local bit line decoding unit block is less than the distance from the first global bit line sub-decoder block to the first local bit line decoding unit block; in the second direction DR2, the distance from the second global bit line sub-decoder block to the third local bit line decoding unit block is less than the distance from the second global bit line sub-decoder block to the fourth local bit line decoding unit block.

[0064] In one embodiment, the logic control circuit further includes a first word line decoding unit 41 and a second word line decoding unit 42. The first word line decoding unit 41 is electrically connected to the first memory block 11, and the first word line decoding unit block formed by the first word line decoding unit 41 is located within a first top-view projection area. The second word line decoding unit 42 is electrically connected to the first memory block 11, and the second word line decoding unit block formed by the second word line decoding unit 42 is located within the first top-view projection area. In the first direction DR1, the projection of the first word line decoding unit block and the projection of the second word line decoding unit block at least partially overlap. Furthermore, both the first word line decoding unit block and the second word line decoding unit block are located between the first global bit line sub-decoder block and the first local bit line decoding unit block (e.g., ...). Figure 4 (When M is 1 and N is 2).

[0065] It is understood that the storage device provided in this embodiment, by constructing the first word line decoding unit block formed by the first word line decoding unit 41 and the second word line decoding unit block formed by the second word line decoding unit 42 within the first top-view projection area, can further reduce the area occupied by the first chip 100 and the second chip 200 after stacking, thereby reducing the space occupied by the storage device and helping to achieve the minimum size of the storage device.

[0066] In some embodiments, both the first word line decoding unit block and the second word line decoding unit block are located between the first global bit line sub-decoder block and the second local bit line decoding unit block. The first word line decoding unit block does not overlap with the first global bit line sub-decoder block and / or the second local bit line decoding unit block, nor does the second word line decoding unit block overlap with the first global bit line sub-decoder block and / or the second local bit line decoding unit block. The first word line decoding unit block and the second word line decoding unit block also do not overlap.

[0067] It should be noted that in this embodiment, the logic control circuit includes a word line decoder 40, which includes at least one word line sub-decoder. Each word line sub-decoder may include two word line decoding units. In some embodiments, each memory block is configured with one or two corresponding word line decoding units. For example, the first word line sub-decoder 40A includes a first word line decoding unit 41 and a second word line decoding unit 42. The first memory block 11 is electrically connected to the first word line decoding unit 41 and the second word line decoding unit 42. The Mth word line sub-decoder 40B includes a 2M-1th word line decoding unit 43 and a 2Mth word line decoding unit 44. Line decoding unit 44, the Mth storage block 12 is electrically connected to the 2M-1th word line decoding unit 43 and the 2Mth word line decoding unit 44, the M+1th word line sub-decoder 40C includes the 2M+1th word line decoding unit 45 and the 2M+2th word line decoding unit 46, the M+1th storage block 13 is electrically connected to the 2M+1th word line decoding unit 45 and the 2M+2th word line decoding unit 46, the Nth word line sub-decoder 40D includes the 2N-1th word line decoding unit 47 and the 2Nth word line decoding unit 48, the Nth storage block 14 is electrically connected to the 2N-1th word line decoding unit 47 and the 2Nth word line decoding unit 48.

[0068] In one embodiment, in the first direction DR1, the first sensing amplifier sub-circuit block is located between the first word line decoding unit block and the second word line decoding unit block; and in the second direction DR2, the first sensing amplifier sub-circuit block is located between the first global bit line sub-decoder block and the first local bit line decoding unit block.

[0069] It is understood that in this embodiment, the first sensing amplifier sub-circuit block does not overlap with the first word line decoding unit block and / or the second word line decoding unit block. Similarly, the first sensing amplifier sub-circuit block does not overlap with the first global bit line sub-decoder block and / or the first local bit line decoding unit block.

[0070] In one embodiment, on the first direction DR1, the projection of the first inductive amplifier sub-circuit block at least partially overlaps with the projection of the first word line decoding unit block and / or the projection of the second word line decoding unit block.

[0071] In one embodiment, on the second direction DR2, the projection of the first inductive amplifier sub-circuit block does not overlap with the projection of the first word line decoding unit block and / or the projection of the second word line decoding unit block.

[0072] In one embodiment, the second chip 200 further includes a plurality of first traces 61, which are electrically connected to the first global bit line decoder 21 and the first local bit line decoder unit 31 to the second M local bit line decoder unit 34.

[0073] In one embodiment, the second chip 200 further includes a plurality of second traces 62 electrically connected to the second global bit line decoder 22 and the 2M+1th to 2Nth local bit line decoder units 35.

[0074] In this configuration, both the first trace 61 and the second trace 62 can be global bit lines. This setup is equivalent to dividing the memory blocks into two groups (first memory array 10A and second memory array 10B). The first memory block 11 to the Mth memory block 12 form the first group of memory blocks (first memory array 10A), and the (M+1)th memory block 13 to the Nth memory block 14 form the second group of memory blocks (second memory array 10B). The first trace 61 electrically connects the first group of memory blocks to the first global bit line sub-decoder 21, and the second trace 62 electrically connects the second group of memory blocks to the second global bit line sub-decoder 22. This grouping of memory blocks, combined with the three-dimensional bonding process (i.e., stacking / bonding the second chip 200 to the first chip 100 on the third side), can comprehensively shorten the connections between each memory block and the global decoder / global bit line decoder 20, and also reduce the connections between the global decoder / global bit line decoder 20 and the local decoder / local bit line decoder 30, thereby significantly reducing chip latency.

[0075] In one embodiment, the second chip 200 further includes a plurality of third traces 71 electrically connected to the first global bit line decoder 21 and the inductive amplifier circuit 50.

[0076] In one embodiment, the second chip 200 further includes multiple fourth traces 72 electrically connected to the second global bit line decoder 22 and the inductive amplifier circuit 50.

[0077] Among them, such as Figure 5 As shown, the first sensing amplifier sub-circuit 51 may include multiple sensing amplifiers arranged along the first direction DR1, such as sensing amplifier 51A, sensing amplifier 51B, sensing amplifier 51C, sensing amplifier 51D, etc. The second sensing amplifier sub-circuit 52 may also include multiple sensing amplifiers arranged along the first direction DR1, such as sensing amplifier 52A, sensing amplifier 52B, sensing amplifier 52C, sensing amplifier 52D, etc. The first direction DR1 may be the bit line arrangement direction of the first memory array 10A or the second memory array 10B.

[0078] Among them, such as Figure 6 As shown, the third inductive amplifier subcircuit 53 may include multiple inductive amplifiers arranged along the first direction DR1, such as inductive amplifier 53A, inductive amplifier 53B, inductive amplifier 53C, inductive amplifier 53D, etc. The fourth inductive amplifier subcircuit 54 may also include multiple inductive amplifiers arranged along the first direction DR1, such as inductive amplifier 54A, inductive amplifier 54B, inductive amplifier 54C, inductive amplifier 54D, etc.

[0079] In one embodiment, the Nth storage block 14 to the first storage block 11 are arranged sequentially along the second direction DR2, which can be the word line arrangement direction of the first storage array 10A or the second storage array 10B.

[0080] In one embodiment, the first chip 100 and the second chip 200 overlap or stack along a third direction DR3. It can be understood that the third direction DR3 can be the thickness direction of the first chip 100 and the second chip 200 after stacking.

[0081] In one embodiment, the logic control circuit further includes a third word line decoding unit and a fourth word line decoding unit. The third word line decoding unit is electrically connected to the second memory block, and the third word line decoding unit block formed by the third word line decoding unit is located within the second top-view projection area. The fourth word line decoding unit is electrically connected to the second memory block, and the fourth word line decoding unit block formed by the fourth word line decoding unit is located within the second top-view projection area. In the first direction DR1, the projection of the third word line decoding unit block and the projection of the fourth word line decoding unit block at least partially overlap. Both the third word line decoding unit block and the fourth word line decoding unit block are located between the second global bit line sub-decoder block and the fourth local bit line decoding unit block.

[0082] In one embodiment, in the first direction DR1, the second sensing amplifier sub-circuit block is located between the third word line decoding unit block and the fourth word line decoding unit block; and in the second direction DR2, the second sensing amplifier sub-circuit block is located between the second global bit line sub-decoder block and the fourth local bit line decoding unit block.

[0083] In one embodiment, on the first direction DR1, the projection of the second inductive amplifier sub-circuit block at least partially overlaps with the projection of the third word line decoding unit block and / or the projection of the fourth word line decoding unit block.

[0084] In one embodiment, on the second direction DR2, the projection of the second inductive amplifier sub-circuit block does not overlap with the projection of the third word line decoding unit block and / or the projection of the fourth word line decoding unit block.

[0085] It should be noted that the projection of the second inductive amplifier sub-circuit block does not overlap with the projection of the third word line decoding unit block and / or the projection of the fourth word line decoding unit block. This means that along the second direction, the second inductive amplifier sub-circuit block can have its own projection, the third word line decoding unit block can have its own projection, and the fourth word line decoding unit block can have its own projection; and along the second direction, the projection of the second inductive amplifier sub-circuit block does not overlap with the projection of the third word line decoding unit block and / or the projection of the fourth word line decoding unit block on any plane perpendicular to the second direction.

[0086] In one embodiment, the first chip 100 includes N memory blocks arranged sequentially along the second direction DR2, the first memory array 10A includes M memory blocks, and the second memory array 10B includes NM memory blocks, where M is less than N, and M and N are both positive integers; the first top-view projection area is the projection area of ​​the Mth memory block 12 on the second chip 200, and the second top-view projection area is the projection area of ​​the (M+1)th memory block 13 on the second chip 200; the first global bit line decoder 21 is electrically connected to at least one of the first local bit line decoding units 31 to the 2Mth local bit line decoding units 34, and the second global bit line decoder 22 is electrically connected to at least one of the 2M+1th local bit line decoding units 35 to the 2Nth local bit line decoding units 38.

[0087] In one embodiment, M is equal to the rounded N / 2; and the second global bit line sub-decoder block, the second M+1 local bit line decoding unit block formed by the second M+1 local bit line decoding unit 35, the second M local bit line decoding unit block formed by the second M local bit line decoding unit 34, and the first global bit line sub-decoder block are arranged adjacent to each other along the second direction DR2.

[0088] In one embodiment, the storage device further includes a plurality of first traces 61 and a plurality of second traces 62. The plurality of first traces 61 are electrically connected to a first global bit line decoder 21 and a first local bit line decoder unit 31 to a second local bit line decoder unit 34. The plurality of second traces 62 are electrically connected to a second global bit line decoder 22 and a second local bit line decoder unit 35 to a second local bit line decoder unit 38.

[0089] In one embodiment, on the second direction DR2, the projection of the second inductive amplifier sub-circuit block does not overlap with the projection of the third word line decoding unit block and / or the projection of the fourth word line decoding unit block.

[0090] like Figure 7 As shown, in one embodiment, this embodiment provides a method for manufacturing a storage device, which includes the following steps:

[0091] Step S10: Construct a first memory array and a second memory array on a first chip. The first memory array includes at least one first memory block. The first memory block includes multiple first word lines extending along a first direction and multiple second bit lines extending along a second direction. The second memory array includes at least one second memory block. The second memory block includes multiple second word lines extending along the first direction and multiple second bit lines extending along the second direction.

[0092] Step S20: Construct a logic control circuit on the second chip. The logic control circuit includes a first global bitline decoder and a second global bitline decoder. The first global bitline decoder is electrically connected to at least one first memory block, and the second global bitline decoder is electrically connected to at least one second memory block. The second chip has a first top-view projection area of ​​a first memory block and a second top-view projection area of ​​a second memory block. The first global bitline decoder block formed by the first global bitline decoder is located within the first top-view projection area, and the second global bitline decoder block formed by the second global bitline decoder is located within the second top-view projection area. In the second direction, the second top-view projection area and the first top-view projection area are arranged sequentially.

[0093] And step S30: stack the second chip on top of the first chip along the third direction.

[0094] It is understood that the fabrication method provided in this embodiment, by constructing a first global bit line decoder block located in a first top-view projection area formed by a first memory block and a second global bit line decoder block located in a second top-view projection area formed by a second memory block, can reduce the area occupied by the first chip and the second chip after stacking, thereby reducing the area occupied by the memory device and helping to achieve the minimum size of the memory device.

[0095] In one embodiment, the fabrication method further includes: constructing an inductive amplifier circuit in a logic control circuit; electrically connecting the inductive amplifier circuit to the output terminal of a first global bit line decoder and the output terminal of a second global bit line decoder; and configuring the inductive amplifier circuit block formed by the inductive amplifier circuit to be located in a first top-view projection area and / or a second top-view projection area.

[0096] In one embodiment, the fabrication method further includes: constructing a first inductive amplifier sub-circuit and a second inductive amplifier sub-circuit in an inductive amplifier circuit; electrically connecting the first inductive amplifier sub-circuit to the output terminal of a first global bit line decoder, and electrically connecting the second inductive amplifier sub-circuit to the output terminal of a second global bit line decoder; and configuring the first inductive amplifier sub-circuit block formed by the first inductive amplifier sub-circuit to be located in a first top-view projection area, and configuring the second inductive amplifier sub-circuit block formed by the second inductive amplifier sub-circuit to be located in a second top-view projection area.

[0097] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0098] The storage devices and their manufacturing methods provided in the embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A storage device, characterized in that, include: A first chip, the first chip including a first memory array and a second memory array, the first memory array including at least one first memory block, the first memory block including a plurality of first word lines extending along a first direction and a plurality of second bit lines extending along a second direction, the second memory array including at least one second memory block, the second memory block including a plurality of second word lines extending along the first direction and a plurality of second bit lines extending along the second direction; A second chip is stacked on top of the first chip along a third direction. The second chip includes a logic control circuit, which includes a first global bitline decoder and a second global bitline decoder. The first global bitline decoder is electrically connected to the at least one first memory block, and the second global bitline decoder is electrically connected to the at least one second memory block. The second chip has a first top-view projection area of ​​the first memory block and a second top-view projection area of ​​the second memory block. The first global bitline decoder block formed by the first global bitline decoder is located within the first top-view projection area, and the second global bitline decoder block formed by the second global bitline decoder is located within the second top-view projection area.

2. The storage device according to claim 1, characterized in that, In the second direction, the first top-view projection area and the second top-view projection area are connected.

3. The storage device according to claim 2, characterized in that, In the first direction, the length of the first global bit line decoder block is less than or equal to the length of the first top-view projection region; in the first direction, the length of the second global bit line decoder block is less than or equal to the length of the second top-view projection region.

4. The storage device according to claim 3, characterized in that, In the first direction, the length of the first top-view projection area is equal to the length of the second top-view projection area.

5. The storage device according to claim 1, characterized in that, The logic control circuit also includes: The inductive amplifier circuit is electrically connected to the output terminals of the first global bit line decoder and the second global bit line decoder. The inductive amplifier circuit block formed by the inductive amplifier circuit is located in the first top-view projection area and / or the second top-view projection area.

6. The storage device according to claim 5, characterized in that, The inductive amplifier circuit includes: The first inductive amplifier sub-circuit is electrically connected to the output of the first global bit line decoder, and the first inductive amplifier sub-circuit block formed by the first inductive amplifier sub-circuit is located within the first top-view projection area; and The second inductive amplifier sub-circuit is electrically connected to the output terminal of the second global bit line decoder, and the second inductive amplifier sub-circuit block formed by the second inductive amplifier sub-circuit is located in the second top-view projection area.

7. The storage device according to any one of claims 1 to 6, characterized in that, The logic control circuit also includes: A first local bitline decoder includes a first local bitline decoding unit and a second local bitline decoding unit electrically connected to the first global bitline decoder. The first local bitline decoding unit block formed by the first local bitline decoding unit and the second local bitline decoding unit block formed by the second local bitline decoding unit are both located within the first top-view projection area. In the second direction, the first global bitline decoder block is located between the first local bitline decoding unit block and the second local bitline decoding unit block.

8. The storage device according to claim 7, characterized in that, The logic control circuit also includes: The second local bitline decoder includes a third local bitline decoding unit and a fourth local bitline decoding unit electrically connected to the second global bitline decoder. The third local bitline decoding unit block formed by the third local bitline decoding unit and the fourth local bitline decoding unit block formed by the fourth local bitline decoding unit are both located within the second top-view projection area. In the second direction, the second global bitline decoder block is located between the fourth local bitline decoding unit block and the third local bitline decoding unit block.

9. The storage device according to claim 8, characterized in that, In the second direction, the fourth local bit-line decoding unit block, the third local bit-line decoding unit block, the second local bit-line decoding unit block, and the first local bit-line decoding unit block are arranged sequentially; in the second direction, the distance from the first global bit-line sub-decoder block to the second local bit-line decoding unit block is less than the distance from the first global bit-line sub-decoder block to the first local bit-line decoding unit block; in the second direction, the distance from the second global bit-line sub-decoder block to the third local bit-line decoding unit block is less than the distance from the second global bit-line sub-decoder block to the fourth local bit-line decoding unit block.

10. The storage device according to claim 7, characterized in that, The logic control circuit also includes: The first word line decoding unit is electrically connected to the first memory block, and the first word line decoding unit block formed by the first word line decoding unit is located in the first top-view projection area. The second word line decoding unit is electrically connected to the first memory block, and the second word line decoding unit block formed by the second word line decoding unit is located in the first top-view projection area. In the first direction, the projection of the first word line decoding unit block and the projection of the second word line decoding unit block at least partially overlap; and both the first word line decoding unit block and the second word line decoding unit block are located between the first global bit line sub-decoder block and the first local bit line decoding unit block.

11. The storage device according to claim 10, characterized in that, In the first direction, the first sensing amplifier sub-circuit block is located between the first word line decoding unit block and the second word line decoding unit block; and in the second direction, the first sensing amplifier sub-circuit block is located between the first global bit line sub-decoder block and the first local bit line decoding unit block.

12. The storage device according to claim 11, characterized in that, In the first direction, the projection of the first inductive amplifier sub-circuit block at least partially overlaps with the projection of the first word line decoding unit block and / or the projection of the second word line decoding unit block.

13. The storage device according to claim 12, characterized in that, In the second direction, the projection of the first inductive amplifier sub-circuit block does not overlap with the projection of the first word line decoding unit block and / or the projection of the second word line decoding unit block.

14. The storage device according to claim 8, characterized in that, The logic control circuit also includes: The third word line decoding unit is electrically connected to the second memory block, and the third word line decoding unit block formed by the third word line decoding unit is located in the second top-view projection area; The fourth word line decoding unit is electrically connected to the second memory block, and the fourth word line decoding unit block formed by the fourth word line decoding unit is located in the second top-view projection area; In the first direction, the projection of the third word line decoding unit block at least partially overlaps with the projection of the fourth word line decoding unit block; and both the third word line decoding unit block and the fourth word line decoding unit block are located between the second global bit line sub-decoder block and the fourth local bit line decoding unit block.

15. The storage device according to claim 14, characterized in that, The first chip includes N memory blocks arranged sequentially along the second direction, the first memory array includes M memory blocks, and the second memory array includes NM memory blocks, where M is less than N, and M and N are both positive integers; The first top-view projection area is the projection area of ​​the Mth memory block on the second chip, and the second top-view projection area is the projection area of ​​the (M+1)th memory block on the second chip; The first global bitline decoder is electrically connected to at least one of the first local bitline decoding units to the 2Mth local bitline decoding units, and the second global bitline decoder is electrically connected to at least one of the 2M+1th to the 2Nth local bitline decoding units.

16. The storage device according to claim 15, characterized in that, M is equal to N / 2 after rounding; and the second global bit line sub-decoder block, the 2M+1 local bit line decoding unit block formed by the 2M+1 local bit line decoding unit, the 2M local bit line decoding unit block formed by the 2M local bit line decoding unit, and the first global bit line sub-decoder block are arranged adjacent to each other along the second direction.

17. The storage device according to claim 16, characterized in that, The storage device further includes: Multiple first traces, wherein the multiple first traces are electrically connected to the first global bit line decoder, the first local bit line decoder unit to the 2Mth local bit line decoder unit; and Multiple second lines are electrically connected to the second global bit line decoder and the 2M+1th to 2Nth local bit line decoder units.

18. The storage device according to claim 17, characterized in that, In the second direction, the projection of the second inductive amplifier sub-circuit block does not overlap with the projection of the third word line decoding unit block and / or the projection of the fourth word line decoding unit block.

19. A storage device, characterized in that, include: A first chip, the first chip including a first memory array and a second memory array, the first memory array including at least one first memory block, the first memory block including a plurality of first word lines extending along a first direction and a plurality of second bit lines extending along a second direction, the second memory array including at least one second memory block, the second memory block including a plurality of second word lines extending along the first direction and a plurality of second bit lines extending along the second direction; The second chip is stacked on top of the first chip along a third direction. The second chip has a first top-view projection area of ​​the first memory block and a second top-view projection area of ​​the second memory block. The second chip includes a logic control circuit, which includes a sensing amplifier circuit. The sensing amplifier circuit block formed by the sensing amplifier circuit is located in the first top-view projection area and / or the second top-view projection area.

20. The storage device according to claim 19, characterized in that, In the second direction, the first top-view projection area and the second top-view projection area are adjacent.

21. The storage device according to claim 20, characterized in that, In the first direction, the length of the first global bit line decoder block is less than or equal to the length of the first top-view projection region; in the first direction, the length of the second global bit line decoder block is less than or equal to the length of the second top-view projection region.

22. The storage device according to claim 21, characterized in that, In the first direction, the length of the first top-view projection area is equal to the length of the second top-view projection area.

23. The storage device according to claim 19, characterized in that, The inductive amplifier circuit includes: The first inductive amplifier sub-circuit is electrically connected to the output of the first global bit line decoder, and the first inductive amplifier sub-circuit block formed by the first inductive amplifier sub-circuit is located within the first top-view projection area; and The second inductive amplifier sub-circuit is electrically connected to the output of the second global bit line decoder, and the second inductive amplifier sub-circuit block formed by the second inductive amplifier sub-circuit is located in the second top-view projection area.

24. The storage device according to any one of claims 19-23, characterized in that, The logic control circuit also includes: A first local bitline decoder includes a first local bitline decoding unit and a second local bitline decoding unit electrically connected to a first global bitline decoder. The first local bitline decoding unit block formed by the first local bitline decoding unit and the second local bitline decoding unit block formed by the second local bitline decoding unit are both located within the first top-view projection area. In the second direction, the first global bitline decoder block is located between the first local bitline decoding unit block and the second local bitline decoding unit block.

25. The storage device according to claim 24, characterized in that, The logic control circuit also includes: The second local bitline decoder includes a third local bitline decoding unit and a fourth local bitline decoding unit electrically connected to the second global bitline decoder. The third local bitline decoding unit block formed by the third local bitline decoding unit and the fourth local bitline decoding unit block formed by the fourth local bitline decoding unit are both located within the second top-view projection area. In the second direction, the second global bitline decoder block is located between the fourth local bitline decoding unit block and the third local bitline decoding unit block.

26. The storage device according to claim 25, characterized in that, In the second direction, the fourth local bit-line decoding unit block, the third local bit-line decoding unit block, the second local bit-line decoding unit block, and the first local bit-line decoding unit block are arranged sequentially; in the second direction, the distance from the first global bit-line sub-decoder block to the second local bit-line decoding unit block is less than the distance from the first global bit-line sub-decoder block to the first local bit-line decoding unit block; in the second direction, the distance from the second global bit-line sub-decoder block to the third local bit-line decoding unit block is less than the distance from the second global bit-line sub-decoder block to the fourth local bit-line decoding unit block.

27. The storage device according to claim 24, characterized in that, The logic control circuit also includes: The first word line decoding unit is electrically connected to the first memory block, and the first word line decoding unit block formed by the first word line decoding unit is located in the first top-view projection area. The second word line decoding unit is electrically connected to the first memory block, and the second word line decoding unit block formed by the second word line decoding unit is located in the first top-view projection area. In the first direction, the projection of the first word line decoding unit block and the projection of the second word line decoding unit block at least partially overlap; and both the first word line decoding unit block and the second word line decoding unit block are located between the first global bit line sub-decoder block and the first local bit line decoding unit block.

28. The storage device according to claim 27, characterized in that, In the first direction, the first sensing amplifier sub-circuit block is located between the first word line decoding unit block and the second word line decoding unit block; and in the second direction, the first sensing amplifier sub-circuit block is located between the first global bit line sub-decoder block and the first local bit line decoding unit block.

29. The storage device according to claim 28, characterized in that, In the first direction, the projection of the first inductive amplifier sub-circuit block at least partially overlaps with the projection of the first word line decoding unit block and / or the projection of the second word line decoding unit block.

30. The storage device according to claim 29, characterized in that, In the second direction, the projection of the first inductive amplifier sub-circuit block does not overlap with the projection of the first word line decoding unit block and / or the projection of the second word line decoding unit block.

31. The storage device according to claim 25, characterized in that, The logic control circuit also includes: The third word line decoding unit is electrically connected to the second memory block, and the third word line decoding unit block formed by the third word line decoding unit is located in the second top-view projection area; The fourth word line decoding unit is electrically connected to the second memory block, and the fourth word line decoding unit block formed by the fourth word line decoding unit is located in the second top-view projection area; In the first direction, the projection of the third word line decoding unit block at least partially overlaps with the projection of the fourth word line decoding unit block; and both the third word line decoding unit block and the fourth word line decoding unit block are located between the second global bit line sub-decoder block and the fourth local bit line decoding unit block.

32. The storage device according to claim 31, characterized in that, The first chip includes N memory blocks arranged sequentially along the second direction, the first memory array includes M memory blocks, and the second memory array includes NM memory blocks, where M is less than N, and M and N are both positive integers; The first top-view projection area is the projection area of ​​the Mth memory block on the second chip, and the second top-view projection area is the projection area of ​​the (M+1)th memory block on the second chip; The first global bitline decoder is electrically connected to at least one of the first local bitline decoding units to the 2Mth local bitline decoding units, and the second global bitline decoder is electrically connected to at least one of the 2M+1th to the 2Nth local bitline decoding units.

33. The storage device according to claim 32, characterized in that, M is equal to N / 2 after rounding; and the second global bit line sub-decoder block, the 2M+1 local bit line decoding unit block formed by the 2M+1 local bit line decoding unit, the 2M local bit line decoding unit block formed by the 2M local bit line decoding unit, and the first global bit line sub-decoder block are arranged adjacent to each other along the second direction.

34. The storage device according to claim 33, characterized in that, The storage device further includes: Multiple first traces, wherein the multiple first traces are electrically connected to the first global bit line decoder, the first local bit line decoder unit to the 2Mth local bit line decoder unit; and Multiple second lines are electrically connected to the second global bit line decoder and the 2M+1th to 2Nth local bit line decoder units.

35. The storage device according to claim 34, characterized in that, In the second direction, the projection of the second inductive amplifier sub-circuit block does not overlap with the projection of the third word line decoding unit block and / or the projection of the fourth word line decoding unit block.

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