Wafer-level chip 3D packaging lead-out structure and preparation method thereof

Abstract

The invention belongs to the technical field of microelectronic packaging, and particularly relates to a wafer-level chip 3D packaging lead-out structure and a preparation method. The method comprises the following steps: preparing a first groove pattern on the front surface of a substrate, and preparing a first conductive layer, a first metal layer and a first insulating layer to form a first rewiring layer; etching holes are formed in the back face of a chip, and vertical interconnection is formed on a pad on the front face of a base body; processing a second groove pattern on the back surface of the substrate again, and preparing a second metal layer and a second insulating layer similarly to form a second rewiring layer; after cutting, the upper groove pattern and the lower groove pattern are separated from the middle, and the side edges are led out through the inclined grooves near the pad to form side edge interconnection. The problem of side edge interconnection is solved while vertical interconnection is provided for chips, an additional connection path is provided for heterogeneous 3D integration, and more excellent electrical performance is achieved.

Description

Technical Field

[0001] The present invention belongs to the technical field of microelectronic packaging, and in particular relates to a wafer-level chip 3D packaging lead-out structure and a preparation method thereof. Background Art

[0002] As electronic products develop towards thinner, lighter, higher interconnection density, lower cost and higher system integration, the packaging technology of single functional chips has gradually failed to meet the needs of the industry. In addition, there are many types of integrated circuit chips in electronic systems, covering various functions such as digital, analog, RF / microwave, MEMS, photonics and passive circuits. These chips have huge differences in process nodes, wafer sizes and chip sizes, so achieving their high-density integration is of great significance for the miniaturization of electronic systems. 3D packaging technology has a far-reaching impact on the development of electronic products. It not only promotes a significant improvement in product performance, but also promotes the innovation of product form. By vertically stacking chips, 3D packaging technology significantly shortens the signal transmission path, reduces RC delay and power consumption, and improves data processing speed, which is particularly important for the pursuit of thin and light, high-performance mobile devices, high-performance computing and artificial intelligence.

[0003] However, the current 3D packaging technology also faces many challenges, such as packaging density and power management, improving packaging density, process complexity, packaging cost, packaging reliability and design layout optimization. After searching, for example, the publication number CN105575913 B discloses a buried silicon substrate fan-out type 3D packaging structure. Although it realizes 3D fan-out packaging on Si, it is only suitable for fan-out packaging of smaller chip sizes, and its cost is very high, and its reliability needs to be verified; In addition, the patent document with publication number CN 111312697A discloses a three-dimensional stacked integrated structure and its multi-chip integrated structure and preparation, which realizes fan-out packaging and 3D integration using Si base. However, its cost is still high, and the low yield rate hinders its market promotion.

[0004] Therefore, it is necessary to provide a wafer-level chip 3D package lead-out structure and preparation method to achieve low-cost, high-density, high-reliability 3D package heterogeneous package integration to meet the needs of modern electronic products for higher performance, smaller package size and lower power consumption. Summary of the invention

[0005] The purpose of the present invention is to provide a wafer-level chip 3D package lead-out structure and a preparation method, which solves the problem that the 3D package cost is high and the multi-directional interconnection requirements are difficult to meet.

[0006] The present invention is achieved through the following technical solutions: A method for preparing a wafer-level chip 3D package lead-out structure comprises the following steps: S1, in the dicing road area on the front side of the substrate, processing a first groove pattern in the chip dicing road area; S2, preparing a first conductive layer on the front side of the substrate; the first conductive layer partially covers the first groove pattern; S3, preparing a first metal layer in the first groove pattern, wherein the first metal layer covers the groove bottom area of ​​the first conductive layer; S4, preparing a first insulating layer in the first groove pattern to form a first redistribution layer; S5, uniformly coating a layer of photoresist on the first redistribution layer; S6, preparing a pattern of the first micro-bump in the photoresist to achieve metallization of the first micro-bump; S7, turning over the substrate to expose the interconnection structure on the back side and prepare a TSV pattern; etching the TSV hole on the back side of the substrate to form an etched hole; the etched hole is connected to the pad structure on the front side of the substrate; S8, completing electroplating in the etched hole, and forming a filling hole after polishing; S9, processing a second groove pattern on the back side of the substrate and in the dicing road area of ​​the chip; S10, evenly coating a layer of photosensitive resin glue on the back of the substrate to prepare a pattern of the second redistribution layer to achieve metallization; S11, preparing a second metal layer in the second groove pattern, the second metal layer covering the groove bottom exposed area of ​​the second metallization wiring layer; S12, preparing a second insulating layer in the second groove pattern to form a second redistribution layer; S13, uniformly coating a layer of photosensitive resin glue on the second redistribution layer; Prepare a pattern of second micro-bumps, and use a metal deposition system to achieve metallization of the second micro-bumps; S14. Through the cutting and scribing method, the metal structure in the chip scribing lane is penetrated to achieve structural separation, thereby obtaining a wafer-level chip 3D packaging lead-out structure.

[0007] Further, in S1, the substrate is a wafer to be packaged, and a pad structure exists on the front side of the substrate.

[0008] Further, in S2, the first conductive layer is prepared by magnetron sputtering or physical vapor deposition.

[0009] Furthermore, in S3, a first metal layer is prepared in the first groove pattern by using a printing method or a metal placement method, and the first metal layer is connected to the first conductive layer through a high temperature process.

[0010] Further, in S4, the first insulating layer is prepared by magnetron sputtering or physical vapor deposition; The first insulating layer covers the first conductive layer and the first metal layer.

[0011] Further, in S6, a first micro-bump pattern is prepared by using an exposure machine and a developer.

[0012] Further, in S7, a TSV pattern is prepared by using an exposure machine and a developer.

[0013] Furthermore, in S10, a layer of photosensitive resin glue is uniformly coated on the back side of the substrate by using a glue coating machine, and a second redistribution layer pattern is prepared by using an exposure machine and a developer.

[0014] Further, in S12, the second insulating layer is prepared by magnetron sputtering or physical vapor deposition.

[0015] The present invention also discloses a wafer-level chip 3D package lead-out structure prepared by the preparation method, comprising a substrate, a first redistribution layer prepared on the front side of the substrate, and a second redistribution layer prepared on the back side of the substrate; The first redistribution layer and the second redistribution layer are interconnected in a vertical direction; Lead-out structures are prefabricated on both sides of the substrate, the lead-out structures include a first groove and a second groove, and a first conductive layer, a first metal layer, and a first insulating layer are processed in the first groove; A second metal layer and a second insulating layer are processed in the second groove.

[0016] Compared with the prior art, the present invention has the following beneficial technical effects: The present invention provides a wafer-level chip 3D package lead-out structure and a preparation method thereof, first preparing a first groove pattern on the front side of a substrate, then preparing a first conductive layer, a first metal layer and a first insulating layer to form a first redistribution layer; by drilling an etching hole on the back side of the chip, drilling it on the pad on the front side of the substrate to form a vertical interconnection; then processing a second groove pattern again on the back side of the substrate, and similarly preparing a second metal layer and a second insulating layer to form a second redistribution layer; after cutting, the upper and lower groove patterns are separated from the middle, and the side edges are externally led out through the oblique grooves near the pad to form side interconnections. While providing vertical interconnections for the chip, the side interconnection problem is solved, providing an additional connection path for heterogeneous heterogeneous 3D integration, and achieving better electrical performance.

[0017] This structure uses TSV structure to achieve vertical interconnection, ensuring the vertical interconnection density while being compatible with high-density wiring processes and structural designs in the horizontal direction. In addition, it can also achieve wafer-level packaging of various finished chips, prepare side lead-out structures and high-density vertical interconnection structures, without the need for additional chip design, to meet the high-density integrated interconnection requirements of heterogeneous and heterogeneous chips.

[0018] The present invention provides a wafer-level chip 3D package lead-out structure, which focuses on making an external lead-out structure for an existing chip to meet the interconnection requirements of the chip. The existing chip lead-out structures are basically planar designs. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 is a schematic diagram of the structure of the matrix; Figure 2 Schematic diagram of substrate groove etching; Figure 3 is a schematic diagram of the first redistribution layer; Figure 4 It is a schematic diagram of metallization in the slot; Figure 5 This is a schematic diagram of the insulation protection in the slot; Figure 6 is a schematic diagram of the first micro-bump metallization; Figure 7 It is a schematic diagram of through hole graphics; Figure 8 It is a schematic diagram of through hole filling; Fig. 9 is a graphical schematic diagram of the second slot; Fig.10 is a schematic diagram of the second redistribution layer; Fig.11 is a schematic diagram of metallization in the second slot; Fig.12 is a schematic diagram of the second redistribution layer; Fig.13 is a schematic diagram of the second micro-bump metallization; Fig.14 It is a schematic diagram of the dicing area; Fig.15 This is a schematic diagram of the structure of wafer-level chip 3D packaging.

[0020] Wherein, 10, substrate; 11, pad structure; 12, first groove pattern; 20. first conductive layer; 30. first metal layer; 40. first insulating layer; 50. first micro bump; 51. photoresist; 60. Filling holes; 70. second redistribution layer; 80. second metal layer; 90. second insulating layer; 100. second micro-bump; 101. photosensitive resin glue. DETAILED DESCRIPTION

[0021] In order to make the purpose, technical solution and advantages of the present invention more clear, the following is further described in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention, that is, the embodiments described are only part of the embodiments of the present invention, not all embodiments.

[0022] The components described and shown in the drawings and embodiments of the present invention may be arranged and designed in various configurations. Therefore, the detailed description of the embodiments of the present invention provided in the following drawings is not intended to limit the scope of the claimed invention, but merely represents a selected embodiment of the present invention. Based on the drawings and embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0023] It should be noted that the terms "comprises", "includes" or any other variations are intended to cover non-exclusive inclusion, so that a process, element, method, article or equipment that includes a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to the process, element, method, article or equipment.

[0024] The features and performances of the present invention are further described in detail below in conjunction with the embodiments.

[0025] The present invention discloses a method for preparing a wafer-level chip 3D package lead-out structure, which realizes a front- and back-side wiring structure and a four-side lead-out structure on a chip through a wafer-level process, and specifically comprises the following steps: A substrate 10 is provided, wherein the substrate 10 is a wafer to be packaged after processing, and a pad structure 11 is required on the wafer for external lead-out of chip functions, such as Figure 1 shown.

[0026] On the front side of the substrate 10, in the chip dicing area, a first groove pattern 12 is processed in the chip dicing area by etching or laser. Figure 2 shown.

[0027] The first conductive layer 20 is prepared by magnetron sputtering or physical vapor deposition (PVD), such as Figure 3 shown.

[0028] A first metal layer 30 is prepared in the first groove pattern 12 by printing or placing metal, and the first metal layer 30 is connected to the first conductive layer 20 by a high temperature process, such as Figure 4shown.

[0029] The first insulating layer 40 is prepared on the substrate 10 by magnetron sputtering or physical vapor deposition. Figure 5 As shown, a first redistribution layer is formed.

[0030] A photoresist 51 is uniformly coated on the first redistribution layer by a coating machine, a first micro-bump pattern 50 is prepared by an exposure machine and a developer, and the first micro-bump 50 is metallized by a metal deposition system, such as Figure 6 shown.

[0031] The substrate 10 is turned over to expose the back interconnection structure. Figure 7 shown.

[0032] Prepare TSV patterns using an exposure machine and a developer; The TSV holes on the back of the substrate 10 are etched by an etching machine to form etching holes. Figure 7 shown.

[0033] Electroplating is performed in the blind hole by using an electroplating machine, and after chemical mechanical polishing, a filling hole 60 structure is formed, such as Figure 8 shown.

[0034] On the back side of the substrate 10, in the chip dicing area, a second groove pattern is processed in the chip dicing area by etching or laser. Fig. 9 shown.

[0035] A layer of photosensitive resin glue is uniformly coated on the back of the substrate 10 by using a glue coating machine, and a pattern of the second redistribution layer 70 is further prepared by using an exposure machine and a developer.

[0036] The second redistribution layer 70 is metallized using a metal deposition system, such as Fig.10 shown.

[0037] A second metal layer 80 is prepared in the second groove pattern by printing or placing metal, and the second metal layer 80 is connected to the pattern of the second redistribution layer 70 in the scribe line area by a high temperature process, such as Fig.11 shown.

[0038] The second insulating layer 90 is prepared on the back of the substrate 10 by magnetron sputtering or physical vapor deposition. Fig.12 shown.

[0039] like Fig.13 As shown, a layer of photosensitive resin glue 101 is evenly coated on the second redistribution layer 70 using a glue coating machine.

[0040] The pattern of the second micro-bump 100 is prepared by using an exposure machine and a developer, and the second micro-bump 100 is metallized by using a metal deposition system, such as Fig.13 shown.

[0041] like Fig.14 As shown, by cutting and scribing, the metal structure in the chip scribing lane is penetrated to achieve structural separation, and the result is as shown in FIG. Fig.15 The 3D chip lead-out structure shown.

[0042] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, ordinary technicians in the relevant field should understand that the specific implementation methods of the present invention can still be modified or replaced by equivalents. Any modification or equivalent replacement that does not depart from the spirit and scope of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A method for preparing a wafer-level chip 3D package lead-out structure, characterized in that: The steps include: S1, in the dicing road area on the front side of the substrate (10), a first groove pattern (12) is processed in the chip dicing road area; S2, preparing a first conductive layer (20) on the front surface of the substrate (10); the first conductive layer (20) partially covers the first groove pattern (12); S3, preparing a first metal layer (30) in the first groove pattern (12), wherein the first metal layer (30) covers the groove bottom area of ​​the first conductive layer (20); S4, preparing a first insulating layer (40) in the first groove pattern (12) to form a first redistribution layer; S5, uniformly coating a layer of photoresist (51) on the first redistribution layer; S6, preparing a pattern of the first micro-bump (50) in the photoresist (51) to achieve metallization of the first micro-bump (50); S7, turning over the substrate (10), exposing the interconnection structure on the back side, and preparing a TSV pattern; etching the TSV hole on the back side of the substrate (10) to form an etched hole; the etched hole is connected to the pad structure (11) on the front side of the substrate (10); S8, completing electroplating in the etched hole, and after polishing, forming a filling hole (60); S9, processing a second groove pattern on the back side of the substrate (10) and in the dicing road area of ​​the chip; S10, uniformly coating a layer of photosensitive resin adhesive on the back of the substrate (10) to prepare a pattern of the second redistribution layer (70) to achieve metallization; S11, preparing a second metal layer (80) in the second groove pattern, the second metal layer (80) covering the exposed area of ​​the groove bottom of the second metallized wiring layer (70); S12, preparing a second insulating layer (90) in the second groove pattern to form a second redistribution layer (70); S13, uniformly coating a layer of photosensitive resin glue (101) on the second redistribution layer (70); Preparing a pattern of second micro-bumps (100), and metallizing the second micro-bumps (100) using a metal deposition system; S14. Through the cutting and scribing method, the metal structure in the chip scribing lane is penetrated to achieve structural separation, thereby obtaining a wafer-level chip 3D packaging lead-out structure.

2. The method for preparing a wafer-level chip 3D package lead-out structure according to claim 1, characterized in that: In S1, the substrate (10) is a wafer to be packaged, and a pad structure (11) is present on the front surface of the substrate (10).

3. The method for preparing a wafer-level chip 3D package lead-out structure according to claim 1, characterized in that: In S2, a first conductive layer (20) is prepared by magnetron sputtering or physical vapor deposition.

4. The method for preparing a wafer-level chip 3D package lead-out structure according to claim 1, characterized in that: In S3, a first metal layer (30) is prepared in the first groove pattern (12) by a printing method or a metal placement method, and the first metal layer (30) is connected to the first conductive layer (20) by a high temperature process.

5. The method for preparing a wafer-level chip 3D package lead-out structure according to claim 1, characterized in that: In S4, a first insulating layer (40) is prepared by magnetron sputtering or physical vapor deposition. The first insulating layer (40) covers the first conductive layer (20) and the first metal layer (30).

6. The method for preparing a wafer-level chip 3D package lead-out structure according to claim 1, characterized in that: In S6, a first micro-bump (50) pattern is prepared using an exposure machine and a developer.

7. The method for preparing a wafer-level chip 3D package lead-out structure according to claim 1, characterized in that: In S7, a TSV pattern is prepared using an exposure machine and a developer.

8. The method for preparing a wafer-level chip 3D package lead-out structure according to claim 1, characterized in that: In S10, a layer of photosensitive resin glue is evenly coated on the back side of the substrate (10) using a glue coating machine, and a second redistribution layer pattern is prepared using an exposure machine and a developer.

9. The method for preparing a wafer-level chip 3D package lead-out structure according to claim 1, characterized in that: In S12, a second insulating layer (90) is prepared by magnetron sputtering or physical vapor deposition.

10. A wafer-level chip 3D package lead-out structure prepared by the preparation method according to any one of claims 1 to 9, characterized in that: It comprises a substrate (10), a first redistribution layer is prepared on the front side of the substrate (10), and a second redistribution layer (70) is prepared on the back side of the substrate (10); The first redistribution layer and the second redistribution layer (70) are interconnected in a vertical direction; Lead-out structures are prefabricated on both sides of the substrate (10), the lead-out structures comprising a first groove and a second groove, and a first conductive layer (20), a first metal layer (30), and a first insulating layer (40) are processed in the first groove; A second metal layer (80) and a second insulating layer (90) are processed in the second groove.

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