Heterogeneous and heterogeneous 3D adapter plate structure and preparation method thereof

Abstract

The invention belongs to the technical field of microelectronic packaging, and relates to a heterogeneous 3D adapter plate structure and a preparation method thereof. A first rewiring layer and a second rewiring layer are prepared on the front surface of the substrate, and a third rewiring layer and a fourth rewiring layer are prepared on the back surface of the substrate; a groove pattern is processed on the front surface of the substrate, and a first conductive layer, a first metal layer, a first insulating layer, a second conductive layer, a second metal layer and a second insulating layer are sequentially arranged in the groove pattern to form a side leading-out structure. The vertical interconnection density of the adapter substrate is ensured, meanwhile, a manufacturing method of a side face lead-out structure is provided for the adapter plate, a new path is provided for signal lead-out of the adapter plate, and the interconnection density of heterogeneous 2.5 D integration is further improved. According to the structure, the high-density interconnection level is achieved in the horizontal direction of the side face of the adapter plate, free leading-out of multi-chip signals in six directions is achieved, and therefore the high-density integration interconnection requirements of various heterogeneous chips are met.

Description

Technical Field

[0001] The present invention belongs to the technical field of microelectronic packaging, and in particular relates to a heterogeneous 3D adapter plate structure and a preparation method thereof. Background Art

[0002] 3D packaging technology has a profound impact on the development of electronic products. It not only promotes a significant improvement in product performance, but also promotes the innovation of product form. By stacking chips vertically, 3D packaging technology significantly shortens the signal transmission path, reduces RC delay and power consumption, and improves data processing speed, which is particularly important for the pursuit of thin and light, high-performance mobile devices, high-performance computing and artificial intelligence. This packaging method also allows small chips (Chiplet) to be manufactured using mature processes and then integrated together through 3D packaging technology, avoiding the use of expensive advanced processes for the entire large chip, thereby reducing production costs. At the same time, the reduction of connecting lines between chips also helps to reduce manufacturing costs. The structural design of 3D packaging technology also allows various functional devices and multiple materials to be integrated in one package, such as RF devices, memory, logic devices, MEMS, etc., to achieve heterogeneous integration, provide flexibility for the functional expansion and customization of electronic products, and meet diverse market needs. As the requirements for performance and integration of electronic products continue to increase, the structural design of 3D packaging technology is the key to achieving high performance, high integration, low cost and high reliability of electronic products. It will continue to play a vital role in the electronics industry and promote the development of electronic products in a more advanced direction.

[0003] However, the current 3D packaging technology also faces many challenges, such as smaller line width, higher interconnection density and more complex system integration. Therefore, in order to overcome the problem that the packaging interconnection density cannot meet the needs of high-end AI computing chips, the industry has made many changes in the design of 3D packaging structures. For example, Chinese invention patent CN105575913 B discloses a buried silicon substrate fan-out 3D packaging structure suitable for packaging of smaller chip sizes. In addition, Chinese invention patent CN 111312697A discloses a three-dimensional stacked integrated structure and its multi-chip integrated structure and preparation, which realizes fan-out packaging and 3D integration using Si base.

[0004] The current 3D integration generally focuses on solving the problem of vertical interconnection. The horizontal interconnection between chips is often realized by planar wiring technology, which limits the type of chips used and the overall package size. Therefore, it is necessary to provide a new high-density heterogeneous 3D adapter board structure and preparation method to achieve universal 3D heterogeneous integration of different chips and meet the needs of modern electronic products for higher performance, more functions, smaller package size and lower power consumption. Summary of the invention

[0005] The purpose of the present invention is to provide a heterogeneous 3D adapter plate structure and a preparation method thereof, which can solve the problem that side lead-out cannot be achieved in the current 3D structure.

[0006] The present invention is achieved through the following technical solutions: The present invention discloses a method for preparing a heterogeneous 3D adapter plate structure, comprising the following steps: S1, preparing a layer of blind holes on the substrate; S2, completing electroplating in the blind hole, and forming a filling hole after chemical mechanical polishing; S3, processing a groove pattern on the front side of the substrate and in the dicing road area of ​​the chip; S4, preparing a first conductive layer on the front side of the substrate; S5, preparing a first metal layer in the groove pattern, and connecting the first conductive layer and the first metal layer; S6. preparing a first insulating layer on the front surface of the substrate; S7, preparing a second conductive layer on the first insulating layer; S8, preparing a second metal layer in the groove pattern and on the second conductive layer, and connecting the second conductive layer to the second metal layer; S9, preparing a second insulating layer on the substrate; S10, on the front side of the substrate, the surface structure is removed to expose only the first conductive layer. At this time, the groove pattern includes the first conductive layer, the first metal layer, the first insulating layer, the second conductive layer, the second metal layer, and the second insulating layer from bottom to top. S11, preparing an adhesion layer and a seed layer on the front side of the substrate; A first redistribution layer pattern is prepared on the front side of the substrate to achieve metallization, thereby obtaining a metallized first redistribution layer; S12, preparing a metallized second redistribution layer again on the metallized first redistribution layer; Evenly coating a layer of photosensitive resin glue on the metallized second redistribution layer; S13, preparing a first micro-bump pattern on the second redistribution layer to realize metallized first micro-bumps; S14, exposing the interconnection structure on the back side of the substrate; Repeat S11-S12 to realize the third redistribution layer and the fourth redistribution layer metallized on the back side of the substrate; Repeat S13 to achieve a second micro-bump metallization on the back side of the substrate; S15, penetrating the metal structure in the dicing lane of the 3D transfer board to obtain a heterogeneous and heterogeneous 3D transfer board structure.

[0007] Furthermore, the base material is silicon or glass.

[0008] Furthermore, in S1, a layer of blind holes is prepared on the substrate by using a laser method or a photolithography pattern followed by etching.

[0009] Further, in S3, a groove pattern is processed in the chip dicing area by etching or laser method.

[0010] Further, in S4, a first conductive layer is prepared on the front surface of the substrate by magnetron sputtering or physical vapor deposition, and the groove pattern is covered by the first conductive layer; In S5, a first metal layer is prepared in the groove pattern by printing or placing metal, and a connection is formed by a high temperature process; In S6, a first insulating layer is prepared on the front surface of the substrate by using a magnetron sputtering or physical vapor deposition method.

[0011] Further, in S7, the second conductive layer is prepared by magnetron sputtering or physical vapor deposition; In S8, a second metal layer is prepared in the groove pattern by printing or placing metal; S9. Prepare a second insulating layer on the substrate by using magnetron sputtering or physical vapor deposition.

[0012] Further, in S11, the adhesion layer and the seed layer are prepared by magnetron sputtering or physical vapor deposition.

[0013] Furthermore, in S10, the surface structure is removed on the front side of the substrate by thinning and chemical mechanical polishing.

[0014] Furthermore, in S14, a thinning machine and a chemical mechanical polishing machine are used to expose the interconnection structure on the back side of the substrate.

[0015] The present invention also discloses a heterogeneous 3D adapter plate structure prepared by the preparation method, comprising a substrate, wherein a plurality of filling holes are prefabricated in the substrate; A metallized first redistribution layer and a metallized second redistribution layer are prepared on the front side of the substrate; a metallized first micro-bump is prepared on the metallized second redistribution layer; The four sides of the substrate are all provided with groove patterns, and the groove patterns are processed with a first conductive layer, a first metal layer, a first insulating layer, a second conductive layer, a second metal layer and a second insulating layer; A metallized third redistribution layer and a metallized fourth redistribution layer are prepared on the back side of the substrate; and a metallized second micro-bump is prepared on the metallized fourth redistribution layer.

[0016] Compared with the prior art, the present invention has the following beneficial technical effects: The present invention discloses a high-density heterogeneous 3D adapter board structure and a preparation method. A first redistribution layer and a second redistribution layer are prepared on the front of a substrate, and a third redistribution layer and a fourth redistribution layer are prepared on the back. The first redistribution layer is connected to the third redistribution layer and the fourth redistribution layer through a filling hole, and the second redistribution layer is connected to the third redistribution layer through a filling hole. The first redistribution layer and the second redistribution layer are connected through a side lead-out structure. The present invention is compatible with a vertical through-hole structure and can simultaneously achieve high-density vertical interconnection. A groove pattern is processed on the front of the substrate, and the groove pattern sequentially includes a first conductive layer, a first metal layer, a first insulating layer, a second conductive layer, a second metal layer, and a second insulating layer to form a side lead-out structure. While ensuring the vertical interconnection density of the adapter substrate, a method for manufacturing a side lead-out structure is provided for the adapter board, providing a new path for signal lead-out of the adapter board, and further improving the interconnection density of heterogeneous 2.5D integration.

[0017] This structure achieves a high-density interconnection level in the horizontal direction of the side of the adapter board. In addition, the lead-out ends of the present invention are located in two directions, the front and back of the adapter board. At the same time, there are lead-out structures on the four sides of the adapter board, a total of six directions. The adapter board structure can be used as any part of the 3D packaging structure to achieve free lead-out of multi-chip signals in six directions, thereby achieving the high-density integrated interconnection requirements of various heterogeneous and heterogeneous chips. It mainly solves the problem that the side lead-out cannot be achieved in the current 3D structure. For structures with multiple multi-layer chips, the adapter board can be inserted in the middle to achieve interconnection between different layers. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a schematic diagram of the substrate; Figure 2 is a schematic diagram of hole etching on the second substrate; Figure 3 Make a schematic diagram for the holes on the substrate; Figure 4 Schematic diagram of substrate groove etching; Figure 5 is a schematic diagram of a first conductive layer on a substrate; Figure 6 is a schematic diagram of the first metal layer on the substrate; Figure 7 is a schematic diagram of a first insulating layer on a substrate; Figure 8 is a schematic diagram of a second conductive layer on a substrate; Fig. 9 is a schematic diagram of the second metal layer on the substrate; Fig.10 is a schematic diagram of a second insulating layer on a substrate; Fig.11 Schematic diagram of substrate surface removal; Fig.12 is a schematic diagram of the first redistribution layer on the substrate; Fig.13 is a schematic diagram of the second redistribution layer on the substrate; Fig.14 is a schematic diagram of the first micro-bump on the substrate after metallization; Fig.15 It is a schematic diagram of the back removal of the substrate; Fig.16 It is a schematic diagram of the second micro-bump metallization on the back side of the substrate; Fig.17 Schematic diagram of the new high-density 3D adapter board structure.

[0019] Among them, 10, substrate; 20, filling hole; 30, first conductive layer; 50, first insulating layer; 60, second conductive layer; 80, second insulating layer; 90, metallized first redistribution layer; 100, photosensitive resin glue; 110, metallized second redistribution layer; 120, metallized first micro-bump; 130, metallized third redistribution layer; 140, metallized fourth redistribution layer; 150, metallized second micro-bump. DETAILED DESCRIPTION

[0020] In order to make the purpose, technical solution and advantages of the present invention more clear, the following is further described in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention, that is, the embodiments described are only part of the embodiments of the present invention, not all embodiments.

[0021] The components described and shown in the drawings and embodiments of the present invention may be arranged and designed in various configurations. Therefore, the detailed description of the embodiments of the present invention provided in the following drawings is not intended to limit the scope of the claimed invention, but merely represents a selected embodiment of the present invention. Based on the drawings and embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0022] It should be noted that the terms "comprises", "includes" or any other variations are intended to cover non-exclusive inclusion, so that a process, element, method, article or equipment that includes a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to the process, element, method, article or equipment.

[0023] The features and performances of the present invention are further described in detail below in conjunction with the embodiments.

[0024] The present invention proposes a high-density heterogeneous 3D adapter plate structure and a preparation method thereof, wherein a 3D adapter plate structure having a front and back wiring structure and a four-side side lead-out structure is manufactured by a wafer-level process, and specifically comprises the following steps: S1. Provide a substrate 10, the substrate 10 is made of silicon or glass, such as Figure 1 shown.

[0025] like Figure 2 As shown, a layer of blind holes is prepared on the substrate 10 by using a laser method or a photolithography pattern followed by etching.

[0026] S2, such as Figure 3 As shown, electroplating is performed in the blind hole using an electroplating machine, and after chemical mechanical polishing, a filling hole 20 structure is formed.

[0027] S3, such as Figure 4 As shown, on the front side of the substrate 10, in the chip dicing area, a groove pattern is processed in the chip dicing area by etching or laser method.

[0028] S4, such as Figure 5 As shown, a first conductive layer 30 is prepared on the front side of the substrate 10 by magnetron sputtering or physical vapor deposition (PVD), and the groove pattern is covered by the first conductive layer 30 .

[0029] S5, such as Figure 6 As shown, a first metal layer 40 is prepared in the groove pattern by a printing method or a metal placement method, and the first metal layer 40 and the first conductive layer 30 are connected by a high temperature process.

[0030] S6, such as Figure 7 As shown, the first insulating layer 50 is formed on the front surface of the substrate 10 by magnetron sputtering or physical vapor deposition.

[0031] S7, such as Figure 8 As shown, the second conductive layer 60 is prepared by magnetron sputtering or physical vapor deposition (PVD).

[0032] S8, such as Fig. 9 As shown, a second metal layer 70 is prepared in the groove pattern by printing or placing metal, and a connection is formed by a high temperature process.

[0033] S9, such as Fig.10 As shown, the second insulating layer 80 is prepared on the substrate 10 by magnetron sputtering or physical vapor deposition.

[0034] S10, such as Fig.11As shown, on the front side of the substrate 10, the surface structure is removed by thinning and chemical mechanical polishing methods, exposing only the first conductive layer 30. At this time, the groove pattern includes the first conductive layer 30, the first metal layer 40, the first insulating layer 50, the second conductive layer 60, the second metal layer 70, and the second insulating layer 80 from bottom to top.

[0035] S11. Prepare an adhesion layer and a seed layer by magnetron sputtering or physical vapor deposition (PVD).

[0036] A layer of photosensitive resin glue is uniformly coated on the front side of the substrate 10 by using a glue coating machine, and a first redistribution layer pattern is prepared by using an exposure machine and a developer.

[0037] like Fig.12 As shown, a first redistribution layer 90 is metallized using a metal deposition system.

[0038] S12, such as Fig.13 As shown, a photosensitive resin glue 100 is evenly coated on the metallized first redistribution layer 90 using a glue coating machine. A connection hole pattern between the first redistribution layer and the second redistribution layer is prepared using an exposure machine, and the second redistribution layer is metallized again using a metal deposition system to obtain a metallized second redistribution layer 110.

[0039] S13, such as Fig.14 As shown, a first micro-bump pattern is prepared using an exposure machine and a developer, and the first micro-bump is metallized using a metal deposition system to obtain a metallized first micro-bump 120.

[0040] S14, such as Fig.15 As shown, a thinning machine and a chemical mechanical polishing machine are used to expose the interconnection structure on the back side of the substrate 10 .

[0041] like Fig.16 As shown, S11 - S12 are repeated to metallize the redistribution layer, and the third redistribution layer and the fourth redistribution layer on the back side of the substrate 10 are metallized to obtain the metallized third redistribution layer 130 and the metallized fourth redistribution layer 140 .

[0042] The micro-bump metallization step is repeated to achieve metallization of the second micro-bump on the back side of the substrate 10 , thereby obtaining a metallized second micro-bump 150 .

[0043] S15, through the metal structure in the 3D transfer board dicing path by cutting and scribing method, to separate the transfer board structure, and obtain Fig.17 The high-density heterogeneous 3D interposer shown.

[0044] High density is mainly reflected in the compatibility of front and back wiring with the hole structure. Combined with the side lead-out, high-density wiring can be achieved.

[0045] The heterogeneity is mainly reflected in the fact that the micro-bump structure is compatible with different forms of chip connections, and the side lead-out method further avoids the horizontal stress problem during the heterogeneous connection process.

[0046] Fig.17 It is just a cross-sectional diagram in one direction. During actual processing, two layers are processed on the four sides of the adapter board to achieve free lead-out of multi-chip signals in six directions, thereby realizing the high-density integration and interconnection requirements of various heterogeneous chips.

[0047] like Fig.17 As shown, the heterogeneous 3D adapter plate structure finally prepared includes a substrate 10, in which a plurality of filling holes 20 are prefabricated; A metallized first redistribution layer 90 and a metallized second redistribution layer 110 are prepared on the front surface of the substrate 10; a metallized first micro-bump 120 is prepared on the metallized second redistribution layer 110; The four sides of the substrate 10 are provided with groove patterns, and the groove patterns are processed with a first conductive layer 30, a first metal layer 40, a first insulating layer 50, a second conductive layer 60, a second metal layer 70 and a second insulating layer 80; A metallized third redistribution layer 130 and a metallized fourth redistribution layer 140 are prepared on the back side of the substrate 10 ; and a metallized second micro bump 150 is prepared on the metallized fourth redistribution layer 140 .

[0048] The front and back wiring process of the present invention is compatible with minimum 2um / 2um line width and line spacing processing, and is compatible with a minimum through hole diameter of 5um, and can meet the transmission requirements of high-density computing chips as a whole.

[0049] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, ordinary technicians in the relevant field should understand that the specific implementation methods of the present invention can still be modified or replaced by equivalents. Any modification or equivalent replacement that does not depart from the spirit and scope of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A method for preparing a heterogeneous 3D adapter plate structure, characterized in that: The steps include: S1, preparing a layer of blind holes on the substrate (10); S2, completing electroplating in the blind hole, and after chemical mechanical polishing, forming a filling hole (20); S3, processing a groove pattern on the front side of the substrate (10) and in the dicing road area of ​​the chip; S4, preparing a first conductive layer (30) on the front surface of the substrate (10); S5, preparing a first metal layer (40) in the groove pattern, and connecting the first conductive layer (30) and the first metal layer (40); S6, preparing a first insulating layer (50) on the front surface of the substrate (10); S7, preparing a second conductive layer (60) on the first insulating layer (50); S8, preparing a second metal layer (70) in the groove pattern and on the second conductive layer (60), and connecting the second conductive layer (60) and the second metal layer (70); S9, preparing a second insulating layer (80) on the substrate (10); S10, on the front side of the substrate (10), the surface structure is removed to expose only the first conductive layer (30), at which point the groove pattern includes, from bottom to top, the first conductive layer (30), the first metal layer (40), the first insulating layer (50), the second conductive layer (60), the second metal layer (70), and the second insulating layer (80); S11, preparing an adhesion layer and a seed layer on the front side of the substrate (10); Preparing a first redistribution layer pattern on the front surface of the substrate (10) and achieving metallization to obtain a metallized first redistribution layer (90); S12, preparing a metallized second redistribution layer (110) again on the metallized first redistribution layer (90); Evenly coating a layer of photosensitive resin glue (100) on the metallized second redistribution layer (110); S13, preparing a first micro-bump pattern on the second redistribution layer to realize metallized first micro-bumps (120); S14, exposing the interconnection structure on the back side of the substrate (10); Repeat S11-S12 to achieve a third redistribution layer and a fourth redistribution layer (130) that are metallized on the back side of the substrate (10); Repeat S13 to achieve a second micro-bump (140) for metallization on the back side of the substrate (10); S15, penetrating the metal structure in the dicing lane of the 3D transfer board to obtain a heterogeneous and heterogeneous 3D transfer board structure.

2. The method for preparing a heterogeneous 3D adapter plate structure according to claim 1, characterized in that: The substrate (10) is made of silicon or glass.

3. The method for preparing a heterogeneous 3D adapter plate structure according to claim 1, characterized in that: In S1, a layer of blind holes is prepared on the substrate (10) by using a laser method or a photolithography pattern followed by etching.

4. The method for preparing a heterogeneous 3D adapter plate structure according to claim 1, characterized in that: In S3, a groove pattern is processed in the chip dicing area by etching or laser method.

5. The method for preparing a heterogeneous 3D adapter plate structure according to claim 1, characterized in that: In S4, a first conductive layer (30) is prepared on the front surface of the substrate (10) by magnetron sputtering or physical vapor deposition, and the groove pattern is covered by the first conductive layer (30); In S5, a first metal layer (40) is prepared in the groove pattern by printing or placing metal, and a connection is formed by a high temperature process; In S6, a first insulating layer (50) is prepared on the front surface of the substrate (10) by using a magnetron sputtering or physical vapor deposition method.

6. The method for preparing a heterogeneous 3D adapter plate structure according to claim 1, characterized in that: In S7, a second conductive layer (60) is prepared by magnetron sputtering or physical vapor deposition. In S8, a second metal layer (70) is prepared in the groove pattern by printing or placing metal; S9. Prepare a second insulating layer (80) on the substrate (10) by using a magnetron sputtering or physical vapor deposition method.

7. The method for preparing a heterogeneous 3D adapter plate structure according to claim 1, characterized in that: In S11, the adhesion layer and the seed layer are prepared by magnetron sputtering or physical vapor deposition.

8. The method for preparing a heterogeneous 3D adapter plate structure according to claim 1, characterized in that: In S10, the surface structure is removed on the front side of the substrate (10) by thinning and chemical mechanical polishing.

9. The method for preparing a heterogeneous 3D adapter plate structure according to claim 1, characterized in that: In S14, a thinning machine and a chemical mechanical polishing machine are used to expose the interconnection structure on the back side of the substrate (10).

10. A heterogeneous 3D adapter plate structure prepared by the preparation method of claims 1-9, characterized in that: It comprises a base body (10), wherein a plurality of filling holes (20) are prefabricated in the base body (10); A metallized first redistribution layer (90) and a metallized second redistribution layer (110) are prepared on the front surface of the substrate (10); and a metallized first micro-bump (120) is prepared on the metallized second redistribution layer (110); The four sides of the substrate (10) are each provided with a groove pattern, and a first conductive layer (30), a first metal layer (40), a first insulating layer (50), a second conductive layer (60), a second metal layer (70) and a second insulating layer (80) are processed in the groove pattern; A metallized third redistribution layer (130) and a metallized fourth redistribution layer (140) are prepared on the back side of the substrate (10); and a metallized second micro-bump (150) is prepared on the metallized fourth redistribution layer (140).

Images