Bump structure, preparation method thereof and semiconductor device

Abstract

The embodiment of the invention provides a bump structure, a preparation method thereof and a semiconductor device. The preparation method of the bump structure comprises the following steps: providing the semiconductor device with a seed layer on the surface; forming a palladium bump on the seed layer through an electroplating process, wherein the thickness range of the formed palladium bump is 0.1-5 [mu] m; a gold bump is formed on the palladium bump through electroplating, so that a palladium-gold bump module is formed, and the thickness range of the formed gold bump is 0.05-3 [mu] m; and continuously stacking on the current palladium-gold bump module through the electroplating process to form at least one palladium-gold bump module. According to the bump structure formed by the method, the single-layer palladium electroplating thickness is reduced, the problem of chip failure caused by hydrogen brittleness of palladium hydrogen evolution is avoided, and the reliability of a semiconductor device is greatly improved. Compared with the existing gold bump, the cost can be reduced by about 50-60%, and the cost reduction is close to the limit of the technical route. And the bump structure can be prepared by adopting the same electroplating equipment, and mass production can be realized.

Description

Technical Field

[0001] The disclosed embodiments belong to the technical field of semiconductor integrated circuit manufacturing, and specifically relate to a bump structure and a preparation method thereof, and a semiconductor device. Background Art

[0002] In the field of display panel driver chips, the current mainstream is through the gold bump structure (such as Figure 1 ) to achieve subsequent packaging with the panel. In recent years, the soaring gold price has been unfavorable to chip processing costs.

[0003] Currently, there are alternatives to gold bumps, such as Figure 2 As shown, there is currently the following palladium-gold bump structure, where the lower layer of the bump is a palladium layer 1 to replace gold to reduce costs, and the upper layer retains the gold layer 2 for subsequent packaging. However, this structure still has the following problems: ① The electroplating palladium process, if the thickness exceeds 5um, will cause metal fracture due to the electroplating hydrogen evolution effect, and then cause chip failure. ② Based on the above-mentioned palladium hydrogen embrittlement problem, the replacement ratio of gold is still not high, and the cost optimization is not prominent enough.

[0004] In view of the above problems, it is necessary to propose a bump structure and a preparation method thereof, and a semiconductor device that are reasonably designed and effectively solve the above problems. Summary of the invention

[0005] The embodiments of the present disclosure aim to solve at least one of the technical problems existing in the prior art, and provide a bump structure and a method for preparing the same, and a semiconductor device.

[0006] One aspect of an embodiment of the present disclosure provides a method for preparing a bump structure.

[0007] Preparation methods include:

[0008] Providing a semiconductor device having a seed layer formed on the surface;

[0009] Forming a palladium bump on the seed layer by an electroplating process, wherein the palladium bump has a thickness ranging from 0.1 μm to 5 μm;

[0010] Electroplating a gold bump on the palladium bump to form a palladium-gold bump module, wherein the thickness of the formed gold bump is in the range of 0.05 μm to 3 μm;

[0011] At least one of the palladium-gold bump modules is continuously stacked on the current palladium-gold bump module through an electroplating process.

[0012] Optionally, forming a palladium bump on the seed layer by an electroplating process includes:

[0013] forming a photoresist layer on the seed layer, wherein the thickness of the photoresist layer is greater than the total thickness of the bump structure;

[0014] exposing and developing the photoresist layer to form an opening on the photoresist layer;

[0015] The palladium bump is formed by electroplating at the opening using a palladium plating solution under the conditions of a first preset current density and a first preset electroplating time.

[0016] Optionally, forming a gold bump by electroplating on the palladium bump includes:

[0017] The gold bump is formed by electroplating on the palladium bump using a gold plating solution under a second preset current density and a second preset electroplating time.

[0018] Optionally, the step of continuously stacking at least one of the palladium-gold bump modules on the current palladium-gold bump module by an electroplating process comprises:

[0019] The palladium bump and the gold bump are sequentially electroplated on the gold bump of the current palladium-gold bump module to form the palladium-gold bump module stacked on the current palladium-gold bump module.

[0020] Optionally, after continuously stacking at least one of the palladium-gold bump modules on the current palladium-gold bump module through the electroplating process, the method further comprises:

[0021] removing the remaining photoresist layer;

[0022] A portion of the seed layer is removed so that the remaining seed layer is only connected to the bottommost palladium bump.

[0023] Optionally, the thickness of the gold bump at the end portion away from the semiconductor device is greater than the thickness of the gold bumps in other layers.

[0024] Another aspect of the embodiment of the present disclosure provides a bump structure, comprising at least two palladium-gold bump modules stacked in sequence, each of the palladium-gold bump modules comprising a palladium bump and a gold bump stacked in sequence; wherein,

[0025] The palladium bump is used to be arranged on a seed layer of a semiconductor device, and the thickness of the palladium bump is in the range of 0.1 μm to 5 μm;

[0026] The gold bump is disposed on the palladium bump, and the thickness of the gold bump is in the range of 0.05 μm to 3 μm.

[0027] Optionally, the palladium bump stack of the upper palladium-gold bump module is arranged on the gold bump of the lower palladium-gold bump module.

[0028] Optionally, the thickness of the gold bump at the end portion away from the semiconductor device is greater than the thickness of the gold bumps in other layers.

[0029] Another aspect of the embodiments of the present disclosure provides a semiconductor device including the bump structure described above.

[0030] The bump structure and preparation method thereof, and semiconductor device of the disclosed embodiment, the bump structure preparation method includes: providing a semiconductor device with a seed layer on the surface; forming a palladium bump on the seed layer by an electroplating process, and the thickness of the formed palladium bump is in the range of 0.1μm to 5μm; electroplating a gold bump on the palladium bump to form a palladium-gold bump module, wherein the thickness of the formed gold bump is in the range of 0.05μm to 3μm; and continuing to stack on the current palladium-gold bump module by an electroplating process to form at least one palladium-gold bump module. The bump structure formed by the bump preparation method reduces the thickness of the single-layer palladium electroplating, avoids the problem of chip failure caused by hydrogen embrittlement caused by palladium hydrogen precipitation, and greatly improves the reliability of semiconductor devices. Compared with the gold bump in the prior art, the cost can be reduced by about 50% to 60%, and the cost reduction is close to the limit of this technical route (close to the complete replacement of gold by palladium). In addition, the same electroplating equipment can be used to achieve the preparation of the bump structure, and mass production can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 It is a structural schematic diagram of a gold bump structure in the prior art;

[0032] Figure 2 It is a structural schematic diagram of a palladium bump structure in the prior art;

[0033] Figure 3 A schematic diagram of a process for preparing a bump structure according to an embodiment of the present disclosure;

[0034] Figures 4 to 12 A schematic diagram of a process flow of a method for preparing a bump structure according to another embodiment of the present disclosure;

[0035] Fig.13 A schematic structural diagram of a bump structure of another embodiment of the disclosed embodiment;

[0036] Fig.14 Schematic diagram of a bump structure of another embodiment of the present disclosure. DETAILED DESCRIPTION

[0037] In order to enable those skilled in the art to better understand the technical solutions of the embodiments of the present disclosure, the embodiments of the present disclosure are further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0038] As shown in Table 1, from the perspective of material physical and chemical properties, stability, oxidation resistance, corrosion resistance, and non-magnetism, palladium / platinum / gold are mutually substitutable in many fields. Palladium and gold both have electroplating technology solutions in the field of integrated circuit manufacturing, and the price of palladium is much lower than that of gold, so the bump solution of palladium replacing gold is considered.

[0039] The existing bump structure still has the following problems: ① The palladium electroplating process, if the thickness exceeds 5um, will cause metal fracture due to the electroplating hydrogen evolution effect, which will cause chip failure. ② Based on the above-mentioned palladium hydrogen embrittlement problem, the replacement ratio of gold is still not high, and the cost optimization is not prominent enough. It is necessary to explore a more effective bump structure to minimize the cost and maximize the reliability.

[0040] Table 1 Performance comparison data of palladium and gold

[0041]

[0042] like Figure 3 As shown, one aspect of an embodiment of the present disclosure provides a bump structure preparation method S100, and the preparation method S100 specifically includes:

[0043] S110 , providing a semiconductor device having a seed layer formed on the surface thereof.

[0044] Specifically, Figure 5 As shown, a semiconductor device 200 is provided, and a seed layer 210 is formed on the surface of the semiconductor device 200 by a sputtering process. In this embodiment, the semiconductor device 200 can be described by taking a wafer as an example. Figure 4 As shown, a pad 211 and a passivation layer 212 are provided on the functional surface of the wafer, wherein the passivation layer 212 has a window corresponding to the pad 211. Figure 5 As shown, a seed layer 210 is formed by sputtering on the pad 211 and the passivation layer 212 through a sputtering process, wherein the seed layer 210 is electrically connected to the pad 211 of the wafer. In this embodiment, the seed layer 210 may be a titanium tungsten / gold seed layer.

[0045] It should be noted that there is no specific limitation on the type of the semiconductor device 200 , and the type can be selected according to actual needs.

[0046] S120 , forming a palladium bump on the seed layer by an electroplating process, wherein the thickness of the formed palladium bump is in a range of 0.1 μm to 5 μm.

[0047] Specifically, Figure 6 As shown, first, a photoresist layer 230 is formed on the seed layer 210 , wherein the thickness of the photoresist layer 230 is greater than the total thickness of the entire bump structure.

[0048] The photoresist layer 230 may be a positive photoresist or a negative photoresist. The type of the photoresist layer 230 is not specifically limited in this embodiment and may be selected according to actual needs.

[0049] Next, the photoresist layer is exposed and developed to form an opening on the photoresist layer.

[0050] Specifically, Figure 7 As shown, a mask is provided, and the mask is placed above the photoresist layer 230. The photoresist layer 230 is exposed and developed using the mask as a mask to form a bonding pad 211 at the photoresist layer 230. Figure 7 The opening 231 shown further transfers the shape of the bump structure to the photoresist layer 230 .

[0051] Thirdly, a palladium plating solution is used to electroplate the palladium bump at the opening under the conditions of a first preset current density and a first preset plating time.

[0052] Specifically, Figure 8 and Fig.12 As shown, a palladium plating solution is used to electroplate a palladium bump 110 at the opening 231 under the conditions of a first preset current density and a second preset electroplating time. The thickness of the formed palladium bump 110 is in the range of 0.1 μm to 5 μm.

[0053] It should be noted that the first preset current density and the first preset electroplating time can be set according to the specific thickness of the palladium bump 110 , and are not specifically limited in this embodiment.

[0054] It should be further explained that the specific thickness of the palladium bump 110 can be set according to actual needs, and this embodiment does not specifically limit it.

[0055] S130, forming gold bumps by electroplating on the palladium bumps to form a palladium-gold bump module, wherein the thickness of the formed gold bumps ranges from 0.05 μm to 3 μm.

[0056] Specifically, Figure 8 and Fig.12 As shown, a gold plating solution is used to electroplate a gold bump 120 on a palladium bump 110 under a second preset current density and a second preset electroplating time, wherein the thickness of the gold bump 120 ranges from 0.05 μm to 3 μm. The palladium bump 110 and the gold bump 120 work together to form a palladium-gold bump module A.

[0057] It should be noted that the second preset current density and the second preset electroplating time can be set according to the specific thickness of the gold bump 120 , and this embodiment does not specifically limit this.

[0058] It should be further explained that the specific thickness of the formed gold bump 120 can be set according to actual needs, and this embodiment does not specifically limit it.

[0059] S140, continue to stack on the current palladium-gold bump module to form at least one palladium-gold bump module through an electroplating process.

[0060] Specifically, Figure 8 As shown, a palladium bump 110 and a gold bump 120 are sequentially electroplated on the gold bump 120 of the current palladium bump module A to form a palladium bump module A stacked on the current palladium bump module A.

[0061] It should be noted that the number of the stacked palladium bump modules A is at least two, and this embodiment does not specifically limit the specific number.

[0062] It should be noted that in the disclosed embodiment, the total thickness of the bump structure ranges from 6 μm to 25 μm. The number of palladium-gold bump modules A and the thickness of the palladium bump 110 and the gold bump 120 in each palladium-gold bump module A can be selected according to the total thickness of the bump structure.

[0063] Exemplarily, after the electroplating process is continued to stack at least one of the palladium-gold bump modules on the current palladium-gold bump module, the method further includes:

[0064] First choice, such as Fig. 9 As shown, the remaining photoresist layer 230 is removed by etching or other processes.

[0065] Secondly, if Fig.10 As shown, a portion of the seed layer 210 is removed by an etching process, so that the remaining seed layer 210 is only connected to the bottommost palladium bump 110 .

[0066] Again, if Fig.11 As shown, at least two palladium-gold bump modules A stacked in sequence are subjected to annealing treatment so that the hardness of the prepared bump structure reaches a preset hardness.

[0067] Exemplarily, the thickness of the gold bump 120 at the end facing away from the semiconductor device 200 is greater than the thickness of the gold bumps 120 in other layers, so that the gold bumps 120 at the top layer can be better packaged with other packaging modules.

[0068] like Fig.12The process of forming a bump structure by electroplating in the embodiment of the present disclosure is shown. The entire bump structure can be prepared in one electroplating machine by using a palladium electroplating solution and a gold electroplating solution in sequence through only one procedure. The current mainstream electroplating machines can implement the preparation process of the bump structure, and the feasibility of mass production is high.

[0069] In the first embodiment, the bump structure prepared by the bump structure preparation method S100 is a three-layer palladium-gold structure, taking a total height of 9 μm as an example. The electroplating process is: rinse → 0.5ASD current density electroplating to form a 2.7μm palladium bump 110 → rinse → 0.5ASD electroplating density electroplating to form a 0.3μm gold bump 120 → rinse → 0.5ASD current density electroplating to form a 2.7μm palladium bump 110 → rinse → 0.5ASD electroplating density electroplating to form a 0.3μm gold bump 120 → rinse → 0.5ASD current density electroplating to form a 2.7μm palladium bump 110 → rinse → 0.5ASD electroplating density electroplating to form a 0.3μm gold bump 120 → rinse, and the preparation of the three-layer palladium-gold structure is completed.

[0070] That is, in the first embodiment, if Fig.13 As shown, the three-layer palladium-gold structure includes three palladium-gold bump modules A stacked in sequence, and the thickness of the palladium bump 110 in each palladium-gold bump module A is 2.7 μm, and the thickness of the gold bump 120 is 0.3 μm. The cost of the three-layer palladium-gold structure can be reduced by 54%, and the hydrogen embrittlement failure problem caused by a single electroplating of too thick palladium is completely avoided.

[0071] In the second embodiment, the bump structure prepared by the bump structure preparation method S100 is a three-layer palladium-gold structure, taking a total height of 9 μm and a surface gold bump 120 with a thickness of 1 μm as an example. The electroplating process is: rinse → electroplating at a current density of 0.5ASD to form a 2.8μm palladium bump 110 → rinse → electroplating at a current density of 0.5ASD to form a 0.2μm gold bump 120 → rinse → electroplating at a current density of 0.5ASD to form a 2.8μm palladium bump → rinse → electroplating at a current density of 0.5ASD to form a 0.2μm gold bump 120 → rinse → electroplating at a current density of 0.5ASD to form a 2μm palladium bump 110 → rinse → electroplating at a current density of 0.5ASD to form a 1μm gold bump 120 → rinse, and the preparation of the three-layer palladium-gold structure is completed.

[0072] That is, in the second embodiment, the three-layer palladium-gold structure includes three palladium-gold bump modules A stacked in sequence, wherein the structures of the two palladium-gold bump modules A stacked at the bottom are the same, wherein the thickness of the palladium bump 110 is 2.8 μm, the thickness of the gold bump 120 is 0.2 μm, and the thickness of the palladium bump 110 in the palladium-gold bump module A stacked at the top layer is 2 μm, and the thickness of the surface gold bump 120 is 1 μm. The thickness of the surface gold bump 120 of the top palladium-gold bump module A is greater than the thickness of the gold bump 120 of other layers, and can be better packaged with other packaging modules.

[0073] In the third embodiment, the bump structure prepared by the bump structure preparation method S100 is a double-stacked palladium-gold structure, such as Fig.14 As shown, the total height of the double-layer palladium-gold structure is 9μm, and 4μm palladium bumps 110, 0.5μm gold bumps 120, 4μm palladium bumps 110 and 0.5μm gold bumps 120 are formed by electroplating in sequence. In other words, the double-layer palladium-gold structure includes two stacked palladium-gold bump modules A, and the thickness of the palladium bump 110 in each palladium-gold bump module A is 4μm, and the thickness of the gold bump 120 is 0.5μm. The cost of the double-layer palladium-gold structure in this embodiment can be reduced by up to 53%, which greatly reduces the hydrogen embrittlement failure problem caused by a single electroplating of too thick palladium.

[0074] In the fourth embodiment, the bump structure prepared by the bump structure preparation method S100 is a three-layer structure, and the total height of the three-layer palladium-gold structure is 9.3μm, including 3 palladium-gold bump modules A, and the palladium bump 110 in each palladium-gold bump module A has a thickness of 0.1μm, and the gold bump 120 has a thickness of 3μm.

[0075] In the fifth embodiment, the bump structure prepared by the bump structure preparation method S100 is a three-layer structure, and the total height of the three-layer palladium-gold structure is 15.15μm, including 3 palladium-gold bump modules A, and the palladium bump 110 in each palladium-gold bump module A is 5μm thick, and the gold bump 120 is 0.05μm thick.

[0076] In the sixth embodiment, the bump structure prepared by the bump structure preparation method S100 is a double-layer structure, which includes two palladium-gold bump modules A. The total height of the double-layer palladium-gold structure is 10.1 μm, and the thickness of the palladium bump 110 in each palladium-gold bump module A is 5 μm, and the thickness of the gold bump 120 is 0.05 μm.

[0077] In the seventh embodiment, the bump structure prepared by the bump structure preparation method S100 is a double-layer structure, which includes two palladium-gold bump modules A. The total height of the double-layer palladium-gold structure is 10μm, and the thickness of the palladium bump 110 in each palladium-gold bump module A is 2μm, and the thickness of the gold bump 120 is 3μm.

[0078] The bump structure and preparation method of the embodiment of the present disclosure, the bump structure formed by the bump preparation method, reduces the thickness of the single-layer palladium electroplating, avoids the problem of chip failure caused by hydrogen embrittlement due to palladium precipitation, and greatly improves the reliability of semiconductor devices. Compared with the gold bumps in the prior art, the cost can be reduced by about 50% to 60%, and the cost reduction is close to the limit of this technical route (close to palladium completely replacing gold). In addition, the same electroplating equipment can be used to achieve the preparation of the bump structure, and mass production can be achieved.

[0079] like Fig.13 and Fig.14 As shown, another aspect of the embodiment of the present disclosure provides a bump structure 100, including at least two palladium-gold bump modules A stacked in sequence, each palladium-gold bump module A including a palladium bump 110 and a gold bump 120 stacked in sequence.

[0080] The palladium bump 110 is used to be disposed on the seed layer 210 of the semiconductor device 200, and the thickness of the palladium bump 110 ranges from 0.1 μm to 5 μm. The gold bump 120 is disposed on the palladium bump 110, and the thickness of the gold bump 120 ranges from 0.05 μm to 3 μm.

[0081] For example, Fig.13 and Fig.14 As shown, the palladium bumps 110 of the upper palladium-gold bump module A are stacked on the gold bumps 120 of the lower palladium-gold bump module A. That is, in the bump structure 100 , the palladium bumps 110 and the gold bumps 120 are stacked alternately.

[0082] It should be noted that the number of palladium bump modules A is not specifically limited in this embodiment and can be as follows: Fig.14 The two palladium bump modules A shown in the figure are stacked in sequence, or they can be stacked in the following manner: Fig.13 The three palladium bump modules A shown are stacked in sequence and can be selected according to actual needs.

[0083] It should be further explained that, in this embodiment, the thickness range of the bump structure 100 is 6μm to 25μm, and the thickness of each layer of palladium bump 110 and gold bump 120 can be selected according to the total thickness of the bump structure 100. The specific thickness of the palladium bump 110 and the gold bump 120 is not specifically limited in this embodiment.

[0084] For example, Fig.13As shown, in one embodiment, the bump structure 100 is a three-layer palladium-gold structure with a total height of 9 μm. The three-layer palladium-gold structure includes three palladium-gold bump modules A stacked in sequence, wherein the thickness of the palladium bump 110 in each palladium-gold bump module A is 2.7 μm, and the thickness of the gold bump 120 is 0.3 μm. The cost of the three-layer palladium-gold structure can be reduced by 54%, and the hydrogen embrittlement failure problem caused by a single electroplating of too thick palladium is completely avoided.

[0085] For example, Fig.14 As shown, in another embodiment, the bump structure 100 is a double-stacked palladium-gold structure with a total height of 9 μm. The double-stacked palladium-gold structure includes two palladium-gold bump modules A, wherein the thickness of the palladium bump 110 in each palladium-gold bump module A is 4 μm, and the thickness of the gold bump 120 is 0.5 μm. The cost of the double-stacked palladium-gold structure can be reduced by 53%, which greatly reduces the hydrogen embrittlement failure problem caused by a single electroplated palladium thickness.

[0086] For example, the thickness of the gold bump 120 at the end facing away from the semiconductor device 200 is greater than the thickness of other layers of gold bumps 120. In other words, the thickness of the gold bump 120 at the outermost layer of the bump structure 100 can be greater than the thickness of other layers of gold bumps 120, so that the bump structure 100 can be better packaged with other packaging modules.

[0087] The bump structure of the disclosed embodiment includes at least two palladium-gold bump modules stacked in sequence, and each palladium-gold bump module includes a palladium bump and a gold bump stacked in sequence. Among them, the palladium bump is used to be set in the seed layer of the semiconductor device, and the thickness range of the palladium bump is 0.1μm to 5μm. The gold bump is set on the palladium bump, and the thickness range of the gold bump is 0.05μm to 3μm. The bump structure reduces the thickness of the single-layer palladium electroplating, avoids the problem of chip failure caused by hydrogen embrittlement due to palladium hydrogen precipitation, and greatly improves the reliability of semiconductor devices. Compared with the gold bumps in the prior art, the cost can be reduced by about 50% to 60%, and the cost reduction is close to the limit of this technical route (close to the complete replacement of gold with palladium).

[0088] Another aspect of the embodiment of the present disclosure provides a semiconductor device 200 including the bump structure 100 described above. The specific structure of the bump structure 100 has been described in detail above and will not be repeated here.

[0089] The semiconductor device of the disclosed embodiment adopts the bump structure described above, which saves cost and improves reliability.

[0090] It is to be understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the embodiments of the present disclosure, but the embodiments of the present disclosure are not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and essence of the embodiments of the present disclosure, and these modifications and improvements are also considered to be within the protection scope of the embodiments of the present disclosure.

Claims

1. A method for preparing a bump structure, characterized in that: The preparation method comprises: Providing a semiconductor device having a seed layer formed on the surface; Forming a palladium bump on the seed layer by an electroplating process, wherein the palladium bump has a thickness ranging from 0.1 μm to 5 μm; Electroplating a gold bump on the palladium bump to form a palladium-gold bump module, wherein the thickness of the formed gold bump is in the range of 0.05 μm to 3 μm; At least one of the palladium-gold bump modules is continuously stacked on the current palladium-gold bump module through an electroplating process.

2. The method according to claim 1, characterized in that The forming of a palladium bump on the seed layer by an electroplating process comprises: forming a photoresist layer on the seed layer, wherein the thickness of the photoresist layer is greater than the total thickness of the bump structure; exposing and developing the photoresist layer to form an opening on the photoresist layer; The palladium bump is formed by electroplating at the opening using a palladium plating solution under the conditions of a first preset current density and a first preset electroplating time.

3. The method according to claim 2, characterized in that Electroplating a gold bump on the palladium bump comprises: The gold bump is formed by electroplating on the palladium bump using a gold plating solution under a second preset current density and a second preset electroplating time.

4. The method according to claim 3, characterized in that The method of continuously stacking at least one palladium-gold bump module on the current palladium-gold bump module through an electroplating process comprises: The palladium bump and the gold bump are sequentially electroplated on the gold bump of the current palladium-gold bump module to form the palladium-gold bump module stacked on the current palladium-gold bump module.

5. The method according to claim 4, characterized in that After continuing to stack at least one of the palladium-gold bump modules on the current palladium-gold bump module by the electroplating process, the method further includes: removing the remaining photoresist layer; A portion of the seed layer is removed so that the remaining seed layer is only connected to the bottommost palladium bump.

6. The method according to any one of claims 1 to 5, characterized in that: The thickness of the gold bump at the end portion away from the semiconductor device is greater than the thickness of the gold bumps in other layers.

7. A bump structure, characterized in that: It comprises at least two palladium-gold bump modules stacked in sequence, each of the palladium-gold bump modules comprises a palladium bump and a gold bump stacked in sequence; wherein, The palladium bump is used to be arranged on a seed layer of a semiconductor device, and the thickness of the palladium bump is in the range of 0.1 μm to 5 μm; The gold bump is disposed on the palladium bump, and the thickness of the gold bump is in the range of 0.05 μm to 3 μm.

8. The bump structure according to claim 7, characterized in that: The palladium bumps of the upper palladium-gold bump module are stacked and arranged on the gold bumps of the lower palladium-gold bump module.

9. The bump structure according to claim 7, characterized in that: The thickness of the gold bump at the end portion away from the semiconductor device is greater than the thickness of the gold bumps in other layers.

10. A semiconductor device, characterized in that: The present invention comprises the bump structure as claimed in any one of claims 7 to 9.

Images