Semiconductor package

Abstract

A semiconductor package includes: a package substrate including a wiring having a plurality of pad patterns, the plurality of pad patterns respectively extending such that at least a portion of each of the pad patterns is exposed in at least one pad opening region; a semiconductor chip mounted on the chip mounting area of the package substrate through a plurality of conductive bumps; and a sealing member on the semiconductor chip on the package substrate. Each of the plurality of pad patterns includes: a main line extending away from a side of the pad opening region in the first direction; and a branch line extending from an end portion of the main line or from a position laterally spaced apart from the end portion of the main line in a second direction different from the first direction.

Description

[0001] This application claims the priority of Korean Patent Application No. 10-2023-0128142 filed on September 25, 2023, in the Korean Intellectual Property Office, and Korean Patent Application No. 10-2023-0142985 filed on October 24, 2023, in the Korean Intellectual Property Office, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] Example embodiments relate to a semiconductor package and a method of manufacturing the semiconductor package. More particularly, example embodiments relate to a semiconductor package including semiconductor chips stacked in a flip-chip bonding manner and a method of manufacturing the semiconductor package. Background Art

[0003] In a semiconductor package using a flip chip bonding method, the semiconductor chip can be mounted on a package substrate using conductive bumps. The bumps can be soldered and bonded to the wiring pads (also called "pads" or "solder pads") of the package substrate through a thermal compression process. However, during the thermal compression process, the softened bumps may overflow along the wiring and contact with adjacent pads, causing a short circuit. Summary of the invention

[0004] Example embodiments provide a semiconductor package having a structure capable of reducing or preventing a short-circuit defect caused by soldering.

[0005] Example embodiments provide a method of manufacturing a semiconductor package.

[0006] According to an example embodiment, a semiconductor package includes: a package substrate including a chip mounting area and at least one pad opening area in the chip mounting area, the package substrate including wiring having a plurality of pad patterns, the plurality of pad patterns respectively extending so that at least a portion of each of the pad patterns is exposed in the at least one pad opening area; a semiconductor chip mounted on the chip mounting area of ​​the package substrate through a plurality of conductive bumps; and a sealing member located on the semiconductor chip on the package substrate. The plurality of pad patterns are laterally spaced apart from each other, and each of the pad patterns includes: a main line extending away from a side of the pad opening area in a first direction; and a branch line extending in a second direction different from the first direction. The branch line extends from an end of the main line, and each of the conductive bumps is located on an upper surface of the branch line, or the branch line extends from a position laterally spaced apart from the end of the main line, and each of the conductive bumps is located on an upper surface of a portion of the main line between the end and the position from which the branch line extends.

[0007] According to example embodiments, a semiconductor package includes: a package substrate including at least one pad opening region, the package substrate including wiring having a plurality of pad patterns, the plurality of pad patterns respectively extending so that at least a portion of each of the pad patterns is exposed in the at least one pad opening region; a semiconductor chip including a plurality of chip pads on a first surface of the semiconductor chip and oriented so that the first surface faces an upper surface of the package substrate; a plurality of conductive bumps, respectively on the plurality of chip pads, wherein the conductive bumps bond the plurality of chip pads to corresponding portions of the plurality of pad patterns; and a sealing member located on the semiconductor chip on the package substrate, the sealing member at least partially surrounding the plurality of conductive bumps between the package substrate and the semiconductor chip. Each of the pad patterns includes: a main line extending away from a side of the pad opening region in a first direction; and a branch line extending from a position laterally spaced apart from an end of the main line in a second direction different from the first direction. Each of the conductive bumps is located on an upper surface of a portion of the main line between the end and the position from which the branch line extends.

[0008] According to example embodiments, a semiconductor package includes: a package substrate including at least one pad opening region, the package substrate including wiring having a plurality of pad patterns, the plurality of pad patterns respectively extending so that at least a portion of each of the pad patterns is exposed in the at least one pad opening region; a semiconductor chip including a plurality of chip pads on a first surface of the semiconductor chip and oriented so that the first surface faces an upper surface of the package substrate; a plurality of conductive bumps, respectively on the plurality of chip pads, wherein the conductive bumps bond the plurality of chip pads to corresponding portions of the plurality of pad patterns; and a sealing member located on the semiconductor chip on the package substrate, the sealing member at least partially surrounding the plurality of conductive bumps between the package substrate and the semiconductor chip. Each of the pad patterns includes: a main line extending away from a side of the pad opening region in a first direction; and a branch line extending from an end of the main line in a second direction different from the first direction. Each of the conductive bumps is located on an upper surface of the branch line.

[0009] According to example embodiments, a semiconductor package may include: a package substrate having a plurality of pad patterns, the plurality of pad patterns respectively extending so that at least a portion of each pad pattern is exposed in a pad opening region; and a semiconductor chip mounted on an upper surface of the package substrate through a plurality of conductive bumps. Each of the plurality of pad patterns may include: a main line extending away from a side of the pad opening region in a first direction; and a branch line extending from an end of the main line or from a position laterally spaced apart from the end of the main line in a second direction different from the first direction.

[0010] Each of the conductive bumps may be on an upper surface of the branch line or on an upper surface of a portion of the main line between an end of the main line and a branch portion of the main line. The solder layer of the conductive bump may at least partially fill a space between a sidewall of the branch line and a sidewall of the main line.

[0011] Therefore, a short circuit defect between adjacent main and branch lines due to overflow of the solder layer can be reduced or prevented. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings. Figures 1 to 35 represents non-limiting example embodiments as described herein.

[0013] Figure 1 is a plan view illustrating a semiconductor package according to example embodiments.

[0014] Figure 2 It is along Figure 1 A cross-sectional view taken along line AA'.

[0015] Figure 3 It is shown Figure 2 A plan view of the conductive bumps on the package substrate.

[0016] Figure 4 It is shown Figure 3 An enlarged plan view of portion "B" in FIG.

[0017] Figure 5 It is along Figure 4 A cross-sectional view taken along line CC'.

[0018] Figure 6 It is along Figure 4 A cross-sectional view taken along line D-D'.

[0019] Figure 7 It is along Figure 4 A cross-sectional view taken along line EE'.

[0020] Figure 8 is shown in the joint Figure 4 A perspective view of a conductive bump on a pad pattern in FIG.

[0021] Fig. 9 , Fig.10 , Fig.11 , Fig.12 , Fig.13 , Fig.14 , Fig.15 , Fig.16 , Fig.17 , Fig.18 , Fig.19 , Fig. 20 and Fig.21 is a diagram illustrating a method of manufacturing a semiconductor package according to example embodiments.

[0022] Fig. 22 is a cross-sectional view illustrating a semiconductor package according to example embodiments.

[0023] Fig.23 It is shown Fig. 22 A plan view of the conductive bumps on the package substrate.

[0024] Fig.24 It is shown Fig.23 An enlarged plan view of portion “L” in FIG.

[0025] Fig.25 It is along Fig.24 A cross-sectional view taken along line M-M'.

[0026] Fig.26 It is along Fig.24 A cross-sectional view taken along line N-N'.

[0027] Fig. 27 It is along Fig.24 A cross-sectional view taken along line O-O'.

[0028] Fig.28 It is along Fig.24 A cross-sectional view taken along line PP'.

[0029] Fig.29 is shown in the joint Fig.23 A perspective view of a conductive bump on a pad pattern.

[0030] Fig.30 , Fig.31 , Fig.32 , Fig.33 , Fig.34 and Fig.35 is a cross-sectional view illustrating a method of manufacturing a semiconductor package according to example embodiments. DETAILED DESCRIPTION

[0031] Hereinafter, example embodiments will be described in detail with reference to the accompanying drawings. The terms "first", "second", etc. may be used herein only to distinguish one component, layer, direction, etc. from another component, layer, direction, etc. When the terms "include", "comprises", and / or variations thereof are used herein, the existence of the stated elements is indicated, but the existence of additional elements is not excluded. The term "and / or" includes any and all combinations of one or more of the relevant listed items. The term "connected" may be used herein to refer to physical connections and / or electrical connections. When a component or layer is referred to herein as being "directly" on, or "in direct contact with", or "directly connected to", there are no intervening components or intervening layers.

[0032] Figure 1 is a plan view illustrating a semiconductor package according to example embodiments. Figure 2 It is along Figure 1 A cross-sectional view taken along line AA'. Figure 3 It is shown Figure 2 A plan view of the conductive bumps on the package substrate. Figure 4 It is shown Figure 3 An enlarged plan view of portion "B" in FIG. Figure 5 It is along Figure 4 A cross-sectional view taken along line CC'. Figure 6 It is along Figure 4 A cross-sectional view taken along line D-D'. Figure 7 It is along Figure 4 A cross-sectional view taken along line EE'. Figure 8 is shown in the joint Figure 4 A perspective view of a conductive bump on a pad pattern in FIG.

[0033] Reference Figures 1 to 8 , the semiconductor package 10 may include a package substrate 100 , a semiconductor chip 200 , a plurality of conductive bumps 300 , and a molding member (sealing member) 400 . In addition, the semiconductor package 10 may further include an external connection member 500 .

[0034] In an example embodiment, the package substrate 100 may be a multilayer circuit board having an upper surface 102 and a lower surface 104 opposite to the upper surface 102. For example, the package substrate 100 may be a printed circuit board (PCB) including wiring arranged in a plurality of layers and vias connected to the wiring. Spatially relative terms such as "top", "above", "upper", "upper portion", "upper surface", "bottom", "below", "lower", "lower portion", "lower surface", "side surface", etc. may be represented by reference numerals and refer to orientations shown by way of example in the accompanying drawings. It will be understood that such spatially relative terms are intended to cover different orientations of the device in addition to the orientations depicted in the figures.

[0035] Specifically, the package substrate 100 may include a plurality of stacked insulating layers 110 and wirings 120 a , 120 b , 120 c , and 120 d , respectively disposed in the insulating layers.

[0036] like Figure 2As shown in , the package substrate 100 may include a first insulating layer 110a, a second insulating layer 110b, a third insulating layer 110c, a fourth insulating layer 110d, and a fifth insulating layer 110e stacked sequentially. The first insulating layer 110a may be an upper cover insulating layer, the second insulating layer 110b may be an upper insulating layer, the third insulating layer 110c may be a core layer, the fourth insulating layer 110d may be a lower insulating layer, and the fifth insulating layer 110e may be a lower cover insulating layer. The third insulating layer 110c as a core layer may include a non-conductive material layer. The third insulating layer 110c may include a reinforced polymer, etc.

[0037] The second wiring 120b may be disposed on the upper surface of the third insulating layer 110c. The second insulating layer 110b may cover the second wiring 120b on the upper surface of the third insulating layer 110c. The first wiring 120a may be disposed on the upper surface of the second insulating layer 110b and may be electrically connected to the second wiring 120b through an opening formed in the second insulating layer 110b.

[0038] The third wiring 120c may be disposed on the lower surface of the third insulating layer 110c. The fourth insulating layer 110d may cover the third wiring 120c on the lower surface of the third insulating layer 110c. The fourth wiring 120d may be disposed on the lower surface of the fourth insulating layer 110d and may be electrically connected to the third wiring 120c through an opening formed in the fourth insulating layer 110d.

[0039] The first to fourth wirings 120a, 120b, 120c, and 120d may be referred to as first to fourth circuit layers stacked in the thickness direction from the upper surface 102 to the lower surface 104 of the package substrate 100. For example, the wirings may include a metal material such as copper, aluminum, etc. It will be understood that the arrangement and number of the insulating layers and wirings are exemplary and not limited thereto.

[0040] The conductive through via 112 may penetrate the third insulating layer 110c as the core layer and electrically connect the second wiring 120b and the third wiring 120c. The first wiring 120a may be exposed from the upper surface 102 of the package substrate 100. The fourth wiring 120d may be exposed from the lower surface 104 of the package substrate 100. The term "exposed" may be used herein to describe the relationship between elements and / or between certain intermediate processes when manufacturing a completed semiconductor device, but external exposure of a specific region, layer, structure, or other element may not be required in the context of a completed device.

[0041] The upper insulating layer 150 may be disposed on the upper surface 102 of the package substrate 100 and may expose at least a portion of the first wiring 120a. The lower insulating layer 152 may be disposed on the lower surface 104 of the package substrate 100 and may expose at least a portion of the fourth wiring 120d. The upper insulating layer 150 and the lower insulating layer 152 may separate the circuit pattern of the package substrate 100 from the external environment to reduce or prevent contamination and electrically insulate the wiring of the circuit pattern from each other. For example, the upper insulating layer and the lower insulating layer may include a photosensitive resin such as a photo epoxy resin or a photosensitive polymer such as a photo solder resist (PSR).

[0042] In addition, the first wiring 120a may include a data signal wiring 120a-1 for transmitting a data signal to the semiconductor chip 200 mounted on the package substrate 100 and a power / ground wiring 120a-2 for transmitting a power signal or a ground signal to the semiconductor chip 200. The data signal wiring 120a-1 used as a data transmission pattern may be provided as a single wiring line, and the power / ground wiring 120a-2 used as a power pattern or a ground wiring may be provided as a plurality of wiring lines and may be electrically connected to each other.

[0043] like Figure 3 As shown in , the package substrate 100 may have a chip mounting region MR and at least one pad opening region POR within the chip mounting region MR. The semiconductor chip 200 may be mounted in the chip mounting region MR on the upper surface 102 of the package substrate 100. The upper insulating layer 150 may expose a portion of the wiring 120a in the pad opening region POR.

[0044] The pad opening region POR may correspond to a central pad region of the chip pad 230 where the semiconductor chip 200 is arranged. Portions of the first wiring 120a exposed through the upper insulating layer 150 in the pad opening region POR may be referred to as pad patterns PP, and the conductive bumps 300 are respectively disposed on the pad patterns PP so that the semiconductor chip 200 is mounted by a flip chip bonding method.

[0045] A plurality of pad patterns PP may be arranged to be spaced apart from each other along one side of the pad opening region POR. For example, the plurality of pad patterns PP may include a first group of pad patterns PP1 and a second group of pad patterns PP2 spaced apart from each other in a first direction (X direction) (also referred to herein as being spaced apart laterally in the first direction). The first group of pad patterns PP1 may be arranged to be spaced apart from each other in a second direction (Y direction) perpendicular to the first direction (X direction) along a first side E1 of the pad opening region POR (also referred to herein as being spaced apart laterally in the second direction), and the second group of pad patterns PP2 may be spaced apart from each other in the second direction (Y direction) along a second side E2 of the pad opening region POR facing the first side E1. The "lateral" direction as used herein may refer to any direction in the XY plane (as shown in the plan view in the accompanying drawings), and may be perpendicular to the vertical direction (Z direction).

[0046] The first group of pad patterns PP1 and the second group of pad patterns PP2 may be symmetrical to each other with respect to a center line ML of the pad opening region POR extending parallel to the second direction (Y direction). The first group of pad patterns PP1 arranged in the second direction (Y direction) may have the same shape. The second group of pad patterns PP2 arranged in the second direction (Y direction) may have the same shape.

[0047] In example embodiments, the semiconductor chip 200 may be mounted on the package substrate 100 using a flip chip bonding method. The semiconductor chip 200 may be mounted on the package substrate 100 via the conductive bumps 300. In this case, the semiconductor chip 200 may be mounted on the package substrate 100 so that the active surface (i.e., the first surface 212) on which the chip pad 230 is formed faces the package substrate 100. The plane area of ​​the semiconductor chip 200 may be smaller than the plane area of ​​the package substrate 100. When viewed in a plan view, the semiconductor chip 200 may be disposed within the chip mounting region MR of the package substrate 100.

[0048] The semiconductor chip 200 may include a memory chip such as a DRAM device or a flash memory device or a non-memory chip such as a logic chip. The semiconductor chip 200 may include a plurality of chip pads 230 disposed on the first surface 212. The chip pads 230 may have a central pad type pad structure in which the chip pads 230 are arranged in a row along a center line. For example, two chip pads 230 adjacent to each other may be arranged in a row along the center line.

[0049] Conductive bumps 300 may be formed on chip pads 230, respectively. Each of the plurality of conductive bumps 300 may include a connection column 310 extending from the chip pad 230 of the semiconductor chip 200 in a vertical direction and a solder layer 320 bonded to an end of the connection column 310. For example, the connection column 310 may include a first metal, and the solder layer 320 may include a second metal different from the first metal. The first metal may include nickel (Ni), copper (Cu), palladium (Pd), platinum (Pt), etc. The second metal may include tin (Sn), tin / silver (Sn / Ag), tin / copper (Sn / Cu), tin / indium (Sn / In), etc.

[0050] When the semiconductor chip 200 is mounted on the package substrate 100 , the conductive bumps 300 on the chip pads 230 may be respectively disposed on the pad patterns PP of the first wirings 120 a , and the solder layer 320 may be softened and bonded to the pad patterns PP through a thermal compression process.

[0051] like Figure 4 As shown in , each of the pad patterns PP may include a main line 132 and a branch line 140. The main line 132 may extend inward from one side E1, E2 of the pad opening region (POR) in the third direction, that is, away from one side E1, E2 and toward the central region and / or the laterally adjacent pad pattern PP. The first wiring 120a may include a wiring line 130 covered by an upper insulating layer 150 and the main line 132 exposed through the upper insulating layer 150.

[0052] The branch line 140 may extend in a fourth direction different from the third direction at a position spaced apart from the end 133 of the main line 132 by a predetermined distance L2. The branch line 140 may extend from one side wall 132a of the main line 132 in the fourth direction. The main line 132 further includes another side wall 132b opposite to the one side wall 132a. An angle θ between the main line 132 and the branch line 140 may be greater than, less than, or equal to 90 degrees. For example, the third direction may be parallel to the X direction, and the fourth direction may be parallel to the Y direction.

[0053] The branches 140 of the first group of pad patterns PP1 arranged along the first side E1 of the pad opening region POR may extend in the same direction (fourth direction). The branches 140 of the second group of pad patterns PP2 arranged along the second side E2 of the pad opening region POR may extend in the same direction (fourth direction).

[0054] When the semiconductor chip 200 is placed on the package substrate 100, a portion of the main line 132 between the end 133 of the main line 132 and the branch portion to which the branch line 140 of the main line 132 is connected may be used as a landing pad on which the conductive bump 300 is disposed. The conductive bump 300 may be disposed on this portion of the main line 132, and during the hot pressing process, the solder layer 320 may be heated and softened, and flow along the main line 132 and the branch line 140 and then be bonded.

[0055] like Figure 5 As shown in FIG. 1 , in the first group of pad patterns PP1 and the second group of pad patterns PP2 spaced apart from each other in the first direction (X direction), the solder layer 320 may flow in directions away from each other (opposite directions) and then respectively bonded to portions of the branch lines 140. Therefore, the occurrence of a short circuit defect due to overflow of the solder layer 320 between adjacent main lines 132 of the first group of pad patterns PP1 and the second group of pad patterns PP2 may be reduced or prevented.

[0056] like Figure 6 As shown in FIG, in the second group of pad patterns PP2 spaced apart from each other in the second direction (Y direction) along the second side E2 of the pad opening region POR, each solder layer 320 may flow to the branch lines 140 extending in the same direction (fourth direction) and may be joined to portions of the branch lines 140. Therefore, a short circuit defect between adjacent main lines 132 due to overflow of the solder layer 320 may be reduced or prevented.

[0057] like Figure 7 and Figure 8 As shown in , a portion of the solder layer 320 may flow along the main line 132 and the branch line 140, and then flow to fill the space between the sidewall 132a of the main line 132 and one sidewall of the branch line 140. The terms "fill" or "cover" or "surround" as may be used herein may not require completely filling or covering or surrounding the described element or layer, but may, for example, refer to partially filling or covering or surrounding the described element or layer, for example, with a void or other space therethrough.

[0058] For example, the branch line 140 may be laterally spaced apart from one side E2 of the pad opening region POR by a first distance L1. The first distance L1 may be in the range of 20 μm to 40 μm. The branch line 140 may extend a third length L3 in the fourth direction. The third length L3 of the branch line 140 may be in the range of 10 μm to 30 μm. The lateral spacing distance L2 from the end 133 of the main line 132 to the position where the branch line 140 branches may be in the range of 50 μm to 100 μm. The first width W1 of the main line 132 and the second width W2 of the branch line 140 may be in the range of 10 μm to 30 μm.

[0059] The long side W3x of the connecting column 310 may be in the range of 40 μm to 80 μm, and the short side W3y of the connecting column 310 may be in the range of 30 μm to 60 μm. The extension direction of the long side W3x of the connecting column 310 (also referred to herein as the longitudinal extension direction of the connecting column 310) may be parallel to the third direction, and the extension direction of the short side W3y of the connecting column 310 may be parallel to the fourth direction. The height W3z of the connecting column 310 may be in the range of 20 μm to 50 μm. The height (thickness) of the solder layer 320 may be in the range of 5 μm to 20 μm.

[0060] In example embodiments, a molding member 400 or other sealing member 400 may be disposed on the package substrate 100 to protect the semiconductor chip 200 from the outside (i.e., from the external environment). The sealing member 400 may be used as an underfill member that fills the space between the package substrate 100 and the semiconductor chip 200. The sealing member 400 may cover the conductive bump 300 between the package substrate 100 and the semiconductor chip 200. The sealing member may include an epoxy molding compound (EMC).

[0061] The external connection member 500 may be disposed on the external connection pad on the lower surface 104 of the package substrate 100, that is, on the portion of the fourth wiring 120d exposed by the lower insulating layer 152. For example, the external connection member 500 may be a solder ball. The semiconductor package 10 may be mounted on a module substrate using the solder ball to form a memory module.

[0062] As mentioned above, the semiconductor package 10 may include a packaging substrate 100 and a semiconductor chip 200, the packaging substrate 100 having a plurality of pad patterns PP, the plurality of pad patterns PP respectively extending so that at least a portion of each pad pattern is exposed within a pad opening region POR, and the semiconductor chip 200 is mounted on an upper surface 102 of the packaging substrate 100 via a plurality of conductive bumps 300.

[0063] Each of the plurality of pad patterns PP may include a main line 132 extending inwardly from one side E1 and E2 of the pad opening region POR in a third direction, and a branch line 140 extending in a fourth direction different from the third direction at a position laterally spaced a predetermined distance L2 from an end 133 of the main line 132. Each of the conductive bumps 300 may be disposed on a portion of the main line 132 between the end 133 of the main line 132 and the branch line 140.

[0064] The branch lines 140 may be formed to extend in the same direction (fourth direction) different from the extending direction (third direction) of the adjacent main lines 132, so that each solder layer 320 of the conductive bump 300 may flow to the branch lines 140 extending in the same direction (fourth direction) and then be bonded to a portion of the branch lines 140. Therefore, the occurrence of a short circuit defect between the adjacent main lines 132 due to overflow of the solder layer 320 may be reduced or prevented.

[0065] In the following, the manufacturing Figure 1 A method for a semiconductor package in a semiconductor device.

[0066] Figures 9 to 21 is a diagram illustrating a method of manufacturing a semiconductor package according to example embodiments. Fig. 9 , Fig.10 , Fig.11 , Fig.12 , Fig.15 and Fig.21 is a cross-sectional view illustrating a method of manufacturing a semiconductor package according to example embodiments. Fig.13 yes Fig.12 Floor plan. Fig.14 It is shown Fig.13 An enlarged cross-sectional view of portion “F” in FIG. Fig.16 It is shown Fig.15 A plan view of the conductive bumps on the package substrate. Fig.17 It is shown Fig.16 An enlarged plan view of portion "G" in FIG. Fig.18 It is along Fig.17 A cross-sectional view taken along line H-H'. Fig.19 It is along Fig.17 A cross-sectional view taken along line II'. Fig. 20 It is along Fig.17 A cross-sectional view taken along line J-J'.

[0067] Reference Figures 9 to 11 , a plurality of conductive bumps 300 may be formed on the chip pad 230 of the semiconductor chip 200 .

[0068] In example embodiments, the conductive bumps 300 may be formed on a chip pad 230 of a wafer W including semiconductor chips at a wafer level.

[0069] like Fig. 9As shown in , the wafer W may include a substrate 210 and a chip pad 230 disposed in a first surface 212 of the substrate 210. The wafer W may include a wiring layer 220 on an active surface of the substrate 210 (i.e., the first surface 212 of the substrate 210). For example, the chip pad 230 may be disposed in the outermost insulating layer of the wiring layer 220. The wafer W may include a die area DA in which circuit patterns and cells are formed and a scribe area SA surrounding the die area DA. As described later, the substrate 210 may be cut along the scribe area SA that divides a plurality of die areas DA of the wafer W for singulation or individualization.

[0070] For example, substrate 210 may include silicon, germanium, silicon germanium, or III-V compounds, such as GaP, GaAs, GaSb, etc. In some embodiments, substrate 210 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0071] A circuit pattern may be provided in the active surface of the substrate 210. The circuit pattern may include a transistor, a diode, etc. The circuit pattern may constitute a circuit element. The chip pad 230 may be electrically connected to the circuit element through wiring in the wiring layer.

[0072] The semiconductor chip 200 may include a memory chip such as a DRAM device or a flash memory device or a non-memory chip such as a logic chip. The chip pad 230 may have a central pad type pad structure in which the chip pads 230 are arranged in a row along a center line. For example, two chip pads 230 adjacent to each other may be arranged in a row along the center line.

[0073] like Fig.10 As shown in FIG. 8 , a plurality of conductive bumps 300 may be formed on a plurality of chip pads 230 .

[0074] A protective layer 240 may be formed on the wiring layer 220 to expose at least a portion of the chip pad 230, and a seed layer may be formed on the chip pad 230. For example, the protective layer 240 may include oxides, nitrides, and the like. These may be used alone or in a mixture thereof. Alternatively, the protective layer 240 may be a polymer layer formed by a spin coating process or a spray coating process. For example, the chip pad 230 may include a conductive metal such as copper (Cu) or aluminum (Al), and the protective layer 240 may include a resin such as photosensitive polyimide (PSPI).

[0075] The seed layer may include an alloy layer made of titanium / copper (Ti / Cu), titanium / palladium (Ti / Pd), titanium / nickel (Ti / Ni), chromium / copper (Cr / Cu), or a combination thereof. The seed layer may be formed by a sputtering process.

[0076] A photoresist pattern having an opening exposing a portion of the seed layer above the chip pad 230 may be formed on the first surface 212 of the substrate 210, and the opening of the photoresist pattern may be filled with a metal material to form the connection pillar 310. The metal material may include nickel (Ni), copper (Cu), palladium (Pd), platinum (Pt), etc.

[0077] A solder layer 320 may be formed on the connection pillar 310 within the opening of the photoresist pattern. The solder layer 320 may be formed on the end of the connection pillar 310. The solder layer 320 may include a metal material having a lower melting point than the melting point of the metal material of the connection pillar 310 and being in a solid state at room temperature. For example, the solder layer 320 may include a solder material. The solder layer 320 may include tin (Sn), tin / silver (Sn / Ag), tin / copper (Sn / Cu), tin / indium (Sn / In), etc. The photoresist pattern may be removed, and the portion of the seed layer exposed by the connection pillar 310 may be removed to form a seed layer pattern 302.

[0078] The connection column 310 may have a rectangular cross-sectional shape with long sides and short sides. The long sides of the connection column 310 may be in the range of 40 μm to 80 μm, and the short sides of the connection column 310 may be in the range of 30 μm to 60 μm. The height (thickness) of the connection column 310 may be in the range of 20 μm to 50 μm. The height (thickness) of the solder layer 320 may be in the range of 5 μm to 20 μm.

[0079] like Fig.11 As shown in FIG. 2 , the wafer W may be cut along the scribe line areas SA by a cutting process to form singulated semiconductor chips 200 .

[0080] Before performing the cutting process, the second surface 214 of the substrate 210 may be polished so that the substrate 210 has a desired thickness.

[0081] Reference Figure 12 to Figure 14 , a package substrate 100 having a chip mounting region MR and at least one pad opening region POR disposed in the chip mounting region MR may be provided. The package substrate 100 may include a wiring 120 having a plurality of pad patterns PP, the plurality of pad patterns PP respectively extending such that at least a portion of each pad pattern is exposed within the at least one pad opening region POR.

[0082] In example embodiments, the package substrate 100 may be a multilayer circuit board having an upper surface 102 and a lower surface 104 opposite to the upper surface 102. For example, the package substrate 100 may be a printed circuit board (PCB) including wirings disposed in a plurality of layers and vias connected to the wirings.

[0083] like Fig.12As shown in FIG. 1 , the package substrate 100 may include a plurality of stacked insulating layers 110 and wirings 120 a , 120 b , 120 c , and 120 d respectively disposed in the insulating layers.

[0084] Specifically, the first insulating layer 110a, the second insulating layer 110b, the third insulating layer 110c, the fourth insulating layer 110d, and the fifth insulating layer 110e may be stacked sequentially. The first insulating layer 110a may be an upper cover insulating layer, the second insulating layer 110b may be an upper insulating layer, the third insulating layer 110c may be a core layer, the fourth insulating layer 110d may be a lower insulating layer, and the fifth insulating layer 110e may be a lower cover insulating layer. The third insulating layer 110c as a core layer may include a non-conductive material layer. The third insulating layer 110c may include a reinforced polymer, etc.

[0085] For example, the insulating layer may include an insulating material having a thermosetting resin such as epoxy resin or a thermoplastic resin such as polyimide. The insulating layer may include a resin impregnated into a core material such as an organic fiber (glass fiber), for example, prepreg, FR-4 or BT (Bismaleimide Triazine).

[0086] The second wiring 120b may be formed on the upper surface of the third insulating layer 110c. The second insulating layer 110b may cover the second wiring 120b on the upper surface of the third insulating layer 110c. The first wiring 120a may be formed on the upper surface of the second insulating layer 110b and may be electrically connected to the second wiring 120b through an opening formed in the second insulating layer 110b.

[0087] The third wiring 120c may be formed on the lower surface of the third insulating layer 110c. The fourth insulating layer 110d may cover the third wiring 120c on the lower surface of the third insulating layer 110c. The fourth wiring 120d may be formed on the lower surface of the fourth insulating layer 110d and may be electrically connected to the third wiring 120c through an opening formed in the fourth insulating layer 110d.

[0088] The first to fourth wirings 120a, 120b, 120c, and 120d may be referred to as first to fourth circuit layers stacked in the thickness direction from the upper surface 102 to the lower surface 104 of the package substrate 100. For example, the wirings may include a metal material such as copper, aluminum, etc. It will be understood that the arrangement and number of the insulating layers and wirings are exemplary and not limited thereto.

[0089] The conductive through via 112 may penetrate the third insulating layer 110c as a core layer and electrically connect the second wiring 120b and the third wiring 120c. The first wiring 120a may be exposed from the upper surface 102 of the package substrate 100. The fourth wiring 120d may be exposed from the lower surface 104 of the package substrate 100.

[0090] The upper insulating layer 150 may be formed on the upper surface 102 of the package substrate 100 and may expose at least a portion of the first wiring 120a. The lower insulating layer 152 may be formed on the lower surface 104 of the package substrate 100 and may expose at least a portion of the fourth wiring 120d. The upper insulating layer 150 and the lower insulating layer 152 may separate the circuit pattern of the package substrate 100 from the external environment to reduce or prevent contamination and electrically insulate the wiring of the circuit pattern from each other. For example, the upper insulating layer and the lower insulating layer may include a photosensitive resin such as a photo epoxy resin or a photosensitive polymer such as a photo solder resist (PSR).

[0091] In addition, the first wiring 120a may include a data signal wiring 120a-1 for transmitting a data signal to the semiconductor chip 200 mounted on the package substrate 100 and a power / ground wiring 120a-2 for transmitting a power signal or a ground signal to the semiconductor chip 200. The data signal wiring 120a-1 used as a data transmission pattern may be provided as a single wiring line, and the power / ground wiring 120a-2 used as a power pattern or a ground wiring may be provided as a plurality of wiring lines and may be electrically connected to each other.

[0092] like Fig.13 As shown in , the upper insulating layer 150 may expose a portion of the wiring 120a within at least one pad opening region POR. The pad opening region POR may correspond to a central pad region of a chip pad 230 where the semiconductor chip 200 is arranged. The portion of the first wiring 120a exposed through the upper insulating layer 150 in the pad opening region POR may be referred to as a pad pattern PP, and the conductive bumps 300 are respectively disposed on the pad patterns PP so that the semiconductor chip 200 is mounted by a flip chip bonding method.

[0093] The plurality of pad patterns PP may be arranged to be laterally spaced apart from each other along one side of the pad opening region POR. For example, the plurality of pad patterns PP may include a first group of pad patterns PP1 and a second group of pad patterns PP2 laterally spaced apart from each other in a first direction (X direction). The first group of pad patterns PP1 may be arranged to be laterally spaced apart from each other in a second direction (Y direction) perpendicular to the first direction along a first side E1 of the pad opening region POR, and the second group of pad patterns PP2 may be arranged to be laterally spaced apart from each other in the second direction (Y direction) along a second side E2 of the pad opening region POR facing the first side E1. The first group of pad patterns PP1 and the second group of pad patterns PP2 may be symmetrical to each other with respect to a center line ML of the pad opening region POR extending parallel to the second direction (Y direction).

[0094] like Fig.14 As shown in FIG. 1 , each of the pad patterns PP may include a main line 132 and a branch line 140. The main line 132 may extend inward from one side E1, E2 of the pad opening region POR in the third direction. The first wiring 120a may include a wiring line 130 covered by an upper insulating layer 150 and a main line 132 exposed through the upper insulating layer 150.

[0095] The branch line 140 may extend in a fourth direction different from the third direction at a position laterally spaced apart by a predetermined distance L2 from the end 133 of the main line 132. The branch line 140 may extend from one side wall 132a of the main line 132 in the fourth direction. An angle θ between the main line 132 and the branch line 140 may be greater than, less than, or equal to 90 degrees. For example, the third direction may be parallel to the X direction, and the fourth direction may be parallel to the Y direction.

[0096] For example, the branch line 140 may be laterally spaced apart from one side E2 of the pad opening region POR by a first distance L1. The first distance L1 may be in the range of 20 μm to 40 μm. The branch line 140 may extend a third length L3 in the fourth direction. The third length L3 of the branch line 140 may be in the range of 10 μm to 30 μm. The lateral spacing distance L2 from the end 133 of the main line 132 to the branch line 140 may be in the range of 50 μm to 100 μm. The first width W1 of the main line 132 and the second width W2 of the branch line 140 may be in the range of 10 μm to 30 μm.

[0097] The branches 140 of the first group of pad patterns PP1 arranged along the first side E1 of the pad opening region POR may extend in the same direction (fourth direction). The branches 140 of the second group of pad patterns PP2 arranged along the second side E2 of the pad opening region POR may extend in the same direction (fourth direction).

[0098] Reference Figures 15 to 20 , the semiconductor chip 200 may be mounted on the package substrate 100 .

[0099] like Fig.15 and Fig.16 As shown in , in example embodiments, the semiconductor chip 200 may be mounted on the package substrate 100 using a flip chip bonding method. In this case, the semiconductor chip 200 may be mounted on the package substrate 100 such that an active surface (ie, the first surface 212) on which the chip pad 230 is formed faces the package substrate 100.

[0100] When the semiconductor chip 200 is placed on the package substrate 100, a portion of the main line 132 between the end 133 of the main line 132 and a branch portion to which the branch line 140 of the main line 132 is connected may be used as a bonding pad on which the conductive bump 300 is disposed. The conductive bump 300 may be disposed on this portion of the main line 132, and during the thermal compression process, the solder layer 320 may be heated and softened, and flow along the main line 132 and the branch line 140 and then be bonded.

[0101] like Fig.17 and Fig.18 As shown in FIG, in the first group of pad patterns PP1 and the second group of pad patterns PP2 spaced apart from each other in the first direction (X direction), during the hot pressing process, the solder layers 320 of the first group of pad patterns PP1 and the second group of pad patterns PP2 may flow in directions A1 and A2 away from each other, respectively, and then be joined to portions of the branch lines 140. That is, the solder layers 320 may flow away from the ends 133 of the adjacent main lines 132 and toward the branch lines 140.

[0102] like Fig.19 As shown in FIG. 1 , in the second group of pad patterns PP2 spaced apart from each other in the second direction (Y direction), each solder layer 320 may flow in the same direction A4 (second direction) during the thermal pressing process and then be bonded to a portion of the branch line 140 .

[0103] like Fig. 20 As shown in , during the hot pressing process, a portion of the solder layer 320 may flow along the main line 132 and the branch line 140 in directions A4 and A2 and may then be solidified to fill a space between the sidewall 132 a of the main line 132 and one sidewall of the branch line 140 .

[0104] Reference Fig.21 , a molding member 400 may be formed on the package substrate 100 to cover the semiconductor chip 200. For example, the molding member 400 may include an insulating material such as an epoxy molding compound.

[0105] For example, a transfer molding device may be used to perform a mold underfill (MUF) process. After placing the semiconductor chip 200 on the package substrate 100 in a cavity between a lower mold and an upper mold of the molding device, a sealing material as a molding resin may be injected into the cavity while the upper mold and the lower mold are clamped to mold the semiconductor chip. For example, the sealing material may include an epoxy molding compound (EMC).

[0106] When the sealing material is injected into the cavity during a mold underfill (MUF) process, air inside the cavity may be discharged to the outside through the sealant passage hole formed in the package substrate 100 , thereby improving resin filling properties. The sealing material may fill the space between the package substrate 100 and the semiconductor chip 200 .

[0107] An external connection member such as a solder ball is formed on the external connection pad on the lower surface 104 of the package substrate 100 (ie, on the portion of the fourth wiring 120d exposed through the lower insulating layer 152) to complete the Figure 1 A semiconductor package 10 is provided.

[0108] Fig. 22 is a cross-sectional view illustrating a semiconductor package according to example embodiments. Fig.23 It is shown Fig. 22 A plan view of the conductive bumps on the package substrate. Fig.24 It is shown Fig.23 An enlarged plan view of portion “L” in FIG. Fig.25 It is along Fig.24 A cross-sectional view taken along line M-M'. Fig.26 It is along Fig.24 A cross-sectional view taken along line N-N'. Fig. 27 It is along Fig.24 A cross-sectional view taken along line O-O'. Fig.28 It is along Fig.24 A cross-sectional view taken along line PP'. Fig.29 is shown in the joint Fig.23 A perspective view of a conductive bump on a pad pattern. Fig. 22 It is along Fig.23 Except for the arrangement of the pad opening area, the pad pattern and the conductive bump, the semiconductor package can be similar to the reference Figures 1 to 8 The semiconductor packages described herein are substantially the same or similar. Therefore, the same reference numerals will be used to refer to the same or similar elements, and any further repeated description of the above elements will be omitted. For example, Fig. 22 The package substrate 100 has the same Figure 2 The package substrate 100 includes the same structure as described above, and Fig. 22Its specific structure will be omitted.

[0109] Reference Figure 22 to Figure 29 The package substrate 100 of the semiconductor package 11 may have a chip mounting region MR and a plurality of pad opening regions POR disposed in the chip mounting region MR. The package substrate 100 may include wiring having a plurality of pad patterns PP, each extending such that at least a portion of the pad pattern is exposed in each pad opening region POR.

[0110] like Fig.23 As shown in , a plurality of pad opening regions POR may be arranged in an array on the package substrate 100. The upper insulating layer 150 may expose a portion of the wiring 120a within each pad opening region POR. The portion of the first wiring 120a exposed by the upper insulating layer 150 in the pad opening region POR may be referred to as a pad pattern PP, and the conductive bumps 300 are respectively disposed on the pad patterns PP so that the semiconductor chip 200 is mounted by a flip chip bonding method. Although four pad opening regions POR are shown, it will be understood that it is not limited thereto.

[0111] In addition, the first wiring 120 a may include a data signal wiring 120 a - 1 for transmitting a data signal to the semiconductor chip 200 mounted on the package substrate 100 and a power / ground wiring 120 a - 2 for transmitting a power signal or a ground signal to the semiconductor chip 200 .

[0112] The plurality of pad patterns PP may be arranged to be laterally spaced apart from each other along one side of the pad opening region POR. For example, the plurality of pad patterns PP may include a first group of pad patterns PP1 and a second group of pad patterns PP2 laterally spaced apart from each other in a first direction (X direction). The first group of pad patterns PP1 may be arranged to be laterally spaced apart from each other in a second direction (Y direction) perpendicular to the first direction along a first side E1 of the pad opening region POR, and the second group of pad patterns PP2 may be arranged to be laterally spaced apart from each other in the second direction (Y direction) along a second side E2 of the pad opening region POR facing the first side E1.

[0113] The first group of pad patterns PP1 and the second group of pad patterns PP2 may be symmetrical to each other with respect to a center line ML of the pad opening region POR extending parallel to the second direction (Y direction). The first group of pad patterns PP1 arranged along the second direction (Y direction) may have the same shape. The second group of pad patterns PP2 arranged along the second direction (Y direction) may have the same shape.

[0114] like Fig.24As shown in FIG. 1 , each of the pad patterns PP may include a main line 132 and a branch line 140. The main line 132 may extend inward from one side E1, E2 of the pad opening region POR in the third direction. The first wiring 120a may include a wiring line 130 covered by an upper insulating layer 150 and a main line 132 exposed through the upper insulating layer 150.

[0115] The branch line 140 may extend from the end 133 of the main line 132 in a fourth direction different from the third direction. The branch line 140 may extend from one side wall 132a of the main line 132 in the fourth direction. An angle θ between the main line 132 and the branch line 140 may be greater than, less than, or equal to 90 degrees. For example, the third direction may be parallel to the X direction, and the fourth direction may be parallel to the Y direction.

[0116] The branches 140 of the first group of pad patterns PP1 arranged along the first side E1 of the pad opening region POR may extend in the same direction (fourth direction). The branches 140 of the second group of pad patterns PP2 arranged along the second side E2 of the pad opening region POR may extend in the same direction (fourth direction).

[0117] When the semiconductor chip 200 is placed on the package substrate 100, a portion of the branch line 140 may be used as a bonding pad on which the conductive bump 300 is disposed. The conductive bump 300 may be disposed on the portion of the branch line 140, and during the thermal compression process, the solder layer 320 may be heated and softened and flow along one sidewall of the branch line 140 and the main line 132 and then be bonded.

[0118] like Fig.25 and Fig.26 As shown in FIG. 1 , in the first group of pad patterns PP1 and the second group of pad patterns PP2 spaced apart from each other in the first direction (X direction), each solder layer 320 may flow in directions away from each other (opposite directions) along the main line 132 and be bonded to a portion of the main line 132. Therefore, the occurrence of a short circuit defect due to overflow of the solder layer 320 between the adjacent main lines 132 and branch lines 140 of the first group of pad patterns PP1 and the second group of pad patterns PP2 may be reduced or prevented.

[0119] like Fig. 27 As shown in FIG. 1 , in the second group of pad patterns PP2 spaced apart from each other in the second direction (Y direction) along the second side E2 of the pad opening region POR, each solder layer 320 may be bonded to a portion of the main line 132 extending in a third direction different from the direction in which the branch line 140 extends. Therefore, a short circuit defect between adjacent main lines 132 and branch lines 140 due to overflow of the solder layer 320 may be reduced or prevented.

[0120] like Fig.28 and Fig.29As shown in FIG. 1 , a portion of the solder layer 320 may flow from the branch line 140 to the main line 132 and then harden to fill a space between one sidewall of the branch line 140 and a sidewall 132 a of the main line 132 .

[0121] For example, the branch line 140 may be spaced apart from one side E2 of the pad opening region POR by a first distance L1. The first distance L1 may be in the range of 20 μm to 40 μm. The branch line 140 may extend a third length L3 in the fourth direction. The third length L3 of the branch line 140 may be in the range of 50 μm to 100 μm. The first width W1 of the main line 132 and the second width W2 of the branch line 140 may be in the range of 10 μm to 30 μm.

[0122] The long side W3y of the connection column 310 may be in the range of 40 μm to 80 μm, and the short side W3x of the connection column 310 may be in the range of 30 μm to 60 μm. The extension direction of the long side W3y of the connection column 310 may be parallel to the fourth direction, and the extension direction of the short side W3x of the connection column 310 may be parallel to the third direction. The height W3z of the connection column 310 may be in the range of 20 μm to 50 μm. The height (thickness) of the solder layer 320 may be in the range of 5 μm to 20 μm.

[0123] As mentioned above, each of the plurality of pad patterns PP may include a main line 132 extending inwardly from one side E1, E2 of the pad opening region POR in a third direction and a branch line 140 extending in a fourth direction different from the third direction from an end 133 of the main line 132. Each of the conductive bumps 300 may be disposed on a portion of the branch line 140.

[0124] The branch lines 140 may be formed to extend in the same direction (fourth direction) so that each solder layer 320 of the conductive bump 300 may flow to the main line 132 extending in the same direction (third direction) and may be bonded to a portion of the main line 132. Therefore, the occurrence of a short circuit defect between the adjacent main lines 132 and branch lines 140 due to overflow of the solder layer 320 may be reduced or prevented.

[0125] In the following, the manufacturing Fig. 22 A method for a semiconductor package in a semiconductor device.

[0126] Figure 30 to Figure 35 is a cross-sectional view illustrating a method of manufacturing a semiconductor package according to example embodiments. Fig.30 , Fig.33 and Fig.35 is a cross-sectional view illustrating a method of manufacturing a semiconductor package according to example embodiments. Fig.31 yes Fig.30 Floor plan. Fig.32 It is shown Fig.31 An enlarged plan view of portion "R" in FIG. Fig.34 It is shown Fig.33 A plan view of the conductive bumps on the package substrate. Fig.30 It is along Fig.31 A cross-sectional view taken along line Q-Q'.

[0127] Reference Fig.30 , a package substrate 100 having a chip mounting region MR and a plurality of pad opening regions POR disposed in the chip mounting region MR may be provided. The package substrate 100 may include wiring having a plurality of pad patterns PP, each of which extends such that at least a portion of the pad pattern is exposed in each pad opening region POR.

[0128] The package substrate 100 may include a plurality of stacked insulating layers 110 and wirings 120a and 120d respectively disposed in the insulating layers. An upper insulating layer 150 may be formed on the upper surface 102 of the package substrate 100 and may expose at least a portion of the first wiring 120a. A lower insulating layer 152 may be formed on the lower surface 104 of the package substrate 100 and may expose at least a portion of the fourth wiring 120d. The package substrate 100 may be connected to the package substrate 100. Figure 1 Therefore, descriptions of the same or similar elements of the package substrate will be omitted.

[0129] like Fig.31 As shown in , a plurality of pad opening regions POR may be arranged in an array on the package substrate 100. The upper insulating layer 150 may expose a portion of the wiring 120a within each pad opening region POR. The portion of the first wiring 120a exposed by the upper insulating layer 150 in the pad opening region POR may be referred to as a pad pattern PP, and the conductive bumps 300 are respectively disposed on the pad patterns PP so that the semiconductor chip 200 is mounted by a flip chip bonding method. Although four pad opening regions POR are shown, it will be understood that it is not limited thereto.

[0130] In addition, the first wiring 120 a may include a data signal wiring 120 a - 1 for transmitting a data signal to the semiconductor chip 200 mounted on the package substrate 100 and a power / ground wiring 120 a - 2 for transmitting a power signal or a ground signal to the semiconductor chip 200 .

[0131] The plurality of pad patterns PP may be arranged to be spaced apart from each other along one side of the pad opening region POR. For example, the plurality of pad patterns PP may include a first group of pad patterns PP1 and a second group of pad patterns PP2 spaced apart from each other in a first direction (X direction). The first group of pad patterns PP1 may be arranged to be spaced apart from each other in a second direction (Y direction) perpendicular to the first direction along a first side E1 of the pad opening region POR, and the second group of pad patterns PP2 may be arranged to be spaced apart from each other in the second direction (Y direction) along a second side E2 of the pad opening region POR facing the first side E1. The first group of pad patterns PP1 and the second group of pad patterns PP2 are symmetrical to each other with respect to a center line ML of the pad opening region POR extending parallel to the second direction (Y direction).

[0132] like Fig.32 As shown in FIG. 1 , each of the pad patterns PP may include a main line 132 and a branch line 140. The main line 132 may extend inward from one side E1, E2 of the pad opening region POR in the third direction. The first wiring 120a may include a wiring line 130 covered by an upper insulating layer 150 and a main line 132 exposed through the upper insulating layer 150.

[0133] The branch line 140 may extend from the end 133 of the main line 132 in a fourth direction different from the third direction. The branch line 140 may extend from one side wall 132a of the main line 132 in the fourth direction. An angle θ between the main line 132 and the branch line 140 may be greater than, less than, or equal to 90 degrees. For example, the third direction may be parallel to the X direction, and the fourth direction may be parallel to the Y direction.

[0134] For example, the branch line 140 may be spaced apart from one side E2 of the pad opening region POR by a first distance L1. The first distance L1 may be in the range of 20 μm to 40 μm. The branch line 140 may extend a third length L3 in the fourth direction. The third length L3 of the branch line 140 may be in the range of 50 μm to 100 μm. The first width W1 of the main line 132 and the second width W2 of the branch line 140 may be in the range of 10 μm to 30 μm.

[0135] The branches 140 of the first group of pad patterns PP1 arranged along the first side E1 of the pad opening region POR may extend in the same direction (fourth direction). The branches 140 of the second group of pad patterns PP2 arranged along the second side E2 of the pad opening region POR may extend in the same direction (fourth direction).

[0136] Reference Fig.33 and Fig.34 , the semiconductor chip 200 may be mounted on the package substrate 100 .

[0137] In example embodiments, the semiconductor chip 200 may be mounted on the package substrate 100 using a flip chip bonding method. In this case, the semiconductor chip 200 may be mounted on the package substrate 100 such that an active surface (ie, the first surface 212 ) on which the chip pad 230 is formed faces the package substrate 100 .

[0138] The semiconductor chip 200 includes a plurality of chip pad regions arranged in an array, and a chip pad 230 may be provided in each chip pad region. The chip pad regions of the semiconductor chip 200 may be arranged to correspond to the pad opening regions POR of the package substrate 100, respectively. The semiconductor chip 200 may be a thermal test chip. The thermal distribution of the chip (die) may be measured through the chip pad 230 of the semiconductor chip 200.

[0139] A plurality of conductive bumps 300 may be formed on the plurality of chip pads 230 , respectively. Each of the plurality of conductive bumps 300 may include a connection column 310 extending from the chip pad 230 of the semiconductor chip 200 and a solder layer 320 bonded to an end of the connection column 310 .

[0140] When the semiconductor chip 200 is placed on the package substrate 100, a portion of the branch line 140 may be used as a bonding pad on which the conductive bump 300 is disposed. The conductive bump 300 may be disposed on the portion of the branch line 140, and during the thermal compression process, the solder layer 320 may be heated and softened and flow along one sidewall of the branch line 140 and the main line 132 and then be bonded.

[0141] like Fig.34 As shown in , during the hot pressing process, a portion of the solder layer 320 may flow from the branch line 140 to the main line 132 and may then be solidified to fill a space between one sidewall of the branch line 140 and a sidewall 132 a of the main line 132 .

[0142] Reference Fig.35 , a molding member 400 may be formed on the package substrate 100 to cover the semiconductor chip 200. The molding member (sealing member) 400 may include an epoxy molding compound (EMC).

[0143] For example, a transfer molding device may be used to perform a molded underfill (MUF) process. During the molded underfill (MUF) process, when a sealing material is injected into the cavity between the lower mold and the upper mold, air in the cavity may be discharged to the outside through a sealant channel hole formed in the package substrate 100 to improve the resin filling property. The sealing material may fill the space between the package substrate 100 and the semiconductor chip 200.

[0144] An external connection member such as a solder ball may be formed on the external connection pad on the lower surface 104 of the package substrate 100 (ie, on a portion of the fourth wiring 120d exposed through the lower insulating layer 152) to complete the Fig. 22 A semiconductor package 11 is provided.

[0145] The semiconductor package may include a semiconductor device such as a logic device or a memory device. The semiconductor package may include a logic device (such as a central processing unit (CPU), a main processing unit (MPU), or an application processor (AP), etc.) and a volatile memory device (such as a DRAM device, an HBM device) or a non-volatile memory device (such as a flash memory device, a PRAM device, an MRAM device, a ReRAM device, etc.).

[0146] The foregoing is an illustration of example embodiments and is not to be construed as limiting thereof. Although several example embodiments have been described, those skilled in the art will readily appreciate that many modifications may be made in the example embodiments without materially departing from the novel teachings and advantages of the present invention. Therefore, all such modifications are intended to be included within the scope of the example embodiments defined in the claims.

Claims

1. A semiconductor package, comprising: a package substrate including a chip mounting area and at least one pad opening area in the chip mounting area, the package substrate including wiring having a plurality of pad patterns, the plurality of pad patterns respectively extending so that at least a portion of each of the plurality of pad patterns is exposed in the at least one pad opening area; A semiconductor chip is mounted on a chip mounting area of ​​a package substrate via a plurality of conductive bumps; as well as A sealing member is located on the semiconductor chip on the packaging substrate, wherein the plurality of pad patterns are laterally spaced apart from each other, Each of the plurality of pad patterns includes: a main line extending in a first direction away from a side of the pad opening area; and a branch line extending in a second direction different from the first direction, and wherein the branch line extends from an end of the main line and each of the plurality of conductive bumps is located on an upper surface of the branch line, or wherein the branch line extends from a position laterally spaced apart from the end of the main line and each of the plurality of conductive bumps is located on an upper surface of a portion of the main line between the end and the position from which the branch line extends.

2. The semiconductor package according to claim 1, wherein: The branch line is laterally spaced apart from the one side of the pad opening area in the first direction by a distance of 20 μm to 40 μm.

3. The semiconductor package according to claim 1, wherein: The branch line extends in the second direction from a position laterally spaced apart from an end of the main line by a length of 10 μm to 30 μm.

4. The semiconductor package according to claim 1, wherein: The branch line extends in the second direction from the end of the main line by a length of 50 μm to 100 μm.

5. The semiconductor package according to claim 1, wherein: The second direction is perpendicular to the first direction.

6. The semiconductor package according to claim 1, wherein: Each of the plurality of conductive bumps includes a connection column extending from a chip pad of the semiconductor chip and a solder layer on an end of the connection column opposite to the chip pad.

7. The semiconductor package according to claim 6, wherein: The branch line extends from a position laterally spaced from an end of the main line, and the solder layer extends along a sidewall of the main line to a sidewall of the branch line to at least partially fill a space between the main line and the branch line.

8. The semiconductor package according to claim 7, wherein: The connecting column has a first side and a second side shorter than the first side, and an extending direction of the first side is parallel to the first direction.

9. The semiconductor package according to claim 6, wherein: The branch line extends from an end of the main line, and the solder layer extends from a side wall of the branch line to a side wall of the main line to at least partially fill a space between the branch line and the main line.

10. The semiconductor package according to claim 9, wherein: The connecting column has a first side and a second side shorter than the first side, and an extending direction of the first side is parallel to the second direction.

11. A semiconductor package, comprising: a package substrate including at least one pad opening region, the package substrate including wiring having a plurality of pad patterns, the plurality of pad patterns respectively extending such that at least a portion of each of the plurality of pad patterns is exposed in the at least one pad opening region; a semiconductor chip including a plurality of chip pads on a first surface of the semiconductor chip and oriented so that the first surface faces an upper surface of the package substrate; a plurality of conductive bumps, respectively on the plurality of chip pads, wherein the plurality of conductive bumps bond the plurality of chip pads to corresponding portions of the plurality of pad patterns; and a sealing member located on the semiconductor chip on the packaging substrate, the sealing member at least partially surrounding the plurality of conductive bumps between the packaging substrate and the semiconductor chip, wherein each of the plurality of pad patterns comprises: a main line extending away from one side of the pad opening area in a first direction; and a branch line extending from a position laterally spaced apart from an end of the main line in a second direction different from the first direction, and Wherein, each of the plurality of conductive bumps is located on an upper surface of a portion of the main line between the end portion and the position from which the branch line extends.

12. The semiconductor package according to claim 11, wherein The branch line is laterally spaced apart from the one side of the pad opening area in the first direction by a distance of 20 μm to 40 μm.

13. The semiconductor package according to claim 11, wherein: The branch line has a length of 10 μm to 30 μm in the second direction.

14. The semiconductor package according to claim 11, wherein Each of the plurality of conductive bumps includes a connection column extending from a corresponding one of the plurality of chip pads of the semiconductor chip and a solder layer on an end of the connection column opposite to the corresponding one of the plurality of chip pads.

15. The semiconductor package according to claim 14, wherein: The solder layer extends along the sidewall of the main line to the sidewall of the branch line to at least partially fill the space between the main line and the branch line.

16. A semiconductor package, comprising: a package substrate including at least one pad opening region, the package substrate including wiring having a plurality of pad patterns, the plurality of pad patterns respectively extending such that at least a portion of each of the plurality of pad patterns is exposed in the at least one pad opening region; a semiconductor chip including a plurality of chip pads on a first surface of the semiconductor chip and oriented so that the first surface faces an upper surface of the package substrate; a plurality of conductive bumps, respectively on the plurality of chip pads, wherein the plurality of conductive bumps bond the plurality of chip pads to corresponding portions of the plurality of pad patterns; and a sealing member located on the semiconductor chip on the packaging substrate, the sealing member at least partially surrounding the plurality of conductive bumps between the packaging substrate and the semiconductor chip, Each of the plurality of pad patterns includes: a main line extending in a first direction away from a side of the pad opening area; and a branch line extending from an end of the main line in a second direction different from the first direction, and Wherein, each of the plurality of conductive bumps is located on an upper surface of the branch line.

17. The semiconductor package according to claim 16, wherein: The branch line is laterally spaced apart from the one side of the pad opening area in the first direction by a distance of 20 μm to 40 μm.

18. The semiconductor package according to claim 16, wherein: The branch line has a length of 50 μm to 100 μm in the second direction.

19. The semiconductor package according to claim 16, wherein: Each of the plurality of conductive bumps includes a connection column extending from a corresponding one of the plurality of chip pads of the semiconductor chip and a solder layer on an end of the connection column opposite to the corresponding one of the plurality of chip pads.

20. The semiconductor package according to claim 19, wherein The solder layer extends along the sidewalls of the branch line to the sidewalls of the main line to at least partially fill the space between the branch line and the main line.

Images