Diode packaging structure and packaging process thereof

Abstract

The invention discloses a diode packaging structure and a packaging process thereof, the diode packaging structure comprises a packaging body, the packaging body is internally and sequentially packaged with a chip from bottom to top, and the output end of the chip is electrically connected with a conductive ball through a ball mounting process; the rewiring layer is electrically connected with the conductive balls, the rewiring layer is arranged at the position, close to the edge of the chip, above the chip in an electroplating mode, and the rewiring layer avoids the central metal area of the chip; the conductive column is vertically and electrically connected to one end of the rewiring layer, and the diameter of the conductive column is the same as that of the rewiring layer; according to the invention, the rewiring layer is electroplated and extended at the position, close to the edge of the chip, on the conductive ball at the output end of the chip, so that a metal area in the center of the chip is avoided, and the rewiring layer is electrically connected to the end, far away from the rewiring layer, of the conductive ball; and parasitic capacitance caused by an electric field and mutual inductance effect between the rewiring layer and chip center metal is effectively reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor packaging, and in particular relates to a diode packaging structure and a packaging process thereof. Background Art

[0002] Semiconductor packaging refers to the process of processing tested wafers into independent chip packages according to product models and functional requirements. The specific packaging process is as follows: the wafers from the front-end wafer process are cut into small chips (Die) through a dicing process, and then the chips are mounted in corresponding positions through a mounting process. The circuit connections are designed according to the product structure requirements, and the chips are sealed through an encapsulation process, that is, the independent chips are packaged and protected with a plastic shell. A series of operations are required after plastic sealing, such as finished product testing after packaging is completed. Usually, it goes through inspection, testing, and packaging processes before being put into storage for shipment. Diodes are one type of semiconductor.

[0003] The existing semiconductor device packaging structure is formed by traditional electroplating and encapsulation processes. The potential difference between the upper and lower connecting circuits is large and the circuit extension routing is random, resulting in strong electric fields and mutual inductance between devices, between circuit layers, and between devices and circuits. The parasitic capacitance of the entire structure is large and cannot meet the ultra-low capacitance product requirements. Summary of the invention

[0004] In order to solve the above problems in the prior art, the present invention provides a diode packaging structure and a packaging process thereof.

[0005] To achieve the above object, the present invention provides a diode packaging structure, including a packaging body, wherein the packaging body sequentially encapsulates: Chip: The output end of the chip is electrically connected to a conductive ball through a ball planting process; Rewiring layer: The rewiring layer is electrically connected to the conductive ball, and the rewiring layer is electroplated and arranged above the chip near the edge of the chip, and the rewiring layer avoids the central metal area of ​​the chip; Conductive column: the conductive column is vertically electrically connected to one end of the redistribution layer, and the diameter of the conductive column is the same as the diameter of the redistribution layer; Solder foot: The solder foot is electrically connected to one end of the conductive column away from the redistribution layer, and the other end of the solder foot is flush with a surface of the package body and exposed.

[0006] Furthermore, the conductive column is a copper column directly formed by electroplating on one end of the redistribution layer or a via column formed by drilling a hole in the encapsulation material to expose the redistribution layer and then mounting it, and the diameter of the conductive column is ≤80 μm.

[0007] Furthermore, the conductive balls, the redistribution layer, the conductive pillars and the solder feet are stacked in sequence by electroplating above the chip output end.

[0008] Furthermore, the total height of the conductive balls, the redistribution layer and the conductive pillars is ≥100 μm.

[0009] Furthermore, the total thickness of the package body is ≤0.25 mm.

[0010] Furthermore, the solder pins are exposed on the surface of the package body and are electroplated with tin or gold.

[0011] A diode packaging process comprises the following steps: Chip encapsulation: After the conductive ball is electrically connected to the chip output end through the ball planting process, the chip and the conductive ball are completely encapsulated with an encapsulation material. After the encapsulation material is cured, the top of the conductive ball is exposed by mechanical grinding at the level of the encapsulation surface; Rewiring layer plating: a rewiring layer electrically connected to the conductive ball is plated on the package surface where the top of the conductive ball is exposed. The rewiring layer plating is set above the chip near the edge of the chip, and the rewiring layer avoids the central metal area of ​​the chip. Conductive column electroplating: an electrically connected conductive column is arranged at one end of the redistribution layer, and the diameter of the conductive column is the same as the diameter of the redistribution layer. The redistribution layer and the conductive column are completely encapsulated with an encapsulating material. After the encapsulating material is cured, mechanical grinding is performed at the level of the encapsulation surface to expose the top surface of the conductive column. Solder foot electroplating: Electroplating the solder feet electrically connected to the conductive pillars on the package surface that exposes the top surface of the conductive pillars, continue to encapsulate the solder feet and grind to expose the top surface of the solder feet to form the final package product unit.

[0012] Furthermore, in the conductive column electroplating step, the conductive column is a copper column directly electroplated on one end of the redistribution layer or a via column formed by encapsulating the redistribution layer, drilling a hole in the encapsulation material to expose the redistribution layer and mounting it, and the diameter of the conductive column is ≤80μm.

[0013] Furthermore, in the solder foot electroplating step, the conductive ball, the redistribution layer, the conductive column and the solder foot are electroplated and stacked in sequence above the chip output terminal.

[0014] Furthermore, in the conductive column electroplating step, the total height of the conductive balls, the redistribution layer and the conductive columns is ≥100 μm.

[0015] Furthermore, in the solder foot electroplating step, the total thickness of the package finally formed is ≤0.25 mm.

[0016] Furthermore, in the solder foot electroplating step, tin or gold protrusions are electroplated on the surface of the solder foot exposed on the package body.

[0017] The present invention: 1. The redistribution layer is electroplated and extended on the conductive ball at the chip output end near the edge of the chip, avoiding the central metal area of ​​the chip, effectively reducing the parasitic capacitance caused by the electric field and mutual inductance between the redistribution layer and the central metal of the chip; 2. The welding feet are encapsulated in the encapsulation material. When the package body is welded to the working area through the welding feet, the thrust and surface bonding force after welding are improved, making the welding structure more stable. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 A product cross-sectional view of a diode packaging structure of the present invention; Figure 2-Figure 4 A cross-sectional view of a chip encapsulation step of a diode packaging process of the present invention; Figure 5 A cross-sectional view of a redistribution layer electroplating step of a diode packaging process of the present invention; Figure 6-Figure 7 A cross-sectional view of a conductive column electroplating step in a diode packaging process of the present invention; Figure 8-Figure 12 The cross-sectional view is a solder foot electroplating step of a diode packaging process of the present invention.

[0019] In the figure: 1. Package body; 2. Chip; 3. Redistribution layer; 4. Conductive column; 5. Solder pin. DETAILED DESCRIPTION

[0020] The content of the present invention will be explained below in conjunction with specific embodiments, examples of which are shown in the accompanying drawings, wherein the same or similar numbers throughout represent the same or similar components or components with the same or similar functions.

[0021] The directional terms mentioned in the present invention, such as: up, down, left, right, front, back, inside, outside, front, back, side, etc., are only reference directions of the drawings. The embodiments described below with reference to the drawings and the directional terms used are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention. In addition, the various specific process and material examples provided in the present invention are all those skilled in the art who can recognize the application of other processes and / or the use of other materials.

[0022] In order to better understand the purpose, structure and function of the present invention, the following is a further detailed description of a diode packaging process proposed by the present invention in conjunction with the accompanying drawings. The process includes the following steps: Chip 2 encapsulation: After the conductive ball is electrically connected to the output end of chip 2 through the ball planting process, the chip 2 and the conductive ball are completely encapsulated with an encapsulation material. After the encapsulation material is cured, the top of the conductive ball is exposed by mechanical grinding at the level of the encapsulation surface; Redistribution layer 3 electroplating: a redistribution layer 3 electrically connected to the conductive ball is electroplated on the package surface where the top of the conductive ball is exposed. The redistribution layer 3 is electroplated above the chip 2 and near the edge of the chip 2. The redistribution layer 3 avoids the central metal area of ​​the chip 2. Conductive column 4 is arranged: an electrically connected conductive column 4 is arranged at one end of the redistribution layer 3, the diameter of the conductive column 4 is the same as the diameter of the redistribution layer 3, and the redistribution layer 3 and the conductive column 4 are completely encapsulated with an encapsulating material. After the encapsulating material is cured, the top surface of the conductive column 4 is exposed by mechanical grinding at the level of the encapsulation surface; Solder pin 5 electroplating: Solder pin 5 electrically connected to conductive pillar 4 is electroplated on the package surface that exposes the top surface of conductive pillar 4, and solder pin 5 is further encapsulated and polished to expose the top surface of solder pin 5 to form a final package 1 product unit.

[0023] Among them, Figure 2-Figure 4 As shown, in the chip 2 encapsulation step, the chip 2 can be one or more of a variety of semiconductor devices, such as transistors, memories, diodes and / or triodes, etc. The present invention takes the diode chip 2 as an example. The diode is also called a crystal diode, which is one of the most commonly used electronic components. The biggest characteristic is unidirectional conductivity, that is, the current can only flow through the diode in one direction. The diode can be a rectifier circuit, a detector circuit, a voltage stabilization circuit and a modulation circuit in the circuit. As a basic semiconductor device, the diode will have parasitic capacitance in the package. The parasitic capacitance can also be called a secondary capacitance or stray capacitance, which refers to the capacitance unintentionally generated in the circuit or component. The parasitic capacitance will have a significant impact on the performance of the circuit. A larger parasitic capacitance will introduce additional capacitive loads, resulting in phase delay and amplitude attenuation of the signal, thereby reducing the operating frequency of the diode. The parasitic capacitance will also interact with other components in the circuit to cause resonance and other influencing behaviors, resulting in a weakening of the circuit signal strength. The existence of parasitic capacitance is related to various factors, including electric fields and mutual inductance between devices, between various layers of the circuit, and between the device and the circuit. The present invention reduces the parasitic capacitance by improving the diode packaging process.

[0024] The chips 2 are evenly distributed on an entire wafer. An electrically connected conductive ball (not shown in the figure) is set on each output end of the chip 2 through a ball planting process. The wafer is diced and cut into chip units, namely chips 2, and qualified chips 2 are tested and screened. The electrical output end on the front side (active side) of each chip 2 is electrically connected with a conductive ball. The back of the chip 2 is facing the substrate and firmly adhered to it through an adhesive layer for mounting. Multiple evenly arranged chips 2 can be adhered to the substrate at one time. The first encapsulation is performed using an encapsulation material. The chip 2 is completely encapsulated on the substrate. After the encapsulation material is solidified, the encapsulation surface is horizontally mechanically ground until the top of the conductive ball is exposed. The ground encapsulation surface is horizontally flat, and the top of the conductive ball is exposed. The substrate serves as a supporting platform for each step in the packaging process. It can be a silicon substrate, a metal substrate, or other suitable materials. The adhesive layer can be removed later by chemical corrosion, mechanical stripping, chemical mechanical polishing, mechanical grinding, etc., so that the substrate is stripped.

[0025] Among them, Figure 5 As shown, in the electroplating step of the redistribution layer 3, the package surface is horizontally flattened and the redistribution layer 3 is electroplated through the electroplating process. The redistribution layer 3 is flatly extended along the package surface. The redistribution layer 3 is electroplated and connected with the conductive ball to form an electrical connection. The redistribution layer 3 is a plated metal material. The redistribution layer 3 extends on the conductive ball at the output end of the chip 2 near the edge of the chip 2. While the output end of the chip 2 is electrically rearranged, the redistribution layer 3 avoids the central metal area of ​​the chip 2, thereby effectively reducing the parasitic capacitance caused by the electric field and mutual inductance between the redistribution layer 3 and the central metal of the chip 2.

[0026] Among them, Figure 6-Figure 7 As shown, in the step of setting the conductive column 4, the conductive column 4 is a copper column directly formed by electroplating at one end of the redistribution layer 3, or a via column formed by drilling a hole in the encapsulation material to expose the redistribution layer 3 and mounting it after encapsulating the redistribution layer 3. Specifically, the conductive column 4 is directly electroplated and connected as one at one end of the redistribution layer 3 extending close to the edge of the chip 2, the conductive column 4 is electrically connected to the redistribution layer 3, and the central axis of the conductive column 4 is vertically electroplated and arranged perpendicular to the redistribution layer 3; or after the redistribution layer 3 is electroplated, the encapsulation material is used to completely encapsulate and solidify it, and a hole is drilled on the encapsulation surface to remove the corresponding encapsulation material on the end of the redistribution layer 3 extending close to the edge of the chip 2, and a conductive column 4 is formed in the transfer hole. The via column is electrically connected to the redistribution layer 3. The present invention adopts a method of directly electroplating a copper column on the redistribution layer 3 to form a conductive column 4. In the designed structure, the diameter of the conductive column 4 is ≤80μm, and the diameter of the conductive column 4 is the same as the diameter of the redistribution layer 3, which ensures the smooth transmission of current, reduces the generation of potential difference between the two, and further reduces the parasitic capacitance. After the conductive column 4 is electrically connected to the redistribution layer 3, the encapsulation material is used again to continue encapsulation on the encapsulation surface where the top of the conductive ball is exposed by grinding. The redistribution layer 3 and the conductive column 4 are completely encapsulated and the top surface of the conductive column 4 is exposed by horizontal mechanical grinding on the encapsulation surface.

[0027] Among them, Figure 8-Figure 10 As shown, in the electroplating step of the solder foot 5, the solder foot 5 continues to be electroplated on the ground package surface, and the solder foot 5 and the exposed top surface of the conductive column 4 are electroplated as a whole to achieve electrical connection between the two, and the encapsulation material continues to be used to encapsulate the package surface on the exposed top surface of the conductive column 4 to completely encapsulate the solder foot 5. After the encapsulation material is solidified, the top surface of the solder foot 5 is exposed by horizontal mechanical grinding on the newly formed package surface; the conductive ball, the redistribution layer 3, the conductive column 4 and the solder foot 5 are electroplated and stacked in sequence above the output end of the chip 2, and the total height of the conductive ball, the redistribution layer 3 and the conductive column 4 is ≥100μm, that is, the distance from the solder foot 5 to the surface of the chip 2 is controlled to be ≥100μm, which weakens the electric field and mutual inductance effects, reduces the parasitic capacitance of the chip 2 device and the circuit layer, and once again reduces the parasitic capacitance. The final product meets the requirements of ultra-low capacitance, and the total capacitance value is ≤0.2PF.

[0028] After the encapsulation is completed, the substrate is peeled off, and the entire encapsulation board is turned upside down and placed back on the substrate. Since the back of the chip 2 is mounted on the substrate, after peeling, the back of the chip 2 is exposed, and then the back of the chip 2 is completely encapsulated through the encapsulation process. After the encapsulation material is solidified, the top surface of the encapsulation is horizontally mechanically ground to make the encapsulation surface level and flat.

[0029] At this point, the packaging process is completed. Since multiple chips 2 are evenly arranged on the substrate and encapsulated at one time, each electroplating, encapsulation, and grinding process completes the same structure on each chip 2, and the entire packaging board is cut into product units of the package body 1 on the cutting path reserved between each chip 2. The total thickness of the final package body 1 is ≤0.25mm, which is suitable for the packaging of ultra-thin products and also suitable for CSP packaging technology.

[0030] In the final product unit of the package 1, the solder foot 5 is flush with the surface of the package 1 and exposed. The solder foot 5 is electroplated with a tin or gold bump (not shown in the figure) on the surface of the package 1 where the solder foot 5 is exposed, which can protect the solder foot 5 from corrosion. At the same time, the solder foot 5 is encapsulated in the encapsulation material. When the package 1 is welded to the working area through the solder foot 5, the thrust force and surface bonding strength after welding are increased, making the welding structure more stable.

[0031] A diode packaging structure can be obtained through the above diode packaging process. Figure 1 As shown, the packaging structure includes a packaging body 1, and the packaging body 1 contains the following from bottom to top: Chip 2: The output end of the chip 2 is electrically connected to a conductive ball through a ball planting process; Redistribution layer 3: the redistribution layer 3 is electrically connected to the conductive ball, and the redistribution layer 3 is electroplated and arranged above the chip 2 near the edge of the chip 2, and the redistribution layer 3 avoids the central metal area of ​​the chip 2; Conductive column 4: The conductive column 4 is vertically electrically connected to one end of the redistribution layer 3, and the diameter of the conductive column 4 is the same as the diameter of the redistribution layer 3; Solder pin 5 : The solder pin 5 is electrically connected to one end of the conductive pillar 4 away from the redistribution layer 3 , and the other end of the solder pin 5 is flush with a surface of the package body 1 and exposed.

[0032] The conductive column 4 is a copper column directly formed by electroplating at one end of the redistribution layer 3, or a via column is formed in the drilled hole after drilling a hole in the encapsulation material to expose the redistribution layer 3, and the diameter of the conductive column 4 is ≤80μm, and the diameter of the conductive column 4 is the same as the diameter of the redistribution layer 3, ensuring the smooth transmission of current, reducing the generation of potential difference between the two, and further reducing parasitic capacitance; the conductive ball, the redistribution layer 3, the conductive column 4 and the solder foot 5 are electroplated and stacked in sequence above the output end of the chip 2; the total height of the conductive ball, the redistribution layer 3 and the conductive column 4 is ≥100μm, that is, the distance from the solder foot 5 to the surface of the chip 2 is controlled to be ≥100μm, which weakens the electric field and mutual inductance effects, reduces the parasitic capacitance of the chip 2 device and the circuit layer, and once again reduces the parasitic capacitance. The final product meets the requirements of ultra-low capacitance, and the capacitance value is ≤0.2PF; the total thickness of the package body 1 is ≤0.25mm, which is suitable for the packaging of ultra-thin products and also suitable for CSP packaging technology.

[0033] The encapsulation material used in the present invention is a plastic encapsulation material, and the specific material can be epoxy resin, cyanate, polyimide, etc., which has low cost and good curing performance. The encapsulation process plays an important role in the field of semiconductor manufacturing, mainly in terms of protection, connection, support, reliability and promotion of technological progress. The protection function refers to the ability to protect the internal structure from mechanical damage, moisture, dust and other external environmental factors, ensuring the normal operation of the device in extreme environments; the connection function refers to the fact that the encapsulation provides a way to connect the device with other electronic components, so that the device can be installed and used on the circuit board; the support function refers to the fact that the encapsulation material can fix the device while supporting the device to prevent it from being damaged; reliability refers to the increasingly high reliability requirements for packaging materials and processes to ensure that the device can operate normally in various extreme environments. The encapsulation material can be encapsulated by injection molding or transfer molding, and then a curing process is performed to harden the encapsulation material. According to the specific component proportion of the encapsulation material, a suitable curing temperature is selected, which is approximately between 100 and 320°C.

[0034] All the steps of the electroplating process of the present invention are to first form electroplating protection on the surface through exposure and development photolithography technology, protect the areas that do not need electroplating, expose the areas that need electroplating, and then form a metal seed layer in the area to be electroplated by sputtering or copper deposition or other appropriate methods. The metal seed layer is copper or other metal materials. The metal seed layer is to ensure the bonding force between the subsequent electroplated metal and the encapsulation material, and at the same time provide a surface for the electroplating to attach conductive ions to ensure the electroplating effect. The entire steps in the electroplating process and the materials used are also technical common sense in the field. The metals electroplated in all the electroplating processes of the present invention are all made of metallic copper.

[0035] The present invention electroplates and extends the redistribution layer 3 on the conductive ball at the output end of the chip 2 near the edge of the chip 2, avoiding the central metal area of ​​the chip 2, and effectively reducing the parasitic capacitance caused by the electric field and mutual inductance between the redistribution layer 3 and the central metal of the chip 2; the diameter of the conductive column 4 is the same as the diameter of the redistribution layer 3, ensuring the smooth transmission of the current, reducing the generation of the potential difference between the two, and further reducing the parasitic capacitance. The final product meets the requirements of ultra-low capacitance, and the capacitance value is ≤0.2PF; the total thickness of the final package 1 is ≤0.25mm, which is suitable for the packaging of ultra-thin products and also suitable for the CSP packaging process; the welding foot 5 is encapsulated in the encapsulation material, and when the package 1 is welded to the working area through the welding foot 5, the thrust after welding and the surface bonding force are improved, so that the welding structure is more stable.

[0036] It is to be understood that the present invention is described by some embodiments, and it is known to those skilled in the art that various changes or equivalent substitutions may be made to these features and embodiments without departing from the spirit and scope of the present invention. In addition, under the teachings of the present invention, these features and embodiments may be modified to adapt to specific circumstances and materials without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited by the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of the present invention are within the scope of protection of the present invention.

Claims

1. A diode packaging structure, comprising a packaging body, characterized in that: The package body contains the following components from bottom to top: Chip: The output end of the chip is electrically connected to a conductive ball through a ball planting process; Rewiring layer: The rewiring layer is electrically connected to the conductive ball, and the rewiring layer is electroplated and arranged above the chip near the edge of the chip, and the rewiring layer avoids the central metal area of ​​the chip; Conductive column: the conductive column is vertically electrically connected to one end of the redistribution layer, and the diameter of the conductive column is the same as the diameter of the redistribution layer; Solder foot: The solder foot is electrically connected to one end of the conductive column away from the redistribution layer, and the other end of the solder foot is flush with a surface of the package body and exposed.

2. The diode packaging structure according to claim 1, characterized in that: The conductive column is a copper column directly formed by electroplating at one end of the redistribution layer or a via column is formed in the drilled hole after drilling a hole in the encapsulation material to expose the redistribution layer, and the diameter of the conductive column is ≤80 μm.

3. The diode packaging structure according to claim 1, characterized in that: The conductive balls, the redistribution layer, the conductive pillars and the soldering feet are stacked in sequence by electroplating above the chip output end.

4. The diode packaging structure according to claim 3, characterized in that: The total height of the conductive balls, the redistribution layer and the conductive pillars is ≥100 μm.

5. The diode packaging structure according to claim 1, characterized in that: The total thickness of the package body is ≤0.25 mm.

6. The diode packaging structure according to claim 1, characterized in that: The solder pins are exposed on the surface of the package body and are electroplated with tin or gold.

7. A diode packaging process, characterized in that: The following steps are involved: Chip encapsulation: After the conductive ball is electrically connected to the chip output end through the ball planting process, the chip and the conductive ball are completely encapsulated with an encapsulation material. After the encapsulation material is cured, the top of the conductive ball is exposed by mechanical grinding at the level of the encapsulation surface; Rewiring layer plating: a rewiring layer electrically connected to the conductive ball is plated on the package surface where the top of the conductive ball is exposed. The rewiring layer plating is set above the chip near the edge of the chip, and the rewiring layer avoids the central metal area of ​​the chip. Conductive column setting: an electrically connected conductive column is set at one end of the redistribution layer, the diameter of the conductive column is the same as the diameter of the redistribution layer, and the redistribution layer and the conductive column are completely encapsulated with an encapsulating material. After the encapsulating material is cured, mechanical grinding is performed at the level of the encapsulation surface to expose the top surface of the conductive column; Solder foot electroplating: Electroplating the solder feet electrically connected to the conductive pillars on the package surface that exposes the top surface of the conductive pillars, continue to encapsulate the solder feet and grind to expose the top surface of the solder feet to form the final package product unit.

8. The diode packaging process according to claim 7, characterized in that: In the conductive column electroplating step, the conductive column is a copper column directly electroplated at one end of the redistribution layer or after encapsulating the redistribution layer, a hole is drilled on the encapsulation material to expose the redistribution layer and a via column is formed in the drilled hole, and the diameter of the conductive column is ≤80μm.

9. The diode packaging process according to claim 7, characterized in that: In the solder foot electroplating step, the conductive ball, the redistribution layer, the conductive column and the solder foot are electroplated and stacked in sequence above the chip output end.

10. The diode packaging process according to claim 9, characterized in that: In the conductive column electroplating step, the total height of the conductive ball, the redistribution layer and the conductive column is ≥100μ.

11. The diode packaging process according to claim 7, characterized in that: In the solder foot electroplating step, the total thickness of the package finally formed is ≤0.25 mm.

12. The diode packaging process according to claim 7, characterized in that: In the solder foot electroplating step, the solder foot is exposed on the surface of the package body and electroplated with tin or gold protrusions.

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