Power module and method of assembling power module

Abstract

The invention relates to a power module and a method of assembling a power module. The power module includes a substrate, a plurality of semiconductor dies coupled to the substrate, and a clip substrate member having a first surface and a second surface. The first surface is coupled to the plurality of semiconductor dies. The clip substrate member includes a first conductive clip and a second conductive clip and a dielectric material portion disposed between the first conductive clip and the second conductive clip. The second surface includes a first contact region and a second contact region. The first contact region includes a portion of the first conductive clip. The second contact region includes a portion of a second conductive clip.

Description

Technical Field

[0001] The present application relates to a power module and a method of assembling a power module. Background Art

[0002] Multiple clips may be used in power modules to connect power components and / or transfer heat away from power components. However, conventional clip structures may increase module size and / or cause alignment issues during the manufacturing process, resulting in longer processing times. Summary of the invention

[0003] In some aspects, the technology described herein relates to a power module comprising: a substrate; a plurality of semiconductor die coupled to the substrate; and a clip substrate member having a first surface and a second surface, the first surface being coupled to the plurality of semiconductor die, the clip substrate member comprising a first conductive clip and a second conductive clip and a dielectric material portion disposed between the first conductive clip and the second conductive clip, the second surface comprising a first contact area and a second contact area, the first contact area comprising a portion of the first conductive clip, and the second contact area comprising a portion of the second conductive clip.

[0004] In some aspects, the technology described herein relates to a power module comprising: a substrate comprising a first conductive layer, a second conductive layer, and a dielectric layer disposed between the first conductive layer and the second conductive layer; a plurality of semiconductor die coupled to the first conductive layer of the substrate; and a clip substrate member comprising a first conductive clip coupled to the plurality of semiconductor die, a second conductive clip coupled to the plurality of semiconductor die, and a dielectric material having a portion disposed between the first conductive clip and the second conductive clip, the clip substrate member comprising a source contact area comprising a first portion of a surface of the clip substrate member, the source contact area comprising a portion of the first conductive clip.

[0005] In some aspects, the technology described herein relates to a method of assembling a power module, the method comprising: assembling a clip substrate assembly, the clip substrate assembly comprising a first conductive clip, a second conductive clip, and a dielectric material, the dielectric material having a portion disposed between the first conductive clip and the second conductive clip, the clip substrate assembly comprising a first surface and a second surface; coupling a plurality of semiconductor die to a conductive layer of a substrate; and coupling the clip substrate assembly to the plurality of semiconductor die such that the plurality of semiconductor die are coupled to the first conductive clip and the second conductive clip.

[0006] The details of one or more implementations are set forth in the accompanying drawings and the description that follows. Other features will be apparent from the description and drawings, and from the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1A A side view of a power module having a clip substrate member according to one aspect is shown.

[0008] Figure 1B A side view of a clip substrate member according to one aspect is shown.

[0009] Figure 1C A top view of a power module according to one aspect is shown.

[0010] FIG. 2A to FIG. 2D A manufacturing process for assembling a clip substrate component according to one aspect is shown.

[0011] Figure 3A A side view of a power module having a clip substrate member according to one aspect is shown.

[0012] Figure 3B A side view of a power module having a clip substrate member according to another aspect is shown.

[0013] Figure 4 An example of a power module having a clip substrate member according to another aspect is shown.

[0014] Figure 5 A flow chart depicting example operations for assembling a power module having a clip substrate assembly is shown, according to one aspect. DETAILED DESCRIPTION

[0015] The present disclosure relates to a power module including a substrate, a plurality of semiconductor chips, and a clip substrate member coupled to the plurality of semiconductor chips. The power module may include a single clip substrate member coupled to a plurality of semiconductor dies (e.g., two, three, or more than three semiconductor dies). The structure of the clip substrate member may reduce alignment issues (resulting in shorter production projects), reduce the size of the power module, and / or improve the thermal performance and mechanical reliability of the power module.

[0016] The clip substrate member includes a multi-material substrate having a conductive material and a dielectric material. In some examples, the clip substrate member includes a pre-molded printed circuit board having a conductive material and a dielectric material. The clip substrate member can electrically connect the plurality of semiconductor dies together (e.g., connect their source terminals and gate terminals together). In some examples, drain terminals of the semiconductor dies are connected to the substrate.

[0017] The clip substrate member includes a first conductive clip, a second conductive clip, and a dielectric material, the dielectric material having a portion disposed between the first conductive clip and the second conductive clip to electrically isolate the second conductive clip from the first conductive clip. A surface (e.g., a top surface) of the clip substrate member may define a contact surface (e.g., a source) for connecting to an external device. The contact surface is defined by the first conductive clip and the second conductive clip. In some examples, the contact surface may include a source contact area and a gate contact area. In some examples, the source contact area defined on the surface of the clip substrate member may include a relatively large area, which may improve the thermal performance and mechanical reliability of the power module. In some examples, the relatively large source contact area may improve the drain-source on-resistance (RDS(on)) performance and / or the junction-to-case thermal resistance (RthJF) performance.

[0018] Figures 1A to 1C A power module 100 is shown according to one aspect. The power module 100 includes a substrate 102, a plurality of semiconductor dies 104 coupled to the substrate 102, and a clip substrate member 106 coupled to the semiconductor dies 104. The clip substrate member 106 can be a multi-material substrate having a conductive material 110 and a dielectric material 112. In some examples, the power module 100 includes a single clip substrate member 106 coupled to three or more semiconductor dies 104. Figure 1A A side view of the power module 100 is shown. Figure 1B An enlarged side view of the clip substrate member 106 is shown. Figure 1C A top view of the power module 100 is shown.

[0019] Substrate 102 includes a dielectric layer 120. Dielectric layer 120 includes an insulating material. In some examples, dielectric layer 120 includes a ceramic material. In some examples, substrate 102 includes a single dielectric layer 120. In some examples, substrate 102 includes a plurality of dielectric layers 120. In some examples, substrate 102 includes a printed circuit board (PCB) substrate (e.g., a single-layer PCB or a multi-layer PCB). In some examples, substrate 102 includes a conductive layer 122 coupled to one surface of dielectric layer 120 and a conductive layer 124 coupled to another surface of dielectric layer 120. In some examples, conductive layer 122 includes a copper layer. In some examples, conductive layer 124 includes a copper layer. In some examples, substrate 102 is a direct bond metal (DBM) substrate (e.g., a substrate having a dielectric disposed between two metal layers), such as a direct bond copper (DBC) substrate.

[0020] Substrate 102 includes first surface 121 and second surface 123. In some examples, first surface 121 is a surface (e.g., a top surface) of conductive layer 122. In some examples, second surface 123 is another surface (e.g., a bottom surface) of conductive layer 124. Second surface 123 may be disposed parallel to first surface 121. A distance between first surface 121 and second surface 123 may define a thickness of substrate 102 in direction A1. First surface 121 is aligned in plane A4. Direction A1 is aligned perpendicular to plane A4, and direction A2 is perpendicular to direction A1. Direction A3 (into the page) Figure 1A and Figure 1B A4 is aligned parallel to the plane A4 and is orthogonal to the directions A1 and A2. For simplicity, the directions A1, A2 and A3 and the plane A4 are used in several of the various views of the embodiments described throughout the drawings.

[0021] Semiconductor die 104 may include semiconductor die 104 - 1 , semiconductor die 104 - 2 , and semiconductor die 104 - 3 . Figures 1A to 1C , but the number of semiconductor dies 104 can be two or any number greater than three, such as four, five, six, seven, eight, etc. In some examples, power module 100 includes three or more semiconductor dies 104. Semiconductor die 104 is a power semiconductor die. Semiconductor die 104 includes a transistor. In some examples, semiconductor die 104 includes a metal oxide semiconductor field effect transistor (MOSFET). In some examples, semiconductor die 104 includes an insulated gate bipolar transistor (IGBT). In some examples, semiconductor die 104 includes a semiconductor thyristor. In some examples, semiconductor die 104 of multiple instances of the same type of transistor.

[0022] Each semiconductor die 104 includes a first surface 111 (e.g., a top surface) and a second surface 113 (e.g., a bottom surface). The first surface 111 and the second surface 113 may be aligned in a plane parallel to the plane A4. The distance between the first surface 111 and the second surface 113 defines the thickness of the semiconductor die 104 in the direction A1. Each semiconductor die 104 includes a source terminal 101, a gate terminal 103, and a drain terminal 105. The source terminal 101, the gate terminal 103, and the drain terminal 105 may be metallization regions in the semiconductor die 104. In some examples, for an IGT transistor, the source terminal 101 is referred to as a collector terminal. In some examples, for an IGT transistor, the drain terminal 105 is referred to as a collector terminal.

[0023] Semiconductor die 104 is coupled to substrate 102. Semiconductor die 104 is coupled to first surface 121 of substrate 102. For example, semiconductor die 104 is coupled to conductive layer 122 of substrate 102 (e.g., second surface 113 of semiconductor die 104 may be coupled to conductive layer 122). Semiconductor die 104 may be coupled to conductive layer 122 using adhesive material 118. Adhesive material 118 may be a die adhesive. Adhesive material 118 may include epoxy, silicone, and / or polyimide. Figure 1A As shown, semiconductor die 104-1 is connected to conductive layer 122 using adhesive material 118, semiconductor die 104-2 is connected to conductive layer 122 using adhesive material 118, and semiconductor die 104-3 is connected to conductive layer 122 using adhesive material 118. In some examples, drain terminal 105 of each semiconductor die 104 is connected to substrate 102 (e.g., conductive layer 122) via adhesive material 118. For example, semiconductor die 104-1, semiconductor die 104-2, and semiconductor die 104-3 are connected to substrate 102 (e.g., conductive layer 122 of substrate 102).

[0024] The clip substrate member 106 is coupled to each of the semiconductor dies 104. In some examples, the clip substrate member 106 is coupled to the semiconductor dies 104 via die pads 116. The die pads 116 can be any type of conductive and / or dielectric material, including metal, ceramic, and / or silicon. The die pads 116 can provide a physical and / or electrical connection between the semiconductor dies 104 and the clip substrate member 106. In some examples, the clip substrate member 106 is coupled to the first surface 111 of each semiconductor die 104 via one or more die pads 116. In some examples, a particular semiconductor die 104 is coupled to the clip substrate member 106 via two die pads 116 (e.g., one die pad 116 for a source connection and another die pad 116 for a gate connection). The clip substrate member 106 includes a first surface 115 (e.g., a top surface) and a second surface 117 (e.g., a bottom surface). The distance between first surface 115 and second surface 117 defines the thickness of clip substrate member 106. In some examples, clip substrate member 106 has a rectangular shape (eg, a 3D rectangular shape) having a width and length defined along directions A2 and A3 and a thickness defined along direction A1.

[0025] The clip substrate member 106 may be a multi-material substrate having a conductive material 110 and a dielectric material 112. For example, the conductive material 110 may define a conductive clip 110-1 and a conductive clip 110-2. The conductive clip 110-1 and the conductive clip 110-2 may be conductive portions (e.g., metal portions) extending within and through the clip substrate member 106. The conductive clip 110-1 and the conductive clip 110-2 may include portions connected to each semiconductor die 104. The dielectric material 112 includes one or more portions 182 disposed between the conductive clip 110-1 and the conductive clip 110-2. For example, the portions 182 of the dielectric material 112 may separate the conductive clip 110-1 from the conductive clip 110-2 so as to electrically isolate the conductive clip 110-1 from the conductive clip 110-2 from each other (e.g., to electrically isolate the source and drain connections). The dielectric material 112 may define an outer perimeter 181 of the clip substrate member 106. For example, the dielectric material 112 may include a perimeter portion 180 that extends around and defines a side of the clip substrate member 106 (e.g., the side of the clip substrate member 106 is a surface extending in the direction A1 between the first surface 115 and the second surface 117).

[0026] The conductive clip 110-1 is connected to each of the semiconductor dies 104. The conductive clip 110-1 is connected to the source terminal 101 (or emitter terminal) of each of the plurality of semiconductor dies 104. For example, the conductive clip 110-1 includes a surface area 154-1 exposed through the second surface 117 of the clip substrate member 106, and the surface area 154-1 is connected to the semiconductor die 104-1 (e.g., the source terminal 101 of the semiconductor die 104-1). In other words, a portion of the second surface 117 is (or is defined by) the surface area 154-1, which is connected to the source terminal 101 of the semiconductor die 104-1 via the die pad 116.

[0027] The conductive clip 110-1 includes a surface area 154-2 exposed through the second surface 117 of the clip substrate member 106, and the surface area 154-2 is connected to the semiconductor die 104-2 (e.g., the source terminal 101 of the semiconductor die 104-2). In other words, another portion of the second surface 117 is (or is defined by) the surface area 154-2, which is connected to the source terminal 101 of the semiconductor die 104-2 via the die pad 116. The conductive clip 110-1 includes a surface area 154-3 exposed through the second surface 117 of the clip substrate member 106, and the surface area 154-3 is connected to the semiconductor die 104-3 (e.g., the source terminal 101 of the semiconductor die 104-3). In other words, another portion of the second surface 117 is (or is defined by) the surface area 154-3, which is connected to the source terminal 101 of the semiconductor die 104-3 via the die pad 116.

[0028] The conductive clip 110-1 defines a source contact area 152 on the first surface 115 of the clip substrate member 106. The source contact area 152 can be a contact area (e.g., a surface area, a contact pad, etc.) on the first surface 115 that is used to connect to an external component or device. In some examples, the source contact area 152 defined on the first surface 115 of the clip substrate member 106 can include a relatively large area, which can improve the thermal performance and mechanical reliability of the power module 100. In some examples, the source contact area 152 can improve the drain-source on-resistance (RDS(on)) performance and / or the junction-to-case thermal resistance (RthJF) performance. In some examples, the source contact area 152 is larger than the gate contact area 156 (which is also defined on the first surface 115).

[0029] like Figure 1B As shown, the conductive clip 110-1 includes a portion 126 extending along the direction A1 between the surface region 154-1 and the source contact region 152. In some examples, the portion 126 extends completely through the thickness of the clip substrate member 106 along the direction A1. The conductive clip 110-1 includes a portion 128 extending along the direction A1 between the surface region 154-2 and the source contact region 152. In some examples, the portion 128 extends completely through the thickness of the clip substrate member 106 along the direction A1. The conductive clip 110-1 includes a portion 130 extending along the direction A1 between the surface region 154-3 and the source contact region 152. In some examples, the portion 130 extends completely through the thickness of the clip substrate member 106 along the direction A1.

[0030] Conductive clip 110-1 includes portion 132 extending between portion 126 and portion 128 along direction A2. In some examples, portion 132 connects source terminal 101 of semiconductor die 104-1 with source terminal 101 of semiconductor die 104-2. In some examples, portion 132 extends in direction A2 along first surface 115 of clip substrate member 106. Conductive clip 110-1 includes portion 134 extending between portion 128 and portion 130 along direction A2. In some examples, portion 134 connects source terminal 101 of semiconductor die 104-3 with source terminal 101 of semiconductor die 104-1 and source terminal 101 of semiconductor die 104-2. In some examples, portion 134 extends in direction A2 along first surface 115 of clip substrate member 106.

[0031] The second conductive clip 110-2 is connected to each of the semiconductor dies 104. The second conductive clip 110-2 is connected to the gate terminal 103 of each of the semiconductor dies 104. For example, the conductive clip 110-2 includes a surface area 158-1 exposed through the second surface 117 of the clip substrate member 106, and the surface area 158-1 is connected to the semiconductor die 104-1 (e.g., the gate terminal 103 of the semiconductor die 104-1). In other words, a portion of the second surface 117 is (or is defined by) the surface area 158-1, which is connected to the gate terminal 103 of the semiconductor die 104-1 via the die pad 116. The conductive clip 110-2 includes a surface area 158-2 exposed through the second surface 117 of the clip substrate member 106, and the surface area 158-2 is connected to the semiconductor die 104-2 (e.g., the gate terminal 103 of the semiconductor die 104-2). In other words, another portion of the second surface 117 is (or is defined by) the surface region 158 - 2 , which is connected to the gate terminal 103 of the semiconductor die 104 - 2 via the die pad 116 .

[0032] The conductive clip 110-2 includes a surface area 158-3 exposed through the second surface 117 of the clip substrate member 106, and the surface area 158-3 is connected to the semiconductor die 104-3 (e.g., the gate terminal 103 of the semiconductor die 104-3). In other words, another portion of the second surface 117 is (or is defined by) the surface area 158-3, which is connected to the gate terminal 103 of the semiconductor die 104-3 via the die pad 116.

[0033] The conductive clip 110-2 defines a gate contact region 156 on the first surface 115 of the clip substrate member 106. The gate contact region 156 may be a contact region on the first surface 115 for connecting to an external component. In some examples, the size (e.g., surface area) of the gate contact region 156 on the first surface 115 of the clip substrate member 106 (e.g., in directions A2 and A3) is smaller than the size (e.g., surface area) of the source contact region 152 (e.g., in directions A2 and A3). In other words, the size (e.g., surface area) of the source contact region 152 on the first surface 115 of the clip substrate member 106 is greater than the size (e.g., surface area) of the gate contact region 156 on the first surface 115. In some examples, the size (e.g., surface area) of the source contact region 152 on the first surface 115 of the clip substrate member 106 is greater than twice the size (e.g., surface area) of the gate contact region 156 on the first surface 115. In some examples, a size (e.g., surface area) of source contact region 152 on first surface 115 is greater than three times a size (e.g., surface area) of gate contact region 156 on first surface 115. In some examples, a size (e.g., surface area) of source contact region 152 on first surface 115 is greater than three times a size (e.g., surface area) of gate contact region 156 on first surface 115.

[0034] The conductive clip 110-2 includes a portion 136 extending from the surface area 158-1 into the clip substrate member 106 along the direction A1. In some examples, the portion 136 extends toward the central axis 119 of the clip substrate member 106. In some examples, the central axis 119 extends along the direction A2 and divides (e.g., equally) the clip substrate member 106 into two halves (e.g., an upper half and a lower half along the direction A1). In some examples, the portion 136 extends to the central axis 119 (e.g., contacts or interacts with the central axis 119). In some examples, the portion 136 extends only partially through the clip substrate member 106 in the direction A1. In some examples, the portion 136 does not extend into the upper half of the clip substrate member 106. The conductive clip 110-2 includes a portion 138 extending from the surface area 158-2 into the clip substrate member 106 along the direction A1. In some examples, the portion 138 extends toward the central axis 119 in the direction A1. In some examples, portion 138 extends to (e.g., contacts or interacts with) central axis 119. In some examples, portion 138 extends only partially through clip substrate member 106 in direction A1. In some examples, portion 138 does not extend into the upper half of clip substrate member 106.

[0035] Conductive clip 110-2 includes portion 140 extending along direction A1 between surface region 158-3 and gate contact region 156. In some examples, portion 140 extends completely through the thickness of clip substrate member 106 along direction A3. Conductive clip 110-2 includes portion 142 extending along direction A2 between portion 136 and portion 138. In some examples, portion 142 connects gate terminal 103 of semiconductor die 104-1 with gate terminal 103 of semiconductor die 104-2. Conductive clip 110-2 includes portion 144 extending along direction A2 between portion 138 and portion 140. In some examples, portion 144 connects gate terminal 103 of semiconductor die 104-3 with gate terminal 103 of semiconductor die 104-2 and gate terminal 103 of semiconductor die 104-1.

[0036] FIG. 2A to FIG. 2D FIG. 2 shows a manufacturing process for forming a clip substrate member 206 according to one aspect. The clip substrate member 206 may be Figures 1A to 1C 106 and may include any of the details discussed with reference to those figures. Figure 2A Operation 201 includes providing a cavity structure 270. The cavity structure 270 may be a portion of an injection mold for forming a shape of a molded part. In some examples, the cavity structure 270 may define a cavity structure for loading conductive clips (e.g., conductive clips 210-1 and conductive clips 210-2) and injection molding (e.g., dielectric material 212). Figure 2B Operation 203 includes loading (eg, inserting, placing, etc.) the conductive clip 210 - 1 and the conductive clip 210 - 2 into the mold cavity structure 270 . Figure 2C Operation 205 includes arranging (eg, placing, coupling) a mold tool component 272 on the mold cavity structure 270. In some examples, the mold tool component 272 is referred to as a core. The mold tool component 272 can be aligned with the mold cavity structure 270 using guide pins and / or bushings.

[0037] Reference Figure 2D , operation 207 includes injecting dielectric material 212 into cavity structure 270. Operation 207 may also include curing dielectric material 212, such as a process of hardening or toughening the material, which may include applying heat to dielectric material 212 for a period of time. In some examples, operation 207 includes cutting (e.g., side cutting) cavity structure 270. In some examples, operation 207 includes grinding the top surface and / or the bottom surface to expose metal portions of conductive clip 210-1 and conductive clip 210-2.

[0038] FIG. 3A to FIG. 3BA power module 300 having a clip substrate member 306 is shown according to one aspect. The power module 300 includes a substrate 302, a plurality of semiconductor dies 304 coupled to the substrate 302, and a clip substrate member 306 coupled to the semiconductor dies 304. The power module 300 and the clip substrate member 306 may be Figures 1A to 1C The power module 100 and the clip substrate member 106 and / or FIG. 2A to FIG. 2D 3. In some examples, substrate 302 includes a recess 348 for holding semiconductor die 304.

[0039] Power module 300 includes substrate 302 having a recess 348 for each semiconductor die 304. In some examples, recess 348 is a depression (or cutout portion) in substrate 302. In some examples, recess 348 is a cavity or well extending from first surface 321 along direction A1 into substrate 302. Semiconductor die 304 includes semiconductor die 304-1, semiconductor die 304-2, and semiconductor die 304-3. Substrate 302 includes conductive layer 322, conductive layer 324, and dielectric layer 320 disposed between conductive layer 322 and conductive layer 324.

[0040] Substrate 302 includes first surface 321 and second surface 323. In some examples, first surface 321 is a surface of conductive layer 322 (e.g., a top surface). In some examples, second surface 323 is another surface of conductive layer 324 (e.g., a bottom surface). Second surface 323 may be disposed parallel to first surface 321. The distance between first surface 321 and second surface 323 may define a thickness of substrate 302 in direction A1. First surface 321 is aligned in plane A4. Direction A1 is aligned perpendicular to plane A4, and direction A2 is perpendicular to direction A1. Direction A3 (into the page) Figure 3A ) is aligned parallel to plane A4 and orthogonal to directions A1 and A2.

[0041] Conductive layer 322 includes a plurality of recesses 348. A particular semiconductor die 304 is inserted into a separate recess 348. Semiconductor die 304-1 is disposed within recess 348 and coupled to conductive layer 322 using adhesive material 318. Semiconductor die 304-2 is disposed within a separate recess 348 and coupled to conductive layer 322 using adhesive material 318. Semiconductor die 304-3 is disposed within another recess 348 and coupled to conductive layer 322 using adhesive material 318. In some examples, a surface 311 (e.g., a top surface) of semiconductor die 304 is aligned with a first surface 321 (e.g., a top surface) of substrate 302 in direction A1. In some examples, surface 311 is located below first surface 321 in direction A1. Power module 300 includes a plurality of die pads 316 coupled to semiconductor die 304. For example, die pad 316 - 1 and die pad 316 - 2 are coupled to semiconductor die 304 - 1 . Die pad 316 - 3 and die pad 316 - 4 are coupled to semiconductor die 304 - 2 . Die pad 316 - 5 and die pad 316 - 6 are coupled to semiconductor die 304 - 3 . Die pad 316 is used to connect to clip substrate member 306 .

[0042] like Figure 3B As shown, clip substrate member 306 is coupled to semiconductor die 304. For example, clip substrate member 306 is coupled to semiconductor die 304-1, semiconductor die 304-2, and semiconductor die 304-3. Clip substrate member 306 may be Figures 1A to 1C The clip substrate member 106 and / or FIG. 2A to FIG. 2D 316-6. Moreover, the clip substrate member 306 includes a source contact area 352 defined by the conductive clip 310-1 and a gate contact area 356 defined by the conductive clip 310-2.

[0043] Figure 4 A power module 400 is shown having a clip substrate member 406. The power module 400 may be Figures 1A to 1C The power module 100 and / or Figure 3A and Figure 3BThe power module 400 includes a substrate 402, a plurality of semiconductor dies 404 coupled to the substrate 402, and a clip substrate member 406 coupled to the semiconductor dies 404. Figure 4 As shown, the power module 400 includes a substrate 466 coupled to the clip substrate member 406 .

[0044] Clip substrate member 406 includes a conductive material 410 and a dielectric material 412. Conductive material 410 includes a conductive clip 410-1 and a conductive clip 410-2. Dielectric material 412 includes a portion disposed between conductive clip 410-1 and conductive clip 410-2. Clip substrate member 406 includes a first surface 415 (e.g., a top surface) and a second surface 417 (e.g., a bottom surface). Power module 400 includes a substrate 466 coupled to clip substrate member 406. In some examples, substrate 466 includes a dielectric substrate. In some examples, substrate 466 includes a substrate similar to or the same as substrate 402. In some examples, substrate 466 includes a DBC substrate.

[0045] Item 1. A power module, comprising: a substrate; a plurality of semiconductor dies coupled to the substrate; and a clip substrate component having a first surface and a second surface, the first surface being coupled to the plurality of semiconductor dies, the clip substrate component comprising a first conductive clip and a second conductive clip and a dielectric material portion disposed between the first conductive clip and the second conductive clip, the second surface comprising a first contact area and a second contact area, the first contact area comprising a portion of the first conductive clip, and the second contact area comprising a portion of the second conductive clip.

[0046] Clause 2. The power module of Clause 1, wherein the first conductive clip is connected to a source terminal of each of the plurality of semiconductor dies.

[0047] Clause 3. The power module of Clause 1 or 2, wherein the second conductive clip is connected to a gate terminal of each of the plurality of semiconductor dies.

[0048] Clause 4. The power module of any of Clauses 1 to 3, wherein each of the plurality of semiconductor dies comprises a drain terminal connected to the substrate.

[0049] Clause 5. The power module of any one of Clauses 1 to 4, wherein the substrate comprises a first conductive layer, a second conductive layer, and a dielectric layer disposed between the first conductive layer and the second conductive layer.

[0050] Clause 6. The power module of any one of clauses 1 to 5, wherein a size of the first contact region is greater than a size of the second contact region.

[0051] Clause 7. The power module of any one of clauses 1 to 6, wherein the first contact region is a source contact for an external device and the second contact region is a gate contact for the external device.

[0052] Clause 8. The power module of any of Clauses 1 to 7, wherein the plurality of semiconductor dies comprises a first semiconductor die, a second semiconductor die, and a third semiconductor die.

[0053] Clause 9. The power module of any of Clauses 1 to 8, wherein the clip substrate member is connected to each of the plurality of semiconductor dies via a die pad.

[0054] Clause 10. The power module of any of Clauses 1 to 9, wherein the clip substrate member includes a plurality of recesses, and each of the plurality of semiconductor dies is included in a separate recess of the plurality of recesses.

[0055] Clause 11. The power module of any one of clauses 1 to 10, wherein the substrate is a first substrate, the power module further comprising: a second substrate coupled to the clip substrate member.

[0056] Item 12. A power module, comprising: a substrate including a first conductive layer, a second conductive layer, and a dielectric layer disposed between the first conductive layer and the second conductive layer; a plurality of semiconductor die coupled to the first conductive layer of the substrate; and a clip substrate component, the clip substrate component comprising a first conductive clip coupled to the plurality of semiconductor die, a second conductive clip coupled to the plurality of semiconductor die, and a dielectric material having a portion disposed between the first conductive clip and the second conductive clip, the clip substrate component comprising a source contact area, the source contact area comprising a first portion of a surface of the clip substrate component, the source contact area comprising a portion of the first conductive clip.

[0057] Clause 13. The power module of Clause 12, wherein the clip substrate member includes a gate contact region, the gate contact region includes a second portion of the surface of the clip substrate member, the gate contact region includes a portion of the second conductive clip.

[0058] Item 14. The power module of Item 13, wherein a size of the source contact region is larger than a size of the gate contact region.

[0059] Clause 15. The power module of any of Clauses 12 to 14, wherein the first conductive clip is connected to a source terminal of each of the plurality of semiconductor dies and the second conductive clip is connected to a gate terminal of each of the plurality of semiconductor dies.

[0060] Clause 16. A power module according to any one of clauses 12 to 15, wherein the plurality of semiconductor dies include a first semiconductor die, a second semiconductor die, and a third semiconductor die, and the clip substrate assembly includes a first recess having the first semiconductor die, a second recess having the second semiconductor die, and a third recess having the third semiconductor die.

[0061] Item 17. A method for assembling a power module, the method comprising: assembling a clip substrate assembly, the clip substrate assembly comprising a first conductive clip, a second conductive clip and a dielectric material, the dielectric material having a portion disposed between the first conductive clip and the second conductive clip, the clip substrate assembly comprising a first surface and a second surface; coupling a plurality of semiconductor die to a conductive layer of a substrate; and coupling the clip substrate assembly to the plurality of semiconductor die such that the plurality of semiconductor die are coupled to the first conductive clip and the second conductive clip.

[0062] Item 18. A method according to Item 17, wherein the clip substrate member includes a source contact area and a gate contact area, the source contact area includes a first portion of the surface of the clip substrate member, the gate contact area includes a second portion of the surface of the clip substrate member, the source contact area includes a portion of the first conductive clip, and the gate contact area includes a portion of the second conductive clip.

[0063] Clause 19. The method of clause 17 or 18, further comprising: forming a plurality of recesses in the substrate; disposing the plurality of semiconductor dies in the plurality of recesses; and coupling the plurality of semiconductor dies to the substrate using a die attach material.

[0064] Clause 20. The method of any one of clauses 17 to 19, wherein assembling the clip substrate member comprises: arranging the first conductive clip and the second conductive clip in a mold cavity structure; and injecting the dielectric material into the mold cavity structure.

[0065] It should be understood that in the foregoing description, when an element is referred to as being connected to another element, electrically connected to another element, coupled to another element or electrically coupled to another element, the element may be directly connected or coupled to another element, or one or more intermediate elements may be present. On the contrary, when an element is referred to as being directly connected to another element or being directly coupled to another element, there is no intermediate element. Although the term directly connected to or directly coupled to may not be used throughout the detailed description, the element shown as being directly connected or directly coupled may be mentioned in this manner. The claims of the present application (if any) may be revised to narrate the example relationship described in the specification or shown in the accompanying drawings. The embodiments of various technologies described herein may be implemented (for example, included therein) in digital electronic circuits, computer hardware, firmware, software or in a combination thereof. The part of the method may also be performed by a dedicated logic circuit such as FPGA (field programmable gate array) or ASIC (application specific integrated circuit), and the device may be implemented as the dedicated logic circuit.

[0066] Figure 5 A flowchart 500 depicting exemplary operations of a method of assembling a power module is depicted. Although reference is made to Figures 1A to 1C Flowchart 500 is described with reference to power module 100 of FIG. 1 , but the flow chart is applicable to any power module discussed herein. Figure 5 The flowchart 500 shows the operations in a sequential order, but it should be understood that this is merely exemplary and may include additional or alternative operations. Figure 5 The operations and related operations may be performed in a different order than shown, or in a parallel or overlapping manner.

[0067] Operation 502 includes assembling a clip substrate member 106 including a first conductive clip (e.g., conductive clip 110-1), a second conductive clip (e.g., conductive clip 110-2), and a dielectric material 112 having a portion 182 disposed between the first conductive clip and the second conductive clip. Operation 504 includes coupling a plurality of semiconductor dies 104 to a conductive layer 122 of a substrate 102. Operation 506 includes coupling the clip substrate member 106 to the plurality of semiconductor dies 104 such that the plurality of semiconductor dies 104 are coupled to the first conductive clip and the second conductive clip.

[0068] Some implementations may be implemented using various semiconductor processing and / or packaging technologies. Some implementations may be implemented using various types of semiconductor processing technologies associated with semiconductor substrates, including but not limited to, for example, silicon (Si), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), etc.

[0069] Although certain features of the specific implementations described have been described as described herein, those skilled in the art will now expect many modifications, alternatives, variations, and equivalents. Therefore, it should be understood that the appended claims are intended to cover all such modifications and variations that fall within the scope of the embodiments. It should be understood that these modifications and variations are presented only by way of example and not limitation, and various changes in form and detail may be made. In addition to mutually exclusive combinations, any part of the apparatus and / or method described herein may be combined in any combination. The embodiments described herein may include various combinations and / or sub-combinations of the functions, components, and / or features of the different embodiments described.

Claims

1. A power module, comprising: substrate; a plurality of semiconductor dies coupled to the substrate; and a clip substrate member having a first surface and a second surface, the first surface being coupled to the plurality of semiconductor dies, the clip substrate member including a first conductive clip and a second conductive clip and a dielectric material portion disposed between the first conductive clip and the second conductive clip, The second surface includes a first contact area and a second contact area, the first contact area includes a portion of the first conductive clip, and the second contact area includes a portion of the second conductive clip. 2 . The power module of claim 1 , wherein the first conductive clip is connected to a source terminal of each of the plurality of semiconductor dies. 3 . The power module of claim 1 , wherein the second conductive clip is connected to a gate terminal of each of the plurality of semiconductor dies. 4 . The power module of claim 1 , wherein each of the plurality of semiconductor dies comprises a drain terminal connected to the substrate. 5 . The power module of claim 1 , wherein the substrate comprises a first conductive layer, a second conductive layer, and a dielectric layer disposed between the first conductive layer and the second conductive layer. The power module according to claim 1 , wherein a size of the first contact region is larger than a size of the second contact region. 7 . The power module of claim 1 , wherein the first contact region is a source contact for an external device, and the second contact region is a gate contact for the external device. 8 . The power module of claim 1 , wherein the plurality of semiconductor dies comprises a first semiconductor die, a second semiconductor die, and a third semiconductor die.

9. The power module of claim 1, wherein the clip substrate member is connected to each of the plurality of semiconductor dies via a die pad. 10 . The power module of claim 1 , wherein the clip substrate member includes a plurality of recesses, and each of the plurality of semiconductor dies is included in a separate recess of the plurality of recesses.

11. The power module according to claim 1, wherein the substrate is a first substrate, and the power module further comprises: A second substrate is coupled to the clip substrate member.

12. A power module, comprising: A substrate comprising a first conductive layer, a second conductive layer, and a dielectric layer disposed between the first conductive layer and the second conductive layer; a plurality of semiconductor dies coupled to the first conductive layer of the substrate; and a clip substrate member including a first conductive clip coupled to the plurality of semiconductor die, a second conductive clip coupled to the plurality of semiconductor die, and a dielectric material having a portion disposed between the first conductive clip and the second conductive clip, The clip substrate member includes a source contact region including a first portion of a surface of the clip substrate member, the source contact region including a portion of the first conductive clip.

13. The power module of claim 12, wherein the clip substrate member includes a gate contact region, the gate contact region includes a second portion of the surface of the clip substrate member, the gate contact region includes a portion of the second conductive clip. 14 . The power module of claim 13 , wherein a size of the source contact region is larger than a size of the gate contact region. 15 . The power module of claim 12 , wherein the first conductive clip is connected to a source terminal of each of the plurality of semiconductor dies and the second conductive clip is connected to a gate terminal of each of the plurality of semiconductor dies.

16. The power module of claim 12, wherein the plurality of semiconductor dies include a first semiconductor die, a second semiconductor die, and a third semiconductor die, and the clip substrate component includes a first recess having the first semiconductor die, a second recess having the second semiconductor die, and a third recess having the third semiconductor die.

17. A method for assembling a power module, the method comprising: Assembling a clip substrate member, the clip substrate member comprising a first conductive clip, a second conductive clip, and a dielectric material, the dielectric material having a portion disposed between the first conductive clip and the second conductive clip, the clip substrate member comprising a first surface and a second surface; coupling a plurality of semiconductor dies to the conductive layer of the substrate; as well as The clip substrate member is coupled to the plurality of semiconductor dies such that the plurality of semiconductor dies are coupled to the first conductive clip and the second conductive clip.

18. A method according to claim 17, wherein the clip substrate member includes a source contact area and a gate contact area, the source contact area includes a first portion of the surface of the clip substrate member, the gate contact area includes a second portion of the surface of the clip substrate member, the source contact area includes a portion of the first conductive clip, and the gate contact area includes a portion of the second conductive clip.

19. The method according to claim 17, further comprising: forming a plurality of recesses in the substrate; disposing the plurality of semiconductor dies in the plurality of recesses; as well as The plurality of semiconductor dies are coupled to the substrate using a die attach material.

20. The method of claim 17, wherein assembling the clip substrate member comprises: Arranging the first conductive clip and the second conductive clip in a mold cavity structure; as well as The dielectric material is injected into the mold cavity structure.

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