Semiconductor package

Abstract

A semiconductor package may include a first dielectric structure, a first pad in the first dielectric structure, a first semiconductor chip disposed on the first dielectric structure, and a bump electrically connected to the first pad. The first semiconductor chip includes: a first substrate; a first chip dielectric layer in contact with the first dielectric structure; and a first chip pad in contact with a top surface of the first pad. The first pad may be disposed between the bump and a first chip pad of the first semiconductor chip. The first pad may include a first conductive layer and a second conductive layer covered by the first conductive layer. The bump may be positioned closer to the first conductive layer than a distance from the second conductive layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0128344 filed in the Korean Intellectual Property Office on September 25, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a semiconductor package, and more particularly, to a semiconductor package including a semiconductor chip. Background Art

[0004] A semiconductor package is provided to implement an integrated circuit chip that is qualified for use in an electronic product. Generally, a semiconductor package is configured such that a semiconductor chip is mounted on a printed circuit board (PCB) and the semiconductor chip is electrically connected to the printed circuit board using bonding wires or bumps. With the development of the electronics industry, various studies have been conducted to improve the reliability and durability of semiconductor packages. Summary of the invention

[0005] One or more example embodiments of the present disclosure provide a semiconductor package having improved electrical characteristics and increased reliability.

[0006] According to one aspect of the present disclosure, a semiconductor package may include: a first dielectric structure; a first solder pad in the first dielectric structure; a first semiconductor chip disposed on the first dielectric structure; and a bump electrically connected to the first solder pad, wherein the first semiconductor chip includes: a first substrate; a first chip dielectric layer in contact with the first dielectric structure; and a first chip solder pad in contact with a top surface of the first solder pad, wherein the first solder pad is between the bump and the first chip solder pad of the first semiconductor chip, wherein the first solder pad includes a first conductive layer and a second conductive layer covered by the first conductive layer, and wherein the bump is positioned closer to the first conductive layer than to the second conductive layer.

[0007] According to another aspect of the present disclosure, a semiconductor package may include: a first dielectric structure; a first solder pad in the first dielectric structure; a first semiconductor chip disposed on the first dielectric structure; and a bump electrically connected to the first solder pad, wherein the first semiconductor chip includes: a first substrate; a first chip dielectric layer in contact with the first dielectric structure; and a first chip solder pad in contact with a top surface of the first solder pad, wherein the first solder pad includes a first conductive layer and a second conductive layer covered by the first conductive layer, wherein the first conductive layer includes a top surface and a bottom surface opposite to each other, wherein the top surface of the first conductive layer is in contact with the first chip solder pad of the first semiconductor chip, and wherein an area of ​​the bottom surface of the first conductive layer is greater than an area of ​​the top surface of the first conductive layer.

[0008] According to some embodiments of the present invention, a semiconductor package may include: a first dielectric structure; a first pad and a plurality of key patterns in the first dielectric structure; a first semiconductor chip in contact with the first dielectric structure; a bump electrically connected to the first pad; a second dielectric structure across the first semiconductor chip and spaced apart from the first dielectric structure; a first gap-filling layer between the first dielectric structure and the second dielectric structure; a second semiconductor chip in contact with the second dielectric structure; and a second gap-filling layer surrounding the second semiconductor chip. The first pad may include a first conductive layer and a second conductive layer in the first conductive layer. The first conductive layer may include: a first portion between the bump and the second conductive layer; and a second portion surrounding the second conductive layer. The first portion of the first conductive layer may include a surface in contact with a bottom surface of the second conductive layer. The top surface of the second portion of the first conductive layer and the top surface of the second conductive layer may be in contact with the first chip pad.

[0009] According to another aspect of the present disclosure, a method for manufacturing a semiconductor package may include: forming a first dielectric structure on a carrier substrate; forming a plurality of alignment keys and first pads in the first dielectric structure at the same manufacturing step; bonding a first semiconductor chip to the first dielectric structure; removing the carrier substrate to expose the first pads and the alignment key; and forming a bump electrically connected to the first pad. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1A A cross-sectional view illustrating a semiconductor package according to some embodiments is shown.

[0011] Figure 1B Shows Shows Figure 1A An enlarged view of part E1.

[0012] Figure 2 , Figure 3A , Figure 3B , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 and Fig. 9 Plan views and cross-sectional views illustrating a method of manufacturing a semiconductor package according to some embodiments are shown.

[0013] Fig.10 A cross-sectional view illustrating a semiconductor package according to some embodiments is shown.

[0014] Fig.11 A cross-sectional view illustrating a method of manufacturing a semiconductor package according to some embodiments is shown.

[0015] Fig.12 A cross-sectional view illustrating a semiconductor package according to some embodiments is shown.

[0016] Fig.13A and Fig. 13B Plan views and cross-sectional views illustrating a method of manufacturing a semiconductor package according to some embodiments are shown.

[0017] Fig.14 An enlarged cross-sectional view illustrating a semiconductor package according to some embodiments is shown.

[0018] Fig.15 An enlarged cross-sectional view illustrating a semiconductor package according to some embodiments is shown.

[0019] Fig.16 A plan view illustrating a plan structure of a semiconductor package according to some embodiments is shown.

[0020] Fig.17 A plan view illustrating a plan structure of a semiconductor package according to some embodiments is shown. DETAILED DESCRIPTION

[0021] Semiconductor packages and methods of manufacturing the same according to some embodiments of the inventive concept will be described in detail below with reference to the accompanying drawings.

[0022] In the present disclosure, the term "surrounding" may be used to describe covering, enclosing or surrounding all sides or a portion of an object. For example, when describing a first layer surrounded by a second layer, it can be interpreted that all sides of the first layer are covered by the second layer, or the first layer is partially covered by the second layer, wherein a portion of the first layer remains exposed.

[0023] Figure 1A A cross-sectional view illustrating a semiconductor package according to some embodiments is shown. Figure 1B Shows Shows Figure 1A An enlarged view of part E1.

[0024] refer to Figure 1A and Figure 1B , the semiconductor package may include a bump BP, a bump connection pad 11, a first dielectric structure IS1, a first pad PA1, a dummy pad DP, a key pattern KP, a first semiconductor chip SC1, a first gap filling layer GP1, a second dielectric structure IS2, a second pad PA2, a second semiconductor chip SC2, a second gap filling layer GP2, a first bonding layer BL1, a second bonding layer BL2, and a dummy substrate DS. The key pattern KP may refer to a specific geometric pattern or graphic pattern on the semiconductor package that acts as a reference feature or an alignment feature. The key pattern KP may also be referred to as an alignment mark or an alignment key. The term "pad" may also be referred to as a contact pad or a connection pad.

[0025] The first dielectric structure IS1 may include a first dielectric layer 21 and a second dielectric layer 22 located on the first dielectric layer 21. Each of the first dielectric layer 21 and the second dielectric layer 22 may have a plate shape elongated along a plane defined by a first direction D1 and a second direction D2. The first direction D1 and the second direction D2 may be perpendicular to each other. For example, the first direction D1 and the second direction D2 may be horizontal directions orthogonal to each other. The first dielectric layer 21 and the second dielectric layer 22 may include dielectric materials different from each other. For example, the first dielectric layer 21 may include silicon oxide, and the second dielectric layer 22 may include silicon carbonitride, silicon nitride, or silicon oxycarbide.

[0026] The top surface 11_T of the bump connection pad 11 may contact the bottom surface 21_B of the first dielectric layer 21 of the first dielectric structure IS1. The bump connection pad 11 may include a conductive material. For example, the bump connection pad 11 may include copper.

[0027] The bump BP may contact the bottom surface of the bump connection pad 11. The first pad PA1 may be electrically connected to the bump BP through the bump connection pad 11. The first pad PA1 may be disposed between the bump BP and the first chip pad 52 of the first semiconductor chip SC1 described later. The semiconductor package may be electrically connected to an external device through the bump BP. The bump BP may include a conductive material. For example, the bump BP may include at least one selected from copper, tin, silver, and gold.

[0028] The first pad PA1, the dummy pad DP and the key pattern KP may penetrate the first dielectric layer 21 and the second dielectric layer 22 of the first dielectric structure IS1 in the third direction D3. The third direction D3 may be perpendicular to the first direction D1 and the second direction D2. For example, the third direction D3 may be a vertical direction perpendicular to the first direction D1 and the second direction D2.

[0029] The first pad PA1, the dummy pad DP and the key pattern KP may be placed in the first dielectric structure IS1 or surrounded by the first dielectric structure IS1. The first pad PA1, the dummy pad DP and the key pattern KP may be arranged in the first dielectric structure IS1. The bottom surface PA1_B of the first pad PA1 may contact the top surface 11_T of the bump connection pad 11. The bottom surface DP_B of the dummy pad DP may contact the top surface 11_T of the bump connection pad 11. The key pattern KP may be spaced apart from the bump connection pad 11. The bottom surface KP_B of the key pattern KP may be exposed. The first pad PA1 and the dummy pad DP may be arranged between the key pattern KP. For example, the key pattern KP may be positioned between two opposite ends of the semiconductor package in the first direction D1, and the first pad PA1 and the dummy pad DP may be placed between the spaced key patterns KP.

[0030] The first pads PA1 may be electrically connected to the first semiconductor chip SC1. The dummy pads DP and the key patterns KP may be electrically spaced apart from the first semiconductor chip SC1.

[0031] The first pad PA1 may include a first conductive layer 31 and a second conductive layer 32 surrounded by the first conductive layer 31. The second conductive layer 32 may be disposed in the first conductive layer 31. A bottom surface PA1_B of the first pad PA1 may be a bottom surface of the first conductive layer 31.

[0032] A distance between the bump BP and the bottom surface of the first conductive layer 31 in the third direction D3 may be smaller than a distance between the bump BP and the bottom surface 32_B of the second conductive layer 32 in the third direction D3.

[0033] The dummy pad DP may include a first dummy layer 36 and a second dummy layer 37 surrounded by the first dummy layer 36. The second dummy layer 37 may be disposed in the first dummy layer 36. A bottom surface DP_B of the dummy pad DP may be a bottom surface of the first dummy layer 36.

[0034] A distance L1 between the bump BP and the bottom surface of the first dummy layer 36 in the third direction D3 may be smaller than a distance L2 between the bump BP and the bottom surface 37_B of the second dummy layer 37 in the third direction D3 .

[0035] The key pattern KP may include a first pattern layer 41 and a second pattern layer 42 surrounded by the first pattern layer 41. The second pattern layer 42 may be disposed in the first pattern layer 41. A bottom surface KP_B of the key pattern KP may be a bottom surface of the first pattern layer 41.

[0036] The first semiconductor chip SC1 may be disposed on the first dielectric structure IS1. The bottom surface of the first semiconductor chip SC1 may be in contact with the top surface 22_T of the second dielectric layer 22 of the first dielectric structure IS1. The first semiconductor chip SC1 may be hybrid-bonded to the first dielectric structure IS1 and the first pad PA1.

[0037] The first semiconductor chip SC1 may include a first chip dielectric layer 51, a first chip pad 52 in the first chip dielectric layer 51, a first wiring structure 53 on the first chip dielectric layer 51, and a first substrate 54 on the first wiring structure 53. The bottom surface of the first chip dielectric layer 51 may contact the top surface 22_T of the second dielectric layer 22 of the first dielectric structure IS1. The first chip dielectric layer 51 may include a dielectric material that is the same as the dielectric material of the second dielectric layer 22. For example, the first chip dielectric layer 51 may include silicon carbon nitride, silicon nitride, or silicon oxycarbide.

[0038] The first chip pad 52 may be surrounded by the first chip dielectric layer 51. The bottom surface 52_B of the first chip pad 52 may contact the top surface PA1_T of the first pad PA1. The dummy pad DP may be spaced apart from the first chip pad 52. The key pattern KP may be spaced apart from the first chip pad 52. The first chip pad 52 may include a conductive material. For example, the first chip pad 52 may include copper.

[0039] The first wiring structure 53 may include a first wiring dielectric layer 53_1 and a first conductive structure 53_2 in the first wiring dielectric layer 53_1. The first wiring dielectric layer 53_1 of the first wiring structure 53 may be disposed on the first chip dielectric layer 51. The first wiring dielectric layer 53_1 of the first wiring structure 53 may include a dielectric material. For example, the first wiring dielectric layer 53_1 of the first wiring structure 53 may include silicon oxide. In some embodiments, the first wiring dielectric layer 53_1 of the first wiring structure 53 may be a multilayer including a plurality of dielectric layers.

[0040] The first conductive structure 53_2 of the first wiring structure 53 may include, for example, at least one selected from a conductive pad, a conductive via, and a conductive line. The first conductive structure 53_2 of the first wiring structure 53 may include a conductive material. The first conductive structure 53_2 of the first wiring structure 53 may be electrically connected to the first chip pad 52.

[0041] The first substrate 54 may be a semiconductor substrate, a dielectric substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate. For example, the semiconductor substrate may include silicon, germanium, silicon-germanium, gallium-phosphorus, or gallium-arsenic.

[0042] The first semiconductor chip SC1 may also include a semiconductor device. For example, the first semiconductor chip SC1 may be a logic semiconductor chip including a logic semiconductor device, or a storage semiconductor chip including a storage semiconductor device. The logic semiconductor chip may be, for example, a central processing unit (CPU), a graphics processing unit (GPU), or an application processor (AP). The storage semiconductor device may be, for example, a dynamic random access memory (DRAM) semiconductor device, a static RAM (SRAM) semiconductor device, a thyristor RAM (TRAM) semiconductor device, a zero capacitor RAM (ZRAM) semiconductor device, a dual transistor RAM (TTRAM) semiconductor device, a flash memory semiconductor device, a magnetic RAM (MRAM) semiconductor device, a spin-transfer torque RAM (STT-MRAM) semiconductor device, a ferroelectric RAM (FRAM) semiconductor device, a phase change RAM (PRAM) semiconductor device, a polymer RAM, or an insulator resistance change storage semiconductor device.

[0043] The first gap filling layer GP1 may be disposed on the first dielectric structure IS1 and the first semiconductor chip SC1. The first gap filling layer GP1 may surround the first semiconductor chip SC1. The first gap filling layer GP1 may contact the top surface 22_T of the second dielectric layer 22, the top surface SC1_T of the first semiconductor chip SC1, and the side wall SC1_S of the first semiconductor chip SC1. The top surface SC1_T of the first semiconductor chip SC1 may be the top surface of the first substrate 54. The side wall SC1_S of the first semiconductor chip SC1 may include the side wall of the first substrate 54, the side wall of the first wiring structure 53, and the side wall of the first chip dielectric layer 51. The first gap filling layer GP1 may include a dielectric material. For example, the first gap filling layer GP1 may include silicon oxide.

[0044] The top surface DP_T of the dummy pad DP may contact the bottom surface GP1_B of the first gap filling layer GP1. The top surface KP_T of the key pattern KP may contact the bottom surface GP1_B of the first gap filling layer GP1. In some embodiments, the top surface DP_T of the dummy pad DP may contact the bottom surface of the first chip dielectric layer 51.

[0045] The first semiconductor chip SC1 may further include a through hole VI. The through hole VI may extend in the third direction D3. The through hole VI may penetrate the first gap filling layer GP1 and the first substrate 54. The through hole VI may be electrically connected to the first conductive structure 53_2 of the first wiring structure 53. The through hole VI may include a conductive material. For example, the through hole VI may include copper.

[0046] The second dielectric structure IS2 may be disposed on the first gap-filling layer GP1. The second dielectric structure IS2 may include a third dielectric layer 23 and a fourth dielectric layer 24 located on the third dielectric layer 23. Each of the third dielectric layer 23 and the fourth dielectric layer 24 may have a plate shape elongated along a plane defined by the first direction D1 and the second direction D2. The third dielectric layer 23 and the fourth dielectric layer 24 may include respective dielectric materials different from each other. For example, the third dielectric layer 23 may include silicon oxide, and the fourth dielectric layer 24 may include silicon carbonitride, silicon nitride, or silicon oxycarbide.

[0047] The second dielectric structure IS2 may be spaced apart from the first dielectric structure IS1 in the third direction D3. The first semiconductor chip SC1 may be disposed between the first dielectric structure IS1 and the second dielectric structure IS2. The first gap-filling layer GP1 may be disposed between the first dielectric structure IS1 and the second dielectric structure IS2.

[0048] The second pad PA2 may penetrate the third dielectric layer 23 and the fourth dielectric layer 24 of the second dielectric structure IS2 in the third direction D3. The bottom surface of the second pad PA2 may contact the top surface of the through hole VI and the top surface of the first gap filling layer GP1. The second pad PA2 may be surrounded by the second dielectric structure IS2. The second pad PA2 may be disposed in the second dielectric structure IS2. The second pad PA2 may be electrically connected to the first semiconductor chip SC1 through the through hole VI.

[0049] The second pad PA2 may include a third conductive layer 33 and a fourth conductive layer 34 surrounded by the third conductive layer 33. The fourth conductive layer 34 may be disposed in the third conductive layer 33. A bottom surface of the second pad PA2 may be a bottom surface of the third conductive layer 33.

[0050] The second semiconductor chip SC2 may be disposed on the second dielectric structure IS2. A bottom surface of the second semiconductor chip SC2 may be in contact with a top surface of the fourth dielectric layer 24. The second semiconductor chip SC2 may be hybrid-bonded to the second dielectric structure IS2 and the second pad PA2.

[0051] The second semiconductor chip SC2 may include a second chip dielectric layer 61, a second chip pad 62 in the second chip dielectric layer 61, a second wiring structure 63 on the second chip dielectric layer 61, and a second substrate 64 on the second wiring structure 63. The bottom surface of the second chip dielectric layer 61 may contact the top surface of the fourth dielectric layer 24 of the second dielectric structure IS2. The second chip dielectric layer 61 may include a dielectric material identical to the dielectric material of the fourth dielectric layer 24. For example, the second chip dielectric layer 61 may include silicon carbonitride, silicon nitride or nitride oxycarbide. In some embodiments, the second chip dielectric layer 61 may be a multilayer including a plurality of dielectric layers.

[0052] The second chip pad 62 may be surrounded by the second chip dielectric layer 61. The bottom surface of the second chip pad 62 may contact the top surface of the second pad PA2. The second chip pad 62 may include a conductive material. For example, the second chip pad 62 may include copper.

[0053] The second wiring structure 63 may include a second wiring dielectric layer and a second conductive structure in the second wiring dielectric layer. The second wiring dielectric layer of the second wiring structure 63 may be disposed on the second chip dielectric layer 61. The second wiring dielectric layer of the second wiring structure 63 may include a dielectric material. For example, the second wiring dielectric layer of the second wiring structure 63 may include silicon oxide. In some embodiments, the second wiring dielectric layer of the second wiring structure 63 may be a multilayer including a plurality of dielectric layers.

[0054] The second conductive structure of the second wiring structure 63 may include, for example, at least one selected from a conductive pad, a conductive via, and a conductive line. The second conductive structure of the second wiring structure 63 may include a conductive material. The second conductive structure of the second wiring structure 63 may be electrically connected to the second chip pad 62.

[0055] The second substrate 64 may be a semiconductor substrate, a dielectric substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate.

[0056] The second semiconductor chip SC2 may further include a semiconductor device. For example, the second semiconductor chip SC2 may be a logic semiconductor chip including a logic semiconductor device, or a memory semiconductor chip including a memory semiconductor device.

[0057] The second gap filling layer GP2 may be disposed on the second dielectric structure IS2 and the second semiconductor chip SC2. The second gap filling layer GP2 may surround the second semiconductor chip SC2. The second gap filling layer GP2 may contact the top surface of the fourth dielectric layer 24 and the sidewall SC2_S of the second semiconductor chip SC2. The sidewall SC2_S of the second semiconductor chip SC2 may include the sidewall of the second substrate 64, the sidewall of the second wiring structure 63, and the sidewall of the second chip dielectric layer 61. The second gap filling layer GP2 may include a dielectric material. For example, the second gap filling layer GP2 may include silicon oxide.

[0058] The first bonding layer BL1 may be disposed on the second gap filling layer GP2 and the second substrate 64 of the second semiconductor chip SC2. The second bonding layer BL2 may be disposed on the first bonding layer BL1. The first bonding layer BL1 and the second bonding layer BL2 may include the same dielectric material. For example, the first bonding layer BL1 and the second bonding layer BL2 may include silicon carbonitride, silicon nitride, or silicon oxycarbide.

[0059] The dummy substrate DS may be disposed on the second bonding layer BL2. The dummy substrate DS may be a semiconductor substrate, a dielectric substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate.

[0060] In some embodiments, the semiconductor package may not include any of the first bonding layer BL1, the second bonding layer BL2, and the dummy substrate DS. In this case, the method of manufacturing the semiconductor package may include: forming a glue layer on the dummy substrate DS, attaching the glue layer to the second gap-filling layer GP2 and the second semiconductor chip SC2, and removing the dummy substrate DS and the glue layer.

[0061] The first conductive layer 31 may include a first portion P1 in contact with the top surface 11T of the bump connection pad 11, and a second portion P2 in contact with the bottom surface 52B of the first chip pad 52. The second portion P2 of the first conductive layer 31 may surround the second conductive layer 32. The second conductive layer 32 may be spaced apart from the bump connection pad 11. The first portion P1 of the first conductive layer 31 may be between the second conductive layer 32 and the bump connection pad 11. The second portion P2 of the first conductive layer 31 may be disposed on the first portion P1 of the first conductive layer 31. The second portion P2 of the first conductive layer 31 may be located at the same height as the second conductive layer 32. The distance between the bump connection pad 11 and the second portion P2 of the first conductive layer 31 in the third direction D3 may be the same as the distance between the bump connection pad 11 and the second conductive layer 32 in the third direction D3.

[0062] The first portion P1 of the first conductive layer 31 may include a first surface P1_S1 in contact with the top surface 11_T of the bump connection pad 11, and a second surface P1_S2 in contact with the bottom surface 32_B of the second conductive layer 32. The first surface P1_S1 of the first portion P1 of the first conductive layer 31 may be the bottom surface PA1_B of the first pad PA1 and the bottom surface of the first conductive layer 31. The first surface P1_S1 and the second surface P1_S2 of the first portion P1 of the first conductive layer 31 may be parallel to each other. The first surface P1_S1 and the second surface P1_S2 of the first portion P1 of the first conductive layer 31 may be parallel to the first direction D1 and the second direction D2. The first surface P1_S1 and the second surface P1_S2 of the first portion P1 of the first conductive layer 31 may stand opposite to each other. The area (e.g., the plane area) at the first surface P1_S1 of the first portion P1 of the first conductive layer 31 may be greater than the area (e.g., the plane area) at the second surface P1_S2 of the first portion P1 of the first conductive layer 31.

[0063] The second portion P2 of the first conductive layer 31 may include an outer sidewall P2_OS and an inner sidewall P2_IS. The inner sidewall P2_IS of the second portion P2 of the first conductive layer 31 may contact the outer sidewall 32_OS of the second conductive layer 32. The outer sidewall P2_OS of the second portion P2 of the first conductive layer 31 may contact the first dielectric layer 21 and the second dielectric layer 22 of the first dielectric structure IS1. The outer sidewall P2_OS and the inner sidewall P2_IS of the second portion P2 of the first conductive layer 31 may be parallel to the third direction D3. The outer sidewall P2_OS and the inner sidewall P2_IS of the second portion P2 of the first conductive layer 31 may stand opposite to each other.

[0064] The second portion P2 of the first conductive layer 31 may include a top surface P2_T in contact with the bottom surface 52_B of the first chip pad 52. The second conductive layer 32 may include a top surface 32_T in contact with the bottom surface 52_B of the first chip pad 52. The top surface P2_T of the second portion P2 of the first conductive layer 31 may be coplanar with the top surface 32_T of the second conductive layer 32. The top surface P2_T of the second portion P2 of the first conductive layer 31 may be located at the same height as the top surface 32_T of the second conductive layer 32. The top surface P2_T of the second portion P2 of the first conductive layer 31 may be the top surface of the first conductive layer 31. The top surface and the bottom surface of the first conductive layer 31 may stand opposite to each other. The top surface and the bottom surface of the first conductive layer 31 may be parallel to each other.

[0065] The area (or plane area) at the first surface P1_S1 of the first portion P1 of the first conductive layer 31 may be greater than the area (e.g., plane area) at the top surface P2_T of the second portion P2 of the first conductive layer 31. When viewed in a plan view, the top surface P2_T of the second portion P2 of the first conductive layer 31 may have an annular shape (e.g., a quadrilateral ring shape or a circular ring shape). The area (e.g., plane area) at the top surface 32_T of the second conductive layer 32 may be greater than the area (e.g., plane area) at the top surface P2_T of the second portion P2 of the first conductive layer 31.

[0066] The first portion P1 of the first conductive layer 31 may have a plate shape (e.g., a quadrilateral plate shape or a circular plate shape). The second portion P2 of the first conductive layer 31 may have a tubular shape (e.g., a quadrilateral tubular shape or a circular tubular shape). The first portion P1 of the first conductive layer 31 may be located at a height lower than that of the second portion P2 of the first conductive layer 31. The distance between the first portion P1 of the first conductive layer 31 and the first chip pad 52 of the first semiconductor chip SC1 in the third direction D3 may be greater than the distance between the second portion P2 of the first conductive layer 31 and the first chip pad 52 of the first semiconductor chip SC1 in the third direction D3.

[0067] The width W1 of the bump connection pad 11 in the first direction D1 may be greater than the width W2 of the first pad PA1 in the first direction D1. The width W3 of the first chip pad 52 in the first direction D1 may be greater than the width W2 of the first pad PA1 in the first direction D1. The width W2 of the first pad PA1 in the first direction D1 may be the width of the first conductive layer 31 in the first direction D1. The width W4 of the second conductive layer 32 in the first direction D1 may be less than the width of the first conductive layer 31 in the first direction D1.

[0068] The first conductive layer 31 and the second conductive layer 32 may include respective conductive materials different from each other. The first conductive layer 31 may include, for example, at least one selected from tantalum nitride, tantalum, titanium nitride, and titanium, but the inventive concept is not limited thereto. The second conductive layer 32 may include, for example, copper.

[0069] In some embodiments, the first conductive layer 31 may be a multilayer including a first layer and a second layer. In this case, the first layer may include one of tantalum nitride, tantalum, titanium nitride, and titanium, and the second layer may include another of tantalum nitride, tantalum, titanium nitride, and titanium.

[0070] The first dummy layer 36 may include a first portion P3 in contact with the top surface 11_T of the bump connection pad 11, and a second portion P4 in contact with the bottom surface GP1_B of the first gap filling layer GP1. The second portion P4 of the first dummy layer 36 may surround the second dummy layer 37. The second dummy layer 37 may be spaced apart from the bump connection pad 11. The first portion P3 of the first dummy layer 36 may be between the second dummy layer 37 and the bump connection pad 11. The second portion P4 of the first dummy layer 36 may be disposed on the first portion P3 of the first dummy layer 36. The second portion P4 of the first dummy layer 36 may be located at the same height as the height of the second dummy layer 37. The distance between the bump connection pad 11 and the second portion P4 of the first dummy layer 36 in the third direction D3 may be the same as the distance between the bump connection pad 11 and the second dummy layer 37 in the third direction D3.

[0071] The first portion P3 of the first dummy layer 36 may include a first surface P3_S1 in contact with the top surface 11_T of the bump connection pad 11, and a second surface P3_S2 in contact with the bottom surface 37_B of the second dummy layer 37. The first surface P3_S1 of the first portion P3 of the first dummy layer 36 may be the bottom surface DP_B of the dummy pad DP. The first surface P3_S1 and the second surface P3_S2 of the first portion P3 of the first dummy layer 36 may be parallel to each other. The first surface P3_S1 and the second surface P3_S2 of the first portion P3 of the first dummy layer 36 may be parallel to the first direction D1 and the second direction D2. The first surface P3_S1 and the second surface P3_S2 of the first portion P3 of the first dummy layer 36 may stand opposite to each other. The area (e.g., plane area) at the first surface P3_S1 of the first portion P3 of the first dummy layer 36 may be greater than the area (e.g., plane area) at the second surface P3_S2 of the first portion P3 of the first dummy layer 36.

[0072] The second portion P4 of the first dummy layer 36 may include an outer sidewall P4_OS and an inner sidewall P4_IS. The inner sidewall P4_IS of the second portion P4 of the first dummy layer 36 may contact the outer sidewall 37_OS of the second dummy layer 37. The outer sidewall P4_OS of the second portion P4 of the first dummy layer 36 may contact the first dielectric layer 21 and the second dielectric layer 22 of the first dielectric structure IS1. The outer sidewall P4_OS and the inner sidewall P4_IS of the second portion P4 of the first dummy layer 36 may be parallel to the third direction D3. The outer sidewall P4_OS and the inner sidewall P4_IS of the second portion P4 of the first dummy layer 36 may stand opposite to each other.

[0073] The second portion P4 of the first dummy layer 36 may include a top surface P4_T in contact with the bottom surface GP1_B of the first gap filling layer GP1. The second dummy layer 37 may include a top surface 37_T in contact with the bottom surface GP1_B of the first gap filling layer GP1. The top surface P4_T of the second portion P4 of the first dummy layer 36 may be coplanar with the top surface 37_T of the second dummy layer 37. The top surface P4_T of the second portion P4 of the first dummy layer 36 may be located at the same height as the top surface 37_T of the second dummy layer 37. The top surface P4_T of the second portion P4 of the first dummy layer 36 may be the top surface of the first dummy layer 36. The area (or plane area) at the first surface P3_S1 of the first portion P3 of the first dummy layer 36 may be greater than the area (e.g., plane area) at the top surface P4_T of the second portion P4 of the first dummy layer 36. When viewed in a plan view, the top surface P4_T of the second portion P4 of the first dummy layer 36 may have an annular shape (e.g., a quadrilateral ring shape or a circular ring shape). The area (e.g., a plane area) at the top surface 37_T of the second dummy layer 37 may be greater than the area (or plane area) at the top surface P4_T of the second portion P4 of the first dummy layer 36.

[0074] The first portion P3 of the first dummy layer 36 may have a plate shape (or a quadrilateral plate shape or a circular plate shape). The second portion P4 of the first dummy layer 36 may have a tubular shape (or a quadrilateral tubular shape or a circular tubular shape). The first portion P3 of the first dummy layer 36 may be located at a height lower than that of the second portion P4 of the first dummy layer 36. The distance between the first portion P3 of the first dummy layer 36 and the first chip pad 52 of the first semiconductor chip SC1 in the third direction D3 may be greater than the distance between the second portion P4 of the first dummy layer 36 and the first chip pad 52 of the first semiconductor chip SC1 in the third direction D3.

[0075] A width W1 of the bump connection pad 11 in the first direction D1 may be greater than a width W5 of the first dummy pad DP in the first direction D1. A width W3 of the first chip pad 52 in the first direction D1 may be greater than a width W5 of the dummy pad DP in the first direction D1.

[0076] The first dummy layer 36 and the second dummy layer 37 may include respective conductive materials different from each other. The first dummy layer 36 may include at least one selected from tantalum nitride, tantalum, titanium nitride, and titanium, but the inventive concept is not limited thereto. The second dummy layer 37 may include, for example, copper.

[0077] In some embodiments, the first dummy layer 36 may be a multilayer including a first layer and a second layer. In this case, the first layer may include one of tantalum nitride, tantalum, titanium nitride, and titanium, and the second layer may include another of tantalum nitride, tantalum, titanium nitride, and titanium.

[0078] The first pattern layer 41 may include a first portion P5 exposed to the outside, and a second portion P6 in contact with the bottom surface GP1_B of the first gap filling layer GP1. The second portion P6 of the first pattern layer 41 may surround the second pattern layer 42. The second portion P6 of the first pattern layer 41 may be disposed on the first portion P5 of the first pattern layer 41. The second portion P6 of the first pattern layer 41 may be located at the same height as the height of the second pattern layer 42. The distance between the bump connection pad 11 and the second portion P6 of the first pattern layer 41 in the third direction D3 may be the same as the distance between the bump connection pad 11 and the second pattern layer 42 in the third direction D3.

[0079] The first portion P5 of the first pattern layer 41 may include a first surface P5_S1 exposed to the outside, and a second surface P5_S2 in contact with the bottom surface 42_B of the second pattern layer 42. The first surface P5_S1 of the first portion P5 of the first pattern layer 41 may be the bottom surface DP_B of the key pattern KP. The first surface P5_S1 of the first portion P5 of the first pattern layer 41 may be coplanar with the first surface P3_S1 of the first portion P3 of the first dummy layer 36, the first surface P1_S1 of the first portion P1 of the first conductive layer 31, and the bottom surface 21B of the first dielectric layer 21. The first surface P5_S1 of the first portion P5 of the first pattern layer 41 may be located at the same height as the first surface P3_S1 of the first portion P3 of the first dummy layer 36, the first surface P1_S1 of the first portion P1 of the first conductive layer 31, and the bottom surface 21_B of the first dielectric layer 21.

[0080] The first surface P5_S1 and the second surface P5_S2 of the first portion P5 of the first pattern layer 41 may be parallel to each other. The first surface P5_S1 and the second surface P5_S2 of the first portion P5 of the first pattern layer 41 may be parallel to the first direction D1 and the second direction D2. The first surface P5_S1 and the second surface P5_S2 of the first portion P5 of the first pattern layer 41 may stand opposite to each other. The area (e.g., the plane area) at the first surface P5_S1 of the first portion P5 of the first pattern layer 451 may be greater than the area (e.g., the plane area) at the second surface P5_S2 of the first portion P5 of the first pattern layer 41.

[0081] The second portion P6 of the first pattern layer 41 may include an outer sidewall P6_OS and an inner sidewall P6_IS. The inner sidewall P6_IS of the second portion P6 of the first pattern layer 41 may contact the outer sidewall 42_OS of the second pattern layer 42. The outer sidewall P6_OS of the second portion P6 of the first pattern layer 41 may contact the first dielectric layer 21 and the second dielectric layer 22 of the first dielectric structure IS1. The outer sidewall P6_OS and the inner sidewall P6_IS of the second portion P6 of the first pattern layer 41 may be parallel to the third direction D3. The outer sidewall P6_OS and the inner sidewall P6_IS of the second portion P6 of the first pattern layer 41 may stand opposite to each other.

[0082] The second portion P6 of the first pattern layer 41 may include a top surface P6_T in contact with the bottom surface GP1_B of the first gap filling layer GP1. The second dummy layer 42 may include a top surface 42_T in contact with the bottom surface GP1_B of the first gap filling layer GP1. The top surface P6_T of the second portion P6 of the first pattern layer 41 may be coplanar with the top surface 42_T of the second pattern layer 42, the top surface P4_T of the second portion P4 of the first dummy layer 36, the top surface 37_T of the second dummy layer 37, the top surface P2_T of the second portion P2 of the first conductive layer 31, the top surface 32_T of the second conductive layer 32, and the top surface 22_T of the second dielectric layer 22. The top surface P6_T of the second portion P6 of the first pattern layer 41 may be located at the same height as the top surface 42_T of the second pattern layer 42, the top surface P4_T of the second portion P4 of the first dummy layer 36, the top surface 37_T of the second dummy layer 37, the top surface P2_T of the second portion P2 of the first conductive layer 31, the top surface 32_T of the second conductive layer 32, and the top surface 22_T of the second dielectric layer 22. The top surface P6_T of the second portion P6 of the first pattern layer 41 may be the top surface of the first pattern layer 41. The area (or plane area) at the first surface P5_S1 of the first portion P5 of the first pattern layer 41 may be greater than the area (e.g., plane area) at the top surface P6_T of the second portion P6 of the first pattern layer 41. The area (e.g., plane area) at the top surface 42_T of the second pattern layer 42 may be greater than the area (e.g., plane area) at the top surface P6_T of the second portion P6 of the first pattern layer 41.

[0083] The first portion P5 of the first pattern layer 41 may be located at a height lower than that of the second portion P6 of the first pattern layer 41. The distance between the first portion P5 of the first pattern layer 41 and the first chip pad 52 of the first semiconductor chip SC1 in the third direction D3 may be greater than the distance between the second portion P6 of the first pattern layer 41 and the first chip pad 52 of the first semiconductor chip SC1 in the third direction D3.

[0084] A width W1 of the bump connection pad 11 in the first direction D1 may be greater than a width W6 of the key pattern KP in the first direction D1. A width W3 of the first chip pad 52 in the first direction D1 may be greater than a width W6 of the key pattern KP in the first direction D1.

[0085] The first pattern layer 41 and the second pattern layer 42 may include respective conductive materials different from each other. The first pattern layer 41 may include at least one selected from tantalum nitride, tantalum, titanium nitride, and titanium, but the inventive concept is not limited thereto. The second pattern layer 42 may include, for example, copper.

[0086] In some embodiments, the first pattern layer 41 may be a multilayer including a first layer and a second layer. In this case, the first layer may include one of tantalum nitride, tantalum, titanium nitride, and titanium, and the second layer may include another of tantalum nitride, tantalum, titanium nitride, and titanium.

[0087] The first conductive layer 31, the first dummy layer 36, and the first pattern layer 41 may include the same conductive material. The second conductive layer 32, the second dummy layer 37, and the second pattern layer 42 may include the same conductive material.

[0088] Figure 2 , Figure 3A , Figure 3B , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 and Fig. 9 Plan views and cross-sectional views illustrating a method of manufacturing a semiconductor package according to some embodiments are shown.

[0089] refer to Figure 2 The first dielectric structure IS1 may be formed on a carrier substrate CA. The carrier substrate CA may be, for example, a silicon substrate. The formation of the first dielectric structure IS1 may include: forming a first dielectric layer 21 on the carrier substrate CA, and forming a second dielectric layer 22 on the first dielectric layer 21 .

[0090] The first pad PA1, the dummy pad DP, and the key pattern KP may be formed in the first dielectric structure IS1. The formation of the first pad PA1, the dummy pad DP, and the key pattern KP may include: exposing the carrier substrate CA by forming a first opening OP1 penetrating the first dielectric structure IS1; forming a first preliminary layer on the carrier substrate CA and the first dielectric structure IS1; forming a second preliminary layer on the first preliminary layer; and removing the upper portion of the first preliminary layer and the upper portion of the second preliminary layer. In some embodiments, the second preliminary layer may be formed by an electroplating process using the first preliminary layer as a seed layer. The first preliminary layer used as a seed layer becomes the first conductive layer 31, the first dummy layer 36, and the first pattern layer 41. The second preliminary layer becomes the second conductive layer 32, the second dummy layer 37, and the second pattern layer 42. According to an embodiment of the present disclosure, the key pattern KP may be formed on the carrier substrate simultaneously with the first pad PA1 and the dummy pad DP or in the same manufacturing process step. Therefore, the key pattern KP, the first pad PA1, and the dummy pad DP have a seed layer of the same structure, and the process of forming the first pad PA1 and the dummy pad DP can be omitted after removing the carrier substrate. Each of the key pattern KP, the first pad PA1, and the dummy pad DP may have an inner conductive layer and an outer conductive layer covering the inner conductive layer. The inner conductive layer may correspond to the second conductive layer 32, the second dummy layer 37, and the second pattern layer 42. The outer conductive layer may correspond to the first conductive layer 31, the first dummy layer 36, and the first pattern layer 41.

[0091] The first preliminary layer and the second preliminary layer may include respective conductive materials different from each other. The first preliminary layer may include at least one selected from tantalum nitride, tantalum, titanium nitride and titanium, but the inventive concept is not limited thereto. The second preliminary layer may include, for example, copper. The upper portion of the first preliminary layer may be removed so that the first preliminary layer may be divided into a first conductive layer 31, a first dummy layer 36 and a first pattern layer 41. The upper portion of the second preliminary layer may be removed so that the second preliminary layer may be divided into a second conductive layer 32, a second dummy layer 37 and a second pattern layer 42. The upper portion of the first preliminary layer may refer to a portion protruding from or extending beyond the outermost surface of the first conductive layer 31, the first dummy layer 36 and the first pattern layer 41, and may be considered as a redundant portion. Similarly, the upper portion of the second preliminary layer may refer to a portion protruding from or extending beyond the outermost surface of the second conductive layer 32, the second dummy layer 37 and the second pattern layer 42, and may be considered as a redundant portion.

[0092] refer to Figure 3A and Figure 3B, a plurality of first semiconductor chips SC1 may be formed. The formation of the first semiconductor chip SC1 may include: forming a through via VI and a first wiring structure 53 on a first substrate 54 , and forming a first chip dielectric layer 51 and a first chip pad 52 on the first wiring structure 53 .

[0093] A plurality of first semiconductor chips SC1 may be bonded to the first dielectric structure IS1. A plurality of first semiconductor chips SC1 may be hybrid bonded to the first dielectric structure IS1 and the first pad PA1. A first chip dielectric layer 51 of the first semiconductor chip SC1 may be bonded to the second dielectric layer 22 of the first dielectric structure IS1. A first chip pad 52 of the first semiconductor chip SC1 may be bonded to the first pad PA1.

[0094] refer to Figure 4 , an upper portion of the first substrate 54 may be removed. The upper portion of the first substrate 54 may be removed to expose a top surface VI_T of the through-hole VI and a portion of a sidewall VI_S of the through-hole VI.

[0095] refer to Figure 5 , the first gap-filling layer GP1 may be formed to surround the first semiconductor chip SC1. The first gap-filling layer GP1 may contact the top surface of the second dielectric layer 22 of the first dielectric structure IS1, the top surface of the dummy pad DP, the top surface of the key pattern KP, the sidewall of the first semiconductor chip SC1, the top surface of the first semiconductor chip SC1, and the sidewall VI_S of the through hole VI.

[0096] The second dielectric structure IS2 may be formed on the first gap filling layer GP1. The second dielectric structure IS2 may include a third dielectric layer 23 disposed on the first gap filling layer GP1, and a fourth dielectric layer 24 disposed on the third dielectric layer 23. The second dielectric structure IS2 includes a second pad PA2 aligned to contact the through hole VI of the first dielectric structure IS1. The top surface VI_T of the through hole VI may contact the bottom surface of the third dielectric layer 23.

[0097] refer to Figure 6 , the second pad PA2 may be formed in the second dielectric structure IS2. The formation of the second pad PA2 may include: exposing the through hole VI and the first gap filling layer GP1 by forming a second opening OP2 penetrating the second dielectric structure IS2; forming a third preliminary layer on the through hole VI, the first gap filling layer GP1, and the second dielectric structure IS2; forming a fourth preliminary layer on the third preliminary layer; and removing the upper portion of the third preliminary layer and the upper portion of the fourth preliminary layer. In some embodiments, the fourth preliminary layer may be formed by an electroplating process using the third preliminary layer as a seed.

[0098] The conductive materials included in the third preliminary layer and the fourth preliminary layer may be different from each other. For example, the third preliminary layer may include at least one selected from tantalum nitride, tantalum, titanium nitride, and titanium, but the embodiments of the present disclosure are not limited thereto. The fourth preliminary layer may include, for example, copper. The upper portion of the third preliminary layer may be removed so that the third preliminary layer may be divided into a third conductive layer 33. The upper portion of the fourth preliminary layer may be removed so that the fourth preliminary layer may be divided into a fourth conductive layer 34.

[0099] refer to Figure 7 , a plurality of second semiconductor chips SC2 may be formed. The formation of the second semiconductor chip SC2 may include: forming a second wiring structure 63 on a second substrate 64 , and forming a second chip dielectric layer 61 and a second chip pad 62 on the second wiring structure 63 .

[0100] A plurality of second semiconductor chips SC2 may be bonded to the second dielectric structure IS2. A plurality of second semiconductor chips SC2 may be hybrid bonded to the second dielectric structure IS2 and the second pad PA2. The second chip dielectric layer 61 of the second semiconductor chip SC2 may be bonded to the fourth dielectric layer 24 of the second dielectric structure IS2. The second chip pad 62 of the second semiconductor chip SC2 may be bonded to the second pad PA2.

[0101] refer to Figure 8 , the second gap-filling layer GP2 may be formed to surround the second semiconductor chip SC2. The second gap-filling layer GP2 may be in contact with the top surface of the fourth dielectric layer 24 and the sidewall of the second semiconductor chip SC2.

[0102] The first bonding layer BL1 may be formed on the second gap-filling layer GP2. The second bonding layer BL2 may be formed on the dummy substrate DS. The first bonding layer BL1 and the second bonding layer BL2 may be bonded to each other using a wafer bonding process.

[0103] refer to Fig. 9 , the carrier substrate CA and the dummy substrate DS may be turned upside down. Thereafter, the carrier substrate CA may be removed. In some embodiments, the carrier substrate CA may be removed by a grinding process. The carrier substrate CA may be removed to expose the first pads PA1, the dummy pads DP, and the key patterns KP.

[0104] A scribe line SB to be discussed below may be defined. Adjacent scribe lines SB may be disposed between the key pattern KP, the dummy pad DP, the first pad PA1, the first semiconductor chip SC1, the second pad PA2, and the second semiconductor chip SC2.

[0105] refer to Figure 1A, a bump connection pad 11 and a bump BP may be formed. The key pattern KP may serve as an alignment key in a process for forming the bump connection pad 11 and the bump BP. In some embodiments, the key pattern KP may serve as an alignment key in a process other than a process for forming the bump connection pad 11 and the bump BP.

[0106] The scribing process may be performed along the scribing line SB and may cut the first and second dielectric layers 21 and 22 of the first dielectric structure IS1, the first gap-filling layer GP1, the third and fourth dielectric layers 23 and 24 of the second dielectric structure IS2, the second gap-filling layer GP2, the first and second bonding layers BL1 and BL2, and the dummy substrate DS.

[0107] The first dielectric layer 21 may be cut and divided into a plurality of first dielectric layers 21. The second dielectric layer 22 may be cut and divided into a plurality of second dielectric layers 22. The third dielectric layer 23 may be cut and divided into a plurality of third dielectric layers 23. The fourth dielectric layer 24 may be cut and divided into a plurality of fourth dielectric layers 24. The first gap-filling layer GP1 may be cut and divided into a plurality of first gap-filling layers GP1. The second gap-filling layer GP2 may be cut and divided into a plurality of second gap-filling layers GP2. The first bonding layer BL1 may be cut and divided into a plurality of first bonding layers BL1. The second bonding layer BL2 may be cut and divided into a plurality of second bonding layers BL2. The dummy substrate DS may be cut and divided into a plurality of dummy substrates DS.

[0108] In the method of manufacturing a semiconductor package according to some embodiments, since the key pattern KP and the first pad PA1 are formed simultaneously with each other, a process for forming a pad in the first dielectric structure IS1 after removing the carrier substrate CA may be omitted, which may lead to simplification of manufacturing the semiconductor package.

[0109] Fig.10 A cross-sectional view of a semiconductor package according to some embodiments is shown. In addition to the following description, Fig.10 The semiconductor package can be Figure 1A and Figure 1B The semiconductor packages are the same or substantially the same.

[0110] refer to Fig.10 The second gap-filling layer GP2a may include a polymer material. For example, the second gap-filling layer GP2a may include epoxy resin.

[0111] The first bonding layer, the second bonding layer, and the dummy wafer may not be disposed on the second semiconductor chip SC2 and the second gap-filling layer GP2a. The second semiconductor chip SC2 and the second gap-filling layer GP2a may have top surfaces exposed to the outside.

[0112] Fig.11 A cross-sectional view illustrating a method of manufacturing a semiconductor package according to some embodiments is shown.

[0113] refer to Fig.11 ,and Figures 2 to 7 Similar to that discussed in, the semiconductor package may include a carrier substrate CA, a first dielectric structure IS1, a first pad PA1, a dummy pad DP, a key pattern KP, a first semiconductor chip SC1, a first gap filling layer GP1, a second dielectric structure IS2, a second pad PA2, a second semiconductor chip SC2 and a second gap filling layer GP2a.

[0114] The glue layer GL may be formed on the dummy substrate DS. The glue layer GL may include an adhesive polymer material. The glue layer GL may be attached to the second semiconductor chip SC2 and the second gap-filling layer GP2a.

[0115] refer to Fig.10 , the dummy substrate DS and the carrier substrate CA may be turned upside down. After removing the carrier substrate CA, the bump connection pads 11 and the bumps BP may be formed. A scribing process may be performed. The glue layer GL and the dummy substrate DS may be removed.

[0116] Fig.12 A cross-sectional view of a semiconductor package according to some embodiments is shown. In addition to the following description, Fig.12 The semiconductor package can be Figure 1A and Figure 1B The semiconductor packages are the same or substantially the same.

[0117] refer to Fig.12 , the first semiconductor chip SC1b may have the same width as the width of the first dielectric structure IS1, the width of the second dielectric structure IS2, the width of the first bonding layer BL1, the width of the second bonding layer BL2, and the width of the dummy substrate DS. For example, the first semiconductor chip SC1b may have the same width as the width of the first dielectric structure IS1, the width of the second dielectric structure IS2, the width of the first bonding layer BL1, the width of the second bonding layer BL2, and the width of the dummy substrate DS in the first direction D1. The first semiconductor chip SC1b may have sidewalls that are coplanar with the sidewalls of the first dielectric structure IS1, the sidewalls of the second dielectric structure IS2, the sidewalls of the first bonding layer BL1, the sidewalls of the second bonding layer BL2, and the sidewalls of the dummy substrate DS.

[0118] The first semiconductor chip SC1b may include a first chip dielectric layer 51b, a first chip pad 52, a first wiring structure 53b, a through hole VIb and a first substrate 54b. The first chip dielectric layer 51b, the first wiring structure 53b and the first substrate 54b may have the same width as the width of the first dielectric structure IS1, the width of the second dielectric structure IS2, the width of the first bonding layer BL1, the width of the second bonding layer BL2, and the width of the dummy substrate DS. For example, the first chip dielectric layer 51b, the first wiring structure 53b and the first substrate 54b may have the same width as the width of the first dielectric structure IS1, the width of the second dielectric structure IS2, the width of the first bonding layer BL1, the width of the second bonding layer BL2, and the width of the dummy substrate DS in the first direction D1. The first chip dielectric layer 51b, the first wiring structure 53b, and the first substrate 54b may have sidewalls coplanar with sidewalls of the first dielectric structure IS1, the second dielectric structure IS2, the first bonding layer BL1, the second bonding layer BL2, and the dummy substrate DS.

[0119] The dummy pad DP and the key pattern KP may have a top surface in contact with the bottom surface of the first chip dielectric layer 51b. The first substrate 54b may have a top surface in contact with the bottom surface of the third dielectric layer 23. The through hole VIb may have a top surface coplanar with the top surface of the first substrate 54b. The top surface of the through hole VIb may be located at the same height as the top surface of the first substrate 54b.

[0120] Fig.13A and Fig. 13B Plan views and cross-sectional views illustrating a method of manufacturing a semiconductor package according to some embodiments are shown.

[0121] refer to Fig.13A and Fig. 13B ,and Figure 2 Similar to what is discussed in , a carrier substrate CA, a first dielectric structure IS1, a first pad PA1, a dummy pad DP, and a key pattern KP may be formed.

[0122] A via VIb may be formed on the first substrate 54b. A first wiring structure 53b may be formed on the first substrate 54b. A first chip dielectric layer 51b may be formed on the first wiring structure 53b. A first chip pad 52 may be formed in the first chip dielectric layer 51b.

[0123] The first chip dielectric layer 51b and the first chip pad 52 may be bonded to the first pad PA1 and the second dielectric layer 22 of the first dielectric structure IS1. The first chip dielectric layer 51b and the first chip pad 52 may be hybrid bonded to the first pad PA1 and the second dielectric layer 22 of the first dielectric structure IS1.

[0124] refer to Fig.12 , the upper portion of the first substrate 54b can be removed. Figures 4 to 9 Similar to what is discussed in , the semiconductor package may include a second dielectric structure IS2, a second pad PA2, a second semiconductor chip SC2, a second gap-filling layer GP2, a first bonding layer BL1, a second bonding layer BL2, and a dummy substrate DS.

[0125] After removing the carrier substrate CA, the bump connection pads 11 and the bumps BP may be formed. A scribing process may be performed. The scribing process may cut the first chip dielectric layer 51b, the first wiring structure 53b, and the first substrate 54b.

[0126] The first chip dielectric layer 51b may be cut and divided into a plurality of first chip dielectric layers 51b. The first wiring structure 53b may be cut and divided into a plurality of first wiring structures 53b. The first substrate 54b may be cut and divided into a plurality of first substrates 54b. The first semiconductor chip SC1b may include a separated first chip dielectric layer 51b, a separated first wiring structure 53b, and a separated first substrate 54b.

[0127] Fig.14 An enlarged cross-sectional view of a semiconductor package according to some embodiments is shown. In addition to the following description, Fig.14 The semiconductor package can be similar to Figure 1A and Figure 1B semiconductor packaging.

[0128] refer to Fig.14 , the semiconductor package may further include a connection structure CS between the first dielectric structure IS1 and the bump connection pad 11. The connection structure CS may be disposed between the bump BP and the first dielectric structure IS1. The width of the connection structure CS in the first direction D1 may be the same as the width of the first dielectric structure IS1 in the first direction D1. The width of the connection structure CS in the second direction D2 may be the same as the width of the first dielectric structure IS1 in the second direction D2.

[0129] The connection structure CS may include a connection dielectric layer CI and a connection conductive structure CC. The top surface of the connection dielectric layer CI may be in contact with the bottom surface of the first dielectric structure IS1. The bottom surface of the key pattern KP may be in contact with the top surface of the connection dielectric layer CI. The bottom surface of the connection dielectric layer CI may be in contact with the top surface of the bump connection pad 11. In some embodiments, unlike shown, at least one of the bump connection pads 11 may be disposed in the connection dielectric layer CI. The connection dielectric layer CI may include a dielectric material. For example, the connection dielectric layer CI may include silicon oxide. In some embodiments, the connection dielectric layer CI may be a multilayer including a plurality of dielectric layers.

[0130] The connecting conductive structure CC may be disposed in the connecting dielectric layer CI. The connecting conductive structure CC may be surrounded by the connecting dielectric layer CI. One of the connecting conductive structures CC may electrically connect the bump connection pad 11 to the first pad PA1. Another of the connecting conductive structures CC may electrically connect the bump connection pad 11 to the dummy pad DP. The connecting conductive structure CC may include, for example, at least one of a conductive pad, a conductive via, and a wire.

[0131] Fig.15 An enlarged cross-sectional view of a semiconductor package according to some embodiments is shown. In addition to the following description, Fig.15 The semiconductor package can be Figure 1A and Figure 1B The semiconductor packages are the same or substantially the same.

[0132] refer to Fig.15 , the semiconductor package may further include a connection structure CSc between the first dielectric structure IS1 and the bump connection pad 11. The connection structure CSc may be a redistribution substrate including a redistribution dielectric layer RI and a redistribution pattern RP.

[0133] The redistribution dielectric layer RI may be stacked along the third direction D3. The redistribution dielectric layer RI may include a photoimageable dielectric material. The photoimageable dielectric material may include, for example, at least one selected from photosensitive polyimide, polybenzoxazole, phenolic polymer, and benzocyclobutene polymer.

[0134] The redistribution pattern RP may be disposed in the redistribution dielectric layer RI. The redistribution pattern RP may be surrounded by the redistribution dielectric layer RI. One of the redistribution patterns RP may electrically connect the bump connection pad 11 to the first pad PA1. Another of the redistribution patterns RP may electrically connect the bump connection pad 11 to the dummy pad DP. The redistribution pattern RP may include a conductive material. The redistribution pattern RP may include a via portion extending in a vertical direction and a line portion extending in a horizontal direction.

[0135] Fig.16 FIG. 2 shows a plan view showing a plan structure of a semiconductor package according to some embodiments. In addition to the following description, Fig.16 The semiconductor package can be similar to Figure 1A and Figure 1B semiconductor packaging.

[0136] refer to Fig.16, when viewed in a plan view, the first pad PA1d and the dummy pad DPd may each have a circular shape. When viewed in a plan view, the first surface of the first portion included in the first conductive layer of the first pad PA1d may have a circular shape, and similarly, when viewed in a plan view, the first surface of the first portion included in the first dummy layer of the dummy pad DPd may have a circular shape. When viewed in a plan view, the key pattern KPd may have a shape different from that of the first pad PA1d and the dummy pad DPd. When viewed in a plan view, the key pattern KPd may have a quadrilateral shape. When viewed in a plan view, the first surface of the first portion included in the first pattern layer of the key pattern KPd may have a quadrilateral shape.

[0137] In some embodiments, the first pad PA1d and the dummy pad DPd may each have an elliptical shape or a polygonal shape when viewed in a plan view.

[0138] The first pad PA1d and the dummy pad DPd may have a planar size smaller than the planar size of the key pattern KPd. For example, a maximum width W11 of the first pad PA1d in the first direction D1 and a maximum width W12 of the dummy pad DPd in ​​the first direction D1 may be smaller than a maximum width W13 of the key pattern KPd in ​​the first direction D1, and a maximum width W14 of the first pad PA1d in the second direction D2 and a maximum width W15 of the dummy pad DPd in ​​the second direction D2 may be smaller than a maximum width W16 of the key pattern KPd in ​​the second direction D2.

[0139] Fig.17 FIG. 2 shows a plan view showing a plan structure of a semiconductor package according to some embodiments. In addition to the following description, Fig.17 The semiconductor package can be Figure 1A and Figure 1B The semiconductor packages are the same or substantially the same.

[0140] refer to Fig.17 , when viewed in a plan view, the first pad PA1e and the dummy pad DPe may each have a quadrilateral shape. When viewed in a plan view, the key pattern KPe may have a shape different from that of the first pad PA1e and the dummy pad DPe. When viewed in a plan view, the key pattern KPe may have a cross shape.

[0141] In a semiconductor package according to some embodiments of the inventive concept, a key pattern and a pad bonded with a semiconductor chip may be simultaneously formed to simplify a manufacturing process of the semiconductor package.

[0142] Although the embodiments of the present disclosure have been described in conjunction with some embodiments of the inventive concept shown in the drawings, it will be understood by those skilled in the art that changes in form and detail may be made therein without departing from the spirit and essential features of the inventive concept. Therefore, the embodiments disclosed above should be considered illustrative rather than restrictive.

Claims

1. A semiconductor package, comprising: a first dielectric structure; a first pad in the first dielectric structure; A first semiconductor chip, disposed on the first dielectric structure; as well as bump, electrically connected to the first pad, Wherein, the first semiconductor chip comprises: a first substrate; a first chip dielectric layer in contact with the first dielectric structure; and a first chip pad in contact with a top surface of the first pad, Wherein, the first pad is arranged between the bump and the first chip pad of the first semiconductor chip, The first pad includes a first conductive layer and a second conductive layer covered by the first conductive layer, and The bump is positioned closer to the first conductive layer than to the second conductive layer.

2. The semiconductor package according to claim 1, wherein The conductive material of the first conductive layer is different from the conductive material of the second conductive layer.

3. The semiconductor package according to claim 1, wherein: The first conductive layer comprises: a first portion in contact with a bottom surface of the second conductive layer; and a second portion in contact with the first chip pad of the first semiconductor chip, Wherein, the second portion covers the second conductive layer.

4. The semiconductor package according to claim 3, wherein: The first portion of the first conductive layer is between the bump and the second conductive layer.

5. The semiconductor package according to claim 3, wherein: An inner sidewall of the second portion of the first conductive layer contacts an outer sidewall of the second conductive layer.

6. The semiconductor package according to claim 1, wherein The first dielectric structure includes a first dielectric layer and a second dielectric layer on the first dielectric layer, wherein the second dielectric layer contacts the first chip dielectric layer of the first semiconductor chip, and The first dielectric layer and the second dielectric layer include dielectric materials different from each other.

7. The semiconductor package according to claim 6, wherein: The first dielectric layer includes silicon oxide, and The second dielectric layer includes silicon nitride, silicon carbonitride or silicon oxynitride carbide.

8. The semiconductor package according to claim 7, wherein: The dielectric material included in the first chip dielectric layer is the same as the dielectric material of the second dielectric layer.

9. The semiconductor package according to claim 1, further comprising: a second dielectric structure spanning the first semiconductor chip and spaced apart from the first dielectric structure; a second pad in the second dielectric structure; as well as a gap-filling layer between the first dielectric structure and the second dielectric structure, The first semiconductor chip includes a through hole, and the through hole electrically connects the second pad and the first semiconductor chip to each other.

10. The semiconductor package according to claim 9, further comprising a second semiconductor chip in contact with the second dielectric structure, in, The second semiconductor chip comprises: a second substrate; a second chip dielectric layer in contact with the second dielectric structure; and The second chip bonding pad contacts the second bonding pad.

11. A semiconductor package, comprising: a first dielectric structure; a first pad in the first dielectric structure; A first semiconductor chip, disposed on the first dielectric structure; as well as bump, electrically connected to the first pad, Wherein, the first semiconductor chip comprises: a first substrate; a first chip dielectric layer in contact with the first dielectric structure; and a first chip pad in contact with a top surface of the first pad, The first pad includes a first conductive layer and a second conductive layer covered by the first conductive layer. wherein the first conductive layer comprises a top surface and a bottom surface opposite to each other, wherein the top surface of the first conductive layer contacts the first chip pad of the first semiconductor chip, and The area of ​​the bottom surface of the first conductive layer is greater than the area of ​​the top surface of the first conductive layer.

12. The semiconductor package according to claim 11, wherein The top surface of the first conductive layer has a ring shape when viewed in a plan view.

13. The semiconductor package according to claim 11, wherein The first conductive layer includes at least one selected from tantalum nitride, tantalum, titanium nitride and titanium, and The second conductive layer includes copper.

14. The semiconductor package according to claim 11, wherein The second conductive layer includes a top surface in contact with the first chip pad, The area of ​​the top surface of the second conductive layer is greater than the area of ​​the top surface of the first conductive layer.

15. The semiconductor package according to claim 11, wherein The width of the first chip pad is greater than the width of the first pad.

16. The semiconductor package according to claim 11, further comprising: a plurality of alignment keys in the first dielectric structure, Wherein, the first pad is between the alignment keys.

17. The semiconductor package according to claim 16, wherein: The alignment key comprises a first pattern layer and a second pattern layer covered by the first pattern layer, Wherein, the first pattern layer comprises: a first portion in contact with a bottom surface of the second pattern layer; and The second portion contacts the outer side wall of the second pattern layer.

18. The semiconductor package according to claim 16, further comprising: a gap-filling layer, the gap-filling layer covering the first semiconductor chip, Wherein, the alignment key contacts the gap filling layer.

19. A semiconductor package, comprising: a first dielectric structure; a first pad and a plurality of key patterns in the first dielectric structure; a first semiconductor chip in contact with the first dielectric structure; a bump electrically connected to the first pad; a second dielectric structure spanning the first semiconductor chip and spaced apart from the first dielectric structure; a first gap-filling layer between the first dielectric structure and the second dielectric structure; a second semiconductor chip in contact with the second dielectric structure; as well as a second gap-filling layer surrounding the second semiconductor chip, The first pad includes a first conductive layer and a second conductive layer located in the first conductive layer. Wherein, the first conductive layer comprises: A first portion between the bump and the second conductive layer; and a second portion, surrounding the second conductive layer, wherein the first portion of the first conductive layer includes a surface in contact with a bottom surface of the second conductive layer, and Wherein a top surface of the second portion of the first conductive layer and a top surface of the second conductive layer are in contact with the first chip pad.

20. The semiconductor package according to claim 19, wherein A top surface of the key pattern contacts a bottom surface of the first gap-filling layer.

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