Wideband amplifier with low balun error, high linearity and low noise

Abstract

The invention discloses a broadband amplifier with low balun error, high linearity and low noise. The broadband amplifier comprises an input end, a common-source amplifier, a differential current balancer, an OTA, a load circuit and an enhanced source follower, an input signal enters from a P1 port and enters the first common source stage amplifier, one path of signal enters the differential current balancer, and the other path of signal enters the second common source stage amplifier and enters the differential current balancer; the two paths of signals are transmitted to ports P5 and P6 to output differential signals; the OTA adjusts the high-order nonlinearity of gds by detecting common-mode levels of P5 and P6 and feeding back a bias level of a control load circuit, compensates offset residues of distortion components of a source follower and a main common-source amplifier, realizes high linearity, and reduces Balun errors through a triple Balun error correction technology. According to the invention, the working frequency range is 0.2 GHz to 6GHz, and the low-Balun error, high-linearity and low-noise performances are realized.

Description

Technical Field

[0001] The present invention relates to the technical field of radio frequency integrated circuits, and in particular to a broadband amplifier with low balun error, high linearity and low noise. Background Art

[0002] With the rapid development of 5G technology, broadband solutions are increasingly seen as both economical and efficient, providing high data transmission rates while saving hardware budgets. Compared with the bulky passive balun transformer structure, the integrated balun low noise amplifier (LNA) is favored for its compact structure and no insertion loss. However, the gain and phase errors of the balun low noise amplifier will adversely affect the IP2 of the subsequent mixer, ultimately reducing the signal-to-noise ratio of the receiver. On the other hand, improving linearity performance is increasingly important for the spectral coexistence of multiple wireless protocols and multiple input / output (MIMO) applications involving analog / digital beamforming. The coexistence and concurrent use of these multiple protocols will inevitably cause interference to the broadband system of 5G communications. Therefore, for the 5G communication band, it has become particularly commercially valuable and technically significant to provide a low-noise amplifier with low balun error and high linearity.

[0003] In the past, traditional balun low noise amplifier technology was mostly implemented using the common source and common gate classic structure. The Chinese patent (CN104065346A) discloses a wide-band low noise amplifier circuit based on cross-coupled feedback, including a CG input stage, a CS input stage and a resistive load stage. The CG input stage includes an NMOS tube M2, and the CS input stage includes an NMOS tube M 1，4 ; By utilizing the feed-forward effect of the CS input stage, the span of the CG input stage is improved, reducing power consumption. The current multiplexing technology of the CS input stage also saves power consumption. This allows the amplifier to achieve low noise index while maintaining low power consumption; however, the asymmetric device size on the CG-CS two paths causes the signal to experience significantly different delays, resulting in a large phase error. Even if the g of the devices on the CG-CS two paths can be adjusted m and R L Good amplitude error control is obtained, so the overall balun error still cannot reach the error range and level of the traditional passive transformer balun; it is also noted that in the above technology, the linearity of the circuit is poor and cannot meet the high linearity requirements of the current broadband system of 5G communication.

[0004] As mentioned above, the existing balun low noise amplifier has poor linearity and high balun error, and cannot meet the requirements of high linearity and low balun error of today's 5G communication broadband system. To this end, the present application provides a low balun error, high linearity low noise broadband amplifier, which has the advantages of low balun error and high linearity. Summary of the invention

[0005] The present invention discloses a low balun error, high linearity and low noise broadband amplifier, comprising: an input end, a common source amplifier, a differential current balancer, an OTA, a load circuit and an enhanced source follower;

[0006] The input terminal includes a resistor R s , port P1, capacitor C0, inductor L0, resistor R f and capacitor C f ;

[0007] The common-source amplifier comprises a first common-source amplifier and a second common-source amplifier, and the first common-source amplifier and the second common-source amplifier have the same structure; ports A and B are arranged on both sides of the first common-source amplifier; ports C and M are arranged on both sides of the second common-source amplifier; and a node X is arranged between the first common-source amplifier and the second common-source amplifier;

[0008] Ports D and E and ports F and G are arranged on both sides of the differential current balancer; a node Y is arranged between port E of the differential current balancer and port M of the second common source amplifier;

[0009] Ports P2, P3 and P4 are set on both sides of the OTA; the port P4 is connected to the port P5 and the port P6 respectively; an R is set between the port P4 and the port P5 L，cm , R is set between the port P4 and the port P6 L，cm1 ; A node Z is set between the port P6 and the differential current balancer port G;

[0010] Ports T and V are provided on both sides of the load circuit;

[0011] Ports H, J and K are provided on both sides of the enhanced source follower;

[0012] The input resistance R s One end receives the input signal V s , the other end is connected to one end of capacitor C0 and connected to port P1; the other end of capacitor C0 is grounded; the input resistor R f One end of the capacitor C f One end is connected to port P1, and the other end is connected to capacitor C f The other end of the input inductor L0 is connected to the H end of the enhanced source follower; one end of the input inductor L0 is connected to the port P1, and the other end is connected to the A end of the first common source amplifier;

[0013] The J terminal of the enhanced source follower is connected to the port P5 of the OTA, the K terminal of the enhanced source follower is connected to the node Z, and the node Z is connected to another output port P6;

[0014] The B terminal of the first common-source amplifier is connected to the node X, the C terminal of the second common-source amplifier is connected to the node X, and the M terminal of the second common-source amplifier is connected to the node Y;

[0015] The D terminal of the differential current balancer is connected to the node X, the E terminal of the differential current balancer is connected to the node Y, the F terminal of the differential current balancer is connected to the output port P5, and the G terminal of the differential current balancer is connected to the node Z;

[0016] The resistor R L，cm One end of the resistor R is connected to the port P5, and the other end is connected to the port P4 of the OTA; L，cm1 One end is connected to port P6, and the other end is connected to port P4 of OTA; port P3 of OTA is connected to power supply voltage V ref , the port P2 is connected to the load circuit;

[0017] The T end of the load circuit is connected to the output port P5, and the V end of the load circuit is connected to another output port P6;

[0018] The input signal V s It comes in from the P1 port, enters the first common-source amplifier through port A, and is transmitted through port B. One signal is transmitted to port D and enters the differential current balancer. The other signal enters the second common-source amplifier through port C, and is transmitted to port E through node Y and enters the differential current balancer. It is transmitted to ports P5 and P6 through ports F and G of the differential current balancer, and then transmitted to port P4 through ports P5 and P6 to enter the OTA. It is transmitted to the load circuit through port P2, and is transmitted through ports T and V of the load circuit, and outputs V through ports P5 and P6. O signal; output V O The signal enters the enhanced source follower through the J and K ports, and reaches the P1 port through the H port of the enhanced source follower to form feedback.

[0019] Preferably, the common source amplifier comprises: an NMOS tube M n1 、NMOS tube M n2 、PMOS tube M p1 、PMOS tube M p2 , capacitor C1, capacitor C2, resistor R1, resistor R2;

[0020] One end of the capacitor C1 is connected to one end of the capacitor C2 and connected to the port A / C. The other end of the capacitor C1 is connected to one end of the resistor R1 and the PMOS transistor M. p1～2 The other end of the resistor R1 is connected to the power supply voltage V b1 , the PMOS tube M p1～2The source terminal is connected to the power supply voltage 1.2V, and the PMOS tube M p1～2 The drain terminal and NMOS tube M n1～2 The drain end is connected to port B / M, and the NMOS tube M n1～2 The source end is grounded, the other end of the capacitor C2 is connected to one end of the resistor R2 and the NMOS tube M n1～2 The other end of the resistor R2 is connected to the power supply voltage V b0 .

[0021] Preferably, the differential current balancer includes: an NMOS tube M3, an NMOS tube M4, a capacitor C6, a capacitor C7, a resistor R6, and a resistor R7;

[0022] One end of the capacitor C6 is connected to the gate end of the NMOS tube M3 and one end of the resistor R6, the other end of the capacitor C6 is connected to the source end of the NMOS tube M4, and the other end of the resistor R6 is connected to one end of the resistor R7 and connected to the power supply voltage V b2 The other end of the resistor R7 is connected to one end of the capacitor C7 and the gate end of the NMOS tube M4, the other end of the capacitor C7 is connected to the source end of the NMOS tube M3, the drain end of the NMOS tube M3 is connected to the port F, the source end of the NMOS tube M3 is connected to the port D, the drain end of the NMOS tube M4 is connected to the port G, and the source end of the NMOS tube M4 is connected to the port E.

[0023] Preferably, the OTA includes: NMOS tube M0, NMOS tube M1, NMOS tube M2, NMOS tube M6, PMOS tube M3, PMOS tube M4, PMOS tube M5, capacitor C L，cm , capacitor C m , capacitor C z , capacitor C L , resistor R m , resistor R z ;

[0024] The capacitor C L，cm One end of the capacitor C is connected to the gate end of the NMOS tube M1 and connected to the port P4. L，cm The other end is grounded, the source end of the NMOS tube M1 is connected to the drain end of the NMOS tube M0 and the source end of the NMOS tube M2, the drain end of the NMOS tube M1 is connected to the drain end of the PMOS tube M3 and the gate end of the PMOS tube M3, the source end of the PMOS tube M3 is connected to the power supply voltage 1.2V, the gate end of the PMOS tube M3 is connected to the gate end of the PMOS tube M4, the source end of the PMOS tube M4 is connected to the power supply voltage 1.2V, the drain end of the PMOS tube M4 is connected to the gate end of the PMOS tube M5 and the drain end of the NMOS tube M2, and the gate end of the NMOS tube M2 is connected to the power supply voltage V ref , the gate terminal of the NMOS tube M0 is connected to the power supply voltage Vb0，ota The source end of the NMOS tube M0 is grounded, the source end of the PMOS tube M5 is connected to the power supply voltage 1.2V, and the resistor R m One end of the resistor R is connected to the gate end of the PMOS tube M5. m The other end of the capacitor C m One end of the capacitor C m The other end is connected to the drain end of the PMOS tube M5 and the drain end of the NMOS tube M6. L One end of the capacitor C is connected to the drain end of the PMOS tube M5 and the drain end of the NMOS tube M6, and is connected to the port P2. L The other end of the capacitor C z One end of the capacitor C is connected to the drain end of the PMOS tube M5 and the drain end of the NMOS tube M6. z The other end of the resistor R z One end of the resistor R is connected to the gate end of the NMOS tube M6. z The other end is connected to the power supply voltage V b1，ota , the source end of the NMOS tube M6 is grounded.

[0025] Preferably, the load circuit includes: a PMOS tube M7, a PMOS tube M8, a resistor R5, a capacitor C L，cmp , capacitor C R，cmp ;

[0026] The capacitor C L，cmp One end of the capacitor C is connected to the source end of the PMOS tube M7, the source end of the PMOS tube M7 is connected to the power supply voltage 1.2V, and the capacitor C L，cmp The other end of the resistor R5 is connected to the drain end of the PMOS tube M7 and connected to the port T. The gate end of the PMOS tube M7 is connected to the gate end of the PMOS tube M8 and connected to the port P2. One end of the resistor R5 is connected to the capacitor C R，cmp The other end of the resistor R5 is connected to the drain end of the PMOS tube M8 and connected to the port V. The capacitor C R，cmp The other end is connected to the source end of the PMOS tube M8, and the source end of the PMOS tube M8 is connected to the power supply voltage 1.2V.

[0027] Preferably, the enhanced source follower includes: NMOS tube M5, NMOS tube M7, capacitor C3, capacitor C4, resistor R3, resistor R4;

[0028] One end of the capacitor C3 is connected to port J and serves as an output port V o+ The other end of the capacitor C3 is connected to one end of the resistor R3 and the gate end of the NMOS tube M5, and the other end of the resistor R3 is connected to the power supply voltage V b4The drain end of the NMOS tube M5 is connected to the power supply voltage 1.2V, the source end of the NMOS tube M5 is connected to the drain end of the NMOS tube M7 and connected to the port H, the source end of the NMOS tube M7 is grounded, one end of the capacitor C4 is connected to the port K and serves as another output port V o- The other end of the capacitor C4 is connected to one end of the resistor R4 and the gate end of the NMOS tube M7, and the other end of the resistor R4 is connected to the power supply voltage V b3 .

[0029] Compared with the prior art, the technical solution of this application has the following technical effects:

[0030] The present invention uses triple balun error correction technology to obtain low balun error, and sets a reasonable differential current balancer M 3～4 The size is preset with a non-unit gain Vy / Vx ratio, which reduces the impact of the asymmetric load resistance at the circuit output port on the gain balance and alleviates the gain amplitude error. Through the current differential balancer, Vy / Vx is transmitted as a forward signal and its amplitude phase error is further corrected. At the circuit output load, an additional capacitor C L，cmp , capacitor C R，cmp , resistor R R，cmp Components to compensate for the high-frequency phase error caused by the different parasitic delays of the X / Y paths.

[0031] The present invention utilizes a source follower to implicitly eliminate the distortion component of the main transistor, thereby effectively improving the linearity of the low noise amplifier.

[0032] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application so that it can be implemented in accordance with the contents of the specification, and to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the following is a detailed description of the preferred embodiments of the present application in conjunction with the accompanying drawings as follows.

[0033] Based on the detailed description of the specific embodiments of the present application in combination with the accompanying drawings below, those skilled in the art will become more aware of the above and other objects, advantages and features of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can also be obtained based on these drawings without creative work. In all drawings, similar elements or parts are generally identified by similar reference numerals. In the drawings, each element or part is not necessarily drawn according to the actual scale.

[0035] Figure 1 is a structural diagram of the present invention;

[0036] Figure 2 It is a schematic diagram of the first and second common source amplifier circuits of the present invention;

[0037] Figure 3 is a schematic diagram of a differential current balancer circuit of the present invention;

[0038] Figure 4 It is a schematic diagram of an OTA circuit of the present invention;

[0039] Figure 5 is a schematic diagram of a load circuit of the present invention;

[0040] Figure 6 It is a schematic diagram of an enhanced source follower circuit of the present invention;

[0041] Figure 7 For an enhanced source follower, V i Convert to I sf Equivalent circuit diagram;

[0042] Figure 8 This is a schematic diagram of a circuit for analyzing a distortion source according to the present invention;

[0043] Fig. 9 The OTA of the present invention generates an unbalanced noise voltage V no+ / - Circuit diagram;

[0044] Fig.10 Z of the present invention L，cl , Z R，cl , Z L，ol , Z R，ol Impedance value graph;

[0045] Fig.11 is a gain error diagram of the present invention;

[0046] Fig.12 is a phase error diagram of the present invention;

[0047] Fig.13 It is a simulated NF diagram under different capacitor configurations inside the CMFB of the present invention;

[0048] Fig.14 is a third-order distortion diagram of the present invention;

[0049] Fig.15 This is the S11, gain, NF, and IIP3 result diagram of the present invention. DETAILED DESCRIPTION

[0050] To make the purpose, technical scheme and advantages of the embodiment of the present application clearer, the technical scheme in the embodiment of the present application will be clearly and completely described below in conjunction with the accompanying drawings in the embodiment of the present application. Obviously, the described embodiment is a part of the embodiment of the present application, rather than all of the embodiments. In the following description, specific details such as specific configuration and components are provided only to help fully understand the embodiments of the present application. Therefore, it should be clear to those skilled in the art that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the present application. In addition, for clarity and brevity, the description of known functions and structures is omitted in the embodiment.

[0051] It should be understood that the references to "one embodiment" or "this embodiment" throughout the specification mean that the specific features, structures, or characteristics associated with the embodiment are included in at least one embodiment of the present application. Therefore, the references to "one embodiment" or "this embodiment" appearing throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0052] In addition, the present application may repeat reference numerals and / or letters in different examples. This repetition is for the purpose of simplicity and clarity, and does not in itself indicate the relationship between the various embodiments and / or settings discussed.

[0053] The term "and / or" in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, B exists alone, and A and B exist at the same time. The term " / and" in this article describes another type of association object relationship, indicating that there can be two relationships. For example, A / and B can mean: A exists alone, and A and B exist alone. In addition, the character " / " in this article generally indicates that the previous and next associated objects are in an "or" relationship.

[0054] The term "at least one" in this article is merely a description of the association relationship of associated objects, indicating that there may be three relationships. For example, at least one of A and B can mean: A exists alone, A and B exist at the same time, and B exists alone.

[0055] It should also be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusions.

[0056] Example 1

[0057] This embodiment mainly describes a low balun error, high linearity, low noise broadband amplifier, such as Figure 1 As shown, it includes: an input end, a common source stage amplifier, a differential current balancer, an OTA, a load circuit and an enhanced source follower;

[0058] The input terminal includes a resistor R s , port P1, capacitor C0, inductor L0, resistor R f and capacitor C f ;

[0059] The common source amplifier includes a first common source amplifier and a second common source amplifier, and the first common source amplifier and the second common source amplifier have the same structure; ports A and B are arranged on both sides of the first common source amplifier; ports C and M are arranged on both sides of the second common source amplifier; and a node X is arranged between the first common source amplifier and the second common source amplifier;

[0060] Ports D and E and ports F and G are provided on both sides of the differential current balancer; a node Y is provided between port E of the differential current balancer and port M of the second common source amplifier;

[0061] Ports P2, P3 and P4 are set on both sides of the OTA; port P4 is connected to port P5 and port P6 respectively; R is set between port P4 and port P5 L，cm , set R between port P4 and port P6 L，cm1 ; A node Z is set between port P6 and the differential current balancer port G;

[0062] Ports T and V are provided on both sides of the load circuit;

[0063] Ports H, J, and K are provided on both sides of the enhanced source follower;

[0064] Input resistance R s One end receives the input signal V s , the other end is connected to one end of capacitor C0 and connected to port P1; the other end of capacitor C0 is grounded; the input resistor R f One end of the capacitor C f One end is connected to port P1, and the other end is connected to capacitor C f The other end of the input inductor L0 is connected to the H end of the enhanced source follower; one end of the input inductor L0 is connected to the port P1, and the other end is connected to the A end of the first common source amplifier;

[0065] The J terminal of the enhanced source follower is connected to the port P5 of the OTA, the K terminal of the enhanced source follower is connected to the node Z, and the node Z is connected to another output port P6;

[0066] The B terminal of the first common-source amplifier is connected to the node X, the C terminal of the second common-source amplifier is connected to the node X, and the M terminal of the second common-source amplifier is connected to the node Y;

[0067] The D terminal of the differential current balancer is connected to the node X, the E terminal of the differential current balancer is connected to the node Y, the F terminal of the differential current balancer is connected to the output port P5, and the G terminal of the differential current balancer is connected to the node Z;

[0068] Resistor R L，cm One end of the resistor is connected to port P5, and the other end is connected to port P4 of the OTA; L，cm1 One end is connected to port P6, and the other end is connected to port P4 of OTA; port P3 of OTA is connected to power supply voltage V ref , port P2 is connected to the load circuit;

[0069] The T end of the load circuit is connected to the output port P5, and the V end of the load circuit is connected to another output port P6;

[0070] Input signal V s It comes in from the P1 port, enters the first common-source amplifier through port A, and is transmitted through port B. One signal is transmitted to port D and enters the differential current balancer. The other signal enters the second common-source amplifier through port C, and is transmitted to port E through node Y and enters the differential current balancer. It is transmitted to ports P5 and P6 through ports F and G of the differential current balancer, and then transmitted to port P4 through ports P5 and P6 to enter the OTA. It is transmitted to the load circuit through port P2, and is transmitted through ports T and V of the load circuit, and outputs V through ports P5 and P6. O signal; output V O The signal enters the enhanced source follower through the J and K ports, and reaches the P1 port through the H port of the enhanced source follower to form feedback.

[0071] Further, if Figure 2 As shown, the common source amplifier includes: NMOS tube M n1 、NMOS tube M n2 、PMOS tube M p1 、PMOS tube M p2 , capacitor C1, capacitor C2, resistor R1, resistor R2;

[0072] One end of capacitor C1 is connected to one end of capacitor C2 and connected to port A / C. The other end of capacitor C1 is connected to one end of resistor R1 and PMOS tube M. p1～2 The gate terminal is connected, and the other end of the resistor R1 is connected to the power supply voltage V b1 , PMOS tube M p1～2 The source terminal is connected to the power supply voltage of 1.2V, and the PMOS tube M p1～2The drain terminal and NMOS tube M n1～2 The drain end is connected to port B / M, NMOS tube M n1～2 The source end is grounded, and the other end of capacitor C2 is connected to one end of resistor R2 and NMOS tube M n1～2 The gate terminal is connected, and the other end of resistor R2 is connected to the power supply voltage V b0 .

[0073] Further, if Figure 3 As shown, the differential current balancer includes: NMOS tube M3, NMOS tube M4, capacitor C6, capacitor C7, resistor R6, resistor R7;

[0074] One end of capacitor C6 is connected to the gate end of NMOS tube M3 and one end of resistor R6, the other end of capacitor C6 is connected to the source end of NMOS tube M4, the other end of resistor R6 is connected to one end of resistor R7, and connected to the power supply voltage V b2 The other end of the resistor R7 is connected to one end of the capacitor C7 and the gate end of the NMOS tube M4, the other end of the capacitor C7 is connected to the source end of the NMOS tube M3, the drain end of the NMOS tube M3 is connected to the port F, the source end of the NMOS tube M3 is connected to the port D, the drain end of the NMOS tube M4 is connected to the port G, and the source end of the NMOS tube M4 is connected to the port E.

[0075] Further, if Figure 4 As shown, OTA includes: NMOS tube M0, NMOS tube M1, NMOS tube M2, NMOS tube M6, PMOS tube M3, PMOS tube M4, PMOS tube M5, capacitor C L，cm , capacitor C m , capacitor C z , capacitor C L , resistor R m , resistor R z ;

[0076] Capacitor C L，cm One end is connected to the gate end of NMOS tube M1 and connected to port P4. Capacitor C L，cm The other end is grounded, the source end of NMOS tube M1 is connected to the drain end of NMOS tube M0 and the source end of NMOS tube M2, the drain end of NMOS tube M1 is connected to the drain end of PMOS tube M3 and the gate end of PMOS tube M3, the source end of PMOS tube M3 is connected to the power supply voltage 1.2V, the gate end of PMOS tube M3 is connected to the gate end of PMOS tube M4, the source end of PMOS tube M4 is connected to the power supply voltage 1.2V, the drain end of PMOS tube M4 is connected to the gate end of PMOS tube M5 and the drain end of NMOS tube M2, and the gate end of NMOS tube M2 is connected to the power supply voltage V ref , the gate terminal of NMOS tube M0 is connected to the power supply voltage V b0，ota , the source end of NMOS tube M0 is grounded, the source end of PMOS tube M5 is connected to the power supply voltage 1.2V, and the resistor Rm One end is connected to the gate end of PMOS tube M5, and the resistor R m The other end of the capacitor C m One end of the capacitor C m The other end is connected to the drain end of the PMOS tube M5 and the drain end of the NMOS tube M6, and the capacitor C L One end is connected to the drain end of the PMOS tube M5 and the drain end of the NMOS tube M6, and is connected to the port P2. The capacitor C L The other end of the capacitor C z One end of the capacitor is connected to the drain end of the PMOS tube M5 and the drain end of the NMOS tube M6, and the capacitor C z The other end of the resistor R z One end is connected to the gate end of NMOS tube M6, and the resistor R z The other end is connected to the power supply voltage V b1，ota , the source end of NMOS tube M6 is grounded.

[0077] Further, if Figure 5 As shown, the load circuit includes: PMOS tube M7, PMOS tube M8, resistor R5, capacitor C L，cmp , capacitor C R，cmp ;

[0078] Capacitor C L，cmp One end of the capacitor is connected to the source end of the PMOS tube M7, the source end of the PMOS tube M7 is connected to the power supply voltage 1.2V, and the capacitor C L，cmp The other end is connected to the drain end of the PMOS tube M7 and connected to port T. The gate end of the PMOS tube M7 is connected to the gate end of the PMOS tube M8 and connected to port P2. One end of the resistor R5 is connected to the capacitor C R，cmp The other end of the resistor R5 is connected to the drain end of the PMOS tube M8 and connected to the port V. The capacitor C R，cmp The other end is connected to the source end of the PMOS tube M8, and the source end of the PMOS tube M8 is connected to the power supply voltage 1.2V.

[0079] Further, if Figure 6 As shown, the enhanced source follower includes: NMOS tube M5, NMOS tube M7, capacitor C3, capacitor C4, resistor R3, resistor R4;

[0080] One end of capacitor C3 is connected to port J and serves as an output port V o+ The other end of capacitor C3 is connected to one end of resistor R3 and the gate end of NMOS tube M5, and the other end of resistor R3 is connected to the power supply voltage V b4 , the drain of NMOS tube M5 is connected to the power supply voltage 1.2V, the source of NMOS tube M5 is connected to the drain of NMOS tube M7 and connected to port H, the source of NMOS tube M7 is grounded, one end of capacitor C4 is connected to port K and serves as another output port Vo- The other end of capacitor C4 is connected to one end of resistor R4 and the gate end of NMOS tube M7, and the other end of resistor R4 is connected to the power supply voltage V b3 .

[0081] This embodiment shows that the CMOS integrated passive mixer has significant advantages of miniaturization and high integration, making it more ideal for broadband system applications in the new 5G communication FR3 band. CMOS technology is highly compatible with digital circuits, which facilitates the logical control of multi-phase digital clocks, reduces manufacturing costs, and enhances market competitiveness. The performance advantages of ultra-wideband and ultra-high linearity enable the CMOS integrated passive mixer to be adjusted according to different application requirements and adapt to various frequency communication requirements.

[0082] Example 2

[0083] This embodiment is based on Embodiment 1 and describes in detail an optimization scheme of a low balun error, high linearity, low noise broadband amplifier, which specifically includes:

[0084] like Figure 1 As shown, in the circuit of the present application, since the output impedance at both ends of the output terminal is asymmetric, the balance of the balun will be destroyed. By adding a feedback loop, the difference in the output impedance at both ends can be significantly reduced. Specifically, as Fig.10 The simulation results shown in the figure show that the impedance Z at both ends of the closed loop at 1GHz L，cl and Z R，cl are 175Ω and 135Ω respectively, and the impedance Z at both ends of the open loop L，ol and Z R，ol 238Ω and 166Ω respectively, feedback is used to output the resistance Z L，cl and Z R，cl Become more balanced, mitigate gain error;

[0085] The present invention designs a triple balun error correction to obtain a low balun error, and sets a reasonable differential current balancer NMOS tube M 3～4 size, preset non-unity gain Vy / Vx ratio, such as Figure 1 As shown, the effect of the asymmetric load resistance at the circuit output port on the gain balance is reduced, thereby alleviating the gain amplitude error; as shown Figure 3 As shown in the figure, the Vy / Vx signal is cross-coupled by the current differential balancer to further correct the error of the Vy / Vx amplitude phase and transmit it to the load direction. When the input signal passes through the first and second common source amplifiers in sequence, two signal paths X / Y are generated. Due to the different distribution of parasitic capacitance of the two paths, the signal phases obtained by the two paths X / Y are delayed differently at high frequencies. In order to overcome the above problem, an additional capacitor C is added at the output load of the circuit. L，cmp , capacitor CR，cmp , resistor R R，cmp Components are used to compensate for the high-frequency phase error caused by the different parasitic delays of the X / Y paths; as mentioned above, by presetting a certain proportion of V y / V x The triple correction of balun, current balancer and high frequency delay compensation ensures the balance of the overall output and achieves low balun error.

[0086] like Fig.11 The figure shows the simulation results of gain error at frequencies between 0.1 and 10 GHz. It can be seen that the gain error is less than 0.5 dB.

[0087] like Fig.12 The simulation results of phase error at frequencies between 0.1 and 10 GHz are given, and it can be seen that the simulated value of phase error is less than 0.5 degrees.

[0088] The function of the source follower is to provide the low impedance required for matching the input port of the main amplifier after feedback. The following analysis shows that its nonlinearity can also be used to eliminate the distortion component of the main transistor. Previous studies often ignored the source follower, which is called implicit distortion elimination here;

[0089] The schematic diagram of the equivalent principle of the enhanced source follower of the present invention is as follows: Figure 7 As shown, it can be equivalent to a device to analyze the input voltage V i Converted to output current i sf Specifically, the current i sf Voltage V i The relationship is: Among them G sf is the first-order linear coefficient, G sf ′ is the second-order linear coefficient, G sf ″ is the third-order linear coefficient. The simulation shows that the second-order linear coefficient and the third-order linear coefficient are negative. When driving a small load, the nonlinearity is more significant, such as Fig.14 shown.

[0090] Figure 8 The simplified circuit diagram of the analysis distortion source is shown. The DCB as a current buffer does not produce additional distortion and can be ignored in the analysis. As a result, its input-output relationship and third-order distortion term are shown in the following formula:

[0091] V o =C1V s +C2V s 2 +C3V s 3 (1)

[0092]

[0093]

[0094] pass Fig.14 The simulation results show that G sf ” is a negative number, and the two terms in the numerator of C3 are both negative, which can achieve the effect of two cancellations. Note that the ESF eliminates the distortion of the main transistor M1, and the amplitude ratio of the three components is roughly 2A 3 v,se G sf ″ / A 3 v,se g″ ds / g″ m1 The ESF distortion multiplied by the cube of the voltage gain means that only a small ESF is needed to achieve distortion cancellation, thereby minimizing additional parasitics. By adjusting the size of the ESF and the load resistance (R f +R s ) to adjust the nonlinear coefficient G sf ″, but it will have an adverse effect on input matching and NF.

[0095] In fact, the ESF is preset to an over-distortion state, and as an additional degree of design freedom, the active load provides a compensatory distortion component to compensate for the offset between the ESF and M1. The load distortion is reflected by the output level V ref The control is dynamically adjusted to adapt to the gain changes at different frequencies and the second-order interaction effects not shown in the equation; if the traditional method is used to design the PMOS size change controlled by the bit switch to adjust the load distortion, additional parasitic effects will be introduced, which is not conducive to the high linearity of the broadband; the PMOS tube M7 uses an LVT device to save the load voltage margin. The load of the present invention adopts an active PMOS load combined with a CMFB module, which can control the output DC level under a limited power supply voltage to obtain the best linearity.

[0096] like Figure 4 As shown, it is a schematic diagram of the circuit principle of the OTA of the present invention, Fig. 9 The OTA’s CM noise source V n，OTA Appears at the differential output, generating an unbalanced noise voltage V no+ / - . V no+ / - The two noise voltages are further combined into a noise signal at the output of the enhanced source follower, and then reach the input CS stage. Correspondingly, the X / Y two paths generate differential feedback noise, which is finally combined with the previous V no+ / -The superposition of the two phases can alleviate the CM noise imbalance to a certain extent. A more effective way to solve this CM-DM noise conversion problem is to absorb the CM noise in the CM path instead of leaking it to the DM path. To achieve the above goal, this technical solution adopts a two-stage OTA structure.

[0097] The first stage is optimized for low noise, and the second stage drives a larger capacitive load to help absorb KT / C noise. At the same time, the CM resistor R L，cm The noise will also be amplified by the OTA and appear as asymmetrical CM noise at the output. To offset this effect, a capacitor C is added. L，cm , to shorten the distance from CM to ground, Millor compensation is used to maintain the stability of gain, and C z / R z The zero contribution roughly compensates the CM capacitance C L，cm and resistor R L，cm The extreme point.

[0098] like Fig.13 As shown, the simulated NF results of different capacitor configurations inside the CMFB are shown at frequencies of 0-10GHz. It can be seen that after the noise conversion of the CM-DM is suppressed, the NF drops by 0.67dB, and the final NF performance is 2-3.6dB;

[0099] The embodiment provides a low balun error, high linearity, low noise broadband amplifier implemented using 65nm process technology. Figure 1 In the circuit, Rf: 350Ω, Cf: 80fF combination produces high-frequency poles to improve the matching bandwidth; L0: 0.55nH, C0: 180fF build a π-type network to improve the matching bandwidth. The circuit finally consumes 14.8mW at a 1.2V power supply, and the operating frequency covers the 5G communication band of 0.2-6GHz. At a frequency of 0.2-6GHz, the test results of the balun low-noise amplifier show that S 11 Less than -10dB, gain is 17-19.5dB, NF minimum is 2.8dB, and IIP3 average is greater than 2.5dBm.

[0100] Example 3

[0101] This embodiment is based on Embodiment 1 and describes in detail a low balun error, high linearity, low noise broadband amplifier. Figure 1 The overall topology implementation effect;

[0102] like Fig.10 As shown, the Z L，cl , Z R，cl , Z L，ol , Z R，olThe impedance value simulation results show that at 1GHz, Z L，cl , Z R，cl , Z L，ol , Z R，ol The impedance values ​​are 175Ω, 135Ω, 238Ω, and 166Ω respectively;

[0103] like Fig.11 As shown in the figure, the simulation results of gain error at frequencies of 0.1-10GHz are given. It can be seen that the final gain error simulation result is less than 0.1dB; and it can be clearly seen that the triple error correction technology gradually corrects the balun error, and that Vy / Vx is preset at around 1.8dB instead of the ideal unity gain;

[0104] like Fig.12 As shown in the figure, the simulation results of phase error at frequencies of 0.1-10 GHz are given. It can be seen that the final phase error simulation result is much less than 0.5 degrees. The triple error correction technology can gradually correct the balun phase error. Taking the 6 GHz frequency point as an example, the phase error reduction trend is: 35.6°->4.5°->0.1°.

[0105] like Fig.13 As shown, the simulated NF under different capacitor configurations inside the CMFB is shown at frequencies of 0-10GHz. It can be seen that after the CM-DM noise conversion effect is suppressed, the NF drops by 0.67dB, and the final NF simulation result is 2-3.6dB;

[0106] like Fig.14 As shown in the figure, the simulation results of the third-order distortion when the input voltage is -0.3-0.3V are given. It can be seen that G sf " is negative;

[0107] like Fig.15 As shown, S is given when the frequency is 0-7GHz. 11 , Gain, NF, IIP3 measurement and simulation results. The measurement results show that S 11 Less than -10dB, Gain is 17-19.5dB, NF minimum is 2.8dB, where IIP3 is measured with a tone interval of 10MHz and an amplitude of -40dBm, it fluctuates between -1.4-8.3dBm, and the average value of the entire passband is greater than 2.5dBm, while the simulated level is only -5dBm when a diode is used to short the PMOS load.

[0108] This embodiment demonstrates the significant advantages of IIP3 linearity of the technical solution through the above technical effects. Fig.15The balun error measurement results of the present invention are given: gain error <0.5dB, phase error <1°. Such a low balun error is comparable to the balun error level of any passive transformer. However, this solution avoids the drawbacks of large size and insertion loss of the passive balun, making this technical solution have high scientific value and technical breakthrough significance.

[0109] The above are only preferred embodiments of the present invention, which do not limit the scope of protection of the present invention. For those skilled in the art, the present invention may have various modifications and changes. Any changes, modifications, replacements, integrations and parameter changes to these embodiments within the spirit and principles of the present invention through conventional substitutions or without departing from the principles and spirit of the present invention fall within the scope of protection of the present invention.

Claims

1. A low balun error, high linearity, low noise broadband amplifier, characterized in that: include: Input terminal, common source stage amplifier, differential current balancer, OTA, load circuit and enhanced source follower; The input terminal includes a resistor R s , port P1, capacitor C0, inductor L0, resistor R f and capacitor C f ; The common-source amplifier comprises a first common-source amplifier and a second common-source amplifier, and the first common-source amplifier and the second common-source amplifier have the same structure; ports A and B are arranged on both sides of the first common-source amplifier; ports C and M are arranged on both sides of the second common-source amplifier; and a node X is arranged between the first common-source amplifier and the second common-source amplifier; Ports D and E and ports F and G are arranged on both sides of the differential current balancer; a node Y is arranged between port E of the differential current balancer and port M of the second common source amplifier; Ports P2, P3 and P4 are set on both sides of the OTA; the port P4 is connected to the port P5 and the port P6 respectively; an R is set between the port P4 and the port P5 L，cm , R is set between the port P4 and the port P6 L，cm1 ; A node Z is set between the port P6 and the differential current balancer port G; Ports T and V are provided on both sides of the load circuit; Ports H, J and K are provided on both sides of the enhanced source follower; The input resistance R s One end receives the input signal V s , the other end is connected to one end of capacitor C0 and connected to port P1; the other end of capacitor C0 is grounded; the input resistor R f One end of the capacitor C f One end is connected to port P1, and the other end is connected to capacitor C f The other end of the input inductor L0 is connected to the H end of the enhanced source follower; one end of the input inductor L0 is connected to the port P1, and the other end is connected to the A end of the first common source amplifier; The J terminal of the enhanced source follower is connected to the port P5 of the OTA, the K terminal of the enhanced source follower is connected to the node Z, and the node Z is connected to another output port P6; The B terminal of the first common-source amplifier is connected to the node X, the C terminal of the second common-source amplifier is connected to the node X, and the M terminal of the second common-source amplifier is connected to the node Y; The D terminal of the differential current balancer is connected to the node X, the E terminal of the differential current balancer is connected to the node Y, the F terminal of the differential current balancer is connected to the output port P5, and the G terminal of the differential current balancer is connected to the node Z; The resistor R L，cm One end of the resistor R is connected to the port P5, and the other end is connected to the port P4 of the OTA; L，cm1 One end is connected to port P6, and the other end is connected to port P4 of OTA; port P3 of OTA is connected to power supply voltage V ref , the port P2 is connected to the load circuit; The T end of the load circuit is connected to the output port P5, and the V end of the load circuit is connected to another output port P6; The input signal V s It comes in from the P1 port, enters the first common-source amplifier through port A, and is transmitted through port B. One signal is transmitted to port D and enters the differential current balancer. The other signal enters the second common-source amplifier through port C, and is transmitted to port E through node Y and enters the differential current balancer. It is transmitted to ports P5 and P6 through ports F and G of the differential current balancer, and then transmitted to port P4 through ports P5 and P6 to enter the OTA. It is transmitted to the load circuit through port P2, and is transmitted through ports T and V of the load circuit, and outputs V through ports P5 and P6. O signal; output V O The signal enters the enhanced source follower through the J and K ports, and reaches the P1 port through the H port of the enhanced source follower to form feedback.

2. A low balun error, high linearity, low noise broadband amplifier according to claim 1, characterized in that: The common source amplifier comprises: an NMOS tube M n1 、NMOS tube M n2 、PMOS tube M p1 、PMOS tube M p2 , capacitor C1, capacitor C2, resistor R1, resistor R2; One end of the capacitor C1 is connected to one end of the capacitor C2 and connected to the port A / C. The other end of the capacitor C1 is connected to one end of the resistor R1 and the PMOS transistor M. p1～2 The other end of the resistor R1 is connected to the power supply voltage V b1 , the PMOS tube M p1～2 The source terminal is connected to the power supply voltage 1.2V, and the PMOS tube M p1～2 The drain terminal and NMOS tube M n1～2 The drain end is connected to port B / M, and the NMOS tube M n1～2 The source end is grounded, the other end of the capacitor C2 is connected to one end of the resistor R2 and the NMOS tube M n1～2 The other end of the resistor R2 is connected to the power supply voltage V b0 .

3. A low balun error, high linearity, low noise broadband amplifier according to claim 1, characterized in that: The differential current balancer includes: an NMOS tube M3, an NMOS tube M4, a capacitor C6, a capacitor C7, a resistor R6, and a resistor R7; One end of the capacitor C6 is connected to the gate end of the NMOS tube M3 and one end of the resistor R6, the other end of the capacitor C6 is connected to the source end of the NMOS tube M4, and the other end of the resistor R6 is connected to one end of the resistor R7 and connected to the power supply voltage V b2 The other end of the resistor R7 is connected to one end of the capacitor C7 and the gate end of the NMOS tube M4, the other end of the capacitor C7 is connected to the source end of the NMOS tube M3, the drain end of the NMOS tube M3 is connected to the port F, the source end of the NMOS tube M3 is connected to the port D, the drain end of the NMOS tube M4 is connected to the port G, and the source end of the NMOS tube M4 is connected to the port E.

4. The low balun error, high linearity, low noise broadband amplifier according to claim 1, characterized in that: The OTA includes: NMOS tube M0, NMOS tube M1, NMOS tube M2, NMOS tube M6, PMOS tube M3, PMOS tube M4, PMOS tube M5, capacitor C L，cm , capacitor C m , capacitor C z , capacitor C L , resistor R m , resistor R z ; The capacitor C L，cm One end of the capacitor C is connected to the gate end of the NMOS tube M1 and connected to the port P4. L，cm The other end is grounded, the source end of the NMOS tube M1 is connected to the drain end of the NMOS tube M0 and the source end of the NMOS tube M2, the drain end of the NMOS tube M1 is connected to the drain end of the PMOS tube M3 and the gate end of the PMOS tube M3, the source end of the PMOS tube M3 is connected to the power supply voltage 1.2V, the gate end of the PMOS tube M3 is connected to the gate end of the PMOS tube M4, the source end of the PMOS tube M4 is connected to the power supply voltage 1.2V, the drain end of the PMOS tube M4 is connected to the gate end of the PMOS tube M5 and the drain end of the NMOS tube M2, and the gate end of the NMOS tube M2 is connected to the power supply voltage V ref The gate of the NMOS tube M0 is connected to the power supply voltage V b0，ota The source end of the NMOS tube M0 is grounded, the source end of the PMOS tube M5 is connected to the power supply voltage 1.2V, and the resistor R m One end of the resistor R is connected to the gate end of the PMOS tube M5. m The other end of the capacitor C m One end of the capacitor C m The other end is connected to the drain end of the PMOS tube M5 and the drain end of the NMOS tube M6. L One end of the capacitor C is connected to the drain end of the PMOS tube M5 and the drain end of the NMOS tube M6, and is connected to the port P2. L The other end of the capacitor C z One end of the capacitor C is connected to the drain end of the PMOS tube M5 and the drain end of the NMOS tube M6. z The other end of the resistor R z One end of the resistor R is connected to the gate end of the NMOS tube M6. z The other end is connected to the power supply voltage V b1，ota , the source end of the NMOS tube M6 is grounded.

5. The low balun error, high linearity, low noise broadband amplifier according to claim 1, characterized in that: The load circuit includes: a PMOS tube M7, a PMOS tube M8, a resistor R5, a capacitor C L，cmp , capacitor C R，cmp ; The capacitor C L，cmp One end of the capacitor C is connected to the source end of the PMOS tube M7, the source end of the PMOS tube M7 is connected to the power supply voltage 1.2V, and the capacitor C L，cmp The other end of the resistor R5 is connected to the drain end of the PMOS tube M7 and connected to the port T. The gate end of the PMOS tube M7 is connected to the gate end of the PMOS tube M8 and connected to the port P2. One end of the resistor R5 is connected to the capacitor C R，cmp The other end of the resistor R5 is connected to the drain end of the PMOS tube M8 and connected to the port V. The capacitor C R，cmp The other end is connected to the source end of the PMOS tube M8, and the source end of the PMOS tube M8 is connected to the power supply voltage 1.2V.

6. A low balun error, high linearity, low noise broadband amplifier according to claim 1, characterized in that: The enhanced source follower includes: NMOS tube M5, NMOS tube M7, capacitor C3, capacitor C4, resistor R3, resistor R4; One end of the capacitor C3 is connected to port J and serves as an output port V o+ The other end of the capacitor C3 is connected to one end of the resistor R3 and the gate end of the NMOS tube M5, and the other end of the resistor R3 is connected to the power supply voltage V b4 The drain end of the NMOS tube M5 is connected to the power supply voltage 1.2V, the source end of the NMOS tube M5 is connected to the drain end of the NMOS tube M7 and connected to the port H, the source end of the NMOS tube M7 is grounded, one end of the capacitor C4 is connected to the port K and serves as another output port V o- The other end of the capacitor C4 is connected to one end of the resistor R4 and the gate end of the NMOS tube M7, and the other end of the resistor R4 is connected to the power supply voltage V b3 .

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