A broadband on-chip driver amplifier

Abstract

The present application provides a broadband on-chip driver amplifier. The driver amplifier includes: an input matching circuit for filtering the radio frequency signal; a driving stage circuit for performing initial amplification processing on the filtered radio frequency signal and sending it to a power divider; a power divider for dividing the radio frequency signal after the initial amplification into a first radio frequency signal and a second radio frequency signal according to a preset power distribution ratio, and sending it to an inter-stage matching circuit; an inter-stage matching circuit for sending the first radio frequency signal and the second radio frequency signal to a final stage circuit; a final stage circuit for re-amplifying the first radio frequency signal and the second radio frequency signal, and sending them to an output matching circuit; an output matching circuit for synthesizing the phases of the re-amplified first radio frequency signal and the second radio frequency signal, and outputting a synthesized signal. The present application can effectively improve the efficiency and operating bandwidth of the circuit at the back-off power point, and at the same time improve the gain flatness and circuit stability of the circuit.

Description

Technical Field

[0001] The present application relates to the field of chip design technology, and in particular to a broadband on-chip driver amplifier. Background Art

[0002] The driver amplifier is located at the front end of the power amplifier. Its main function is to provide the power amplifier with sufficient power while ensuring the system linearity indicators and share the gain pressure of the power amplifier. If the gain and linearity of the driver amplifier are not enough, the performance of the final power amplifier will be greatly reduced. Therefore, the quality of the driver amplifier design directly affects the performance of the entire system.

[0003] Complex modulation technologies such as QAM, QPSK, and OFDM increase the peak-to-average ratio (PAR). To improve communication quality, power back-off is often employed. Traditional linear power amplifiers, such as Class A and Class AB, have power utilization rates of less than 15% when backed off by 8dB. Summary of the Invention

[0004] The present application provides a broadband on-chip driver amplifier to solve the problem of low power utilization during power fallback in the prior art.

[0005] In a first aspect, the present application provides a broadband on-chip driver amplifier, comprising: an input matching circuit, a driver stage circuit, a power divider, an inter-stage matching circuit, a final stage circuit, and an output matching circuit connected in series in sequence; wherein the input matching circuit, the driver stage circuit, the power divider, the inter-stage matching circuit, and the final stage circuit are integrated on the chip;

[0006] The input matching circuit is used to receive an input radio frequency signal, filter the radio frequency signal, and send the filtered radio frequency signal to the driving stage circuit;

[0007] The driving stage circuit is used to perform a primary amplification process on the filtered radio frequency signal and send the primary amplified radio frequency signal to the power divider;

[0008] The power divider is configured to divide the radio frequency signal after the initial amplification into a first radio frequency signal and a second radio frequency signal according to a preset power distribution ratio, and send the first radio frequency signal and the second radio frequency signal to the inter-stage matching circuit;

[0009] The inter-stage matching circuit is used to send the first radio frequency signal and the second radio frequency signal to the final stage circuit;

[0010] The final stage circuit is configured to re-amplify the first radio frequency signal and the second radio frequency signal, and send the re-amplified first radio frequency signal and the second radio frequency signal to the output matching circuit;

[0011] The output matching circuit is used to synthesize the re-amplified first radio frequency signal and the second radio frequency signal with equal phases and output a synthesized signal.

[0012] The present application provides a broadband on-chip driver amplifier, which includes an input matching circuit, a driver stage circuit, a power divider, an inter-stage matching circuit, a final stage circuit, and an output matching circuit connected in series in sequence; and the input matching circuit, the driver stage circuit, the power divider, the inter-stage matching circuit, and the final stage circuit are integrated on the chip; the input matching circuit is used to receive an input radio frequency signal, filter the radio frequency signal, and send the filtered radio frequency signal to the driver stage circuit; the driver stage circuit is used to perform initial amplification processing on the filtered radio frequency signal and send the initially amplified radio frequency signal to the power divider; the power divider is used to divide the initially amplified radio frequency signal into a first radio frequency signal and a second radio frequency signal according to a preset power distribution ratio, and send the first radio frequency signal and the second radio frequency signal to the inter-stage matching circuit; the inter-stage matching circuit is used to send the first radio frequency signal and the second radio frequency signal to the final stage circuit; the final stage circuit is used to re-amplify the first radio frequency signal and the second radio frequency signal, and send the re-amplified first radio frequency signal and the second radio frequency signal to the output matching circuit; the output matching circuit is used to synthesize the phases of the re-amplified first radio frequency signal and the second radio frequency signal, and output the synthesized signal. This application utilizes a driver-stage circuit to initially amplify the filtered RF signal, providing sufficiently large gain and power for the final-stage circuit. While meeting the gain index, it can not only effectively improve the efficiency and operating bandwidth at the circuit's fallback power point, but also improve the circuit's gain flatness and circuit stability. At the same time, the amplifier adopts a broadband on-chip design, integrating various functional units on the same chip, which not only reduces the size and weight of the device, but also improves the system's integration and reliability, which helps to reduce production costs, simplify system design, and enhance the product's market competitiveness. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments or descriptions of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0014] Figure 1 Schematic diagram of the structure of a broadband on-chip driver amplifier provided in an embodiment of the present application;

[0015] Figure 2 is a schematic structural diagram of an input matching circuit provided in an embodiment of the present application;

[0016] Figure 3 1 is a schematic structural diagram of a driver-stage circuit provided in an embodiment of the present application;

[0017] Figure 4 is a structural diagram of a first amplification unit provided in an embodiment of the present application;

[0018] Figure 5 Schematic diagram of the structure of the power divider provided in the embodiment of the present application;

[0019] Figure 6 is a structural diagram of an inter-stage matching circuit provided in an embodiment of the present application;

[0020] Figure 7 1 is a schematic structural diagram of the final stage circuit provided in an embodiment of the present application;

[0021] Figure 8 Schematic diagram of the output matching circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0022] In the following description, specific details such as specific system structures and techniques are provided for purposes of illustration rather than limitation to facilitate a thorough understanding of the embodiments of the present application. However, it will be apparent to those skilled in the art that the present application may be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to avoid obscuring the description of the present application with unnecessary detail.

[0023] In order to make the purpose, technical solutions and advantages of this application clearer, specific embodiments will be described below with reference to the accompanying drawings.

[0024] Because traditional linear power amplifiers, such as Class A and Class AB amplifiers, have a power utilization rate of less than 15% when backed off by 8dB, power amplifiers based on the Doherty structure can achieve high efficiency under power back-off by dynamically adjusting the load impedance.

[0025] Therefore, this application provides a broadband on-chip driver amplifier based on a Doherty circuit structure, which improves efficiency at the power back-off point within the operating frequency band and simplifies off-chip application solutions. The circuit structure of this driver amplifier is manufactured using a GaAsHBT semiconductor process and has excellent characteristics such as high breakdown voltage, high power density, and high linearity, which can meet the application requirements of driver amplifiers.

[0026] The embodiment of the present application utilizes the Doherty structure, which can more effectively utilize the power supply energy, amplify the input RF signal in stages, and perform power synthesis at the final stage. It can not only achieve higher power added efficiency within a broadband range, but also help reduce energy loss and improve the overall efficiency of the system.

[0027] Figure 1 This is a schematic diagram of the structure of the broadband on-chip driver amplifier provided in the embodiment of the present application. Figure 1 As shown, the broadband on-chip driver amplifier includes an input matching circuit 1, a driver stage circuit 2, a power divider 3, an inter-stage matching circuit 4, a final stage circuit 5 and an output matching circuit 6 connected in series in sequence; and the input matching circuit 1, the driver stage circuit 2, the power divider 3, the inter-stage matching circuit 4 and the final stage circuit 5 are integrated on the chip.

[0028] Input matching circuit 1, used to receive the input radio frequency signal RF in , for radio frequency signal RF in Perform filtering processing and send the filtered radio frequency signal to the driving stage circuit 2.

[0029] The driving stage circuit 2 is used to perform primary amplification processing on the filtered radio frequency signal and send the primary amplified radio frequency signal to the power divider 3.

[0030] The power divider 3 is used to divide the RF signal after the initial amplification into a first RF signal and a second RF signal according to a preset power distribution ratio, and send the first RF signal and the second RF signal to the inter-stage matching circuit 4.

[0031] The inter-stage matching circuit 4 is used to send the first radio frequency signal and the second radio frequency signal to the final stage circuit 5 .

[0032] The final stage circuit 5 is configured to re-amplify the first radio frequency signal and the second radio frequency signal, and send the re-amplified first radio frequency signal and the second radio frequency signal to the output matching circuit 6 .

[0033] The output matching circuit 6 is used to synthesize the first RF signal and the second RF signal after re-amplification with equal phases, and output a synthesized signal.

[0034] Among them, the signals on the entire radio frequency signal chain are continuous radio frequency signals (sine waves).

[0035] For example, refer to Figure 1 For a 50Ω system, input matching circuit 1 matches the input impedance of the driver amplifier circuit to 50Ω within the operating frequency band, reducing reflections of the RF input signal and achieving maximum power transmission. Correspondingly, output matching circuit 6 matches the output impedance to 50Ω.

[0036] It should also be noted that the input port is connected to the input matching circuit via a bond wire, and correspondingly, the output port is connected to the output matching circuit via a 50Ω strip line.

[0037] At the same time, the input matching circuit 1, the driving stage circuit 2, the power divider 3, the inter-stage matching circuit 4 and the final stage circuit 5 are integrated on-chip. The chip here refers to the chip level, and integrated on-chip means implemented on the chip. It can also be called a broadband on-chip amplifier.

[0038] The embodiments of this application utilize a die-plus-substrate structure similar to a monolithic microwave integrated circuit (MMIC), integrating the input matching circuit, driver circuit, power divider, inter-stage matching circuit, and final circuit. Bonding wires interconnect the individual chips, significantly improving integration. A portion of the output matching circuit is integrated into the substrate package for pre-matching. Final matching is achieved using only five components on the PCB, leaving a margin for debugging to meet the needs of applications in different frequency bands.

[0039] In addition, the embodiment of the present application adopts a broadband on-chip design, integrating various functional units on the same chip, which not only reduces the size and weight of the device, but also improves the integration and reliability of the system, which helps to reduce production costs, simplify system design, and enhance the market competitiveness of the product.

[0040] In one possible implementation, refer to Figure 1 The broadband on-chip driver amplifier may further include an active bias circuit 7 for providing current signals to the driver stage circuit 2 and the final stage circuit 5 respectively.

[0041] The first input terminal IB1 of the active bias circuit 7 is connected to the driving stage circuit 2 , and the second input terminal IB2 of the active bias circuit 7 and the third input terminal IB3 of the active bias circuit 7 are connected to the final stage circuit 5 respectively.

[0042] Optionally, an embodiment of the present application adopts an adaptive linearized active bias circuit structure based on the evolution of a mirror current source circuit, and utilizes the characteristics of the active bias circuit to automatically adjust the operating point of the driver amplifier under large signals, which can effectively improve the gain compression and phase distortion characteristics of the driver amplifier, while providing linearity and reducing the sensitivity of the bias current to device parameters and ambient temperature.

[0043] In one possible implementation, refer to Figure 2 The input matching circuit 1 may include a first inductor L1, a second inductor L2, a first capacitor C1 and a second capacitor C2.

[0044] A first end of the second capacitor C2 is connected to the input end of the input matching circuit 1 and the first end of the second inductor L2, respectively. A second end of the second capacitor C2 is connected to the first end of the first capacitor C1 and the first end of the first inductor L1, respectively. A second end of the second inductor L2 is grounded, and a second end of the first capacitor C1 is grounded.

[0045] The second end of the first inductor L1 is connected to the output end of the input matching circuit 1 .

[0046] Optionally, the input matching circuit is located at the front end of the broadband on-chip driver amplifier and adopts a bandpass composite network matching structure, which is based on an LC low-pass and high-pass matching network and consists of a first-stage LC low-pass network and a CL high-pass network. Figure 2 The LC low-pass network is composed of a first inductor L1 and a first capacitor C1, and the CL high-pass network is composed of a second inductor L2 and a second capacitor C2.

[0047] The embodiment of the present application combines two matching networks with opposite frequency response characteristics, which can effectively expand the bandwidth and improve out-of-band suppression, thereby improving in-band linearity and gain flatness.

[0048] In the embodiment of the present application, the input matching circuit filters the radio frequency signal, which helps to eliminate noise and interference in the input signal and improve the purity of the signal.

[0049] In one possible implementation, refer to Figure 3 The driving stage circuit 2 may include a first amplifying unit circuit T1, a first resistor R f , the third capacitor C f and the third inductor l d1 ;

[0050] The base of the first amplifying unit circuit T1 is respectively connected to the input end of the driving stage circuit 2, the first input end IB1 of the active bias circuit and the first resistor R f The collector of the first amplifying unit circuit T1 is connected to the first end of the third capacitor C f The first end of the third inductor l d1 The first end is connected to the output end of the driving stage circuit, and the emitter of the first amplifying unit circuit T1 is grounded;

[0051] The second end of the first resistor and the third capacitor C f The second end of the third inductor L d1 The second end of is connected to the first power supply VCC1.

[0052] The driving stage circuit and the power divider are connected via a bonding wire W1.

[0053] Optionally, the driver-stage circuit in the embodiment of the present application is primarily used to amplify the RF signal, providing sufficiently large gain and power for the final-stage circuit. Since the RF signal chain has gain requirements, the final-stage circuit alone would not have sufficient gain to amplify the received RF signal to the required power value. Therefore, the embodiment of the present application incorporates a driver-stage circuit to provide sufficient gain, first amplifying the RF signal input to the matching circuit, and then providing the amplified RF signal to the final-stage circuit, so that the overall circuit can achieve the required power.

[0054] The driving stage circuit in the embodiment of the present application introduces a resistor-capacitor feedback circuit series feedback structure between the base and the collector of the first amplifying unit circuit, that is, the first resistor R f and the third capacitor C f The feedback circuit can effectively improve the gain flatness and stability of the circuit while meeting the gain index. f and the third capacitor C f , which can effectively reduce the circuit Q value, expand the bandwidth and improve the gain flatness.

[0055] In addition, in the embodiment of the present application, the first amplifier unit circuit is composed of four first amplifier units with the same structure connected in parallel. The corresponding structure of the first amplifier unit circuit is as follows: the bases of the four first amplifier units are connected in parallel and connected to the base of the first amplifier unit circuit; the collectors of the four first amplifier units are connected in parallel and connected to the collector of the first amplifier unit circuit; the emitters of the four first amplifier units are connected in parallel and connected to the emitter of the first amplifier unit circuit; and the signal input terminals of the four first amplifier units are connected in parallel and connected to the first input terminal of the active bias circuit.

[0056] In the embodiment of the present application, since a driving stage circuit and a final stage circuit are included, and the final stage circuit receives two RF signals distributed by a power divider for re-amplification, the amplifier has a stronger power handling capability, which enables it to maintain stable performance in application scenarios with high power requirements while reducing the risk of equipment damage due to excessive power.

[0057] In one possible implementation, refer to Figure 4 , the first amplifying unit may include a DC blocking capacitor C b , ballast resistor R b , bias resistor R ib and transistor VT;

[0058] DC blocking capacitor C b The first end of the first amplifying unit is connected to the base of the first amplifying unit, and the DC blocking capacitor C b The second end of the ballast resistor R b The first end of the bias resistor R ibThe first end of the connection;

[0059] Ballast resistor R b The second end is connected to the base B of the transistor VT, and the bias resistor R ib The second end is connected to the first input terminal IB of the active bias circuit;

[0060] The collector C of the transistor VT is connected to the collector of the first amplifying unit, and the emitter of the transistor VT is connected to the emitter E of the first amplifying unit.

[0061] Optionally, in this embodiment, a ballast resistor R is added to the base of the transistor VT. b To ensure the dynamic thermal balance of transistor VT and suppress thermal collapse. At the same time, a DC blocking capacitor C is connected in series to the base of transistor VT. b Provides a low impedance path for the RF signal and blocks the potential of the previous circuit. The bias resistor R between the two ib , participate in the compensation of the base voltage of the transistor VT and stabilize the DC bias.

[0062] In one possible implementation, refer to Figure 5 , the power divider 3 may include a fourth capacitor C3, a fifth capacitor C4, a sixth capacitor C5, a seventh capacitor C6, a fourth inductor L3, a fifth inductor L4 and a balancing resistor R0;

[0063] The first end of the fourth inductor L3 is connected to the first input end of the power divider 3, the first end of the fourth capacitor C3, the first end of the sixth capacitor C5 and the first end of the fifth inductor L4 respectively. The second end of the fourth inductor L3 is connected to the first end of the fifth capacitor C4, the balancing resistor R o The first end of the fourth capacitor C3, the second end of the fifth capacitor C4 and the second end of the sixth capacitor C5 are all grounded;

[0064] The second end of the fifth inductor L4 is respectively connected to the first end of the seventh capacitor C6 , the second end of the balancing resistor R0 , and the second output end of the power divider 3 , and the second end of the seventh capacitor C6 is grounded.

[0065] Optionally, the power divider in the embodiment of the present application adopts a lumped form power divider, which inputs the output signal of the driving stage circuit from the first input terminal and outputs it from the two output terminals (i.e., the first output terminal and the second output terminal). After the power is distributed according to the preset power distribution ratio, it becomes two signals and enters the inter-stage matching circuit respectively. Because the final stage of the Doherty power amplifier structure is divided into two main power amplifiers and auxiliary power amplifiers, the embodiment of the present application requires a power divider to divide the output signal of the driving stage into two and provide them to the main power amplifier and auxiliary power amplifier of the final stage circuit respectively. The 1 / 4 wavelength transmission lines on the two output paths are replaced by an equivalent low-pass π-type network, which miniaturizes the power divider, reduces the chip area, and saves costs. Adjust the balancing resistor R0 to maintain impedance matching, reduce signal reflection and interference, and thus improve the performance and reliability of the power divider.

[0066] For example, the power divider of the embodiment of the present application may be a Wilkinson power divider, referring to Figure 5 The power divider 3 is composed of a fourth capacitor C3, a fifth capacitor C4, a sixth capacitor C5, a seventh capacitor C6, a fourth inductor L3, a fifth inductor L4 and a balancing resistor R0, wherein the fourth capacitor C3, the fifth capacitor C4 and the fourth inductor L3 form an upper half equivalent low-pass π-type network, and the sixth capacitor C5, the seventh capacitor C6 and the fifth inductor L4 form a lower half equivalent low-pass π-type network.

[0067] Since the traditional Wilkinson power splitter structure is composed of two 1 / 4 wavelength transmission lines, in the actual design process of the embodiment of the present application, it is necessary to make the volume as small as possible and the circuit symmetrical. However, in the low frequency band, the size of the 1 / 4 wavelength transmission line is too large. Therefore, the 1 / 4 wavelength transmission line in the traditional structure is replaced by an equivalent low-pass π-type network composed of lumped parameter elements on the broadband chip to miniaturize the power splitter.

[0068] In addition, the balancing resistor R0 in the power divider can not only be used to provide the best match between the input and output, but also eliminate reflections and interference inside the power divider, suppress odd-mode oscillations, and thus improve the performance and reliability of the power divider.

[0069] In one possible implementation, refer to Figure 6 The inter-stage matching circuit 4 may include a sixth inductor L5, a seventh inductor L6, an eighth inductor L7, an eighth capacitor C7, a ninth capacitor C8, a tenth capacitor C9 and an eleventh capacitor C 10 ;

[0070] The first end of the sixth inductor L5 is connected to the first input end of the inter-stage matching circuit 4 and the first end of the eighth capacitor C7 respectively, and the second end of the sixth inductor L5 is connected to the first end of the ninth capacitor C8 and the eleventh capacitor C 10The first end of the eighth inductor L7 is connected to the first end of the eighth capacitor C7, the second end of the ninth capacitor C8 and the eleventh capacitor C 10 The second ends of are grounded;

[0071] The second end of the eighth inductor L7 is connected to the first output end of the inter-stage matching circuit 4;

[0072] The first end of the seventh inductor L6 is connected to the second input end of the inter-stage matching circuit 4 and the first end of the tenth capacitor C9 respectively. The second end of the seventh inductor L6 is connected to the second output end of the inter-stage matching circuit 4. The second end of the tenth capacitor C9 is grounded.

[0073] The first output terminal of the inter-stage matching circuit is connected to the first input terminal of the final stage circuit via a bonding wire W2 , and the second output terminal of the inter-stage matching circuit is connected to the second input terminal of the final stage circuit via a bonding wire W3 .

[0074] Optionally, in an embodiment of the present application, the inter-stage matching circuit is located between the power divider and the final circuit. Its main function is to form an optimal power match between the input ends of the main power amplifier and the auxiliary power amplifier in the final circuit and the output end of the power divider, so that the output signal of the driving stage circuit is transmitted to the final circuit to the maximum extent. If there is a large phase difference between the main power amplifier and the auxiliary power amplifier of the final circuit, the signal will be attenuated after the two signals are combined, reducing the output power and efficiency indicators. Therefore, the phase difference between the output signals of the upper and lower branches of the main power amplifier and the auxiliary power amplifier is compensated, so that the phase of the output combining point position of the output matching circuit is consistent, thereby improving the overall output power and efficiency.

[0075] The inter-stage matching circuit utilizes two single-stage L-shaped low-pass matching networks to match the conjugate input impedance of the main and auxiliary power amplifier branches to the characteristic impedance of the power divider. This L-shaped matching structure is simple and easy to implement, reducing device losses. A phase compensation line, consisting of a low-pass π-shaped network converted from a transmission line, is placed before the main power amplifier's L-shaped matching circuit. Its primary function is to compensate for the phase difference between the output signals of the upper and lower branches of the main and auxiliary power amplifiers, ensuring phase alignment at the output combining point and improving overall output power and efficiency.

[0076] For example, refer to Figure 6 The inter-stage matching circuit is composed of the sixth inductor L5, the seventh inductor L6, the eighth inductor L7, the eighth capacitor C7, the ninth capacitor C8, the tenth capacitor C9 and the eleventh capacitor C 10 The seventh inductor L6 and the tenth capacitor C9 form an L-type matching circuit before the auxiliary power amplifier, the eighth inductor L7 and the eleventh capacitor C 10The L-type matching circuit preceding the main amplifier and the inter-stage matching circuits all utilize L-type matching circuits. L-type matching circuits offer the lowest cost and most reliable performance. They occupy the smallest layout area on a broadband chip compared to other basic matching circuit structures, minimizing losses and making them the easiest to implement. The eighth and ninth capacitors C7 and C8, along with the sixth inductor L5, preceding the L-type inter-stage matching circuits of the main amplifier, form an equivalent low-pass π-type network. Its primary function is to compensate for the phase difference between the upper and lower output signals, aligning their phases and achieving optimal power and efficiency after combining.

[0077] The design of the inter-stage matching circuit and the output matching circuit in the embodiment of the present application also helps to ensure the phase consistency of the signal, so that a high-quality output signal can be obtained during synthesis.

[0078] In one possible implementation, refer to Figure 7 The final stage circuit 5 may include a second amplifying unit circuit T2, a third amplifying unit circuit T3, a ninth inductor L d2 and the tenth inductor L d3 ;

[0079] The base of the second amplifier unit circuit T2 is connected to the first input terminal of the final stage circuit 5 and the second input terminal IB2 of the active bias circuit respectively. The collector of the second amplifier unit circuit T2 is connected to the first output terminal of the final stage circuit 5 and the ninth inductor L respectively. d2 The first end of the second amplifying unit circuit T2 is connected to the ground, and the ninth inductor L d2 The second end is connected to the second power supply VCC2;

[0080] The base of the third amplifier unit circuit T3 is connected to the second input terminal of the final stage circuit 5 and the third input terminal IB3 of the active bias respectively. The collector of the third amplifier unit circuit T3 is connected to the second output terminal of the final stage circuit 5 and the tenth inductor L respectively. d3 The first end of the third amplifying unit circuit T3 is connected to the ground, and the tenth inductor L d3 The second end of is connected to the third power supply VCC3.

[0081] The first output terminal and the second output terminal of the final stage circuit are connected to the first input terminal and the second input terminal of the output matching circuit through three bonding wires respectively. Figure 7 The second amplifying unit circuit T2 is connected to the first input terminal of the output matching circuit through three bonding wires W4, and the third amplifying unit circuit T3 is connected to the second input terminal of the output matching circuit through three bonding wires W5.

[0082] Optionally, in an embodiment of the present application, the final stage circuit is the main amplification part of the driving amplifier, the main power amplifier operates in class AB, the auxiliary power amplifier operates in class C, the two power amplifiers are synthesized in equal phase, and the efficiency of the back-off point is improved by the active load modulation effect of the active bias circuit. The back-off power range can be adjusted by adjusting the area ratio of the main and auxiliary power amplifier tubes, the preset power distribution ratio of the power divider, and the bias points of the main and auxiliary power amplifiers.

[0083] The final stage circuit consists of a main power amplifier and an auxiliary power amplifier in parallel. The appropriate emitter area of ​​the final stage circuit is selected through LoadPull load-pull simulation to achieve the expected output power and efficiency indicators.

[0084] In the embodiment of the present application, the saturated output power is taken into consideration, and the main power amplifier (i.e., the second amplifying unit circuit T2) is implemented by connecting eight second amplifying units with the same structure in parallel, and the auxiliary power amplifier (i.e., the third amplifying unit circuit T3) is implemented by connecting eight third amplifying units with the same structure in parallel.

[0085] Among them, for the second amplifier unit circuit, the bases of the eight second amplifier units are connected in parallel and connected to the base of the second amplifier unit circuit, the collectors of the eight second amplifier units are connected in parallel and connected to the collector of the second amplifier unit circuit, the emitters of the eight second amplifier units are connected in parallel and connected to the emitter of the second amplifier unit circuit, and the signal input ends of the eight second amplifier units are connected in parallel and connected to the second input end of the active bias circuit.

[0086] For the third amplifier unit circuit, the bases of the eight third amplifier units are connected in parallel and connected to the base of the third amplifier unit circuit, the collectors of the eight third amplifier units are connected in parallel and connected to the collector of the third amplifier unit circuit, the emitters of the eight third amplifier units are connected in parallel and connected to the emitter of the third amplifier unit circuit, and the signal input ends of the eight third amplifier units are connected in parallel to the third input end of the active bias circuit.

[0087] In addition, the structures of the first amplifying unit circuit, the second amplifying unit circuit and the third amplifying power supply circuit are the same. Therefore, the structures of the second amplifying unit and the third amplifying unit are the same. Figure 4 shown.

[0088] The embodiment of the present application utilizes the final stage circuit and the output matching circuit to improve the efficiency of the back-off point through the active load modulation effect, and the back-off power range can be adjusted by adjusting the main and auxiliary power amplifier tube area ratio, the power distribution ratio of the power divider, and the main and auxiliary power amplifier bias points.

[0089] In one possible implementation, refer to Figure 1The output matching circuit 6 may include a substrate pre-matching circuit 61 and a PCB matching circuit 62. The first input end of the substrate pre-matching circuit 61 is connected to the first input end of the output matching circuit 6. The second input end of the substrate pre-matching circuit 61 is connected to the second input end of the output matching circuit 6. The first output end of the substrate pre-matching circuit 61 is connected to the first input end of the PCB matching circuit 62. The second output end of the substrate pre-matching circuit 61 is connected to the second input end of the PCB matching circuit 62. The output end of the PCB matching circuit 62 is connected to the output end of the output matching circuit 6.

[0090] Reference Figure 8 The substrate pre-matching circuit 61 includes an eleventh inductor L8, a twelfth inductor L9, a twelfth capacitor C 11 and the thirteenth capacitor C 12 PCB matching circuit 62 includes a thirteenth inductor L 10 , Fourteenth capacitor C 13 , the fifteenth capacitor C 14 , the sixteenth capacitor C 15 and the seventeenth capacitor C 16 ;

[0091] The first end of the eleventh inductor L8 is connected to the first input end of the substrate pre-matching circuit 61 and the twelfth capacitor C 11 The first end of the eleventh inductor L8 is connected to the first output end of the substrate pre-matching circuit 61, and the twelfth capacitor C 11 The second end of is grounded;

[0092] The first end of the twelfth inductor L9 is connected to the second input end of the substrate pre-matching circuit 61 and the thirteenth capacitor C 12 The first end of the twelfth inductor L9 is connected to the second output end of the substrate pre-matching circuit 61, and the thirteenth capacitor C 12 The second end of is grounded;

[0093] Thirteenth inductor L 10 The first end of the PCB matching circuit 62 and the first input end of the fourteenth capacitor C 13 The first end of the thirteenth inductor L 10 The second end of each of the fifteenth capacitor C 14 The first terminal and the seventeenth capacitor C 16 The first end is connected to the seventeenth capacitor C 16 The second end of the fourteenth capacitor C is connected to the output end of the PCB matching circuit 62. 13 The second end of is grounded;

[0094] The fifteenth capacitor C 14 The second end is respectively connected to the first input end of the PCB matching circuit 62 and the sixteenth capacitor C15 The first end of the sixteenth capacitor C 15 The second end is grounded.

[0095] Optionally, in an embodiment of the present application, the output matching circuit is located after the final stage circuit, including a substrate pre-matching circuit and a PCB matching circuit on the substrate. Both are matching circuits at the output end. The substrate pre-matching circuit is implemented inside the device package. After the device is finally completed, it is internal and invisible from the outside. This reduces the complexity of debugging compared to placing all debugging components on the PCB, making it more convenient and simpler. The PCB matching circuit is on the test board, which is convenient for debugging and can be debugged according to actual application needs, including the frequency band and output power indicators of the application. Its main function is to achieve optimal power-load matching at the output ends of the main power amplifier and auxiliary power amplifier of the final stage circuit, that is, the power output of the main power amplifier and auxiliary power amplifier is optimized, and cooperate with the inter-stage matching circuit to jointly compensate for the phase difference between the output signals of the upper and lower branches of the main power amplifier and the auxiliary power amplifier, so that the phase of the output combining point is consistent, thereby improving the overall output power and efficiency. (With the same inter-stage matching circuit, if there is a large phase difference between the main power amplifier and the auxiliary power amplifier, the signal will be attenuated after the two signals are combined, reducing the output power and efficiency indicators).

[0096] Reference Figure 8 , the eleventh inductor L8 and the twelfth capacitor C on the substrate 11 , the twelfth inductor L9 and the thirteenth capacitor C 12 They form two L-type matching circuits respectively, which can effectively suppress the second harmonic and improve the linearity index. At the same time, they match the optimal load impedance of the main and auxiliary amplifiers to an intermediate impedance value, which can effectively expand the bandwidth. Then, through the thirteenth inductor L on the PCB board, 10 and the fourteenth capacitor C 13 , the fifteenth capacitor C 14 and the sixteenth capacitor C 15 The two L-type matching circuits match the output impedance of the main and auxiliary amplifier substrates to the junction point, and finally pass through the seventeenth capacitor C 16 Match the final output impedance to 50Ω.

[0097] The output matching circuits in the embodiments of this application all adopt an L-type matching circuit structure, which reduces losses and ensures reliable performance. The use of a substrate pre-matching circuit and a PCB matching circuit reduces the substrate area, saves costs, and facilitates subsequent debugging to meet the application requirements of different frequency bands and achieve optimal output power and efficiency indicators.

[0098] The present application provides a broadband on-chip driver amplifier, which includes an input matching circuit, a driver stage circuit, a power divider, an inter-stage matching circuit, a final stage circuit, and an output matching circuit connected in series in sequence; and the input matching circuit, the driver stage circuit, the power divider, the inter-stage matching circuit, and the final stage circuit are integrated on the broadband chip; the input matching circuit is used to receive an input radio frequency signal, filter the radio frequency signal, and send the filtered radio frequency signal to the driver stage circuit; the driver stage circuit is used to perform initial amplification processing on the filtered radio frequency signal and send the initially amplified radio frequency signal to the power divider; the power divider is used to divide the initially amplified radio frequency signal into a first radio frequency signal and a second radio frequency signal according to a preset power distribution ratio, and send the first radio frequency signal and the second radio frequency signal to the inter-stage matching circuit; the inter-stage matching circuit is used to send the first radio frequency signal and the second radio frequency signal to the final stage circuit; the final stage circuit is used to re-amplify the first radio frequency signal and the second radio frequency signal, and send the re-amplified first radio frequency signal and the second radio frequency signal to the output matching circuit; the output matching circuit is used to synthesize the phases of the re-amplified first radio frequency signal and the second radio frequency signal, and output the synthesized signal. This application utilizes a driver-stage circuit to initially amplify the filtered RF signal, providing sufficiently large gain and power for the final-stage circuit. While meeting the gain index, it can not only effectively improve the efficiency and operating bandwidth at the circuit's fallback power point, but also improve the circuit's gain flatness and circuit stability. At the same time, the amplifier adopts a broadband on-chip design, integrating various functional units on the same chip, which not only reduces the size and weight of the device, but also improves the system's integration and reliability, which helps to reduce production costs, simplify system design, and enhance the product's market competitiveness.

[0099] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0100] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present application, and should all be included in the scope of protection of the present application.

Claims

1. A broadband on-chip driver amplifier, characterized in that: include: An input matching circuit, a driver stage circuit, a power divider, an inter-stage matching circuit, a final stage circuit, and an output matching circuit are sequentially connected in series; and the input matching circuit, the driver stage circuit, the power divider, the inter-stage matching circuit, and the final stage circuit are integrated on a chip; The input matching circuit is used to receive an input radio frequency signal, filter the radio frequency signal, and send the filtered radio frequency signal to the driving stage circuit; The driving stage circuit is used to perform a primary amplification process on the filtered radio frequency signal and send the primary amplified radio frequency signal to the power divider; The power divider is configured to divide the radio frequency signal after the initial amplification into a first radio frequency signal and a second radio frequency signal according to a preset power distribution ratio, and send the first radio frequency signal and the second radio frequency signal to the inter-stage matching circuit; The inter-stage matching circuit is used to send the first radio frequency signal and the second radio frequency signal to the final stage circuit; The final stage circuit is configured to re-amplify the first radio frequency signal and the second radio frequency signal, and send the re-amplified first radio frequency signal and the second radio frequency signal to the output matching circuit; The output matching circuit is used to synthesize the phases of the re-amplified first radio frequency signal and the second radio frequency signal, and output a synthesized signal; The driving amplifier further includes an active bias circuit based on adaptive linearization of the mirror current source circuit evolution, which is used to provide current signals to the driving stage circuit and the final stage circuit respectively; The first input terminal of the active bias circuit is connected to the driving stage circuit, and the second input terminal of the active bias circuit and the third input terminal of the active bias circuit are respectively connected to the final stage circuit.

2. The broadband on-chip driver amplifier according to claim 1, wherein: The input matching circuit includes a first inductor, a second inductor, a first capacitor and a second capacitor; The first end of the second capacitor is connected to the input end of the input matching circuit and the first end of the second inductor respectively, the second end of the second capacitor is connected to the first end of the first capacitor and the first end of the first inductor respectively, the second end of the second inductor is grounded, and the second end of the first capacitor is grounded; The second end of the first inductor is connected to the output end of the input matching circuit.

3. The broadband on-chip driver amplifier according to claim 1, wherein: The driving stage circuit includes a first amplifying unit circuit, a first resistor, a third capacitor and a third inductor; The base of the first amplifying unit circuit is respectively connected to the input terminal of the driving stage circuit, the first input terminal of the active bias circuit, and the first terminal of the first resistor; the collector of the first amplifying unit circuit is respectively connected to the first terminal of the third capacitor, the first terminal of the third inductor, and the output terminal of the driving stage circuit; and the emitter of the first amplifying unit circuit is grounded; The second end of the first resistor is connected to the second end of the third capacitor, and the second end of the third inductor is connected to the first power supply.

4. The broadband on-chip driver amplifier according to claim 1, wherein: The power divider includes a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor, a fourth inductor, a fifth inductor and a balancing resistor; The first end of the fourth inductor is respectively connected to the first input end of the power divider, the first end of the fourth capacitor, the first end of the sixth capacitor, and the first end of the fifth inductor; the second end of the fourth inductor is respectively connected to the first end of the fifth capacitor, the first end of the balancing resistor, and the first output end of the power divider; the second end of the fourth capacitor, the second end of the fifth capacitor, and the second end of the sixth capacitor are all grounded; The second end of the fifth inductor is respectively connected to the first end of the seventh capacitor, the second end of the balancing resistor and the second output end of the power divider, and the second end of the seventh capacitor is grounded.

5. The broadband on-chip driver amplifier according to claim 1, wherein: The inter-stage matching circuit includes a sixth inductor, a seventh inductor, an eighth inductor, an eighth capacitor, a ninth capacitor, a tenth capacitor and an eleventh capacitor; The first end of the sixth inductor is connected to the first input end of the inter-stage matching circuit and the first end of the eighth capacitor respectively, the second end of the sixth inductor is connected to the first end of the ninth capacitor, the first end of the eleventh capacitor and the first end of the eighth inductor respectively, and the second end of the eighth capacitor, the second end of the ninth capacitor and the second end of the eleventh capacitor are all grounded; The second end of the eighth inductor is connected to the first output end of the inter-stage matching circuit; The first end of the seventh inductor is connected to the second input end of the inter-stage matching circuit and the first end of the tenth capacitor respectively, the second end of the seventh inductor is connected to the second output end of the inter-stage matching circuit, and the second end of the tenth capacitor is grounded.

6. The broadband on-chip driver amplifier according to claim 3, wherein: The final stage circuit includes a second amplifying unit circuit, a third amplifying unit circuit, a ninth inductor, and a tenth inductor; The base of the second amplifying unit circuit is connected to the first input terminal of the final stage circuit and the second input terminal of the active bias circuit respectively, the collector of the second amplifying unit circuit is connected to the first output terminal of the final stage circuit and the first terminal of the ninth inductor respectively, the emitter of the second amplifying unit circuit is grounded, and the second terminal of the ninth inductor is connected to a second power supply; The base of the third amplifying unit circuit is respectively connected to the second input terminal of the final stage circuit and the third input terminal of the active bias, the collector of the third amplifying unit circuit is respectively connected to the second output terminal of the final stage circuit and the first terminal of the tenth inductor, the emitter of the third amplifying unit circuit is grounded, and the second terminal of the tenth inductor is connected to the third power supply.

7. The broadband on-chip driver amplifier according to claim 6, wherein: The first amplifying unit circuit is composed of four first amplifying units with the same structure connected in parallel, the second amplifying unit circuit is composed of eight second amplifying units with the same structure connected in parallel, and the third amplifying unit circuit is composed of eight third amplifying units with the same structure connected in parallel. The first amplifying unit, the second amplifying unit and the third amplifying unit have the same structure. The bases of the four first amplifying units are connected in parallel to the base of the first amplifying unit circuit, the collectors of the four first amplifying units are connected in parallel to the collector of the first amplifying unit circuit, the emitters of the four first amplifying units are connected in parallel to the emitter of the first amplifying unit circuit, and the signal input terminals of the four first amplifying units are connected in parallel to the first input terminal of the active bias circuit; The bases of the eight second amplifying units are connected in parallel to the base of the second amplifying unit circuit, the collectors of the eight second amplifying units are connected in parallel to the collector of the second amplifying unit circuit, the emitters of the eight second amplifying units are connected in parallel to the emitter of the second amplifying unit circuit, and the signal input terminals of the eight second amplifying units are connected in parallel to the second input terminal of the active bias circuit; The bases of the eight third amplifying units are connected in parallel to the base of the third amplifying unit circuit, the collectors of the eight third amplifying units are connected in parallel to the collector of the third amplifying unit circuit, the emitters of the eight third amplifying units are connected in parallel to the emitter of the third amplifying unit circuit, and the signal input ends of the eight third amplifying units are connected in parallel to the third input end of the active bias circuit.

8. The broadband on-chip driver amplifier according to claim 7, wherein: The first amplifying unit includes a DC blocking capacitor, a ballast resistor, a bias resistor and a transistor; The first end of the DC blocking capacitor is connected to the base of the first amplifying unit, and the second end of the DC blocking capacitor is connected to the first end of the ballast resistor and the first end of the bias resistor respectively; The second end of the ballast resistor is connected to the base of the transistor, and the second end of the bias resistor is connected to the first input end of the active bias circuit; The collector of the triode is connected to the collector of the first amplifying unit, and the emitter of the triode is connected to the emitter of the first amplifying unit.

9. The broadband on-chip driver amplifier according to claim 1, wherein: The output matching circuit includes a substrate pre-matching circuit and a PCB matching circuit, wherein a first input end of the substrate pre-matching circuit is connected to a first input end of the output matching circuit, a second input end of the substrate pre-matching circuit is connected to a second input end of the output matching circuit, a first output end of the substrate pre-matching circuit is connected to a first input end of the PCB matching circuit, a second output end of the substrate pre-matching circuit is connected to a second input end of the PCB matching circuit, and an output end of the PCB matching circuit is connected to an output end of the output matching circuit; The substrate pre-matching circuit includes an eleventh inductor, a twelfth inductor, a twelfth capacitor, and a thirteenth capacitor, and the PCB matching circuit includes a thirteenth inductor, a fourteenth capacitor, a fifteenth capacitor, a sixteenth capacitor, and a seventeenth capacitor; The first end of the eleventh inductor is connected to the first input end of the substrate pre-matching circuit and the first end of the twelfth capacitor respectively, the second end of the eleventh inductor is connected to the first output end of the substrate pre-matching circuit, and the second end of the twelfth capacitor is grounded; A first end of the twelfth inductor is connected to the second input end of the substrate pre-matching circuit and a first end of the thirteenth capacitor respectively, a second end of the twelfth inductor is connected to the second output end of the substrate pre-matching circuit, and a second end of the thirteenth capacitor is grounded; A first end of the thirteenth inductor is connected to the first input end of the PCB matching circuit and the first end of the fourteenth capacitor, respectively; a second end of the thirteenth inductor is connected to the first end of the fifteenth capacitor and the first end of the seventeenth capacitor, respectively; a second end of the seventeenth capacitor is connected to the output end of the PCB matching circuit; and a second end of the fourteenth capacitor is grounded; The second end of the fifteenth capacitor is connected to the first input end of the PCB matching circuit and the first end of the sixteenth capacitor respectively, and the second end of the sixteenth capacitor is grounded.

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