Gain compensation circuit and electronic equipment

Abstract

The invention relates to the technical field of electronic circuits, and provides a gain compensation circuit and an electronic device. The gain compensation circuit comprises a dynamic range enhancement unit, a storage unit and a compensation gain calculation unit. According to the scheme provided by the invention, the difference value between the second-stage gain value and the first-stage gain value is taken as the digital compensation gain while the gain amplification effect of the analog signal in the analog-to-digital conversion process is not changed, and the gain compensation operation is performed on the digital signal to be adjusted, so that the digital signal to be adjusted can be adjusted without configuring a multiplier or a divider. Therefore, the gain compensation operation in the analog-to-digital conversion process of the analog signal can be realized, and the implementation cost of the gain compensation circuit is reduced.

Description

Technical Field

[0001] The present application belongs to the technical field of electronic circuits, and in particular, relates to a gain compensation circuit and an electronic device. Background Art

[0002] At present, as intelligent electronic devices are widely used in various fields, the audio interaction function of electronic devices has also become one of the important ways to improve the intelligence of electronic devices. When using electronic devices to send and receive audio signals, since the audio signals are analog signals, they need to be converted into analog-to-digital signals. And in the process of analog-to-digital conversion, a gain compensation circuit needs to be used to compensate the analog signal for gain.

[0003] However, after the compensated analog signal is converted into a digital signal, the digital signal needs to be adjusted and outputted through a multiplier or a divider in the gain compensation circuit. In this case, a multiplier and its peripheral circuits, or a divider and its peripheral circuits need to be configured in the gain compensation circuit, which makes the implementation cost of the gain compensation circuit too high. Summary of the invention

[0004] The purpose of the present application is to provide a gain compensation circuit, aiming to solve the problem of excessively high implementation cost of traditional gain compensation circuits.

[0005] A first aspect of an embodiment of the present application provides a gain compensation circuit, comprising:

[0006] A dynamic range enhancement unit, configured to output first gain index information and second gain index information;

[0007] A storage unit, used to determine a first-level gain value according to the first gain index information, and to determine a second-level gain value according to the second gain index information; wherein the first-level gain value is a preset constant; and the second-level gain value is used to indicate a multiple of gain amplification of an analog signal;

[0008] The compensation gain calculation unit is used to receive the digital signal to be adjusted, perform a gain compensation operation on the digital signal to be adjusted based on the difference between the second-stage gain value and the first-stage gain value, and output a target digital signal; wherein the digital signal to be adjusted is obtained by performing analog-to-digital conversion after gain amplification on the analog signal.

[0009] A second aspect of an embodiment of the present application provides an electronic device, comprising the gain compensation circuit provided by the first aspect.

[0010] Compared with the prior art, the embodiments of the present invention have the following beneficial effects: the above-mentioned gain compensation circuit includes a dynamic range enhancement unit, a storage unit, and a compensation gain calculation unit. The dynamic range enhancement unit outputs first gain index information and second gain index information. Since the storage unit is configured with a corresponding relationship between the gain index information and gain values ​​of different levels, the storage unit can be used to determine the first-level gain value according to the first gain index information, and the second-level gain value according to the second gain index information. Since the first-level gain value is a preset constant, and in the process of analog-to-digital conversion of the analog signal, the second-level gain value is used to indicate the multiple of gain amplification of the analog signal, and the analog signal after gain amplification can be converted into a digital signal to be adjusted after analog-to-digital conversion, the compensation gain calculation unit can perform a gain compensation operation on the digital signal to be adjusted based on the difference between the second-level gain value and the first-level gain value when receiving the digital signal to be adjusted, and then output the target digital signal. The solution of the present application uses the difference between the second-stage gain value and the first-stage gain value as the digital compensation gain to perform a gain compensation operation on the digital signal to be adjusted, while not changing the gain amplification effect of the analog signal in the analog-to-digital conversion process. This achieves the gain compensation operation of the analog signal in the analog-to-digital conversion process without configuring a multiplier or divider, thereby reducing the implementation cost of the gain compensation circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a schematic diagram of a gain compensation circuit in a related scheme;

[0012] Figure 2 A schematic diagram of the structure of a gain compensation circuit provided in an embodiment of the present application;

[0013] Figure 3 A schematic diagram of the structure of a gain compensation circuit provided by another embodiment of the present application;

[0014] Figure 4 A schematic diagram of the structure of a gain compensation circuit provided in yet another embodiment of the present application;

[0015] Figure 5 It is a schematic diagram of the overall scheme of the embodiment of the present application;

[0016] Figure 6 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0017] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0018] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0019] It should be understood that the orientation or position relationship indicated by terms such as "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside" and "outside" are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0020] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0021] As smart electronic devices are widely used in various fields, the audio interaction function of electronic devices has become one of the important ways to improve the intelligence of electronic devices. When using electronic devices to send and receive audio signals, since the audio signals are analog signals, they need to be converted to digital signals. And in the process of analog-to-digital conversion, a gain compensation circuit needs to be used to compensate the analog signal for gain.

[0022] Figure 1 FIG. 2 shows a schematic diagram of a gain compensation circuit in a related scheme. Figure 1As shown, in some existing schemes, in the process of analog-to-digital conversion of an analog signal, when the analog signal needs to be gain-amplified, the dynamic range enhancement unit provides an analog gain to the analog gain control unit (Programmable Gain Amplifier, PGA), and provides a digital compensation gain to the compensation gain calculation unit. Here, the dynamic range enhancement unit is usually referred to as DRE or DRE unit, and the analog gain control unit can also be referred to as PGA or PGA unit. The analog-to-digital conversion unit performs analog-to-digital conversion on the gain-amplified analog signal to obtain a digital signal to be adjusted. Here, since the analog gain control unit performs a gain amplification operation on the received analog signal according to the analog gain, the signal is amplified according to a certain gain amplification factor, so the digital compensation gain provided by the dynamic range enhancement unit meets a certain proportional relationship with the analog gain. That is, when the dynamic range enhancement unit provides the digital compensation gain, it is necessary to use a multiplier or a divider to calculate the digital compensation gain based on the analog gain. In this way, it is also necessary to configure a corresponding peripheral circuit for the multiplier, or to configure a corresponding peripheral circuit for the divider, so that the implementation cost of the gain compensation circuit is too high.

[0023] In order to solve the above technical problems, an embodiment of the present application provides a gain compensation circuit, including a dynamic range enhancement unit, a storage unit and a compensation gain calculation unit. The dynamic range enhancement unit outputs first gain index information and second gain index information. Since the storage unit is configured with a correspondence between the gain index information and different levels of gain values, the storage unit can be used to determine the first-level gain value according to the first gain index information, and the second-level gain value can be determined according to the second gain index information. Since the first-level gain value is a preset constant, and in the process of analog-to-digital conversion of the analog signal, the second-level gain value is used to indicate the multiple of gain amplification of the analog signal, and the analog signal after gain amplification can be converted into digital form to obtain a digital signal to be adjusted. Therefore, when the compensation gain calculation unit receives the digital signal to be adjusted, it can perform a gain compensation operation on the digital signal to be adjusted based on the difference between the second-level gain value and the first-level gain value, and then output the target digital signal. The solution of the present application uses the difference between the second-stage gain value and the first-stage gain value as the digital compensation gain to perform a gain compensation operation on the digital signal to be adjusted, while not changing the gain amplification effect of the analog signal in the analog-to-digital conversion process. This achieves the gain compensation operation of the analog signal in the analog-to-digital conversion process without configuring a multiplier or divider, thereby reducing the implementation cost of the gain compensation circuit.

[0024] See also Figure 2 , Figure 2A schematic diagram of the structure of a gain compensation circuit provided in an embodiment of the present application is shown. For ease of explanation, only the part related to the present embodiment is shown, which is described in detail as follows:

[0025] exist Figure 2 In the embodiment, the gain compensation circuit 100 includes: a dynamic range enhancement unit 10, a storage unit 20 and a compensation gain calculation unit 30. Specifically:

[0026] The dynamic range enhancement unit 10 is configured to output first gain index information and second gain index information.

[0027] The storage unit 20 is used to determine the first-level gain value according to the first gain index information, and determine the second-level gain value according to the second gain index information; wherein the first-level gain value is a preset constant; and the second-level gain value is used to indicate the multiple of gain amplification of the analog signal.

[0028] The compensation gain calculation unit 30 is used to receive the digital signal to be adjusted, perform a gain compensation operation on the digital signal to be adjusted based on the difference between the second-stage gain value and the first-stage gain value, and output a target digital signal; wherein the digital signal to be adjusted is an analog signal that is gain amplified and then converted into an analog-to-digital signal.

[0029] In this embodiment, the first gain index information and the second gain index information output by the dynamic range enhancement unit 10 may also be collectively referred to as gain index information. Here, the gain index information is used to search for or indicate a specific gain value.

[0030] It is understandable that, in the process of performing analog-to-digital conversion on an analog signal, if there is a need to amplify the analog signal, the dynamic range enhancement unit 10 can output different gain index information according to different gain amplification requirements. That is, in the first gain index information and the second gain index information, the first and the second are only used to distinguish different gain values ​​corresponding to different gain index information.

[0031] In a specific implementation, the dynamic range enhancement unit 10 may determine whether to perform a gain compensation operation according to the real-time mode conversion of the analog signal.

[0032] For example, in the process of performing analog-to-digital conversion on an analog signal, the analog-to-digital conversion unit (not shown in the figure) feeds back the digital signal to be adjusted to the dynamic range enhancement unit 10, the dynamic range enhancement unit 10 receives the digital signal to be adjusted, and when determining to perform a gain compensation operation based on the digital signal to be adjusted, outputs first gain index information and second gain index information.

[0033] In a specific implementation, the dynamic range enhancement unit 10 can also adjust the gain compensation strategy according to the actual output digital signal, that is, the target digital signal, and then output the first gain index information and the second gain index information. In addition, when the analog signal does not need to be amplified, the dynamic range enhancement unit 10 may not output any gain index information.

[0034] As an embodiment, the dynamic range enhancement unit 10 includes: a DRE controller, configured to output first gain index information in a first working state, and output second gain index information in a second working state.

[0035] In this embodiment, the first working state can be understood as a general state, that is, a state where gain compensation is not required for the digital signal to be adjusted. The second working state can be understood as an enhanced state, that is, a working state where gain compensation is required for the digital signal to be adjusted.

[0036] In some embodiments, the DRE controller may first enter the first working state and then switch to the second working state. That is, the DRE controller may first enter the first working state and after outputting the first gain index information, switch to the second working state and then output the second gain index information.

[0037] In other embodiments, the DRE controller may also output the first gain index information and the second gain index information simultaneously in the first working state. In the first working state, the first gain index information and the second gain index information output by the DRE controller may point to the same gain value, and the gain magnification corresponding to the gain value may be 0. Accordingly, the DRE controller may also output the first gain index information and the second gain index information simultaneously in the second working state. Different from the first working state, in the second working state, the first gain index information output by the DRE controller may point to a gain value that may be a preset constant, and the second gain index information output by the DRE controller may point to a gain value that is greater than the above-mentioned preset constant, that is, the gain magnification indicated by the gain value is greater than the above-mentioned preset constant.

[0038] It is understandable that, in the process of analog-to-digital conversion of an analog signal, if the analog signal is gain-amplified and the gain-amplified analog signal is converted into a digital signal to be adjusted, it is necessary to perform gain compensation on the digital signal to be adjusted to restore the signal content, thereby avoiding signal distortion. Based on this, when it is determined that the analog signal needs to be gain-amplified based on attribute information such as the signal strength or signal assignment of the analog signal, it is necessary to determine that the corresponding digital signal to be adjusted needs to be gain-compensated to restore the signal content.

[0039] In one embodiment, the DRE controller is specifically used to receive a digital signal to be adjusted, and output first gain index information when entering a first working state according to the digital signal to be adjusted, and output second gain index information when entering a second working state according to the digital signal to be adjusted.

[0040] In this embodiment, the digital signal to be adjusted may be a signal fed back by an analog-to-digital conversion unit (not shown) to the DRE controller. When the DRE controller determines that no gain compensation operation is required according to the digital signal to be adjusted, the DRE controller enters a first working state and outputs first gain index information. When the DRE controller determines that a gain compensation operation is required according to the digital signal to be adjusted, the DRE controller enters a second working state and outputs second gain index information.

[0041] In another embodiment, the DRE controller is specifically used to receive a historical target digital signal, and when entering the first working state according to the historical target digital signal, output the first gain index information, and when entering the second working state according to the historical target digital signal, output the second gain index information.

[0042] In this embodiment, the historical target digital signal may be a signal fed back by the compensation gain calculation unit 30. Here, the historical target digital signal may be obtained by performing analog-to-digital conversion based on the historical analog signal received in the previous analog-to-digital conversion cycle. When the DRE controller determines that it is not necessary to perform gain amplification on the analog signal in the current analog-to-digital conversion cycle based on the historical target digital signal, it enters a first working state and outputs first gain index information. When the DRE controller determines that it is necessary to perform gain amplification on the analog signal in the current analog-to-digital conversion cycle based on the historical target digital signal, it enters a second working state and outputs second gain index information.

[0043] Exemplarily, in a specific implementation, a corresponding mapping list may be configured in the storage unit 20, and the information in the mapping list describes the correspondence between different gain index information and different gain values. Therefore, the storage unit 20 may determine the first-level gain value according to the first gain index information, and determine the second-level gain value according to the second gain index information.

[0044] In this embodiment, the storage unit 20 determines the first-level gain value according to the first gain index information. Since the first-level gain value is a preset constant, the first-level gain value is only used as a reference benchmark and is not used for gain amplification of the analog signal. Here, the storage unit 20 also determines the second-level gain value according to the second gain index information. Among them, although the second-level gain value is used to indicate the multiple of gain amplification of the analog signal. Because the second-level gain value is used to indicate the multiple of gain amplification of the analog signal, the degree of amplification of the analog signal can be obtained according to the second-level gain value, which can be used to further determine the degree of gain compensation of the digital signal to be adjusted.

[0045] In this embodiment, the compensation gain calculation unit 30 is configured to perform a gain compensation operation on the digital signal to be adjusted. Specifically, when receiving the digital signal to be adjusted, the compensation gain calculation unit 30 performs a gain compensation operation on the digital signal to be adjusted based on the difference between the second-stage gain value and the first-stage gain value, and outputs a target digital signal.

[0046] In a specific implementation, the digital signal to be adjusted can be obtained by performing analog-to-digital conversion on the analog signal after gain amplification by an analog-to-digital conversion unit, and the analog-to-digital conversion unit provides the digital signal to be adjusted to the compensation gain calculation unit 30. Since the first-stage gain value is a preset constant, the second-stage gain value is used to indicate the multiple of gain amplification of the analog signal, so the difference between the second-stage gain value and the first-stage gain value can be used to characterize the degree of gain compensation for the digital signal to be adjusted. A corresponding index table can be configured in the compensation gain calculation unit 30, and the corresponding relationship between the above-mentioned difference and the gain compensation value is described by the information in the index table. That is, according to the difference between the second-stage gain value and the first-stage gain value, a specific gain compensation value is determined from the index table, and a gain compensation operation is performed on the digital signal to be adjusted.

[0047] In practical applications, when performing analog-to-digital conversion on an analog signal, an analog gain control unit, namely, PGA, is used to amplify the analog signal. Since the PGA has certain manufacturing errors, the gain amplification factor of the analog signal is not an ideal amplification factor or a calibrated amplification factor.

[0048] For example, the calibrated amplification factor of the PGA is 2 times, but the analog signal that is gain-amplified by the PGA is only amplified 1.9 times.

[0049] It can be understood that, without considering the PGA manufacturing error, different levels of gain values ​​can be adapted only for different gain index information.

[0050] As an embodiment, the storage unit 20 may include: a first memory configured with a first preset gain table. The first memory is used to determine a first-level gain value from the first preset gain table according to the first gain index information, and to determine a second-level gain value from the first preset gain table according to the second gain index information.

[0051] In this embodiment, the information in the first preset gain table is used to describe the correspondence between gain index information and gain values. Here, gain index information generally refers to index information used to query gain values ​​corresponding to different levels from the first preset gain table.

[0052] It can be understood that if the PGA manufacturing error is taken into consideration, a corresponding error compensation strategy can be configured for the manufacturing errors corresponding to different levels of PGA. After determining the gain value of the corresponding level according to the gain index information, the error compensation is added to balance the gain amplification error caused by the manufacturing error as much as possible.

[0053] As an embodiment, the storage unit 20 includes:

[0054] The register group is used to store the first compensation gain value and the second compensation gain value.

[0055] The second memory is configured with a second preset gain table. The second memory is used to determine the first gain value from the second preset gain table according to the first gain index information, and to determine the second gain value from the second preset gain table according to the second gain index information.

[0056] The register group is further used to obtain the first compensation gain value according to the first gain index information, and to obtain the second compensation gain value according to the second gain index information.

[0057] The adder is used to calculate the sum of the first compensation gain value and the first gain value as the first-stage gain value, and to calculate the sum of the second compensation gain value and the second gain value as the second-stage gain value.

[0058] In this embodiment, the information in the second preset gain table is used to characterize the correspondence between the gain index information and the gain value. Similar to the above embodiment, the gain index information here generally refers to the index information used to query different gain values ​​from the second preset gain table. In addition, in this embodiment, the first compensation gain value and the second compensation gain value stored in the register group are respectively used to compensate for the manufacturing errors of different gain amplification levels of the PGA. That is, when the second memory determines the first gain value from the second preset gain table according to the first gain index information, the register group obtains the first compensation gain value according to the first gain index information, and then calculates the sum of the first compensation gain value and the first gain value through the adder, thereby obtaining the first-level gain value. When the second memory determines the second gain value from the second preset gain table according to the second gain index information, the register group obtains the second compensation gain value according to the second gain index information, and then calculates the sum of the second compensation gain value and the second gain value through the adder, thereby obtaining the second-level gain value.

[0059] It is easy to understand that the second memory can be specifically a read-only memory (ROM). In this embodiment, by configuring the register group, the second memory and the adder, the manufacturing error of the PGA can be taken into account, and the effect of adjusting the digital signal to be adjusted can be further optimized, thereby improving the accuracy of signal restoration.

[0060] In a specific implementation, the register group can be set according to the actual gain amplification stage of the PGA. That is, the number of registers in the register group is positively correlated with the gain amplification stage of the PGA. Alternatively, the number of registers in the register group is equal to the gain amplification stage of the PGA.

[0061] For example, the actual number of amplification stages of the PGA is N, and accordingly the register group may include N registers.

[0062] As an embodiment, the register group includes: N registers, where N is a positive integer greater than 1. The N registers are used to store N compensation gain values ​​corresponding to N gain magnifications of an analog gain control unit (ie, PGA).

[0063] It is easy to understand that the N compensation gain values ​​corresponding to the N gain magnifications can also be understood as the one-to-one correspondence between the N gain magnifications and the N compensation gain values. In practice, the compensation gain values ​​between the N gain magnifications can be partially the same or completely different, which is specifically determined according to the production error at the time. That is, among the N compensation gain values, there may be a situation where some compensation gain values ​​are the same in value. Of course, among the N compensation gain values, there may also be a situation where N compensation gain values ​​are completely different in value.

[0064] Corresponding to the above embodiment, as an embodiment, the N registers are specifically used to obtain a first compensation gain value from the N compensation gain values ​​according to the first gain index information, and to obtain a second compensation gain value from the N compensation gain values ​​according to the second gain index information.

[0065] It is easy to understand that there is only a difference in numerical value between the first compensation gain value and the second compensation gain value, so without distinguishing the numerical value, the first compensation gain value and the second compensation gain value can be collectively referred to as compensation gain value. Here, the compensation gain value is used to characterize the gain part used to balance the PGA manufacturing error during the adjustment of the digital signal to be adjusted.

[0066] As an embodiment, the compensation gain calculation unit 30 is configured with a logarithmic gain table.

[0067] The compensation gain calculation unit 30 is specifically used to determine a target gain value from the logarithmic gain table based on the difference between the second-stage gain value and the first-stage gain value, and to compensate the digital signal to be adjusted using the target gain value to output a target digital signal.

[0068] In this embodiment, the information in the logarithmic gain table is used to describe the corresponding relationship between the difference between the second-stage gain value and the first-stage gain value and the target gain value.

[0069] In a specific implementation, the logarithmic gain table can be configured on a processor with input and output functions, and the processor can take the difference between the second-stage gain value and the first-stage gain value, and the digital signal to be adjusted as input, and take the target digital signal as output. Alternatively, the second-stage gain value, the first-stage gain value, and the digital signal to be adjusted can be taken as input, and the target digital signal can be taken as output.

[0070] As a possible implementation method, the compensation gain calculation unit 30 can also be a logarithmic gain calculator. For example, a logarithmic gain calculation script can be configured for a programmable processing chip, and a corresponding logarithmic gain table can be configured in the script to describe the difference between the second-stage gain value and the first-stage gain value and the corresponding relationship between the target gain value. As shown in Table 1 below, Table 1 shows an implementation example of a logarithmic gain table.

[0071] △G Target gain value 0x400 0db 0x3ff -0.09db 0x3fe -0.18db 0x3fd -0.27db

[0072] Table 1

[0073] In Table 1, △G represents the difference between the second-stage gain value and the first-stage gain value. It can be seen from Table 1 that the maximum target gain value is 0db, and starting from 0db, it gradually decreases as △G increases. This is because when the analog signal is gain-amplified, the analog signal is amplified from a smaller signal to a larger gain signal. Therefore, in order to better restore the signal, it is necessary to perform digital gain compensation on the digital signal to be adjusted, that is, to perform a reduction operation. Therefore, in Table 1, the target gain value starts from 0db and gradually decreases as △G increases.

[0074] Taking the logarithmic gain table shown in Table 1 as an example, when the difference △G between the second-stage gain value and the first-stage gain value is 0x400, the target gain value determined from the logarithmic gain table is 0db. When the target gain value is used to compensate the digital signal to be adjusted, since the target gain value is 0db, the target digital signal can be output without gain compensation of the digital signal to be adjusted.

[0075] When the difference △G between the second-stage gain value and the first-stage gain value is 0x3fe, the target gain value determined from the logarithmic gain table is -0.18db. When the target gain value is used to compensate the digital signal to be adjusted, the digital signal to be adjusted is reduced by 0.18db, and then the target digital signal is output.

[0076] Figure 3 FIG. 2 shows a schematic diagram of a gain compensation circuit provided by another embodiment of the present application. Figure 3 As shown, as an embodiment, the gain compensation circuit 100 further includes: a first latch unit, a subtraction calculation unit and a second latch unit.

[0077] The first latch unit 40 is used to store the first stage gain value and the second stage gain value.

[0078] The subtraction calculation unit 50 is used to calculate the difference between the first stage gain value and the second stage gain value.

[0079] The second latch unit 60 is used to latch the difference.

[0080] In this embodiment, the first latch unit 40 may be a latch, and the first-stage gain value and the second-stage gain value may be stored in the register in sequence according to the existing order. The subtraction calculation unit 50 may include a subtractor for calculating the difference between the first-stage gain value and the second-stage gain value. That is, the subtractor is input by the first-stage gain value and the second-stage gain value, and outputs the difference between the two.

[0081] In a specific implementation, the dynamic range enhancement unit 10 may provide the first gain index information and the second gain index information to the storage unit 20 in sequence. When receiving the first gain index information, the storage unit 20 outputs the first-level gain value to the first latch unit 40 according to the first gain index information. Subsequently, the storage unit 20 receives the second gain index information and outputs the second-level gain value to the first latch unit 40 according to the second gain index information.

[0082] As an example, the first latch unit 40 may also be composed of two latches. For example, the first latch unit 40 includes a first latch and a second latch, wherein the first latch is used to store the first stage gain value, and the second latch is used to store the second stage gain value.

[0083] In this embodiment, the second latch unit 60 may be a latch for latching the difference between the first-stage gain value and the second-stage gain value. The compensation calculation unit 30 may obtain the difference between the first-stage gain value and the second-stage gain value from the latch for performing a gain compensation operation on the digital signal to be adjusted.

[0084] Figure 4 FIG. 2 shows a schematic diagram of a gain compensation circuit provided by another embodiment of the present application. Figure 4 As shown, as an embodiment, the gain compensation circuit 100 further includes: an analog gain control unit 70 and an analog-to-digital conversion unit 80 .

[0085] In combination with any of the above embodiments, in this embodiment, the dynamic range enhancement unit 10 is further configured to send second gain index information to the analog gain control unit 70. The analog gain control unit 70 is configured to amplify the received analog signal according to the second gain index information to obtain an amplified analog signal.

[0086] It is understandable that, in this embodiment, the second gain index information is not only used to query the second-stage gain value. Here, the second gain index information is used to instruct the analog gain control unit 70 to amplify the received analog signal with the second-stage gain value to obtain the amplified analog signal. Then, the analog-to-digital conversion unit 80 is used to perform analog-to-digital conversion on the amplified analog signal to obtain the digital signal to be adjusted.

[0087] In a specific implementation, the dynamic range enhancement unit 10 may include a DRE controller. The analog gain control unit 70 may include an amplifier with different amplification levels. The amplifier is controlled by the dynamic range enhancement unit 10, that is, by the DRE controller, and takes the analog signal as input.

[0088] Exemplarily, when the amplifier receives the second gain index information sent by the DRE controller, the amplifier selects the corresponding gain magnification factor according to the second gain index information, amplifies the received analog signal, and obtains the amplified analog signal. The analog-to-digital conversion unit 80 can be implemented by using an existing analog-to-digital converter or an existing circuit with an analog-to-digital conversion function, so it is not described here in detail.

[0089] Figure 5 The overall schematic diagram of the embodiment of the present application is shown. Figure 5 In the DRE state, the DRE controller is the working state of the DRE controller. The DRE controller also provides a normal gain index G1 and an enhanced gain index G2. For example, the DRE controller receives a historical target digital signal fed back by a compensation gain calculator.

[0090] Specifically, after the DRE controller receives the historical target digital signal, it determines to enter the corresponding DRE state according to the historical target digital signal. Here, the DRE state may include a first working state and a second working state. That is, the first working state may be a general state, and the second working state may be an enhanced state.

[0091] When the DRE controller determines that the amplitude of the historical target digital signal is greater than a certain threshold value within a certain period of time, the DRE controller enters the first working state, that is, the general state. When the DRE controller determines that the amplitude of the historical target digital signal is equal to or less than a certain threshold value within a certain period of time, the DRE controller enters the second working state, that is, the enhanced state.

[0092] When the DRE state of the DRE controller is in the general state, the DRE controller selects the normal gain index G1 (constant) from the gain table as input, and outputs the gain coefficient GT1 of the corresponding gear by searching the gain table. At the same time, the compensation value GC1 of the corresponding gear is selected from the analog gain compensation register group GC according to the normal gain index G1, and then the result of adding the gain coefficient GT1 and the compensation value GC1 is latched into the normal gain register.

[0093] When the DRE state of the DRE controller is in the enhanced state, the gain table selects the enhanced gain index G2 as input, and the DRE controller outputs the gain coefficient GT2 of the corresponding gear by searching the gain table. At the same time, the compensation value GC2 of the corresponding gear is selected from the analog gain compensation register group GC according to the enhanced gain index G2, and then the result of adding the gain coefficient GT2 and the compensation value GC2 is latched into the enhanced gain register.

[0094] The compensation gain G3 is obtained by subtracting GR2 from GR1 through a subtractor, and the input data, that is, the digital signal to be adjusted, is amplified / reduced by the corresponding db value according to the compensation gain G3 using a logarithmic gain calculator.

[0095] Figure 6 FIG. 1 is a schematic diagram showing the structure of an electronic device provided by an embodiment of the present application. Figure 6 As shown, the electronic device 200 includes the gain compensation circuit 100 provided in any one of the embodiments of the present application.

[0096] exist Figure 6 In the electronic device 200 shown, the analog signal may be an analog signal generated in the electronic device, or an analog signal received by the electronic device 200. Similarly, the digital signal may be a digital signal generated in the electronic device, or a digital signal received by the electronic device 200.

[0097] It is easy to understand that the electronic device 200 provided in this embodiment can be any electronic product with analog-to-digital conversion function. For example, mobile terminals such as mobile phones and tablet computers. Another example is a product with voice interaction function such as a voice robot and smart speakers. Another example is a wearable device with audio signal receiving and transmitting function such as a smart bracelet, a phone watch, and a wireless headset.

[0098] It is understandable that in Figure 6 In the embodiment shown, due to the improvements and specific implementations related to the present application, Figures 2 to 5 The corresponding embodiments are described in detail, so they will not be described again here.

[0099] Those skilled in the art can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example. In actual applications, the above-mentioned functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units.

[0100] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A gain compensation circuit, characterized in that: include: A dynamic range enhancement unit, configured to output first gain index information and second gain index information; A storage unit, used to determine a first-level gain value according to the first gain index information, and to determine a second-level gain value according to the second gain index information; wherein the first-level gain value is a preset constant; and the second-level gain value is used to indicate a multiple of gain amplification of an analog signal; The compensation gain calculation unit is used to receive the digital signal to be adjusted, perform a gain compensation operation on the digital signal to be adjusted based on the difference between the second-stage gain value and the first-stage gain value, and output a target digital signal; wherein the digital signal to be adjusted is obtained by performing analog-to-digital conversion after gain amplification on the analog signal.

2. The gain compensation circuit according to claim 1, wherein: The dynamic range enhancement unit comprises: The DRE controller is configured to output the first gain index information in a first working state and output the second gain index information in a second working state.

3. The gain compensation circuit according to claim 2, characterized in that: The DRE controller is specifically used to receive the digital signal to be adjusted, and when entering the first working state according to the digital signal to be adjusted, output the first gain index information, and when entering the second working state according to the digital signal to be adjusted, output the second gain index information.

4. The gain compensation circuit according to claim 2, characterized in that: The DRE controller is specifically used to receive a historical target digital signal, and when entering the first working state according to the historical target digital signal, output the first gain index information, and when entering the second working state according to the historical target digital signal, output the second gain index information.

5. The gain compensation circuit according to claim 1, wherein: The storage unit comprises: A first memory configured with a first preset gain table; The first memory is used to determine a first-level gain value from the first preset gain table according to the first gain index information, and to determine a second-level gain value from the first preset gain table according to the second gain index information.

6. The gain compensation circuit according to claim 1, wherein: The storage unit comprises: A register group, used to store a first compensation gain value and a second compensation gain value; a second memory configured with a second preset gain table; The second memory is used to determine a first gain value from the second preset gain table according to the first gain index information, and to determine a second gain value from the second preset gain table according to the second gain index information; The register group is further used to obtain the first compensation gain value according to the first gain index information, and to obtain the second compensation gain value according to the second gain index information; An adder is used to calculate the sum of the first compensation gain value and the first gain value as the first stage gain value, and to calculate the sum of the second compensation gain value and the second gain value as the second stage gain value.

7. The gain compensation circuit according to claim 6, characterized in that: The register group includes: N registers, where N is a positive integer greater than 1; The N registers are used to store N compensation gain values ​​corresponding to N gain magnifications of the analog gain control unit.

8. The gain compensation circuit according to claim 7, characterized in that: The N registers are specifically used to obtain the first compensation gain value from the N compensation gain values ​​according to the first gain index information, and to obtain the second compensation gain value from the N compensation gain values ​​according to the second gain index information.

9. The gain compensation circuit according to claim 1, wherein: The compensation gain calculation unit is configured with a logarithmic gain table; The compensation gain calculation unit is specifically used to determine a target gain value from the logarithmic gain table based on the difference between the second-stage gain value and the first-stage gain value, and use the target gain value to compensate the digital signal to be adjusted to output a target digital signal.

10. The gain compensation circuit according to claim 1, wherein: Also includes: A first latch unit, used for storing the first-stage gain value and the second-stage gain value; a subtraction calculation unit, configured to calculate a difference between the first-stage gain value and the second-stage gain value; The second latch unit is used to latch the difference.

11. The gain compensation circuit according to any one of claims 1 to 10, characterized in that: Also includes: Analog gain control unit and analog-to-digital conversion unit; The dynamic range enhancement unit is further configured to send the second gain index information to the analog gain control unit; The analog gain control unit is used to amplify the received analog signal according to the second gain index information to obtain an amplified analog signal; The analog-to-digital conversion unit is used to perform analog-to-digital conversion on the amplified analog signal to obtain a digital signal to be adjusted.

12. The gain compensation circuit according to claim 11, wherein: The analog gain control unit is specifically configured to select a corresponding gain amplification factor according to the second gain index information, amplify the received analog signal, and obtain an amplified analog signal.

13. An electronic device, characterized in that: The electronic device comprises the gain compensation circuit according to any one of claims 1 to 12.

Images