OPA linear offset calibration circuit

Abstract

The invention provides an OPA linear offset calibration circuit, and the circuit is characterized in that the circuit comprises a comparison module which compares the voltages of the positive and negative input ends of an operational amplifier, and obtains an offset voltage; the positive end calibration module is used for calibrating by adopting a decoding calibration mode when the offset voltage is less than zero; and the negative end calibration module is used for calibrating by adopting a binary calibration mode when the offset voltage is greater than zero. According to the invention, decoding calibration is adopted for negative offset, binary calibration is adopted for positive offset, continuous linear calibration is realized, decoding calibration is only adopted for negative offset, one high bit b < it > is omitted, logic control units required by decoding calibration are reduced, and decoding is simpler.

Description

Technical Field

[0001] The present invention relates to the field of operator offset calibration, and in particular to an OPA linear offset calibration circuit. Background Art

[0002] Currently, there are two main methods for the offset calibration of the operator: first, binary calibration; and second, decoding calibration.

[0003] The binary calibration has the advantages of simple structure, easy implementation and few components. Figure 4 As shown, the trim control bits must be separated from the negative end and the positive end, which will result in a waste of X-1 bits of register. In addition, the trim is not continuous because the negative end and the positive end are divided into two sections, and the offset is 0 to the negative maximum and 0 to the positive maximum, respectively, which affects the CP efficiency.

[0004] Decoding calibration improves the calibration by decoding the input register into binary, so the logic control needs to be increased accordingly. The output bit width is two times the input bit width. Figure 5 As shown in the figure, compared with binary calibration, the decoding calibration trip control register is reduced by nearly half, and the offset range increases linearly from the most negative to the most positive, which facilitates CP testing. However, since the corresponding logic control needs to be increased, if the calibration bit width is large, decoding requires a lot of logic control. Summary of the invention

[0005] In order to solve the above problems, the present invention provides an OPA linear offset calibration circuit, which is characterized by comprising:

[0006] A comparison module compares the voltages at the positive and negative input terminals of the operational amplifier to obtain an offset voltage;

[0007] A positive terminal calibration module, when the offset voltage is less than zero, performs calibration in a decoding calibration mode;

[0008] The negative terminal calibration module adopts a binary calibration mode for calibration when the offset voltage is greater than zero.

[0009] In one embodiment of the present invention, the positive-end calibration module includes (N+1) / 2 decoding control units, which are connected in parallel to form the positive-end calibration module, wherein N is a positive integer greater than or equal to 1, and the number of the decoding control units is rounded up.

[0010] In another embodiment of the present invention, the decoding control unit includes: a first MOS tube M1, a first controllable current source I5;

[0011] The source of the first MOSFET M1 is connected to the negative end calibration module, the drain of the first MOSFET M1 is connected to the first controllable current source, and the gate of the first MOSFET M1 outputs a voltage signal VIP.

[0012] In another embodiment of the present invention, the negative terminal calibration module includes N binary control units, which are connected in parallel to form the negative terminal calibration module, wherein N is a positive integer greater than or equal to 1.

[0013] In another embodiment of the present invention, the binary control unit includes: a second MOS tube M2, a second controllable current source I2;

[0014] The source of the second MOSFET M2 is connected to the negative end calibration module, the drain of the second MOSFET M2 is connected to the second controllable current source, and the gate of the second MOSFET M2 outputs a voltage signal VI N.

[0015] In another embodiment of the present invention, the circuit further comprises a third controllable current source I 0;

[0016] The third controllable current source is connected to the positive end calibration module and the negative end calibration module to provide a bus current I_OPA.

[0017] In another embodiment of the present invention, the offset voltage is offset=X=Vg1-Vg2, wherein Vg1=VIP, Vg2=VI N, which are the gate voltages of M1 and M2 respectively.

[0018] In another embodiment of the present invention, when the offset voltage offset is a positive value, that is, Vgs1>Vgs2;

[0019] The second controllable current source I2 is used to increase the current ids2 so that I ds2 = I ds1 , and then Vgs2 = Vgs1 is maintained, thereby eliminating the offset voltage;

[0020] Where Vgs2 is the gate-source voltage of M2, Vgs1 is the gate-source voltage of M1, Ids2 is the source-drain current of M2, and Ids1 is the source-drain current of M1.

[0021] In another embodiment of the present invention, when the offset voltage offset is a negative value, that is, Vgs1 <Vgs2;

[0022] The first controllable current source I1 increases the current of ids1 so that I ds2 = I ds1 , and then maintains Vgs2 = Vgs1 , thereby eliminating the offset voltage.

[0023] In another embodiment of the present invention, when the offset voltage offset is zero, Vgs2 = Vgs1; I ds2 = I ds1 = I_OPA / 2.

[0024] Compared with the prior art, the present invention has the following beneficial effects:

[0025] (1) Compared with binary calibration, the present invention adopts decoding calibration for negative offset and binary calibration for positive offset, thereby realizing continuous linear calibration.

[0026] (2) Compared with decoding calibration, the present invention adopts decoding calibration only for negative offset, processes one less high-order bit, reduces the logic control unit required for decoding calibration, and makes decoding more concise. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 A schematic diagram of a calibration circuit in one embodiment of the present invention is shown;

[0028] Figure 2 A comparison diagram of technical effects in one embodiment of the present invention is shown;

[0029] Figure 3 A comparison diagram of simulation effect and binary calibration in one embodiment of the present invention is shown;

[0030] Figure 4 A binary calibration circuit diagram in the prior art is shown;

[0031] Figure 5 The decoding calibration circuit diagram in the prior art is shown;

[0032] Figure 6 A data chart of a binary calibration method in the prior art is shown; and

[0033] Figure 7 A data chart of a decoding calibration method in the prior art is shown. Specific embodiments

[0034] In the following description, the present invention is described with reference to various embodiments. However, those skilled in the art will recognize that various embodiments can be implemented without one or more specific details or with other replacement and / or additional methods, materials or components. In other cases, well-known structures, materials or operations are not shown or described in detail to avoid blurring the inventive point of the present invention. Similarly, for the purpose of explanation, specific quantities, materials and configurations are set forth to provide a comprehensive understanding of embodiments of the present invention. However, the present invention is not limited to these specific details. In addition, it should be understood that the various embodiments shown in the drawings are illustrative representations and are not necessarily drawn in correct proportions.

[0035] In the description of the present invention, it is necessary to understand that the terms "center", "longitudinal", "lateral", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than explicitly or implicitly indicating that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as explicitly or implicitly indicating relative importance.

[0036] In this specification, reference to "one embodiment" or "the embodiment" means that a particular feature, structure, or characteristic described in conjunction with the embodiment is included in at least one embodiment of the present invention. The phrase "in one embodiment" appearing in various places in this specification does not necessarily all refer to the same embodiment.

[0037] Figure 1 The schematic diagram of the calibration circuit in one embodiment of the present invention is shown, wherein the positive end calibration unit includes a decoding control unit, and the negative end calibration unit includes a binary control unit.

[0038] Wherein, I_OPA is the total current, and the voltage offset value is offset=X=Vg1-Vg2, where Vg1=V IP, Vg2=VIN.

[0039] When the voltage offset value offset=0, that is, Vgs2=Vgs1, I ds2=I ds1=I_OPA / 2, wherein Vgs2 is the gate-source voltage of M2, Vgs1 is the gate-source voltage of M1, I ds2 is the source-drain current of M2, and I ds1 is the source-drain current of M1.

[0040] When the voltage offset value offset>0, since the sources of M1 and M2 are collinear and have the same potential, when offset=Vg1-Vg0 is a positive value, Vgs1>Vgs0, and since all devices are working in the saturation region, where u n , C ox is the process constant, W / L is the MOS width-to-length ratio, and Vth is the MOS threshold voltage.

[0041] From the I d formula, it can be seen that I ds1>I ds2. At this time, the present invention controls the second controllable current source I 2 to adjust the I_Ntr im current, thereby increasing the I ds2 current, so that I ds2=I ds1, and then maintains Vgs2=Vgs1, so that offset=Vg1-Vg2 approaches 0. Wherein Vg1=V IP, Vg2=VI N, which are the gate voltages of M1 and M2 respectively.

[0042] On the contrary, when offset=Vg1-Vg2=X is a negative value, the I_Ptr im current is increased by the first controllable current source I1, so as to achieve the same purpose.

[0043] The specific implementation of the present invention will be described in detail below in combination with the binary calibration method and the decoding calibration method in the prior art.

[0044] In the prior art, binary calibration is performed as Figure 4 As shown, by connecting a plurality of two-stage calibration units in parallel to the positive and negative input terminals of the operational amplifier and regulating the trip current, the offset voltage of the operational amplifier can be eliminated.

[0045] Combination Figure 6 From the specific embodiment of binary calibration, it can be seen that an OPA needs 3 bits to calibrate the negative current and 3 bits to calibrate the positive current. Each step offset is 1mV, so binary calibration requires 6 bits of registers, and the calibration ranges are 0 to -7mV and 0 to 7mV respectively. Step calibration is achieved by connecting the same number of registers in parallel at the positive and negative ends.

[0046] Binary calibration has the advantages of simple structure, easy implementation and few components. Figure 6 As shown, the trim control bit must be separated into the negative and positive ends, wasting X-1 bits of register, and because the negative and positive ends are divided into two sections, the offset is 0 to the negative maximum and 0 to the positive maximum respectively. The chart clearly shows that the calibration result is divided into two ends and is not linear.

[0047] Figure 5 The schematic diagram of decoding calibration is shown. The improved calibration decodes the input register into binary, so the logic control needs to be increased accordingly, and the output bit width is two times the input bit width. That is, through the decoding process, the registers at the positive and negative input ends of the operational amplifier are controlled at the same time.

[0048] Combination Figure 7 As shown, in Figure 6In the embodiment shown, under the same conditions, the decoding calibration method only requires 4 bit registers, and the calibration range is -8mV to 7mV. By decoding and controlling the 4 bit registers, 16 output results are obtained, and the calibration of the voltage offset from -8mV to 7mV is completed. Compared with the two-level calibration, the use of decoding control requires corresponding increase in logic control. Figure 7 In the calibration shown in the figure, to realize the decoding control of the 4-bit it register, 8 three-input NAND gates, 14 two-input NAND gates, 4 two-input NOR gates, and 4 NOT gates are required. And as the decoding bandwidth increases, such as 5-bit decoding, the number of devices required doubles, and the decoding difficulty increases significantly.

[0049] The present invention combines binary calibration with decoding calibration, that is, binary calibration is used for positive offset voltage and decoding calibration is used for negative offset voltage. First, the positive and negative of the deflection voltage are determined by a comparison module. If the offset voltage is greater than 0, the binary control unit at the negative input port of the operational amplifier is used to calibrate the offset voltage. If the offset voltage is less than 0, the decoding control unit at the positive input port of the operational amplifier is used to calibrate.

[0050] like Figure 1 As shown, in one embodiment of the present invention, an OPA linear offset calibration circuit is provided, characterized in that it includes:

[0051] A comparison module compares the voltages at the positive and negative input terminals of the operational amplifier to obtain an offset voltage;

[0052] A positive terminal calibration module, when the offset voltage is less than zero, performs calibration in a decoding calibration mode;

[0053] The negative terminal calibration module adopts a binary calibration mode for calibration when the offset voltage is greater than zero.

[0054] The positive-end calibration module includes (N+1) / 2 decoding control units, which are connected in parallel to form the positive-end calibration module.

[0055] The decoding control unit comprises: a first MOS tube M1, a first controllable current source I5;

[0056] The source of the first MOSFET M1 is connected to the negative end calibration module, the drain of the first MOSFET M1 is connected to the first controllable current source, and the gate of the first MOSFET M1 outputs a voltage signal VIP.

[0057] The negative terminal calibration module includes N binary control units, which are connected in parallel to form the negative terminal calibration module.

[0058] The binary control unit comprises: a second MOS tube M2, a second controllable current source I2;

[0059] The source of the second MOSFET M2 is connected to the negative end calibration module, the drain of the second MOSFET M2 is connected to the second controllable current source, and the gate of the second MOSFET M2 outputs a voltage signal VI N.

[0060] In one embodiment of the present invention, Figure 1 The circuit diagram shown completes the calibration of the offset in the range of -2mV-1mV.

[0061] Combination Figure 2 It can be seen that in one embodiment of the present invention, for the offset calibration range of -8mV-7mV, compared with the binary system calibration, the present invention retains the binary positive continuous part and decodes the binary negative end to obtain a continuous linear calibration result.

[0062] like Figure 3 As shown, compared with the traditional simulation results, the structure of the present invention is simple and convenient, and the Offset range increases linearly from the most negative to the most positive.

[0063] Compared with the decoding calibration technology with the same linearity, the present invention processes one less high-bit bit, reduces the number of decoding devices by half, and makes decoding more concise.

[0064] The present invention is more suitable for calibration greater than 4 bits, and reduces the register bit width, reduces decoding difficulty, reduces device waste, and achieves the linear calibration target.

[0065] The terms and expressions used herein are for descriptive purposes only, and the present invention should not be limited to these terms and expressions. The use of these terms and expressions does not mean to exclude any equivalent features of the illustrations and descriptions (or parts thereof), and it should be recognized that various modifications that may exist should also be included in the scope of the claims. Other modifications, variations and substitutions may also exist. Accordingly, the claims should be deemed to cover all such equivalents.

[0066] Similarly, it should be pointed out that although the present invention has been described with reference to the current specific embodiments, ordinary technicians in this technical field should realize that the above embodiments are only used to illustrate the present invention, and various equivalent changes or substitutions may be made without departing from the spirit of the present invention. Therefore, as long as the changes and modifications to the above embodiments are within the scope of the essential spirit of the present invention, they will fall within the scope of the claims of this application.

Claims

1. An OPA linear offset calibration circuit, characterized in that: include: A comparison module compares the voltages at the positive and negative input terminals of the operational amplifier to obtain an offset voltage; A positive terminal calibration module, when the offset voltage is less than zero, performs calibration in a decoding calibration mode; The negative terminal calibration module adopts a binary calibration mode for calibration when the offset voltage is greater than zero.

2. The OPA linear offset calibration circuit according to claim 1, wherein: The positive end calibration module includes (N+1) / 2 decoding control units, which are connected in parallel to form the positive end calibration module, wherein N is a positive integer greater than or equal to 1, and the number of the decoding control units is rounded up.

3. The OPA linear offset calibration circuit according to claim 2, characterized in that: The decoding control unit comprises: a first MOS tube M1, a first controllable current source I1; The source of the first MOSFET M1 is connected to the negative end calibration module, the drain of the first MOSFET M1 is connected to the first controllable current source, and the gate of the first MOSFET M1 outputs a voltage signal VIP.

4. The OPA linear offset calibration circuit according to claim 1, wherein: The negative terminal calibration module includes N binary control units, which are connected in parallel to form the negative terminal calibration module, wherein N is a positive integer greater than or equal to 1.

5. The OPA linear offset calibration circuit according to claim 4, characterized in that: The binary control unit comprises: a second MOS tube M2, a second controllable current source I2; The source of the second MOSFET M2 is connected to the negative end calibration module, the drain of the second MOSFET M2 is connected to the second controllable current source, and the gate of the second MOSFET M2 outputs a voltage signal VIN.

6. The OPA linear offset calibration circuit according to claim 4, characterized in that: The circuit also includes a third controllable current source I0; The third controllable current source is connected to the positive end calibration module and the negative end calibration module to provide a bus current I_OPA.

7. The OPA linear offset calibration circuit according to claim 5, characterized in that: The offset voltage is offset=X=Vg1-Vg2, where Vg1=VIP, Vg2=VI N, which are the gate voltages of M1 and M2 respectively.

8. The OPA linear offset calibration circuit according to claim 7, characterized in that: When the offset voltage offset is a positive value, that is, Vgs1>Vgs2; By increasing the current of ids2 through the second controllable current source I2, Ids2=Ids1 is made, and Vgs2=Vgs1 is maintained, thereby eliminating the offset voltage; Where Vgs2 is the gate-source voltage of M2, Vgs1 is the gate-source voltage of M1, Ids2 is the source-drain current of M2, and Ids1 is the source-drain current of M1.

9. The OPA linear offset calibration circuit according to claim 8, characterized in that: When the offset voltage offset is negative, that is, Vgs1 <Vgs2; The first controllable current source I1 increases the current of ids1 so that Ids2 = Ids1 , and then maintains Vgs2 = Vgs1 , thereby eliminating the offset voltage.

10. The OPA linear offset calibration circuit according to claim 8, characterized in that: When the offset voltage offset is zero, Vgs2 = Vgs1; I ds2 = I ds1 = I_OPA / 2.

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