Method and related device for improving sampling accuracy

Abstract

The present application discloses a method and related device for improving sampling accuracy. The method includes: determining a first error of first sampling data according to a first analog signal and a second analog signal to be sampled; detecting that a first reference voltage of an analog-to-digital converter and a second reference voltage of a digital-to-analog converter are different, and determining a plurality of first adjustment parameters according to the first reference voltage and the second reference voltage; adjusting the first sampling data according to the plurality of first adjustment parameters to obtain first output data of the digital-to-analog converter; determining a plurality of second adjustment parameters according to the plurality of first adjustment parameters, the first reference voltage, and the second reference voltage; adjusting the first output data according to the plurality of second adjustment parameters to obtain a second error; and determining a sampling result according to the first error, the second error, and the first sampling data. The present application can improve sampling accuracy.

Description

Technical Field

[0001] This application relates to the technical field of circuit signal acquisition, and in particular to a method for improving sampling accuracy and related devices. Background Art

[0002] With the continuous progress of semiconductor technology, the switching power supply industry is also constantly developing, and more and more products with high voltage and high current have emerged on the market. However, when the resolution of the current switching power supply control chip remains unchanged, if the sampling amount increases, the sampling error will become larger, resulting in lower sampling accuracy. Summary of the Invention

[0003] Embodiments of this application provide a method for improving sampling accuracy and related devices, which reduce sampling error and improve sampling accuracy.

[0004] In a first aspect, embodiments of this application provide a method for improving sampling accuracy, which is applied to a processor of a sampling system. The sampling system further includes an analog-to-digital converter and a digital-to-analog converter, and includes:

[0005] Determine a first error of first sampling data according to a first analog signal and a second analog signal to be sampled, where the first sampling data is data obtained by the analog-to-digital converter sampling the first analog signal, and the second analog signal is data output by the digital-to-analog converter after quantifying the first sampling data;

[0006] Detect that a first reference voltage of the analog-to-digital converter and a second reference voltage of the digital-to-analog converter are different, and determine a plurality of first adjustment parameters according to the first reference voltage and the second reference voltage;

[0007] Adjust the first sampling data according to the plurality of first adjustment parameters to obtain first output data of the digital-to-analog converter;

[0008] Determine a plurality of second adjustment parameters according to the plurality of first adjustment parameters, the first reference voltage, and the second reference voltage;

[0009] Adjust the first output data according to the plurality of second adjustment parameters to obtain a second error;

[0010] Determine a sampling result according to the first error, the second error, and the first sampling data.

[0011] Among them, the determining a plurality of first adjustment parameters according to the first reference voltage and the second reference voltage includes:

[0012] Determine a plurality of voltage adjustment parameters according to the first reference voltage and the second reference voltage;

[0013] Determine a third analog signal output by the digital-to-analog converter according to the first preset input data of the digital-to-analog converter; and determine a fourth analog signal output by the digital-to-analog converter according to the second preset input data of the digital-to-analog converter;

[0014] Determine second sampling data of the analog-to-digital converter under the third analog signal and third sampling data of the analog-to-digital converter under the fourth analog signal according to the multiple voltage adjustment parameters;

[0015] Determine the multiple first adjustment parameters according to the first preset input data, the second preset input data, the second sampling data, and the third sampling data.

[0016] Wherein, the multiple first adjustment parameters include an adjustment parameter M1 and an adjustment parameter M2, the adjustment parameter M1 satisfies the following formula: M1 = (X2 - X1) / (Y2 - Y1); the adjustment parameter M2 satisfies the following formula: (X2Y1 - X1Y2) / (Y2 - Y1), where X1 is the first preset input data, X2 is the second preset input data, Y1 is the second sampling data, and Y2 is the third sampling data.

[0017] Wherein, the determining the multiple second adjustment parameters according to the multiple first adjustment parameters, the first reference voltage, and the second reference voltage includes:

[0018] Obtain a fifth analog signal input to the analog-to-digital converter and fourth sampling data output by the analog-to-digital converter; and obtain a sixth analog signal input to the analog-to-digital converter and fifth sampling data output by the analog-to-digital converter;

[0019] Adjust the fourth sampling data according to the multiple first adjustment parameters to obtain second output data of the digital-to-analog converter; and adjust the fifth sampling data according to the multiple first adjustment parameters to obtain third output data of the digital-to-analog converter;

[0020] Determine a seventh analog signal of the digital-to-analog converter according to the second output data and the second reference voltage; and determine an eighth analog signal of the digital-to-analog converter according to the third output data and the second reference voltage;

[0021] Determine a third error of the fourth sampling data according to the fifth analog signal, the seventh analog signal, and the first reference voltage; and determine a fourth error of the fifth sampling data according to the sixth analog signal, the eighth analog signal, and the first reference voltage;

[0022] Determine the multiple second adjustment parameters according to the third error, the fourth error, the second output data, and the third output data.

[0023] Among them, the multiple second adjustment parameters include an adjustment parameter N1 and an adjustment parameter N2. The adjustment parameter N1 satisfies the following formula: N1 = (Y3 - Y4) / (X4 - X3); the adjustment parameter N2 satisfies the following formula: (X3Y4 - X4Y3) / (X3 - X4), where X3 is the second output data, X4 is the third output data, Y3 is the third error, and Y4 is the fourth error.

[0024] Among them, the sampling system further includes a differential amplifier circuit. The determining of the first error of the first sampling data according to the first analog signal and the second analog signal to be sampled includes:

[0025] Perform a difference determination operation and an amplification operation on the first analog signal and the second analog signal through the differential amplifier circuit to obtain a fifth error;

[0026] Perform a quantization operation on the fifth error through the analog-to-digital converter to obtain the first error.

[0027] Among them, the multiple voltage adjustment parameters include a first voltage adjustment parameter and a second voltage adjustment parameter. The determining of the multiple voltage adjustment parameters according to the first reference voltage and the second reference voltage includes:

[0028] Determine the first voltage adjustment parameter according to the first reference voltage and the second reference voltage;

[0029] Determine the second voltage adjustment parameter according to the first reference voltage.

[0030] In a second aspect, an embodiment of the present application provides a method for improving sampling accuracy, which is applied to a processor of a sampling system. The sampling system further includes an analog-to-digital converter, pulse width modulation, and a low-pass filter circuit. The pulse width modulation is connected to the low-pass filter circuit, and includes:

[0031] Determine the first error of the first sampling data according to the first analog signal and the second analog signal to be sampled. The first sampling data is the data obtained by the analog-to-digital converter sampling the first analog signal, and the second analog signal is the data output after quantifying the first sampling data through the pulse width modulation and the low-pass filter circuit;

[0032] Detect that the first reference voltage of the analog-to-digital converter and the second reference voltage of the pulse width modulation are different, and determine multiple first adjustment parameters according to the first reference voltage and the second reference voltage;

[0033] Adjust the first sampled data according to the multiple first adjustment parameters to obtain the first output data of the digital-to-analog converter;

[0034] Determine multiple second adjustment parameters according to the multiple first adjustment parameters, the first reference voltage, and the second reference voltage;

[0035] Adjust the first output data according to the multiple second adjustment parameters to obtain a second error;

[0036] Determine a sampling result according to the first error, the second error, and the first sampled data.

[0037] In a third aspect, an embodiment of the present application provides a sampling system, including: a processor, an analog-to-digital converter, and a digital-to-analog converter;

[0038] The analog-to-digital converter is configured to obtain a first analog signal to be sampled and perform analog-to-digital conversion on the first analog signal to obtain first sampled data;

[0039] The digital-to-analog converter is configured to perform digital-to-analog conversion on the first sampled data and output a second analog signal;

[0040] The processor is configured to determine a first error of the first sampled data according to the first analog signal and the second analog signal; and, the processor is further configured to detect that a first reference voltage of the analog-to-digital converter is different from a second reference voltage of the digital-to-analog converter, and determine multiple first adjustment parameters according to the first reference voltage and the second reference voltage; and, the processor is further configured to adjust the first sampled data according to the multiple first adjustment parameters to obtain the first output data of the digital-to-analog converter; and, the processor is further configured to determine multiple second adjustment parameters according to the multiple first adjustment parameters, the first reference voltage, and the second reference voltage; and, the processor is further configured to adjust the first output data according to the multiple second adjustment parameters to obtain a second error; and, the processor is further configured to determine a sampling result according to the first error, the second error, and the first sampled data.

[0041] In a fourth aspect, an embodiment of the present application provides a sampling system, including: a processor, an analog-to-digital converter, a pulse width modulation, and a low-pass filter circuit;

[0042] The analog-to-digital converter is configured to obtain a first analog signal to be sampled and perform analog-to-digital conversion on the first analog signal to obtain first sampled data;

[0043] The pulse width modulation is configured to perform digital-to-analog conversion on the first sampled data and output a reference analog signal;

[0044] The low-pass filter circuit is used to smooth the reference analog signal and output a second analog signal;

[0045] The processor is configured to determine a first error of the first sampled data according to the first analog signal and the second analog signal; and, the processor is further configured to detect that a first reference voltage of the analog-to-digital converter is different from a second reference voltage of the pulse width modulation, and determine a plurality of first adjustment parameters according to the first reference voltage and the second reference voltage; and, the processor is further configured to adjust the first sampled data according to the plurality of first adjustment parameters to obtain first output data of the digital-to-analog converter; and, the processor is further configured to determine a plurality of second adjustment parameters according to the plurality of first adjustment parameters, the first reference voltage and the second reference voltage; and, the processor is further configured to adjust the first output data according to the plurality of second adjustment parameters to obtain a second error; and, the processor is further configured to determine a sampling result according to the first error, the second error and the first sampled data.

[0046] In a fifth aspect, an embodiment of the present application provides an electronic device, including a memory, a processor, and executable program code stored on the memory and executable on the processor. When the processor executes the executable program code, the steps of the methods described in the first aspect and the second aspect are performed.

[0047] In a sixth aspect, an embodiment of the present application provides a computer-readable storage medium, on which executable program code is stored. The executable program code includes execution instructions for performing the steps of the methods described in the first aspect and the second aspect.

[0048] In a seventh aspect, an embodiment of the present application provides a computer program product. The computer program product includes a non-transitory computer-readable storage medium storing a computer program. The computer program is operable to cause a computer to perform some or all of the steps described in the first aspect and the second aspect of the embodiments of the present application. The computer program product may be a software installation package.

[0049] It can be seen that in the embodiment of the present application, first, a first error of first sampling data is determined according to a first analog signal and a second analog signal to be sampled, where the first sampling data is data obtained by the analog-to-digital converter sampling the first analog signal, and the second analog signal is data output after the digital-to-analog converter quantizes the first sampling data; then it is detected that a first reference voltage of the analog-to-digital converter and a second reference voltage of the digital-to-analog converter are different, and a plurality of first adjustment parameters are determined according to the first reference voltage and the second reference voltage; then the first sampling data is adjusted according to the plurality of first adjustment parameters to obtain first output data of the digital-to-analog converter; then a plurality of second adjustment parameters are determined according to the plurality of first adjustment parameters, the first reference voltage and the second reference voltage; then the first output data is adjusted according to the plurality of second adjustment parameters to obtain a second error; finally, a sampling result is determined according to the first error, the second error and the first sampling data.

[0050] The present application converts the value sampled by the analog-to-digital converter into an analog signal, compares it with the real analog signal to be sampled, and obtains a first sampling error. Since there is a conversion error in the process from the analog-to-digital converter sampling to the digital-to-analog converter output, stratified adjustment is combined with different influencing factors. First, the conversion from the analog-to-digital converter sampling value to the corresponding output value of the digital-to-analog converter is adjusted, and then the second sampling error of the analog-to-digital converter is determined according to the preliminarily adjusted data. Furthermore, the final sampling result is determined by combining the original sampling value, the first sampling error and the second sampling error, which can solve the problem of reduced sampling accuracy and obtain a high-precision sampling result. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0052] Figure 1 is a system architecture diagram of a sampling system provided by an embodiment of the present application;

[0053] Figure 2 is a system architecture diagram of another sampling system provided by an embodiment of the present application;

[0054] Figure 3 is a flowchart of a method for improving sampling accuracy provided by an embodiment of the present application;

[0055] Figure 4It is a schematic diagram of the operation of an EPWM module and a low-pass filter circuit provided by an embodiment of the present application;

[0056] Figure 5 It is a schematic diagram of a sampling adjustment process provided by an embodiment of the present application;

[0057] Figure 6 It is another schematic diagram of a sampling adjustment process provided by an embodiment of the present application;

[0058] Figure 7 It is a block diagram of the functional units of a device for improving sampling accuracy provided by an embodiment of the present application;

[0059] Figure 8 It is another block diagram of the functional units of a device for improving sampling accuracy provided by an embodiment of the present application;

[0060] Figure 9 It is a schematic diagram of the structure of an electronic device proposed by an embodiment of the present application. Detailed implementation manners

[0061] In order to enable those skilled in the art to better understand the solution of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0062] The terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally further includes steps or units not listed, or optionally further includes other steps or units inherent to these processes, methods, products or devices.

[0063] Referring to "embodiment" in this article means that a specific feature, structure or characteristic described in connection with the embodiment may be included in at least one embodiment of the present application. The phrase appears in various places in the specification and does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will explicitly and implicitly understand that the embodiments described herein may be combined with other embodiments.

[0064] Currently, there is a problem that the sampling accuracy becomes lower after the sampling volume increases.

[0065] In view of the above problems, the embodiments of the present application provide a method and related device for improving sampling accuracy, and the embodiments of the present application will be introduced in detail below with reference to the accompanying drawings.

[0066] Please refer to Figure 1 , Figure 1 which is a system architecture diagram of a sampling system provided by the embodiments of the present application. As Figure 1 shown, the sampling system 10 is a functional subsystem in a control chip. The sampling system 10 includes a microcontroller 11 and a differential amplifier circuit 12. The microcontroller 11 includes a first processor 111, an analog-to-digital converter (ADC) 112, and a digital-to-analog converter (DAC) 113. The first processor 111 is connected to the ADC 112, and the first processor 111 is connected to the DAC 113. Among them, the blue line is the analog signal to be sampled, the orange line is the analog signal output by the DAC, and the green line is the amplified sampling error value. The sampling error value is the difference between the analog signal to be sampled and the analog signal output by the DAC 113.

[0067] Among them, the first processor 111 is the control core of the sampling system 10, and is used to obtain the input and output data of the ADC 112, obtain the input and output data of the DAC 113, and perform data processing operations on the obtained input and output data; the ADC 112 is used to obtain the analog signal to be sampled and convert the analog signal into a digital signal; the DAC 113 is used to convert the digital signal into an analog signal and output the analog signal; the differential amplifier circuit 12 is used to calculate the difference between the analog signal to be sampled and the analog signal output by the DAC 113, amplify it by a preset multiple, and finally transmit it to the ADC 112 and the first processor 111.

[0068] Specifically, when there is no DAC in the microcontroller 11, the function of the DAC can be implemented by pulse width modulation (PWM) plus a low-pass filter circuit. Please refer to Figure 2 , Figure 2 which is a system architecture diagram of another sampling system provided by the embodiments of the present application. As Figure 2As shown, the microcontroller 11 in the sampling system 10 may further include a PWM module 114. The sampling system 10 further includes a low-pass filter circuit 13, which is composed of a capacitor C1 and a resistor R1. Among them, the output of the PWM module 114 is externally connected to the low-pass filter circuit. The first processor 111 is connected to the analog-to-digital converter 112, and the first processor 111 is connected to the PWM module 114. Among them, the blue line is the analog signal to be sampled, the solid black line is the discrete analog signal output by the PWM module 114, the dashed black line is the continuous analog signal output by the low-pass filter circuit 13, and the green line is the amplified sampling error value. The sampling error value is the difference between the analog signal to be sampled and the analog signal output by the low-pass filter circuit 13.

[0069] Among them, the first processor 111 is the control core of the sampling system 10, and is used to obtain the input and output data of the analog-to-digital converter 112, obtain the input and output data of the PWM module 114, and obtain the input and output of the low-pass filter circuit 13, and perform data processing operations on the obtained input and output data; the analog-to-digital converter 112 is used to obtain the analog signal to be sampled and perform analog-to-digital conversion on the analog signal to obtain a digital signal; the PWM module 114 is used to perform digital-to-analog conversion on the digital signal and output a discrete analog signal; the low-pass filter circuit 13 is used to smooth the discrete analog signal and output a continuous analog signal; the differential amplifier circuit 12 is used to calculate the difference between the analog signal to be sampled and the analog signal output by the low-pass filter circuit 13, and amplify it by a preset multiple, and finally transmit it to the analog-to-digital converter 112 and the first processor 111.

[0070] Further, when there is no digital-to-analog converter in the microcontroller 11, the function of the digital-to-analog converter can also be implemented by an enhanced pulse width modulation (Enhanced Pulse Width Modulation, EPWM) plus a low-pass filter circuit.

[0071] Based on this, the present application provides a method and related device for improving sampling accuracy. The present application will be described in detail below with reference to the accompanying drawings.

[0072] Please refer to Figure 3 , Figure 3 which is a schematic flowchart of a method for improving sampling accuracy provided by an embodiment of the present application. As Figure 3 shown, the method includes the following steps:

[0073] S210, determining a first error of first sampling data according to a first analog signal and a second analog signal to be sampled.

[0074] Among them, the first sampled data is the data obtained by the analog-to-digital converter sampling the first analog signal, and the second analog signal is the data output after the digital-to-analog converter quantizes the first sampled data.

[0075] Among them, the working process of the ADC mainly includes four steps: sampling, holding, quantization, and encoding. First, for the sampling step, the analog signal is sampled at a certain time interval to discretize the continuous analog signal in time. For the holding step, since the sampling time is usually very short, in order to provide a stable input signal for the subsequent quantization and encoding processes, it is necessary to hold the sampled value at the sampling instant so that it remains unchanged during quantization and encoding. For the quantization step, the amplitude of the sampled analog signal is divided according to a certain quantization level and converted into discrete quantization values. Among them, the quantization process will introduce a certain error, called quantization error. For the encoding step, the quantized value is represented by a binary code to form a digital signal.

[0076] Among them, the performance indicators of the ADC include resolution, conversion accuracy, conversion speed, etc. Among them, the resolution refers to the smallest change in the analog signal that the ADC can distinguish, usually expressed in the number of binary digits. The higher the resolution, the smaller the change in the analog signal that the ADC can distinguish, and the higher the conversion accuracy. The conversion accuracy represents the degree of approximation between the digital signal output by the ADC and the actual analog signal, usually measured by error, including quantization error, gain error, offset error, etc. The conversion speed is the time required for the ADC to complete one conversion from an analog signal to a digital signal, usually expressed by the sampling frequency, and the unit is Hertz (Hz). The faster the conversion speed, the higher the frequency of the analog signal that the ADC can process.

[0077] Among them, the externally input first analog signal to be sampled is sampled and converted by the ADC to obtain the first sampled data. Exemplarily, if the resolution of the ADC in the control chip is 12 bits, the first analog signal will be converted and divided into the range of 0 - 4095, a total of 4096 points. Therefore, the first sampled data The calculation formula (1) is:

[0078] ,

[0079] Among them, i is the quantization number of the first analog signal, which can be 4096 in this embodiment, is the first analog signal, is the reference voltage corresponding to the ADC.

[0080] Among them, the basic working principle of the DAC is to generate a corresponding analog voltage or current output by means of weighted summation according to the input digital code. Common DAC circuit structures include R-2R ladder resistor networks, weighted resistor networks, etc. Taking the R-2R ladder resistor network as an example, it converts the input binary digital code into a corresponding current or voltage output through different resistor combinations.

[0081] Among them, the main types of DACs include voltage-output DACs and current-output DACs. The output of a voltage-output DAC is an analog voltage signal. Different circuit structures and component parameters can be selected according to the range and accuracy requirements of the output voltage. The output of a current-output DAC is an analog current signal, which is commonly used in some applications that require driving load current, such as driving light-emitting diodes (LEDs), etc.

[0082] Among them, in the embodiment of the present application, the DAC is a voltage-output DAC.

[0083] Among them, the first sampled data is converted into an analog signal through the DAC, and the second analog signal The calculation formula (2) is:

[0084] .

[0085] Specifically, the sampling system further includes a differential amplifier circuit. The determining of the first error of the first sampled data according to the first analog signal and the second analog signal to be sampled includes: performing a difference determination operation and an amplification operation on the first analog signal and the second analog signal through the differential amplifier circuit to obtain a fifth error; performing a quantization operation on the fifth error through the analog-to-digital converter to obtain the first error.

[0086] Among them, a differential amplifier circuit has two input terminals and one or two output terminals. The two input terminals are usually referred to as the non-inverting input terminal and the inverting input terminal. It can amplify the difference between the two input signals and has an inhibitory effect on the same part of the two input signals, that is, the common-mode signal. This characteristic enables the differential amplifier circuit to effectively extract and amplify useful signals in an environment with interference and noise.

[0087] Among them, the differential amplifier circuit includes differential-mode signal amplification and common-mode signal suppression.

[0088] Among them, the differential-mode signal refers to the difference between the two input signals. When the differential-mode signal is input to the differential amplifier circuit, the circuit will amplify it. In an ideal differential amplifier circuit, the two input signals act on two symmetric amplification branches respectively. Due to the symmetry of the circuit, the differential-mode signal will cause opposite changes in the outputs of the two branches, so that an amplified differential-mode signal can be obtained at the output terminal.

[0089] Among them, the common-mode signal refers to the same part of the two input signals. In practical applications, the common-mode signal is usually caused by interference or noise. The differential amplifier circuit utilizes its symmetric structure and characteristics to make the common-mode signal generate the same response in the two amplification branches, and cancel each other out or be greatly attenuated at the output end, so as to achieve the suppression of the common-mode signal.

[0090] Among them, when a DAC is included in the sampling system, one input terminal of the differential amplifier circuit is connected to the input terminal of the first analog signal to be sampled, and the other input terminal of the differential amplifier circuit is connected to the output terminal of the digital-to-analog converter, for inputting the first analog signal and the second analog signal to be sampled. The output terminal of the differential amplifier circuit is connected to the ADC, for sending the error amplified by a preset multiple to the ADC.

[0091] Among them, when a DAC is not included in the sampling system, exemplarily, the function of the DAC can be realized by adding a low-pass filter circuit to the EPWM module. One input terminal of the differential amplifier circuit is connected to the input terminal of the first analog signal to be sampled, and the other input terminal of the differential amplifier circuit is connected to the output terminal of the low-pass filter circuit, for inputting the first analog signal and the second analog signal to be sampled. The output terminal of the differential amplifier circuit is connected to the ADC, for sending the error amplified by a preset multiple to the ADC.

[0092] Among them, PWM is a method of digitally encoding the level of an analog signal. By controlling the pulse width of a fixed-period signal, that is, the duration of the high level, the required analog signal is equivalently obtained. Among them, the PWM signal consists of a series of periodic pulses, and each period contains a high level and a low level stage. By changing the proportion of the high level in a period, that is, the duty cycle, the control of the output signal is realized. For example, in a PWM signal with a period of T, if the duration of the high level is t, then the duty cycle D = t / T. The larger the duty cycle, the higher the average level of the equivalent output analog signal; the smaller the duty cycle, the lower the average level.

[0093] Among them, EPWM is a pulse width modulation technology that expands and enhances functions on the basis of traditional PWM. It exists as a peripheral module in many microcontrollers and digital signal processors (DSPs). The basic working principle of EPWM is similar to that of PWM, and it also realizes signal modulation by controlling the duty cycle of the pulse. However, EPWM adds more control functions and characteristics. For example, it can precisely control the frequency, duty cycle, and phase of the pulse, and can also realize more complex waveform generation and synchronization operations.

[0094] Specifically, please refer to Figure 4 , Figure 4 which is a working schematic diagram of an EPWM module and a low-pass filter circuit provided by an embodiment of the present application. As shown in Figure 4As shown, the sampled value is the ADC sampled value, and the output is the filtered voltage. . Among them, configure the EPWM module to the up - counting mode, set high at zero crossing, set low at the comparison value point, the EPWM period value is 4095, and the comparison value of EPWM is the ADC sampled value. Connect the output of the EPWM module to the low - pass filter circuit composed of C1 and R1. At this time, the filtered voltage can be equivalent to the analog quantity output by the DAC , that is:

[0095] ,

[0096] Among them, 3.3V is the reference voltage of the EPWM module.

[0097] Specifically, as Figure 4 shown, in the up - counting mode of the EPWM module, the counter counts up from 0. When the count value reaches the set comparison value, that is, reaches the ADC sampled value ( ), the output signal changes from high level to low level; when the count value reaches the period value 4095, the counter is cleared and starts counting again, and at the same time the output signal changes from low level to high level.

[0098] Among them, by using the ADC sampled value as the comparison value, the dynamic adjustment of the duty cycle is realized. Among them, the period value of EPWM is an example value and can be modified and adjusted according to actual needs.

[0099] Among them, the formula (3) for the first error is:

[0100] ,

[0101] Among them, K is the preset magnification amplified by the differential amplifier circuit. Exemplarily, K can be 100, is the first analog signal, is the second analog signal, is the quantization number of the first analog signal, which is determined by the resolution. If the resolution is 8 - bit, it corresponds to the range of 0 - 255, a total of 256 points, then the quantization number is 256, is the reference voltage of the ADC.

[0102] Among them, the difference determination operation is used to perform a subtraction operation on the first analog signal and the second analog signal, and then perform an amplification operation, which is used to amplify the difference between the first analog signal and the second analog signal by K times, and then output the fifth error, corresponding to , which is an analog signal, is then input into the ADC for quantization. First, the fifth error is quantized and converted into a digital signal, and then a rounding operation is performed on the error converted into a digital signal. Exemplarily, if the error converted into a digital signal is 23.3456, the first error obtained after rounding is 23.

[0103] Among them, since the sampled value cannot be a decimal and can only slide on the 1-unit scale within the interval determined by the resolution, when the sampled analog signal falls between the scales, the accuracy will be reduced. The existing sampling error value The calculation formula (4) is:

[0104] ,

[0105] Furthermore, and are added to obtain the final sampling result.

[0106] In a possible embodiment, in order to obtain a higher-precision sampling value, the embodiment of the present application converts the value sampled by the ADC into an analog signal, compares it with the actual sampled signal, takes the actual error value for amplification and performs additional sampling. In this way, the sampling result plus the error value obtained by sampling constitutes a high-precision sampling result.

[0107] Specifically, the amplified error value is , that is, the first error. The calculation formula (5) for the high-precision sampling result is:

[0108] ,

[0109] Furthermore, according to the calculation formula (5), a new error value is obtained, and its calculation formula (6) is:

[0110] .

[0111] Exemplarily, if the sampled analog signal = 1.6V, the reference voltage of the ADC = 3.3V, the resolution is 12 bits, and the amplification factor K = 10, then according to the calculation formulas (4) and (6), and are calculated, that is:

[0112]

[0113]

[0114] Among them, is 0.939, is 0.039. If the maximum sampling value is 1000 A, the actual sampling error obtained by using the method of the prior art is: 1000 A × 0.939 / 4096 = 0.2292 A; the actual sampling error obtained by using the method of this embodiment is: 1000 A × 0.039 / 4096 = 0.0095 A. It can be seen that the sampling accuracy is greatly improved.

[0115] It can be seen that in the embodiment of the present application, the analog signal output by the DAC module or the low-pass filter circuit , and the real sampling signal are compared, the error between them is amplified, and then the sampling value is determined according to the error, reducing the sampling error and achieving the improvement of the sampling accuracy without replacing the control chip.

[0116] S220, it is detected that the first reference voltage of the analog-to-digital converter is different from the second reference voltage of the digital-to-analog converter, and a plurality of first adjustment parameters are determined according to the first reference voltage and the second reference voltage.

[0117] Among them, in actual use, there is a situation where the reference voltages of the ADC and the DAC are different, or there is a situation where the reference voltages between the ADC and the EPWM functional module are different. For example, the ADC uses an external reference voltage of 3.2 V, the DAC uses the digital signal voltage of the microcontroller of 3.3 V, or the EPWM uses the digital signal voltage of the microcontroller of 3.3 V. Therefore, additional adjustment is required.

[0118] Specifically, the determining a plurality of first adjustment parameters according to the first reference voltage and the second reference voltage includes: determining a plurality of voltage adjustment parameters according to the first reference voltage and the second reference voltage; determining a third analog signal output by the digital-to-analog converter according to the first preset input data of the digital-to-analog converter; and determining a fourth analog signal output by the digital-to-analog converter according to the second preset input data of the digital-to-analog converter; determining a second sampling data of the analog-to-digital converter under the third analog signal and a third sampling data of the analog-to-digital converter under the fourth analog signal according to the plurality of voltage adjustment parameters; and determining the plurality of first adjustment parameters according to the first preset input data, the second preset input data, the second sampling data, and the third sampling data.

[0119] Specifically, the plurality of voltage adjustment parameters include a first voltage adjustment parameter and a second voltage adjustment parameter. The determining a plurality of voltage adjustment parameters according to the first reference voltage and the second reference voltage includes: determining the first voltage adjustment parameter according to the first reference voltage and the second reference voltage; and determining the second voltage adjustment parameter according to the first reference voltage.

[0120] Among them, different reference voltages will cause errors in the ADC sampling value and the DAC output value, so the DAC output value needs to be calibrated. Since the ADC sampling value cannot be a decimal, the exemplary ADC sampling value can only slide on the scale of 1 in the range of 0~4095. Therefore, when the sampled analog signal falls between the scales, the accuracy will be reduced, so the error ADC sampling value needs to be calibrated.

[0121] Among them, when the control chip includes DAC, the second reference voltage is the reference voltage of DAC, when the control chip does not include DAC, the second reference voltage is the reference voltage of PMW, or the second reference voltage is the reference voltage of EPMW, or other reference voltage that replaces the DAC function.

[0122] The DAC output value is first calibrated, wherein in the embodiment of the present application, the DAC output value corresponds to the DAC setting value, that is, the input data of the DAC. Specifically, the ADC and DAC functional modules are configured to obtain any two DAC setting values ​​X1 and DAC setting values ​​X2, control the DAC output value X1, obtain the ADC sampling value Y1 of the DAC output voltage at this time, and control the DAC output value X2 to obtain the ADC sampling value Y2 of the DAC output voltage at this time.

[0123] The DAC setting value is used as the input digital signal, which will be converted by the DAC into the corresponding analog voltage or current output. Specifically, the DAC setting value is a digital quantity, and the processor receives user instructions to control the DAC output. The DAC will convert this setting value into the corresponding analog voltage or current output based on its own working principle and reference voltage and other parameters.

[0124] Among them, there is a mapping relationship between X1 and Y1, and the mapping relationship is reflected by multiple voltage adjustment parameters. Specifically, the ratio of the second reference voltage to the first reference voltage is the first voltage adjustment parameter, and the second voltage adjustment parameter is determined with reference to the first reference voltage. The second voltage adjustment parameter can be an ADC sampling bias, and its mapping relationship is: ADC sampling value = INT (DAC setting value × second reference voltage / first reference voltage + ADC sampling bias).

[0125] Exemplarily, the first reference voltage is 3.2V, the second reference voltage is 3.3V, the ADC sampling bias is 3, X1 is 1000, X2 is 3000, and according to the mapping relationship between the ADC sampling value and the DAC setting value, 1034.25 and 3096.75 are obtained, and rounded to obtain Y1=1034, Y2=3096.

[0126] Wherein, X1 is the first preset input data, X2 is the second preset input data, the third analog signal is the DAC output voltage when the DAC outputs the value X1, the fourth analog signal is the DAC output voltage when the DAC outputs the value X2, Y1 is the second sampling data, and Y2 is the third sampling data.

[0127] Wherein, the ADC sampling bias refers to a fixed deviation between the actual sampling value and the ideal sampling value during the ADC sampling process. Ideally, when the input analog signal is a specific value, the digital value output by the ADC should be an exactly corresponding value. However, due to the influence of various factors, the digital value actually output by the ADC will deviate from this ideal value, and this fixed amount of deviation is the sampling bias.

[0128] Wherein, the ADC sampling bias is used to improve the dynamic range and signal-to-noise ratio of the signal, solve the problems of distortion or noise caused by too small signals, so as to improve the signal quality, reduce the quantization error, and improve the measurement accuracy of the ADC.

[0129] Specifically, the multiple first adjustment parameters include an adjustment parameter M1 and an adjustment parameter M2. The adjustment parameter M1 satisfies the following formula: M1 = (X2 - X1) / (Y2 - Y1); the adjustment parameter M2 satisfies the following formula: (X2Y1 - X1Y2) / (Y2 - Y1), wherein, X1 is the first preset input data, X2 is the second preset input data, Y1 is the second sampling data, and Y2 is the third sampling data.

[0130] Wherein, M1 and M2 are used to calibrate the DAC output value. The conversion formula (7) from the ADC sampling value to the corresponding DAC output value is: DAC output value = ADC sampling value × M1 + M2.

[0131] In this embodiment, the DAC output value is the set value of the DAC, that is, corresponding to inputting this set value, controlling the DAC to output.

[0132] Wherein, please refer to Figure 5 , Figure 5 is a schematic flow chart of a sampling adjustment provided by an embodiment of the present application. As Figure 5 shown, the blue line is the flow direction of the analog signal to be sampled, the orange line is the flow direction of the input and output data of the DAC, the green line is the flow direction of the sampling error. This adjustment refers to the corresponding adjustment 1. The analog signal to be sampled is input into the analog-to-digital converter to obtain the ADC sampling value, and before inputting into the digital-to-analog converter, it is adjusted by multiple first adjustment parameters and then input into the DAC to obtain the output value of the DAC, reducing the error caused by the conversion and making the output value of the DAC equal to the sampling value of the ADC.

[0133] Exemplarily, assume that the first reference voltage is 3.2V, the second reference voltage is 3.3V, the first voltage adjustment parameter is determined to be 3.3V / 3.2V, the second voltage adjustment parameter is 3, the first set value of the DAC is 1000. According to the above first voltage adjustment parameter and the second voltage adjustment parameter, the actual value corresponding to the ADC is 1034.25, and the output value corresponding to the ADC is 1034; the second set value of the DAC is 3000. According to the above first voltage adjustment parameter and the second voltage adjustment parameter, the actual value corresponding to the ADC is 3096.75, and the output value corresponding to the ADC is 3096. According to the formulas of adjustment parameter M1 and adjustment parameter M2, M1 is calculated to be 0.969932105, and M2 is calculated to be -2.909796314. Then, calibration is performed according to M1 and M2, so that the value of the ADC after calibration is equal to the set value of the DAC.

[0134] It can be seen that in the embodiment of the present application, before inputting the ADC sampling value into the DAC, the ADC sampling value is adjusted to reduce the error caused by the conversion between the DAC and the ADC, and thus the sampling accuracy of the analog signal can be improved.

[0135] S230. Adjust the first sampling data according to the plurality of first adjustment parameters to obtain the first output data of the digital-to-analog converter.

[0136] Among them, after calculating the adjustment parameter M1 and the adjustment parameter M2, the first sampling data is adjusted. Specifically, the first sampling data is used as the ADC sampling value and substituted into the conversion formula (7) to obtain the first output data.

[0137] S240. Determine a plurality of second adjustment parameters according to the plurality of first adjustment parameters, the first reference voltage, and the second reference voltage.

[0138] Specifically, obtain the fifth analog signal input to the analog-to-digital converter and the fourth sampled data output from the analog-to-digital converter; and, obtain the sixth analog signal input to the analog-to-digital converter and the fifth sampled data output from the analog-to-digital converter; adjust the fourth sampled data according to the multiple first adjustment parameters to obtain the second output data of the digital-to-analog converter; and, adjust the fifth sampled data according to the multiple first adjustment parameters to obtain the third output data of the digital-to-analog converter; determine the seventh analog signal of the digital-to-analog converter according to the second output data and the second reference voltage; and, determine the eighth analog signal of the digital-to-analog converter according to the third output data and the second reference voltage; determine the third error of the fourth sampled data according to the fifth analog signal, the seventh analog signal and the first reference voltage; and, determine the fourth error of the fifth sampled data according to the sixth analog signal, the eighth analog signal and the first reference voltage; determine the multiple second adjustment parameters according to the third error, the fourth error, the second output data and the third output data.

[0139] Among them, the multiple second adjustment parameters are used to determine the error ADC sampled values. Specifically, obtain any two ADC sampled integer values. For example, the fourth sampled data is 1000 and the fifth sampled data is 3000. Input the voltage 1 corresponding to one of the ADC sampled integer values, that is, the fifth analog signal. For example, the voltage 1 corresponding to the fourth sampled data 1000 is 0.77890625. Determine the output value of the DAC according to the fourth sampled data and the conversion formula (7), that is, the second output data of the digital-to-analog converter, which is 967.0223084; input the voltage 2 corresponding to the other ADC sampled integer value, that is, the sixth analog signal. For example, the voltage 2 corresponding to the fifth sampled data 3000 is 2.34140625. Determine the output value of the DAC according to the fifth sampled data and the conversion formula (7), that is, the third output data of the digital-to-analog converter is 2906.886518.

[0140] Further, quantize the second output data and the third output data respectively to obtain the output voltage corresponding to each output data, that is, the corresponding analog signal. Specifically, quantize each output data according to the resolution of the control chip and the reference voltage of the DAC, that is: output voltage = output data / quantization number × DAC reference voltage, where the quantization number is determined according to the resolution of the control chip. Exemplarily, the resolution is 12 bits and the quantization number is 4096. If the DAC reference voltage is 3.3V, according to the above quantization formula, determine that the seventh analog signal is 0.779095122 and the eighth analog signal is 2.341974001.

[0141] Among them, the fifth analog signal and the seventh analog signal are input into a differential amplifier circuit to obtain a third error, and the sixth analog signal and the eighth analog signal are input into a differential amplifier circuit to obtain a fourth error. Specifically, subtract the seventh analog signal from the fifth analog signal to obtain a first difference, and after amplifying the first difference by a preset multiple, convert it into a digital signal through an ADC; and subtract the eighth analog signal from the sixth analog signal to obtain a second difference, and after amplifying the second difference by a preset multiple, convert it into a digital signal through an ADC. Exemplarily, the reference voltage of the ADC is 3.2V, the quantization number is 4096, the amplification factor is 100, the third error = (0.77890625 - 0.779095122) / 3.2×100×4096 = -24.175616, and the fourth error = (2.34140625 - 2.341974001) / 3.2×100×4096 = -72.67213312.

[0142] Further, in the actual use process, considering the influence that the differential circuit cannot collect negative values, 1 can be subtracted first when converting the ADC value to the DAC value and then the conversion is performed. Specifically, the DAC output value = (ADC sampling value - 1)×M1 + M2.

[0143] Specifically, the multiple second adjustment parameters include an adjustment parameter N1 and an adjustment parameter N2. The adjustment parameter N1 satisfies the following formula: N1 = (Y3 - Y4) / (X4 - X3); the adjustment parameter N2 satisfies the following formula: (X3Y4 - X4Y3) / (X3 - X4), where X3 is the second output data, X4 is the third output data, Y3 is the third error, and Y4 is the fourth error.

[0144] Exemplarily, according to the calculation formulas of the adjustment parameter N1 and the adjustment parameter N2, the adjustment parameter N1 is obtained as 0.025, and the adjustment parameter N2 is 0.

[0145] Among them, as Figure 5 shown, this adjustment refers to the corresponding adjustment 2, adjusts the truncated part of the ADC rounding, inputs the amplified error into the analog-to-digital converter, and obtains the error converted into a digital signal, realizing the correction of the truncated part of the ADC rounding.

[0146] Further, when realizing the function of the DAC through the EPWM module plus a low-pass filter circuit in the sampling system, please refer to Figure 6 , Figure 6 which is another flow schematic diagram of sampling adjustment provided by the embodiment of the present application. As Figure 6 shown, the blue line is the flow direction of the analog signal to be sampled, the purple line is the flow direction of the input and output data of the EPWM module and the low-pass filter circuit, and the green line is the flow direction of the sampling error. Specifically,Figure 6 The sampling adjustment method embodied and Figure 5 The sampling adjustment method embodied is the same, Figure 6 The adjustment method of adjustment 2 shown in is corresponding to the above Figure 5 The method of adjustment 2 shown in, Figure 6 The adjustment method of adjustment 3 shown in is the same as the method of the above adjustment 1.

[0147] S250, adjust the first output data according to the multiple second adjustment parameters to obtain a second error.

[0148] Furthermore, the adjustment amount of the error ADC sampling value follows the conversion formula (8) of the corresponding output value of the DAC as: N1×DAC output value + N2, that is, the second error = N1×DAC output value + N2.

[0149] Specifically, take the first output data as the DAC output value and substitute it into the conversion formula (8) to obtain the second error.

[0150] S260, determine the sampling result according to the first error, the second error and the first sampling data.

[0151] Among them, the final sampling result is: original sampling value + (first error + DAC output value × N1 + N2) / K, where K is the magnification factor amplified by the differential amplifier circuit, the original sampling value is the sampling data obtained after the sampled analog signal is input into the ADC. First, convert the value sampled by the ADC into an analog signal through the DAC, and input the analog signal and the real sampled analog signal into the differential amplifier circuit and the ADC in sequence. The finally obtained data is the first error, and the second error is (DAC output value × N1 + N2).

[0152] It can be seen that in the embodiment of the present application, the value sampled by the analog-to-digital converter is converted into an analog signal and compared with the real sampled analog signal to obtain the first sampling error. Since there is a conversion error in the process from the analog-to-digital converter sampling to the digital-to-analog converter output, different influencing factors are combined for hierarchical adjustment. First, adjust the conversion from the analog-to-digital converter sampling value to the corresponding output value of the digital-to-analog converter, and then determine the second sampling error of the analog-to-digital converter according to the preliminarily adjusted data. Furthermore, combine the original sampling value, the first sampling error and the second sampling error to determine the final sampling result, which can solve the problem of reduced sampling accuracy and obtain a high-precision sampling result.

[0153] Meanwhile, this application is user-friendly. High-precision sampling results can be achieved without replacing the control chip, and it has a wide adaptation range and can be implemented with any control chip. Moreover, the modification of the peripheral circuit of the control chip is simple. When the control chip has a DAC function, only a differential amplifier circuit needs to be added. If the control chip has a differential signal sampling function, no additional circuit is required. When the control chip does not have a DAC function, only a differential amplifier circuit and a low-pass filter circuit need to be added.

[0154] Consistent with the above embodiments, please refer to Figure 7 , Figure 7 which is a functional unit composition block diagram of a device for improving sampling accuracy provided by an embodiment of this application. As Figure 7 shown, the device 70 for improving sampling accuracy includes: a first determination unit 71, configured to determine a first error of first sampling data according to a first analog signal and a second analog signal to be sampled, where the first sampling data is data obtained by the analog-to-digital converter sampling the first analog signal, and the second analog signal is data output after the digital-to-analog converter quantifies the first sampling data; a second determination unit 72, configured to detect that a first reference voltage of the analog-to-digital converter and a second reference voltage of the digital-to-analog converter are different, and determine a plurality of first adjustment parameters according to the first reference voltage and the second reference voltage; a first adjustment unit 73, configured to adjust the first sampling data according to the plurality of first adjustment parameters to obtain first output data of the digital-to-analog converter; a third determination unit 74, configured to determine a plurality of second adjustment parameters according to the plurality of first adjustment parameters, the first reference voltage, and the second reference voltage; a second adjustment unit 75, configured to adjust the first output data according to the plurality of second adjustment parameters to obtain a second error; and a fourth determination unit 76, configured to determine a sampling result according to the first error, the second error, and the first sampling data.

[0155] In a possible embodiment, in terms of determining a plurality of first adjustment parameters according to the first reference voltage and the second reference voltage, the second determination unit 72 is specifically configured to: determine a plurality of voltage adjustment parameters according to the first reference voltage and the second reference voltage; determine a third analog signal output by the digital-to-analog converter according to a first preset input data of the digital-to-analog converter; and determine a fourth analog signal output by the digital-to-analog converter according to a second preset input data of the digital-to-analog converter; determine second sampling data of the analog-to-digital converter under the third analog signal and third sampling data of the analog-to-digital converter under the fourth analog signal according to the plurality of voltage adjustment parameters; and determine the plurality of first adjustment parameters according to the first preset input data, the second preset input data, the second sampling data, and the third sampling data.

[0156] In a possible embodiment, the multiple first adjustment parameters include an adjustment parameter M1 and an adjustment parameter M2. The adjustment parameter M1 satisfies the following formula: M1 = (X2 - X1) / (Y2 - Y1); the adjustment parameter M2 satisfies the following formula: (X2Y1 - X1Y2) / (Y2 - Y1), where X1 is the first preset input data, X2 is the second preset input data, Y1 is the second sampling data, and Y2 is the third sampling data.

[0157] In a possible embodiment, in terms of determining multiple second adjustment parameters according to the multiple first adjustment parameters, the first reference voltage, and the second reference voltage, the third determination unit 74 is specifically configured to: obtain a fifth analog signal input to the analog-to-digital converter and fourth sampling data output from the analog-to-digital converter; and obtain a sixth analog signal input to the analog-to-digital converter and fifth sampling data output from the analog-to-digital converter; adjust the fourth sampling data according to the multiple first adjustment parameters to obtain second output data of the digital-to-analog converter; and adjust the fifth sampling data according to the multiple first adjustment parameters to obtain third output data of the digital-to-analog converter; determine a seventh analog signal of the digital-to-analog converter according to the second output data and the second reference voltage; and determine an eighth analog signal of the digital-to-analog converter according to the third output data and the second reference voltage; determine a third error of the fourth sampling data according to the fifth analog signal, the seventh analog signal, and the first reference voltage; and determine a fourth error of the fifth sampling data according to the sixth analog signal, the eighth analog signal, and the first reference voltage; determine the multiple second adjustment parameters according to the third error, the fourth error, the second output data, and the third output data.

[0158] In a possible embodiment, the multiple second adjustment parameters include an adjustment parameter N1 and an adjustment parameter N2. The adjustment parameter N1 satisfies the following formula: N1 = (Y3 - Y4) / (X4 - X3); the adjustment parameter N2 satisfies the following formula: (X3Y4 - X4Y3) / (X3 - X4), where X3 is the second output data, X4 is the third output data, Y3 is the third error, and Y4 is the fourth error.

[0159] In a possible embodiment, the sampling system further includes a differential amplifier circuit. In terms of determining a first error of first sampling data according to a first analog signal and a second analog signal to be sampled, the first determination unit 71 is specifically further configured to: perform a difference determination operation and an amplification operation on the first analog signal and the second analog signal through the differential amplifier circuit to obtain a fifth error; perform a quantization operation on the fifth error through the analog-to-digital converter to obtain the first error.

[0160] In a possible embodiment, the multiple voltage adjustment parameters include a first voltage adjustment parameter and a second voltage adjustment parameter. In terms of determining the multiple voltage adjustment parameters according to the first reference voltage and the second reference voltage, the second determination unit 72 is specifically further configured to: determine the first voltage adjustment parameter according to the first reference voltage and the second reference voltage; and determine the second voltage adjustment parameter according to the first reference voltage.

[0161] It can be understood that since the method embodiment and the device embodiment are different presentation forms of the same technical concept, the content of the method embodiment part in this application should be synchronously adapted to the device embodiment part, and will not be elaborated here.

[0162] In the case of adopting an integrated unit, please refer to Figure 8 , Figure 8 is a functional unit composition block diagram of another device for improving sampling accuracy provided by the embodiment of the present application. As Figure 8 shown, the device 70 for improving sampling accuracy includes: a processing module 702 and a communication module 701. The processing module 702 is used to control and manage the operations of the device 70 for improving sampling accuracy. For example, it executes the steps of the first determination unit 71, the second determination unit 72, the first adjustment unit 73, the third determination unit 74, the second adjustment unit 75, and the fourth determination unit 76, and / or is used to execute other processes of the technologies described herein. The communication module 701 is used for the interaction between the device 70 for improving sampling accuracy and other devices. As Figure 8 shown, the device 70 for improving sampling accuracy may further include a storage module 703, and the storage module 703 is used to store the program code and data of the device 70 for improving sampling accuracy.

[0163] Among them, the processing module 702 can be a processor or a controller. For example, it can be a Central Processing Unit (CPU), a general-purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. It can implement or execute various exemplary logic blocks, modules, and circuits described in connection with the disclosure of this application. The processor can also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, and so on. The communication module 701 can be a transceiver, an RF circuit, a communication interface, or the like. The storage module 703 can be a memory.

[0164] Among them, all relevant contents of each scenario involved in the above method embodiment can be cited in the function description of the corresponding functional module, and will not be elaborated here. The above device 70 for improving sampling accuracy can execute the above Figure 3 method for improving sampling accuracy shown.

[0165] Please refer to Figure 9 , Figure 9 which is a schematic structural diagram of an electronic device proposed in an embodiment of this application. As shown in Figure 9 , the electronic device 900 includes a second processor 910, a memory 920, a communication interface 930, and one or more programs 921. The above one or more programs 921 are stored in the above memory and are configured to be executed by the above processor. When the program is executed, it includes some or all of the steps of any method for improving sampling accuracy described in the above method embodiment. The processor, the memory, and the communication interface are interconnected and complete the communication work between them.

[0166] Among them, the memory can be a volatile memory such as a Dynamic Random Access Memory (DRAM), or a non-volatile memory such as a mechanical hard disk. The above memory is used to store a set of executable program codes. The above processor is used to call the executable program codes stored in the memory and can execute some or all of the steps of any method for improving sampling accuracy described in the above method embodiment for improving sampling accuracy.

[0167] It can be seen that for the electronic device 900 described in the embodiments of the present application, first, the first error of the first sampling data is determined according to the first analog signal and the second analog signal to be sampled, where the first sampling data is the data obtained by the analog-to-digital converter sampling the first analog signal, and the second analog signal is the data output after the digital-to-analog converter quantizes the first sampling data; then it is detected that the first reference voltage of the analog-to-digital converter and the second reference voltage of the digital-to-analog converter are different, and multiple first adjustment parameters are determined according to the first reference voltage and the second reference voltage; then the first sampling data is adjusted according to the multiple first adjustment parameters to obtain the first output data of the digital-to-analog converter; then multiple second adjustment parameters are determined according to the multiple first adjustment parameters, the first reference voltage and the second reference voltage; then the first output data is adjusted according to the multiple second adjustment parameters to obtain the second error; finally, the sampling result is determined according to the first error, the second error and the first sampling data. In the present application, the value sampled by the analog-to-digital converter is converted into an analog signal and compared with the real analog signal to be sampled to obtain the first sampling error. Since there are conversion errors in the process from the analog-to-digital converter sampling to the digital-to-analog converter output, hierarchical adjustment is performed in combination with different influencing factors. First, the conversion from the analog-to-digital converter sampling value to the corresponding output value of the digital-to-analog converter is adjusted, and then the second sampling error of the analog-to-digital converter is determined according to the preliminarily adjusted data. Furthermore, the final sampling result is determined in combination with the original sampling value, the first sampling error and the second sampling error, which can solve the problem of reduced sampling accuracy and obtain a high-precision sampling result.

[0168] The embodiments of the present application further provide a computer storage medium. The computer storage medium stores a computer program for electronic data exchange, and the computer program enables a computer to execute some or all of the steps of any of the methods described in the above method embodiments. The above computer includes an electronic device.

[0169] The embodiments of the present application further provide a computer program product. The computer program product includes a non-transitory computer-readable storage medium storing a computer program, and the computer program is operable to enable a computer to execute some or all of the steps of any of the methods described in the above method embodiments. The computer program product can be a software installation package, and the above computer includes an electronic device.

[0170] It should be noted that, for the foregoing method embodiments, for the sake of simple description, they are all expressed as a series of action combinations. However, those skilled in the art should know that this application is not limited by the described action sequence, because according to this application, certain steps can be performed in other sequences or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all optional embodiments, and the actions and modules involved are not necessarily essential to this application.

[0171] In the above embodiments, the descriptions of each embodiment have their own emphases. For the parts not detailed in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0172] In several embodiments provided by this application, it should be understood that the disclosed device can be implemented in other ways. For example, the device embodiments described above are only illustrative. For example, the division of the units is only a logical function division. In actual implementation, there can be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed couplings or direct couplings or communication connections to each other can be through some interfaces. The indirect couplings or communication connections of the devices or units can be in electrical or other forms.

[0173] The units described as separate components may or may not be physically separated. The components displayed as units may or may not be physical units, that is, they can be located in one place or distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0174] In addition, in each embodiment of this application, the functional units can be integrated in a processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit. The above integrated units can be implemented in the form of hardware or in the form of software program modules.

[0175] If the integrated unit is implemented in the form of a software program module and sold or used as an independent product, it can be stored in a computer-readable memory. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a memory and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of this application. The aforementioned memory includes: various media that can store program codes, such as USB flash drives, read-only memories (ROM), random access memories (RAM), mobile hard disks, magnetic disks, or optical discs.

[0176] Those of ordinary skill in the art can understand that all or part of the steps in the various methods of the above embodiments can be completed by instructing relevant hardware through a program. This program can be stored in a computer-readable memory, and the memory can include: flash drives, read-only memories, random access memories, magnetic disks, or optical discs, etc.

[0177] The above has introduced the embodiments of this application in detail. Specific examples are used in this article to elaborate on the principles and embodiments of this application. The description of the above embodiments is only used to help understand the method and its core idea of this application; at the same time, for those of ordinary skill in the art, according to the idea of this application, there will be changes in the specific embodiments and application scopes. In summary, the content of this specification should not be construed as a limitation to this application.

Claims

1. A method for improving sampling accuracy, characterized in that: A processor applied to a sampling system, wherein the sampling system further comprises an analog-to-digital converter and a digital-to-analog converter, wherein the processor is connected to the analog-to-digital converter, and wherein the processor is connected to the digital-to-analog converter, and comprises: Acquire a sampled first analog signal input to the analog-to-digital converter; Receiving first sampling data obtained by the analog-to-digital converter performing analog-to-digital conversion on the first analog signal; Inputting the first sampled data into the digital-to-analog converter; Receiving a second analog signal obtained by performing digital-to-analog conversion on the first sampled data by the digital-to-analog converter; determining a first error of the first sampling data according to the first analog signal and the second analog signal; detecting that a first reference voltage of the analog-to-digital converter and a second reference voltage of the digital-to-analog converter are different, and determining a plurality of voltage adjustment parameters according to the first reference voltage and the second reference voltage; Determining a third analog signal output by the digital-to-analog converter according to first preset input data of the digital-to-analog converter; and determining a fourth analog signal output by the digital-to-analog converter according to second preset input data of the digital-to-analog converter; Determine, according to the plurality of voltage adjustment parameters, second sampling data of the analog-to-digital converter under the third analog signal and third sampling data of the analog-to-digital converter under the fourth analog signal; Determine a plurality of first adjustment parameters according to the first preset input data, the second preset input data, the second sampling data and the third sampling data; wherein the plurality of first adjustment parameters include an adjustment parameter M1 and an adjustment parameter M2, wherein the adjustment parameter M1 satisfies the following formula: M1=(X2-X1) / (Y2-Y1); the adjustment parameter M2 satisfies the following formula: M2=(X2Y1-X1Y2) / (Y2-Y1), wherein X1 is the first preset input data, X2 is the second preset input data, Y1 is the second sampling data, and Y2 is the third sampling data; Adjust the first sampling data according to the plurality of first adjustment parameters to obtain first output data of the digital-to-analog converter; Acquire a fifth analog signal input to the analog-to-digital converter and fourth sampled data output from the analog-to-digital converter; and, acquire a sixth analog signal input to the analog-to-digital converter and fifth sampled data output from the analog-to-digital converter; Adjusting the fourth sampled data according to the plurality of first adjustment parameters to obtain second output data of the digital-to-analog converter; and adjusting the fifth sampled data according to the plurality of first adjustment parameters to obtain third output data of the digital-to-analog converter; determining a seventh analog signal of the digital-to-analog converter according to the second output data and the second reference voltage; and determining an eighth analog signal of the digital-to-analog converter according to the third output data and the second reference voltage; determining a third error of the fourth sampling data according to the fifth analog signal, the seventh analog signal and the first reference voltage; and determining a fourth error of the fifth sampling data according to the sixth analog signal, the eighth analog signal and the first reference voltage; Determine a plurality of second adjustment parameters according to the third error, the fourth error, the second output data, and the third output data; wherein the plurality of second adjustment parameters include an adjustment parameter N1 and an adjustment parameter N2, wherein the adjustment parameter N1 satisfies the following formula: N1=(Y3-Y4) / (X4-X3); and the adjustment parameter N2 satisfies the following formula: N2=(X3Y4-X4Y3) / (X3-X4), wherein X3 is the second output data, X4 is the third output data, Y3 is the third error, and Y4 is the fourth error; Adjust the first output data according to the plurality of second adjustment parameters to obtain a second error; The first sampling data is compensated according to the first error and the second error to obtain a sampling result.

2. The method according to claim 1, characterized in that The sampling system further includes a differential amplifier circuit, and the determining of a first error of the first sampling data according to the sampled first analog signal and the second analog signal includes: performing a difference determination operation and an amplification operation on the first analog signal and the second analog signal through the differential amplifier circuit to obtain a fifth error; The first error is obtained by performing a quantization operation on the fifth error through the analog-to-digital converter.

3. The method according to claim 1, characterized in that The multiple voltage adjustment parameters include a first voltage adjustment parameter and a second voltage adjustment parameter, and determining the multiple voltage adjustment parameters according to the first reference voltage and the second reference voltage includes: determining a first voltage adjustment parameter according to the first reference voltage and the second reference voltage; A second voltage adjustment parameter is determined according to the first reference voltage.

4. A method for improving sampling accuracy, characterized in that: A processor applied to a sampling system, wherein the sampling system further comprises an analog-to-digital converter, a pulse width modulation and a low-pass filter circuit, wherein the pulse width modulation is connected to the low-pass filter circuit, the processor is connected to the analog-to-digital converter, and the pulse width modulation is connected to the processor, comprising: Acquire a sampled first analog signal input to the analog-to-digital converter; Receiving first sampling data obtained by the analog-to-digital converter performing analog-to-digital conversion on the first analog signal; Inputting the first sampling data into the pulse width modulation; Receiving a reference analog signal obtained by performing digital-to-analog conversion on the first sampling data by pulse width modulation; Inputting the reference analog signal into the low-pass filter circuit; Receiving a second analog signal obtained by smoothing the reference analog signal by the low-pass filtering circuit; determining a first error of the first sampling data according to the first analog signal and the second analog signal; detecting that a first reference voltage of the analog-to-digital converter and a second reference voltage of the pulse width modulation are different, and determining a plurality of voltage adjustment parameters according to the first reference voltage and the second reference voltage; Determining a third analog signal output by the low-pass filter circuit according to the first preset input data of the pulse width modulation; and determining a fourth analog signal output by the low-pass filter circuit according to the second preset input data of the pulse width modulation; Determine, according to the plurality of voltage adjustment parameters, second sampling data of the analog-to-digital converter under the third analog signal and third sampling data of the analog-to-digital converter under the fourth analog signal; Determine a plurality of first adjustment parameters according to the first preset input data, the second preset input data, the second sampling data and the third sampling data; wherein the plurality of first adjustment parameters include an adjustment parameter M1 and an adjustment parameter M2, wherein the adjustment parameter M1 satisfies the following formula: M1=(X2-X1) / (Y2-Y1); the adjustment parameter M2 satisfies the following formula: M2=(X2Y1-X1Y2) / (Y2-Y1), wherein X1 is the first preset input data, X2 is the second preset input data, Y1 is the second sampling data, and Y2 is the third sampling data; Adjust the first sampling data according to the multiple first adjustment parameters to obtain first output data of the low-pass filter circuit; Acquire a fifth analog signal input to the analog-to-digital converter and fourth sampled data output from the analog-to-digital converter; and, acquire a sixth analog signal input to the analog-to-digital converter and fifth sampled data output from the analog-to-digital converter; The fourth sampling data is adjusted according to the plurality of first adjustment parameters to obtain second output data of the low-pass filter circuit; and the fifth sampling data is adjusted according to the plurality of first adjustment parameters to obtain third output data of the low-pass filter circuit; determining a seventh analog signal of the low-pass filter circuit according to the second output data and the second reference voltage; and determining an eighth analog signal of the low-pass filter circuit according to the third output data and the second reference voltage; determining a third error of the fourth sampling data according to the fifth analog signal, the seventh analog signal and the first reference voltage; and determining a fourth error of the fifth sampling data according to the sixth analog signal, the eighth analog signal and the first reference voltage; Determine a plurality of second adjustment parameters according to the third error, the fourth error, the second output data, and the third output data; wherein the plurality of second adjustment parameters include an adjustment parameter N1 and an adjustment parameter N2, wherein the adjustment parameter N1 satisfies the following formula: N1=(Y3-Y4) / (X4-X3); and the adjustment parameter N2 satisfies the following formula: N2=(X3Y4-X4Y3) / (X3-X4), wherein X3 is the second output data, X4 is the third output data, Y3 is the third error, and Y4 is the fourth error; Adjust the first output data according to the plurality of second adjustment parameters to obtain a second error; The first sampling data is compensated according to the first error and the second error to obtain a sampling result.

5. A sampling system, characterized in that: include: processors, analog-to-digital converters, and digital-to-analog converters; The analog-to-digital converter is used to acquire a sampled first analog signal and perform analog-to-digital conversion on the first analog signal to obtain first sampled data; The digital-to-analog converter is used to perform digital-to-analog conversion on the first sampling data and output a second analog signal; The processor is configured to determine a first error of the first sampling data according to the first analog signal and the second analog signal; and The processor is further configured to detect that a first reference voltage of the analog-to-digital converter and a second reference voltage of the digital-to-analog converter are different, and determine a plurality of voltage adjustment parameters according to the first reference voltage and the second reference voltage; Determine a third analog signal output by the digital-to-analog converter according to first preset input data of the digital-to-analog converter; and, determining a fourth analog signal output by the digital-to-analog converter according to the second preset input data of the digital-to-analog converter; determining a second sampling data of the analog-to-digital converter under the third analog signal and a third sampling data of the analog-to-digital converter under the fourth analog signal according to the multiple voltage adjustment parameters; determining multiple first adjustment parameters according to the first preset input data, the second preset input data, the second sampling data and the third sampling data; wherein the multiple first adjustment parameters include an adjustment parameter M1 and an adjustment parameter M2, wherein the adjustment parameter M1 satisfies the following formula: M1=(X2-X1) / (Y2-Y1); wherein the adjustment parameter M2 satisfies the following formula: M2=(X2Y1-X1Y2) / (Y2-Y1), wherein X1 is the first preset input data, X2 is the second preset input data, Y1 is the second sampling data, and Y2 is the third sampling data; and, The processor is further configured to adjust the first sampling data according to the plurality of first adjustment parameters to obtain first output data of the digital-to-analog converter; and The processor is further used to obtain a fifth analog signal input to the analog-to-digital converter and fourth sampling data output from the analog-to-digital converter; and, to obtain a sixth analog signal input to the analog-to-digital converter and fifth sampling data output from the analog-to-digital converter; to adjust the fourth sampling data according to the plurality of first adjustment parameters to obtain second output data of the digital-to-analog converter; and, to adjust the fifth sampling data according to the plurality of first adjustment parameters to obtain third output data of the digital-to-analog converter; to determine a seventh analog signal of the digital-to-analog converter according to the second output data and the second reference voltage; and, to determine an eighth analog signal of the digital-to-analog converter according to the third output data and the second reference voltage; and, and the first reference voltage to determine the third error of the fourth sampling data; and, determine the fourth error of the fifth sampling data according to the sixth analog signal, the eighth analog signal and the first reference voltage; determine a plurality of second adjustment parameters according to the third error, the fourth error, the second output data and the third output data; wherein the plurality of second adjustment parameters include an adjustment parameter N1 and an adjustment parameter N2, wherein the adjustment parameter N1 satisfies the following formula: N1=(Y3-Y4) / (X4-X3); the adjustment parameter N2 satisfies the following formula: N2=(X3Y4-X4Y3) / (X3-X4), wherein X3 is the second output data, X4 is the third output data, Y3 is the third error, and Y4 is the fourth error; and, The processor is further configured to adjust the first output data according to the plurality of second adjustment parameters to obtain a second error; and The processor is further configured to compensate the first sampling data according to the first error and the second error to obtain a sampling result.

6. A sampling system, characterized in that: include: processor, analog-to-digital converter, pulse width modulation, and low-pass filtering circuits; The analog-to-digital converter is used to acquire a sampled first analog signal and perform analog-to-digital conversion on the first analog signal to obtain first sampled data; The pulse width modulation is used to perform digital-to-analog conversion on the first sampling data and output a reference analog signal; The low-pass filter circuit is used to smooth the reference analog signal and output a second analog signal; The processor is configured to determine a first error of the first sampling data according to the first analog signal and the second analog signal; and The processor is further configured to detect that a first reference voltage of the analog-to-digital converter and a second reference voltage of the pulse width modulation are different, and determine a plurality of voltage adjustment parameters according to the first reference voltage and the second reference voltage; Determine a third analog signal output by the low-pass filter circuit according to the first preset input data of the pulse width modulation; And, determining a fourth analog signal output by the low-pass filter circuit according to the second preset input data of the pulse width modulation; determining the second sampling data of the analog-to-digital converter under the third analog signal and the third sampling data of the analog-to-digital converter under the fourth analog signal according to the multiple voltage adjustment parameters; determining multiple first adjustment parameters according to the first preset input data, the second preset input data, the second sampling data and the third sampling data; wherein the multiple first adjustment parameters include an adjustment parameter M1 and an adjustment parameter M2, and the adjustment parameter M1 satisfies the following formula: M1=(X2-X1) / (Y2-Y1); the adjustment parameter M2 satisfies the following formula: M2=(X2Y1-X1Y2) / (Y2-Y1), wherein X1 is the first preset input data, X2 is the second preset input data, Y1 is the second sampling data, and Y2 is the third sampling data; and, The processor is further configured to adjust the first sampling data according to the plurality of first adjustment parameters to obtain first output data of the low-pass filter circuit; and The processor is also used to obtain a fifth analog signal input to the analog-to-digital converter and a fourth sampling data output from the analog-to-digital converter; and, to obtain a sixth analog signal input to the analog-to-digital converter and a fifth sampling data output from the analog-to-digital converter; to adjust the fourth sampling data according to the multiple first adjustment parameters to obtain second output data of the low-pass filter circuit; and, to adjust the fifth sampling data according to the multiple first adjustment parameters to obtain third output data of the low-pass filter circuit; to determine a seventh analog signal of the low-pass filter circuit according to the second output data and the second reference voltage; and, to determine an eighth analog signal of the low-pass filter circuit according to the third output data and the second reference voltage; and The method comprises the following steps: determining a third error of the fourth sampling data according to the sixth analog signal, the eighth analog signal and the first reference voltage; and determining a fourth error of the fifth sampling data according to the sixth analog signal, the eighth analog signal and the first reference voltage; determining a plurality of second adjustment parameters according to the third error, the fourth error, the second output data and the third output data; wherein the plurality of second adjustment parameters include an adjustment parameter N1 and an adjustment parameter N2, wherein the adjustment parameter N1 satisfies the following formula: N1=(Y3-Y4) / (X4-X3); and the adjustment parameter N2 satisfies the following formula: N2=(X3Y4-X4Y3) / (X3-X4), wherein X3 is the second output data, X4 is the third output data, Y3 is the third error, and Y4 is the fourth error; and, The processor is further configured to adjust the first output data according to the plurality of second adjustment parameters to obtain a second error; and The processor is further configured to compensate the first sampling data according to the first error and the second error to obtain a sampling result.

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