Semiconductor memory device and method for manufacturing semiconductor memory device

Abstract

The invention provides a semiconductor memory device and a method for manufacturing the semiconductor memory device, which can reduce bending and inclination of layers and suppress reduction of voltage resistance performance. A semiconductor memory device according to an embodiment includes: a first stacked body in which first conductive layers and first insulating layers are alternately stacked layer by layer, the first stacked body including a first stepped portion in which the first conductive layers are processed into a stepped shape; a first interlayer insulating film covering the first stepped portion; a second laminate which is provided above the first laminate, in which second conductive layers and second insulating layers are alternately laminated layer by layer, and which includes a second stepped portion in which the second conductive layers are processed into a stepped shape; a second interlayer insulating film covering the second stepped portion; first and second plate-shaped parts penetrating the first and second laminated bodies in the lamination direction, respectively; and first and second bridging portions disposed at the upper ends of the first and second plate-shaped portions, respectively, and connecting the first and second interlayer insulating films on both sides, respectively. The lower end portions of the first and second bridging portions are positioned above the uppermost first and second conductive layers in each of the first and second laminated bodies.

Description

[0001] Related Applications

[0002] This application claims priority based on Japanese Patent Application No. 2023-153890 (filing date: September 20, 2023). This application incorporates all the contents of the basic application by reference. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor storage device and a method for manufacturing the semiconductor storage device. Background Art

[0004] For example, in semiconductor storage devices such as three-dimensional nonvolatile memories, there are devices having a laminated body in which a plurality of conductive layers and a plurality of insulating layers are alternately laminated layer by layer. Such a laminated body is formed by forming grooves in insulating layers and sacrificial layers formed of different materials, respectively, and allowing a processing liquid to penetrate through the grooves to replace the sacrificial layers with conductive layers.

[0005] However, in the process of forming such a semiconductor storage device, the layer may be warped and tilted due to the stress generated in various materials. In order to reduce such warping and tilting, a bridge portion that can support the materials on both sides is sometimes formed on the upper part of the groove portion. The more the number of layers of the stacked body increases, the greater the stress generated in the layer, so it is required to make the bridge portion thicker.

[0006] However, if the bridge portion is thickened to the depth of forming the conductive layer, the conductive layer may be poorly formed when the sacrificial layer is replaced by the conductive layer. As a result, the distance between the metal layer formed in the groove and the conductive layer becomes shorter, and the withstand voltage performance may be reduced. Summary of the invention

[0007] One embodiment provides a semiconductor memory device capable of reducing warping and tilting of a layer and suppressing a decrease in withstand voltage performance, and a method for manufacturing the semiconductor memory device.

[0008] The semiconductor storage device of the embodiment comprises: a first stacking body, in which a plurality of first conductive layers and a plurality of first insulating layers are stacked alternately layer by layer, including processing the plurality of first conductive layers into a first stepped portion extending in a first direction intersecting the stacking direction of the first conductive layers; a first interlayer insulating film covering the first stepped portion; a second stacking body, arranged above the first stacking body, in which a plurality of second conductive layers and a plurality of second insulating layers are stacked alternately layer by layer, including processing the plurality of second conductive layers into a second stepped portion continuous with the first stepped portion in the first direction; a second interlayer insulating film covering the second stepped portion; a first plate The first and second plate-shaped portions are provided with a first plate-shaped portion, extending along the first direction and penetrating the first laminated body along the lamination direction; the second plate-shaped portion, extending along the first direction, penetrating the second laminated body along the lamination direction and connected to the upper end of the first plate-shaped portion; the first bridge portion, arranged at the upper end of the first plate-shaped portion, connecting the first interlayer insulating film on both sides of the first plate-shaped portion; and the second bridge portion, arranged at the upper end of the second plate-shaped portion, connecting the second interlayer insulating film on both sides of the second plate-shaped portion; and the lower ends of the first and second bridge portions are located above the first and second conductive layers which are the uppermost layers in each of the first and second laminated bodies. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 This is a partial plan view schematically showing the structure of the semiconductor memory device according to the first embodiment.

[0010] Figure 2A It is a cross-sectional view showing the detailed structure of the cell array region according to the first embodiment.

[0011] 2B(a) and 2B(b) are cross-sectional views showing the detailed structure of the step region according to the first embodiment.

[0012] Figure 3 (a) and (b) are diagrams for explaining the positional relationship between the first bridging portion and the second bridging portion in the first embodiment.

[0013] Figure 4 (Aa) to (Ad) and (Ba) to (Bd) are diagrams illustrating a part of the procedure of the method for forming the semiconductor memory device according to the first embodiment.

[0014] Figure 5 (Ae) to (Ag) and (Be) to (Bg) are diagrams illustrating a part of the sequence of the method for manufacturing the semiconductor memory device according to the first embodiment.

[0015] Figure 6(Ah) to (Ai) and (Bh) to (Bi) are diagrams illustrating a part of the sequence of the method for manufacturing the semiconductor memory device according to the first embodiment.

[0016] Figure 7 (Aj) to (Ak) and (Bj) to (Bk) are diagrams illustrating a part of the sequence of the method for manufacturing the semiconductor memory device according to the first embodiment.

[0017] Figure 8 (Al) to (Am) and (Bl) to (Bm) are diagrams illustrating a part of the sequence of the method for manufacturing the semiconductor memory device according to the first embodiment.

[0018] Fig. 9 (An) to (Ao) and (Bn) to (Bo) are diagrams illustrating a part of the sequence of the method for manufacturing the semiconductor memory device according to the first embodiment.

[0019] Fig.10 (Ap) and (Bp) in FIG. 1 are diagrams illustrating a part of the sequence of the method for manufacturing the semiconductor memory device according to the first embodiment.

[0020] Fig.11 (a) to (d) are cross-sectional views showing detailed structures of a cell array region of a semiconductor memory device according to a comparative example.

[0021] Fig.12 (a) and (b) are cross-sectional views showing detailed structures of a cell array region of a semiconductor memory device according to a variation of the first embodiment.

[0022] Fig.13 (a) to (d) are diagrams illustrating a part of the sequence of a method for manufacturing a semiconductor memory device according to a variation of the first embodiment.

[0023] Fig.14A This is a partial plan view illustrating an example of the configuration of a semiconductor storage device according to a second embodiment.

[0024] Fig. 14B (a) and (b) are cross-sectional views illustrating a configuration example of a semiconductor memory device according to the second embodiment.

[0025] Fig.15 (a) and (b) are diagrams for explaining the positional relationship between the first bridging portion and the second bridging portion in the second embodiment.

[0026] Fig.16 (Aa) to (Ac), (Ba) to (Bc), and (Cb) to (Cc) are diagrams illustrating a part of the sequence of the method for manufacturing the semiconductor memory device according to the second embodiment.

[0027] Fig.17 (Ad) to (Ae) and (Bd) to (Be), and (Ce) are diagrams illustrating a part of the sequence of the method for manufacturing the semiconductor memory device according to the second embodiment.

[0028] Fig.18 (Af) to (Ag) and (Bf) to (Bg) are diagrams illustrating a part of the sequence of the method for manufacturing the semiconductor memory device according to the second embodiment.

[0029] Fig.19 (Ah) to (Ai), (Bh) to (Bi), and (Ch) are diagrams illustrating a part of the sequence of the method for manufacturing the semiconductor memory device according to the second embodiment.

[0030] Fig. 20 (Aj) and (Bj) in FIG. 1 are diagrams illustrating a part of the sequence of the method for manufacturing the semiconductor memory device according to the second embodiment.

[0031] Fig.21 This is a diagram showing an example of arrangement of the first bridge portion in Modification 1 of Embodiment 2.

[0032] Fig. 22 This is a diagram showing an example of arrangement of the first bridge portion in Modification 2 of Embodiment 2. DETAILED DESCRIPTION

[0033] Hereinafter, non-limiting illustrative embodiments of the present invention will be described with reference to the attached drawings. In all the attached drawings, the same or corresponding components or parts are marked with the same or corresponding reference symbols, and repeated descriptions are omitted. In addition, the purpose of the drawings is not to show the relative ratio between components or parts, or between the thicknesses of various layers. Therefore, the specific thickness or size can be determined by those skilled in the art according to the following non-limiting embodiments.

[0034] (Implementation Method 1)

[0035] refer to Figures 1 to 3 , a configuration example of a semiconductor memory device 1 according to Embodiment 1 is described. The semiconductor memory device 1 according to this embodiment includes a cell array region and a step region.

[0036] Figure 1 FIG. 1 is a partial top view showing a schematic configuration of a semiconductor memory device 1 according to Embodiment 1. Figure 1 1, a portion of each of the cell array region CA and the step region SA of the semiconductor memory device 1 is shown. Upper wiring or plugs are provided in the cell array region CA and the step region SA, but Figure 1 Their illustrations are omitted.

[0037] In this specification, the x direction and the y direction are directions along the surface orientation of the plurality of conductive layers described later, and the x direction and the y direction are orthogonal to each other. In addition, the direction intersecting the x direction and the y direction, that is, the stacking direction of the plurality of conductive layers is referred to as the z direction. The x direction is an example of the first direction, and the y direction is an example of the second direction.

[0038] The cell array region CA includes a laminated body (described later) in which a plurality of conductive layers and a plurality of insulating layers are alternately laminated one by one, and a plurality of memory pillars MP penetrating the laminated body in the z direction. The memory pillars MP are arranged in a grid pattern in the xy plane in the figure and extend in the z direction in the figure.

[0039] The step region SA has a step portion SR. In the present embodiment, the step portion SR has a predetermined length in the x direction. In the y direction, a plurality of step portions SR extending in the x direction are arranged at predetermined intervals from each other.

[0040] In the step portion SR, the stacked body is processed into a step shape in such a way that the step surfaces (stepping surfaces) are formed by a plurality of conductive layers, and a second interlayer insulating film 40 is formed at least above it. The second interlayer insulating film 40 is, for example, a silicon oxide layer. In addition, in the step portion SR, a contact CC is provided that penetrates the second interlayer insulating film 40 and is connected to the step surface. In addition, in this specification, the direction in which the step surfaces of each stage of the step portion SR face is defined as an upward direction.

[0041] A plurality of plate-like portions STL are formed in the cell array region CA and the step region SA to divide them. Each of the plurality of plate-like portions STL crosses the cell array region CA and the step region SA in the x direction, extends along the z direction in the figure, and terminates in the source line (described later). In addition, each of the plurality of plate-like portions STL has a pad layer LL and a conductive portion EC inside thereof. The pad layer LL is, for example, a silicon oxide layer. The conductive portion EC is, for example, a tungsten layer, a tungsten nitride layer, a titanium layer, a titanium nitride layer, a molybdenum layer, or a molybdenum nitride layer as a conductive material. The plate-like portion STL connected to the source line (described later) in the conductive portion EC functions as a source line contact. Each of the plurality of plate-like portions STL has, at the upper end, a plurality of second bridge portions BT2 intermittently arranged in the length direction (x direction) of the plate-like portion STL.

[0042] Next, use Figure 2A 2B will describe the details of the cell array region CA and the step region SA. Figure 2A 1 is a cross-sectional view showing the detailed structure of the cell array region CA according to Embodiment 1. More specifically, Figure 2A It is along Figure 1FIG2B is a cross-sectional view showing the detailed structure of the step area SA according to the first embodiment. More specifically, FIG2B (a) is a cross-sectional view taken along the line L1-L1. Figure 1 The yz cross-sectional view of the L2a-L2a line, FIG2B (b) is a cross-sectional view along the L2a-L2a line. Figure 1 yz cross-sectional view of line L2b-L2b.

[0043] like Figure 2A As shown in FIG. 2B , the semiconductor memory device 1 includes a first stacked body LM1 on the source line SL and a second stacked body LM2 on the first stacked body LM1 .

[0044] The source line SL is, for example, a conductive polysilicon layer. The source line SL is arranged on the electrode film EL via the insulating layer 50. A plurality of plugs (not shown) are arranged in the insulating layer 50, and the source line SL and the electrode film EL are electrically connected via the plugs. Thus, a source potential is applied to the source line SL from the outside of the semiconductor memory device 1 via the electrode film EL and the plugs.

[0045] The first laminated body LM1 has a structure in which a plurality of conductive layers WL1 and a plurality of insulating layers OL1 are alternately laminated, and the second laminated body LM2 has a structure in which a plurality of conductive layers WL2 and a plurality of insulating layers OL2 are alternately laminated. The conductive layers WL1 and WL2 are, for example, tungsten layers, tungsten nitride layers, titanium layers, titanium nitride layers, molybdenum layers, molybdenum nitride layers, etc. The insulating layers OL1 and OL2 are, for example, silicon oxide layers or aluminum oxide layers, etc. In addition, the conductive layer WL1 is an example of the first conductive layer, and the insulating layer OL1 is an example of the first insulating layer. In addition, the conductive layer WL2 is an example of the second conductive layer, and the insulating layer OL2 is an example of the second insulating layer.

[0046] In addition, Figure 2A 2B shows the number of conductive layers WL1 and WL2 and insulating layers OL1 and OL2 suitable for the description, but the number of conductive layers WL1 and WL2 is not limited to the example shown in the figure and can be determined appropriately. For example, 48 conductive layers, 64 conductive layers, or 96 conductive layers can be formed.

[0047] Between the first laminate LM1 and the second laminate LM2, an insulating layer 31, an insulating layer 32, and an insulating layer 33 are sequentially formed so as to cover the first laminate LM1. The insulating layers 31 to 33 are composed of an insulating material such as a silicon oxide layer. In addition, above the second laminate LM2, an insulating layer 41 and an insulating layer 42 are sequentially formed so as to cover the second laminate LM2. The insulating layers 41 to 42 are composed of an insulating material such as a silicon oxide layer.

[0048] like Figure 2A As shown in FIG. 1 , the memory pillar MP and the plate-like portion STL are formed in the cell array area CA.

[0049] The memory column MP penetrates the first stacked body LM1, the insulating layers 31 to 33, the second stacked body LM2 and the insulating layer 41 along the z direction and terminates in the source line SL. The memory column MP has a roughly cylindrical shape, and has a core layer COR, a channel layer CHN and a memory film MEM formed in concentric circles from the center to the outside, and a cap layer CAP on the top. Here, the core layer COR is, for example, silicon oxide, and the channel layer CHN and the cap layer CAP are, for example, conductive polycrystalline silicon or amorphous silicon. In addition, the memory film MEM has a tunnel insulating layer, a charge storage layer and a blocking insulating layer, which are not shown in the figure and are formed in sequence along the direction from the center of the memory column MP to the outside. The tunnel insulating layer and the blocking insulating layer are, for example, a silicon oxide layer, and the charge storage layer is, for example, a silicon nitride layer.

[0050] A memory cell (not shown) is formed in the portion where the conductive layer WL1 and the conductive layer WL2 are respectively opposite to the memory membrane MEM of the memory column MP. In the above case, the conductive layer WL1 and the conductive layer WL2 function as a word line. However, there are cases where the portion where the bottommost and topmost conductive layers of the conductive layers WL1 and the conductive layers WL2 are opposite to the memory column MP functions as a selection transistor. Therefore, for example, there is a case where the topmost conductive layer WL2 in the second laminate body LM2 functions as a drain side selection gate line SGD.

[0051] A plug PG is provided on the memory column MP. The plug PG penetrates the insulating layer 42 and is connected to the upper wiring ML. The upper wiring ML is connected to the transistor Tr formed on the substrate SB1 such as a silicon wafer via a via hole V. Such upper wiring ML, via hole V, transistor Tr, etc. are covered by an insulating layer 50 such as silicon oxide, and control the memory cell as a peripheral circuit unit PER. In addition, in the description after FIG. 2B, for the sake of convenience, a part of the peripheral circuit unit PER may be omitted.

[0052] The plate-like portion STL penetrates the first laminated body LM1, the second laminated body LM2, the insulating layers 31 to 33, and the insulating layers 41 to 42 along the z direction and terminates in the source line SL. Specifically, the plate-like portion STL includes: a first plate-like portion ST1 extending along the x direction and penetrating the first laminated body LM1 and the insulating layers 31 to 33 along the z direction; and a second plate-like portion ST2 extending along the x direction and penetrating the second laminated body LM2 and the insulating layers 41 to 42 along the z direction and connected to the upper end of the first plate-like portion ST1.

[0053] In the first plate-like portion ST1, a conductive portion EC containing a conductive material and a liner layer LL are formed in order from the inside. In addition, in the second plate-like portion ST2, a conductive portion EC and a liner layer LL are also formed from the inside. The conductive portion EC of the second plate-like portion ST2 is connected at its upper end to the lower end of the conductive portion EC of the first plate-like portion ST1.

[0054] As shown in (a) in FIG2B , the first bridge portion BT1 and the second bridge portion BT2 are formed at the upper end portions of a portion of the first plate-like portion ST1 and the second plate-like portion ST2 extending in the x-direction. In contrast, as shown in (b) in FIG2B , the first bridge portion BT1 and the second bridge portion BT2 are not formed at other portions of the upper end portions of the first plate-like portion ST1 and the second plate-like portion ST2. This is because the first bridge portion BT1 and the second bridge portion BT2 are each disposed intermittently in the x-direction. For the specific positional relationship between the first bridge portion BT1 and the second bridge portion BT2, use Figure 3 This will be described later.

[0055] The first bridge portion BT1 has an upper structure BTU1 that reaches a predetermined depth from the upper surface of the first interlayer insulating film 30, and a lower structure BTB1 that penetrates the first interlayer insulating film 30 from a predetermined depth of the first interlayer insulating film 30 and reaches a predetermined depth of the first plate-like portion ST1. The lower structure BTB1 is located above the uppermost conductive layer WL1 in the first laminate LM1. In addition, the width of the lower structure BTB1 in the y direction is substantially equal to the width of the first plate-like portion ST1 in the y direction, and is narrower than the width of the upper structure BTU1 in the y direction. The first bridge portion BT1 is, for example, a silicon oxide layer.

[0056] The joint portion BTO1 is formed in the upper structure BTU1 of the first bridge portion BT1. In addition, in the joint portion BTO1, a conductive portion EC containing a conductive material and a liner layer LL are also formed in sequence from the inside. The width of the conductive portion EC of the joint portion BTO1 in the y direction is at least wider than the width of the lower end of the second plate-like portion ST2 in the y direction, and is connected to the lower end of the conductive portion EC of the second plate-like portion ST2. In addition, the width of the conductive portion EC of the joint portion BTO1 in the y direction may also be wider than the width of the conductive portion EC of the first plate-like portion ST1 in the y direction.

[0057] The second bridge portion BT2 has an upper structure BTU2 that reaches a specified depth from the upper surface of the second interlayer insulating film 40, and a lower structure BTB2 that penetrates the second interlayer insulating film 40 from a specified depth of the second interlayer insulating film 40 and reaches a specified depth of the second plate-like portion ST2. The lower structure BTB2 is located above the uppermost conductive layer WL2 in the second laminate LM2, that is, above the drain side selection gate line SGD. In addition, the width of the lower structure BTB2 in the y direction is approximately equal to the width of the second plate-like portion ST2 in the y direction, and is narrower than the width of the upper structure BTU2 in the y direction. The second bridge portion BT2 is, for example, a silicon oxide layer.

[0058] As shown in (a) and (b) of FIG. 2B , a first step portion SR1 , a second step portion SR2 , a contact CC, and a columnar portion HR are formed in the step region SA.

[0059] The first step portion SR1 and the second step portion SR2 are formed by processing the first stacked body LM1 and the second stacked body LM2 into a step shape, respectively. Specifically, as shown in (a) of FIG. 2B , the first step portion SR1 is included in the first stacked body LM1, and the plurality of conductive layers WL1 are processed into a step shape extending in the x direction. In addition, as shown in (b) of FIG. 2B , the second step portion SR2 is included in the second stacked body LM2, and the plurality of conductive layers WL2 are processed into a step shape continuous with the first step portion SR1 in the x direction.

[0060] In (a) of FIG. 2B , the lowest section of the first step portion SR1, that is, the portion where the conductive layer WL1 of the lowest layer of the first laminate LM1 is processed into a step shape is shown. That is, in (a) of FIG. 2B , the first step portion SR1 extends toward the front side of the paper. In addition, virtual step portions are formed on both sides of the y direction of the first step portion SR1 extending along the x direction. These virtual step portions are formed simultaneously when the first step portion SR1 is formed, and do not have the function of electrically leading out the conductive layer WL1 of each layer like the regular first step portion SR1.

[0061] In addition, in (b) of FIG. 2B, the lowest section of the second step portion SR2, that is, the portion where the conductive layer WL2 of the lowest layer of the second laminate LM2 is processed into a step-like shape is shown. That is, in (b) of FIG. 2B, the second step portion SR2 also extends toward the front side of the paper. In addition, on both sides of the second step portion SR2 extending in the x direction in the y direction, virtual step portions that do not function as the regular second step portion SR2 are also formed.

[0062] At the height position of the first laminate body LM1, the first step portion SR1 is covered by an insulating layer 34, and insulating layers 31 to 33 are formed on the insulating layer 34. The insulating layer 34 is, for example, a silicon oxide layer. Therefore, the insulating layers 31 to 34 are substantially integrated. In the following description, the insulating layers 31, 32, and 34 are collectively referred to as the first interlayer insulating film 30. In addition, at the height position of the second laminate body LM2, the second step portion SR2 is covered by an insulating layer 43, and insulating layers 41 to 42 are formed on the insulating layer 43. The insulating layer 43 is, for example, a silicon oxide layer. Therefore, the insulating layers 41 to 43 are substantially integrated. In the following description, the insulating layers 41 to 43 are collectively referred to as the second interlayer insulating film 40.

[0063] Part of the plurality of contacts CC penetrates the first interlayer insulating film 30 and the second interlayer insulating film 40, and is connected to the conductive layer WL1 of each stage constituting the first step portion SR1. The other parts of the plurality of contacts CC penetrate the second interlayer insulating film 40, and are connected to the conductive layer WL2 of each stage constituting the second step portion SR2. In (a) and (b) of FIG. 2B , the first step portion SR1 and the contact CC connected to the lowest section of the second step portion SR2 are respectively shown. The contact CC is connected to the upper wiring not shown in (a) and (b) of FIG. 2B . Thus, the conductive layers WL1 and WL2 of each layer are electrically led out.

[0064] The columnar portion HR penetrates the first laminated body LM1, the insulating layers 31 to 33, the second laminated body LM2, and the insulating layer 41 in the z direction and terminates in the source line SL. In the present embodiment, the columnar portion HR has the same layer structure as the memory pillar MP by filling the hole with the same material as the core layer COR, the channel layer CHN, the memory film MEM, and the cap layer CAP, but does not contribute to the function of the semiconductor memory device 1. The columnar portion HR supports these structures when the first laminated body LM1 and the second laminated body LM2 are formed by a laminated body (described later) in which a sacrificial layer and an insulating layer are laminated.

[0065] Figure 3 This is a diagram for explaining the positional relationship between the first bridging portion BT1 and the second bridging portion BT2 according to the first embodiment. Figure 3 (a) is along the L3-L3 line in (a) of FIG. 2B , Figure 3 (b) is an xy cross-sectional view along the L4-L4 line of (a) in FIG. 2B . That is, Figure 3 (a) and (b) are top views of the first plate-like portion ST1 and the second plate-like portion ST2 in the extending direction. Figure 1 Similarly, along the L2a-L2a line shown Figure 3 The yz cross section taken along the line L2a-L2a shown in (a) and (b) in FIG. 2A corresponds to the surface shown in (a) in FIG. 2B .

[0066] like Figure 3 As shown in (a) and (b) in the figure, each of the first bridge portion BT1 and the second bridge portion BT2 is intermittently provided at the upper end portions of the first plate-like portion ST1 and the second plate-like portion ST2 extending in the x direction. Each of the first bridge portion BT1 and the second bridge portion BT2 is formed in a manner spanning the first plate-like portion ST1 and the second plate-like portion ST2 in the y direction. In addition, when viewed from the z direction, the first bridge portion BT1 and the second bridge portion BT2 are arranged to be offset from each other in the x direction.

[0067] Specifically, the position in the x direction is Figure 3 In the case of position R1, the first bridge portion BT1 and the second bridge portion BT2 are arranged so as to overlap each other. In addition, in the case of position R4 in the x direction, no first bridge portion BT1 and second bridge portion BT2 are arranged. In this position R4, the shapes of the first plate-like portion ST1 and the second plate-like portion ST2 are as follows: Figure 2A As shown in the figure, the shapes do not have any of the first bridge portion BT1 and the second bridge portion BT2 at their respective upper ends. In addition, at positions R2 and R3, any one of the first bridge portion BT1 or the second bridge portion BT2 is arranged on one of the first plate-like portion ST1 and the second plate-like portion ST2, but these first bridge portions BT1 or the second bridge portions BT2 do not overlap with each other when viewed from the z direction.

[0068] in addition, Figure 3 The positional relationship between the first bridge portion BT1 and the second bridge portion BT2 shown is only an example and is not limited thereto. The positional relationship between the first bridge portion BT1 and the second bridge portion BT2, the length in the x direction, the adjacent interval, the number, etc. can be appropriately determined.

[0069] Below, while referring to Figures 4 to 10 , while describing a method for forming each structure in the cell array region CA and the step region SA according to the first embodiment. Figures 4 to 10 This is a diagram illustrating a part of the procedure of the method for manufacturing the semiconductor memory device 1 according to the first embodiment. Figure 4 (Aa) to Fig.10 The (Ap) in the equation is along Figure 1 The yz cross-sectional view of the L1-L1 line is equivalent to Figure 2A Cross section shown. Figure 4 (Ba) to Fig.10 The (Bp) in is along Figure 1 The yz cross-sectional view taken along the line L2a-L2a is equivalent to the cross-sectional view shown in (a) in FIG2B .

[0070] exist Figure 4In (Aa) and (Ba) of FIG. 1 , a first laminate LMs1 and an insulating layer 31 are sequentially formed on a substrate SB2 such as a silicon wafer. The first laminate LMs1 is formed by alternately laminating a plurality of insulating layers OL1 and a plurality of sacrificial layers SN1. Figure 4 As shown in (Ba) in FIG. 1 , a portion of the first stacked body LMs1 and the insulating layer 31 is processed into the first step portion SR1 through a series of steps including forming a mask using a photoresist, etching using the mask, thinning the mask, and etching using the thinned mask. The first step portion SR1 is formed into a step shape in which a plurality of sacrificial layers SN1 extend along the x direction. At this time, since the mask is thinned not only in the x direction but also in the y direction by thinning, virtual step portions are formed on both sides of the first step portion SR1 in the y direction. Then, the first step portion SR1 is covered by the insulating layer 34.

[0071] The insulating layer OL1 is an example of a first insulating layer, and the sacrificial layer SN1 is an example of a second insulating layer. The insulating layer OL1 is, for example, a silicon oxide layer, and the sacrificial layer SN1 is, for example, a silicon nitride layer.

[0072] exist Figure 4 In (Ab) and (Bb) in FIG. 1 , a memory hole MHA1 and a hole HRA1 are formed that penetrate the first laminate body LMs1, the insulating layer 31, and the insulating layer 34. The memory hole MHA1 and the hole HRA1 are provided to form the memory column MP and the columnar portion HR, respectively. Then, amorphous carbon is buried in the memory hole MHA1 and the hole HRA1. At this time, the amorphous carbon deposited on the insulating layer 31 and the insulating layer 34 is removed by, for example, a chemical mechanical polishing (CMP (Chemical Mechanical Polishing)) method.

[0073] exist Figure 4 In (Ac) and (Bc), the insulating layer 32 is formed on the insulating layer 31 and the insulating layer 34. In this way, the first step portion SR1 is covered by the first interlayer insulating film 30. Next, the slit STA1 that ends at the substrate SB2 is formed by penetrating the first laminated body LMs1 and the first interlayer insulating film 30. The slit STA1 is an example of the first groove portion and is also a structure that becomes the first plate-like portion ST1 later. Therefore, the slit STA1 also extends in the direction along the x direction.

[0074] Next, an oxide layer BO is formed at the bottom of the slit STA1. Then, amorphous silicon is buried in the slit STA1. Thus, the oxide layer BO can function as an etching stopper when the amorphous silicon is removed from the slit STA1 later.

[0075] Then, if Figure 4As shown in the cross section of (Bd) in FIG. 1 , in the region where the first bridge portion BT1 and the second bridge portion BT2 are to be configured later, a photoresist film RF is coated on the insulating layer 32, and the photoresist film RF is opened by exposure and development so that the top of the slit STA1 is exposed. The photoresist film RF is used as a mask, and the insulating layer 32 is dry-etched to a depth that does not penetrate the insulating layer 32. Thus, an opening OPA is formed at the upper end of the slit STA1. The opening OPA is a portion that will later become the upper structure BTU1 of the first bridge portion BT1.

[0076] In addition, as described above, the photoresist film RF is opened in such a way that the width of the opening OPA in the y direction is wider than the width of the slit STA1 in the y direction. Thus, it is possible to ensure that the allowable range of positional deviation of the opening of the photoresist film RF relative to the slit STA1 is wide, so that the first bridge portion BT1 can be formed more reliably at the upper end of the first plate-like portion ST1.

[0077] In contrast, Figure 4 As shown in the cross section (Ad) in FIG. 1 , in a region where the first bridge portion BT1 and the second bridge portion BT2 are not arranged later, an opening is not formed in the photoresist film RF, and thus the opening OPA is not formed.

[0078] Then, if Figure 5 As shown in the cross-section (Be) in FIG, in the area where the first bridge portion BT1 and the second bridge portion BT2 are later configured, after the opening portion OPA is formed, the amorphous silicon exposed at the bottom of the opening portion OPA is dry-etched to a specified depth by a gas different from the etching gas used to process the opening portion OPA. The so-called specified depth is a depth above the uppermost sacrificial layer SN1 of the first laminate body LMs1. Thus, an opening portion OPB is formed at the bottom of the opening portion OPA. The opening portion OPB is a portion that will later become the lower structure BTB1 of the first bridge portion BT1. In contrast, as Figure 5 As shown in the cross section (Ae) in FIG. 1 , the opening OPB is not formed in a region where the first bridge portion BT1 and the second bridge portion BT2 are not arranged later.

[0079] exist Figure 5 In (Bf), after removing the photoresist film RF, the insulating layer 33 is deposited on the insulating layer 32. The insulating layer 33 is deposited on the bottom surface and side walls of the openings OPA and OPB. When the insulating layer 33 is deposited on the above-mentioned parts and reaches a predetermined film thickness, the opening OPB is almost completely filled with the insulating layer 33, forming the lower structure BTB1 of the first bridge portion BT1.

[0080] In addition, at this time, the opening OPC is formed inside the opening OPA covered by the insulating layer 33. At this time, the insulating layer 33 is formed so as to maintain the width of the opening OPC in the y direction wider than the width of the lower end of the slit STA2 to be formed later in the y direction. Thus, it is possible to ensure a wide allowable range of positional deviation of the slit STA2 to be formed later relative to the opening OPC.

[0081] In contrast, Figure 5 In (Af), the insulating layer 33 is deposited only on the insulating layer 32 .

[0082] exist Figure 5 In (Bg), the opening OPC is filled with an amorphous carbon layer CB. The amorphous carbon layer CB functions as an etching stopper when the second plate-like portion ST2 is processed later. Figure 5 In the (Ag) in the above embodiment, the amorphous carbon layer CB is not formed.

[0083] Below, in Figure 6 (Bh) in FIG. 1 shows the state where the second laminate LMs2 and the second step portion SR2 are formed. Figure 6 In (Bh), in order to illustrate the second step portion SR2, Figure 4 (Ba) to Fig.10 The other figures of (Bp) in FIG. 1 are different cross-sections.

[0084] like Figure 6 As shown in (Bh) in FIG. 1 , a second laminated body LMs2 and an insulating layer 41 are sequentially formed on the insulating layer 33. The second laminated body LMs2 is formed by alternately laminating a plurality of insulating layers OL2 and a plurality of sacrificial layers SN2 layer by layer. A portion of the second laminated body LMs2 and the insulating layer 41 is processed into the second step portion SR2, for example, by the same process as the first step portion SR1. The second step portion SR2 is processed into a step shape in which a plurality of sacrificial layers SN2 are continuous with the first step portion SR1 in the x direction.

[0085] exist Figure 6 (Bh) in FIG. 1 shows the bottom section of the second step portion, that is, the sacrificial layer SN2 of the bottom layer of the second laminate LMs2 is processed into a step-shaped portion. In addition, when forming the second step portion SR2, similarly to when forming the first step portion SR1, virtual step portions are also formed on both sides of the second step portion SR2 in the y direction.

[0086] Then, the second step portion SR2 is covered with the insulating layer 43 .

[0087] The insulating layer OL2 is an example of a third insulating layer, and the sacrificial layer SN2 is an example of a fourth insulating layer. The insulating layer OL2 is, for example, a silicon oxide layer, and the sacrificial layer SN2 is, for example, a silicon nitride layer.

[0088] exist Figure 6 In (Ai) and (Bi) in FIG. 1 , a memory hole MHA2 and a hole HRA2 are formed that penetrate the second laminate body LMs2, the insulating layer 41, and the insulating layer 43. The memory hole MHA2 and the hole HRA2 are connected to the upper ends of the memory hole MHA1 and the hole HRA1 formed in the first laminate body LMs1, respectively. Then, the amorphous carbon buried in the memory hole MHA1 and the hole HRA1 is removed by ashing or the like through the memory hole MHA2 and the hole HRA2.

[0089] exist Figure 7 In (Aj) and (Bj), a memory membrane MEM, a channel layer CHN, and a core layer COR are sequentially formed inside the memory holes MHA1 and MHA2. Next, the core layer COR is retreated by dry etching and the cap layer CAP is buried. Thus, a memory column MP is formed. In addition, while forming the memory column MP, the holes HRA1 and HRA2 are also processed in the same manner to form a columnar portion HR.

[0090] exist Figure 7 In (Ak) and (Bk) in FIG. 1 , an insulating layer 42 is formed on the first laminate LMs1 forming the memory column MP and the columnar portion HR, and on the insulating layers 41 and 43 covering the second laminate LMs2. In this way, the second step portion SR2 is covered by the second interlayer insulating film 40. Next, a slit STA2 is formed that has an opening at a position overlapping with the slit STA1 formed in the first laminate LMs1 in the z direction and penetrates the second laminate LMs2 and the second interlayer insulating film 40. The slit STA2 is provided to form the second plate-like portion ST2. In addition, the slit STA2 is an example of a second groove portion.

[0091] like Figure 7 As shown in the cross section (Ak) in FIG. 1 , in a region where the first bridge portion BT1 and the second bridge portion BT2 are not arranged later, the slit STA2 extends along the x direction and penetrates the insulating layer 33 covering the slit STA1 to be connected to the upper end of the slit STA1 .

[0092] Specifically, if Figure 7 As shown in (Ak) in FIG. 1 , in the upper end of the slit STA1, where the lower structure BTB1 of the first bridge portion BT1 and the opening OPC filled with the amorphous carbon layer CB are not formed, the slit STA2 is directly connected to the upper end opening of the slit STA1. Figure 7 As shown in (Bk), the lower structure BTB1 of the first bridge portion BT1 and the opening OPC filled with the amorphous carbon layer CB are formed in the upper end portion of the slit STA1, and the slit STA2 is connected to the amorphous carbon layer CB formed in the opening OPC.

[0093] At this time, the etching conditions of the slit STA2 are the same as those of the insulating layer 33, and do not have selectivity with the silicon oxide layer or the like constituting the lower structure BTB1 of the first bridge portion BT1 provided at the upper end of the slit STA1. By providing the amorphous carbon layer CB above the lower structure BTB1, the etching of the slit STA2 can be stopped on the amorphous carbon layer CB, and the lower end of the slit STA2 can be prevented from penetrating the lower structure BTB1. Thus, the first bridge portion BT1 formed later maintains the function of connecting the first interlayer insulating film 30 on both sides of the y direction above the first plate-like portion ST1 formed later.

[0094] In addition, as described above, by forming the amorphous carbon layer CB to be wider than the width of the lower end of the slit STA2 in the y direction, it is possible to ensure that the allowable range of the positional deviation of the slit STA2 relative to the amorphous carbon layer CB is wide, and the lower end of the slit STA2 can be more reliably brought into the surface of the amorphous carbon layer CB. Therefore, the etching of the lower end of the slit STA2 can be more reliably stopped by the amorphous carbon layer CB.

[0095] Although in Figure 7 Although not shown in (Bk), the amorphous carbon layer CB is removed by ashing or the like after the slit STA2 is formed, and the opening OPC is exposed again in the portion where the amorphous carbon layer CB is removed.

[0096] Then, if Figure 8 As shown in (A1) and (B1) in FIG. 4 , amorphous silicon is filled in the slit STA2 and the opening OPC, so that the silicon nitride layer NI is deposited on the insulating layer 42. Figure 8 As shown in the cross section of (Bl) in FIG. 1 , in the region where the first bridge portion BT1 and the second bridge portion BT2 are to be configured later, a process equivalent to Figure 4 In the treatment of (Bd) and (Be), an opening OPD having a width in the y direction wider than the slit STA2 is formed in the silicon nitride layer NI above the slit STA2, and an opening OPE having a width in the y direction substantially equal to that of the slit STA2 and reaching a predetermined depth of the slit STA2 is formed. The opening OPE is formed to a depth above the sacrificial layer SN2 which is the uppermost layer of the second stacked body LMs2. In addition, the silicon nitride layer NI functions as a CMP stop layer when the second bridge portion BT2 is formed in the opening OPD. In contrast, Figure 8 As shown in the cross section of (A1) in FIG. 1 , the openings OPD and OPE are not formed in the region where the first bridge portion BT1 and the second bridge portion BT2 are not configured later.

[0097] exist Figure 8In (Bm), silicon oxide is buried in the openings OPD and OPE. The silicon oxide deposited on the silicon nitride layer NI is removed by, for example, a CMP method. Thus, a second bridge portion BT2 is formed in the openings OPD and OPE. In this way, the second bridge portion BT2 connects the second interlayer insulating film 40 on both sides of the slit STA1. In addition, as described above, the lower end portion of the opening OPE is located above the uppermost sacrificial layer SN2 of the second laminate body LMs2. Therefore, the lower end portion of the second bridge portion BT2 is also located above the uppermost sacrificial layer SN2.

[0098] Next, when the silicon nitride layer NI is removed by dry etching or the like, as shown in FIG. Figure 8 As shown in (Am), the upper end of the slit STA2 where the second bridge portion BT2 is not formed is partially opened. Next, the amorphous silicon filled in the slit STA1, the opening portion OPC, and the slit STA2 is removed by wet etching. The processing liquid enters from the upper end opening of the slit STA2 (the portion where the second bridge portion BT2 is not formed), reaches the opening portion OPC from the bottom of the second bridge portion BT2, or diffuses to the lower end of the slit STA1 through the upper end opening of the slit STA1 (the portion where the lower structure BTB1 of the first bridge portion BT1 and the opening portion OPC filled with amorphous silicon are not formed). Thus, the amorphous silicon is removed from the slit STA1, the opening portion OPC, and the slit STA2.

[0099] Afterwards, if Fig. 9 As shown in (An) and (Bn) in FIG. 1 , conductive layers WL1 and WL2 are formed at the portions where the sacrificial layers SN1 and SN2 of the first laminate LMs1 and the second laminate LMs2 are located, thereby forming the first laminate LM1 and the second laminate LM2. Specifically, first, the sacrificial layers SN1 and SN2 are removed by wet etching. As described above, the processing liquid enters from the upper end opening of the slit STA2 and diffuses to the lower end through the opening OPC and the upper end opening of the slit STA1. As a result, the sacrificial layers SN1 and SN2 exposed on the side surfaces of the slits STA1 and STA2 are removed in the x-direction and the y-direction, and a space not shown in the figure is generated between the insulating layers OL1 and OL2, which extends in the xy plane and is layered in the z-direction.

[0100] Next, after forming an insulating layer such as aluminum oxide in the space through the slits STA1 and STA2 by using an atomic layer deposition (ALD) method, and then embedding it with a metal layer such as tungsten or molybdenum, conductive layers WL1 and WL2 can be obtained. That is, the sacrificial layers SN1 and SN2 are replaced by the conductive layers WL1 and WL2 to form the first laminated body LM1 and the second laminated body LM2. Next, the metal layer remaining on the side wall portion of the slits STA1 and STA2 is removed by a wet etching process. In addition, this process of replacing the sacrificial layers SN1 and SN2 with the conductive layers WL1 and WL2 is sometimes called a replacement process.

[0101] exist Fig. 9 In (Ao) and (Bo), a liner layer LL and a conductive portion EC are sequentially formed inside the slits STA1 and STA2. The raw material gases of the liner layer LL and the conductive portion EC enter from the upper end opening of the slit STA2 and reach the opening OPC, or diffuse to the lower end of the slit STA1 through the upper end opening of the slit STA1, similarly to the processing liquid. Thus, the first plate-like portion ST1 and the second plate-like portion ST2 are formed. In addition, a bonding portion BTO1 is formed in the opening OPC, and a first bridge portion BT1 having the bonding portion BTO1 is formed at the upper end of the slit STA1. In addition, a contact CC reaching the conductive layers WL1 and WL2, respectively, can also be formed here.

[0102] The first bridge portion BT1 connects the first interlayer insulating film 30 on both sides of the slit STA1 .

[0103] exist Fig.10 In (Ap) and (Bp) in FIG. 4 , a plug PG, a bit line BL, an upper wiring ML0, a via hole V1, and an upper wiring ML1 connected to a memory column MP or a contact CC are formed on the upper surface of the insulating layer 42, and they are covered with an insulating layer 51. The upper wiring ML1 is exposed on the surface of the insulating layer 51. On the other hand, a transistor Tr, a via hole V2, and an upper wiring ML2 are formed on a substrate SB1 different from the substrate SB2, and they are covered with an insulating layer 52. The upper wiring ML2 is exposed on the surface of the insulating layer 52. The substrate SB1 and the substrate SB2 are bonded together in such a way that the upper wiring ML1 and the upper wiring ML2 overlap each other. The insulating layers 51 and 52 are, for example, silicon oxide layers, and the insulating layers 51 and 52 are substantially integrated.

[0104] Next, the substrate SB2 is ground from below the first laminate LM1 to expose the lower end of the memory column MP, the columnar portion HR, and the first plate-like portion ST1, and the source line SL, the insulating layer 50, and the electrode film EL are sequentially formed on the exposed surface. Thus, the conductive portion EC formed on the first plate-like portion ST1 and the second plate-like portion ST2 is connected to the source line SL. In addition, the channel layer CHN of the memory column MP is connected to the source line SL. Based on the above, the semiconductor memory device 1 is manufactured.

[0105] (Comparative Example)

[0106] Fig.11 1 is a cross-sectional view showing a detailed structure of a cell array region of a semiconductor memory device 1x according to a comparative example. The semiconductor memory device 1x according to the comparative example is different from the semiconductor memory device 1 according to the first embodiment in the number and positions of bridge portions. Fig.11 (a) is a diagram for explaining the state of the laminated body LMsx before the replacement process. Fig.11 (b) and (c) are diagrams for explaining the state of the laminate LMx during the replacement process. Fig.11 (d) is a diagram for explaining the state of the layered body LMx after the replacement process.

[0107] like Fig.11 As shown in (a), when the distance L in the y direction from the slit STAx to the memory pillar MP is different on both sides of the slit STAx extending in the x direction in the cell array region, the contraction stress of the laminated body LMsx divided by the slit STAx on both sides of the slit STAx in the y direction may be different. In addition, the step portion not shown is covered by a thick interlayer insulating film, and stresses different from expansion stress and contraction stress may be generated between such a thick interlayer insulating film and the laminated body having a laminated structure with different layers.

[0108] As a result, the laminated body LMsx, the memory pillars and the columnar portions provided in the laminated body LMsx may be warped or tilted. If warping or tilting occurs in the laminated body LMsx, there is a concern that the laminated body LMsx may collapse, and the space between the insulating layers OL may be blocked, which may result in poor formation of the conductive layer WL. If warping or tilting occurs in the memory pillars and the columnar portions, there is a concern that they may contact the slits STAx or the contacts formed in the step portions.

[0109] Therefore, in order to reduce such deflection and inclination, a bridge portion BTx is sometimes formed above the slit STAx to connect the interlayer insulating films on both sides of the slit STAx in the y direction. Thus, the stress difference on both sides of the slit STAx in the y direction can be alleviated via the bridge portion BTx.

[0110] In recent years, as the storage capacity of semiconductor storage devices increases, the number of layers of the stacked body LMx has increased. As the number of layers of the stacked body LMx increases, the stress generated in the layers increases, so it is required to thicken the bridge portion BTx. However, if the film thickness of the bridge portion BTx increases, the bridge portion BTx may be formed to a depth opposite to the sacrificial layer SN of the stacked body LMsx.

[0111] Here, during the replacement process, the raw material gas of the conductive layer WL tends to be retained just below the bridge portion BTx, and a thicker metal layer MT may be formed on the lower surface of the bridge portion BTx in the slit STAx. Fig.11 As shown in (b), when the bridge portion BTx is formed to a depth opposite to the sacrificial layer SN of the laminate LMsx, a thicker metal layer MT is locally formed in the exposed surface A of the conductive layer WL formed directly below the bridge portion BTx and exposed in the slit STAx.

[0112] like Fig.11 As shown in (c) in FIG. 1 , the metal layer MT formed thickly on the exposed surface A may sometimes remain directly below the bridge portion BTx even after the metal layer is removed from the side wall portion of the slit STAx after the replacement process. Fig.11 As shown in (d) in FIG. 1 , the conductive portion EC of the plate-shaped portion STx that subsequently functions as a source line contact is close to the metal layer MT attached to the exposed surface A of the conductive layer WL, which may reduce the withstand voltage performance. On the other hand, if excessive treatment is performed to remove such a metal layer MT, the metal layer of the conductive layer WL may be dissolved more than necessary.

[0113] According to the semiconductor storage device 1 of embodiment 1, it comprises: a first bridge portion BT1, which is arranged at the upper end portion of the first plate-like portion ST1 and connects the first interlayer insulating film 30 on both sides of the first plate-like portion ST1; and a second bridge portion BT2, which is arranged at the upper end portion of the second plate-like portion ST2 and connects the second interlayer insulating film 40 on both sides of the second plate-like portion ST2.

[0114] In this way, by respectively providing the first bridge portion BT1 and the second bridge portion BT2 on the first plate-like portion ST1 and the second plate-like portion ST2, each of the first interlayer insulating film 30 and the second interlayer insulating film 40 can be more firmly connected on both sides of the first plate-like portion ST1 and the second plate-like portion ST2, compared with, for example, providing the bridge portion only on the upper end portion of the second plate-like portion ST2, thereby reducing the deflection and inclination of the first laminate LM1 and the second laminate LM2.

[0115] According to the semiconductor memory device 1 of the first embodiment, the lower ends of the first bridge portion BT1 and the second bridge portion BT2 are located above the uppermost conductive layers WL1 and WL2 in the first stacked body LM1 and the second stacked body LM2 , respectively.

[0116] As described above, since the first bridge portion BT1 and the second bridge portion BT2 corresponding to the first laminate LM1 and the second laminate LM2 are provided, the first bridge portion BT1 and the second bridge portion BT2 can be formed thinner. As a result, the metal layer MT formed thicker directly below the first bridge portion BT1 and the second bridge portion BT2 can be prevented from being attached to the exposed surface of the conductive layer WL1 and WL2 directly below the first bridge portion BT1 and the second bridge portion BT2. As a result, the reduction in the withstand voltage performance between the conductive layers WL1 and WL2 and the first plate-like portion ST1 and the second plate-like portion ST2 can be prevented.

[0117] According to the semiconductor storage device 1 of embodiment 1, the first bridge portion BT1 includes: an upper structure BTU1, whose width in the y direction is wider than the width of the first plate-like portion ST1 in the y direction; and a lower structure BTB1, whose width in the y direction is narrower than the width of the upper structure BTU1 in the y direction, connecting the upper structure BTU1 with the first plate-like portion ST1.

[0118] Thus, by providing the first bridge portion BT1 with the upper structure BTU1, a wider allowable range of positional deviation from the first plate-like portion ST1 can be ensured when the first bridge portion BT1 is formed. Therefore, the first interlayer insulating film 30 on both sides of the first plate-like portion ST1 in the y direction can be more reliably connected by the first bridge portion BT1.

[0119] According to the semiconductor memory device 1 of the first embodiment, the bonding portion BTO1 of the upper structure BTU1 of the first bridge portion BT1 has the conductive portion EC having a width in the y direction greater than the width in the y direction of the lower end portion of the second plate-shaped portion ST2 .

[0120] As described above, when the slit STA2 that becomes the second plate-shaped portion ST2 is formed later, the amorphous carbon layer CB that becomes the etching stop layer processed by the slit STA2 is filled in the conductive portion EC of the bonding portion BTO1. By forming the width of the amorphous carbon layer CB in the y direction to be wider than the width of the lower end of the slit STA2 in the y direction, it is possible to ensure that the allowable range of positional deviation between the slit STA2 and the amorphous carbon layer CB is wide, and the etching of the slit STA2 can be stopped on the amorphous carbon layer CB more reliably.

[0121] In addition, in the first embodiment, the first bridge portion BT1 and the second bridge portion BT2 are arranged to be offset from each other in the x direction when viewed from the z direction. More specifically, the first bridge portion BT1 and the second bridge portion BT2 are arranged in a manner such that, at a predetermined position in the x direction, there are portions where both the first bridge portion BT1 and the second bridge portion BT2 are arranged, portions where neither is arranged, and portions where either the first bridge portion BT1 or the second bridge portion BT2 is arranged.

[0122] However, the configuration example of the first bridge portion BT1 and the second bridge portion BT2 offset in the x direction is not limited to the above configuration. The first bridge portion BT1 and the second bridge portion BT2 may be configured as follows: when viewed from the z direction, the end of the first bridge portion BT1 and the end of the second bridge portion BT2 are configured to overlap with each other without generating a portion where neither the first bridge portion BT1 nor the second bridge portion BT2 is not configured. In addition, the first bridge portion BT1 and the second bridge portion BT2 may be configured at any position in the x direction in such a manner that the first bridge portion BT1 and the second bridge portion BT2 do not overlap with each other in the z direction.

[0123] Alternatively, the first bridge portion BT1 and the second bridge portion BT2 may be arranged so that the first bridge portion BT1 and the second bridge portion BT2 overlap each other in the z direction, that is, so that no offset occurs in the x direction. In this way, by arbitrarily determining the arrangement of the first bridge portion BT1 and the second bridge portion BT2, the bridge strength of each of the first bridge portion BT1 and the second bridge portion BT2 can be appropriately adjusted, and the deflection and tilting of the first laminate LM1 and the second laminate LM2 can be further suppressed.

[0124] (Variation Example)

[0125] Next, refer to Figure 12-13 , a semiconductor memory device according to a modification of the first embodiment will be described. In the semiconductor memory device according to the modification, the width of the conductive portion EC formed in the first bridge portion BT11 in the y direction is different from that in the first embodiment.

[0126] Fig.12 1 is a cross-sectional view showing a detailed structure of a cell array region CA of a semiconductor memory device 2 according to a modified example of the first embodiment. Fig.12 (a) is a yz cross-sectional view of a portion of the first plate-like portion ST11 where the first bridge portion BT11 is not formed. Fig.12 (b) is a yz cross-sectional view of a portion of the first plate-shaped portion ST11 where the first bridge portion BT11 is formed.

[0127] like Fig.12As shown in (a) of FIG. 1 , in the first plate-like portion ST11, the conductive portion EC and the liner layer LL are formed in order from the inside, and the conductive portion EC in the upper end portion of the first plate-like portion ST11 has a width L1 in the y direction. Fig.12 As shown in (b), the first bridge portion BT11 includes: a lower structure BTB11, which is constructed in the same manner as the lower structure BTB1 of the first embodiment; and an upper structure BTU11, which has a joint portion BTO11 different from the joint portion BTO1 of the first embodiment. The upper structure BTU11 of the variation has a conductive portion EC and a joint portion BTO11 on which a liner layer LL is formed, and the conductive portion EC in the joint portion BTO11 has a width L2 in the y direction. The width L2 in the y direction of the conductive portion EC formed in the first bridge portion BT11 is less than the width L1 in the y direction of the upper end portion of the conductive portion EC formed in the first plate-like portion ST11. Thus, it is possible to ensure that the distance L3 between the end portion in the y direction of the conductive portion EC formed in the first bridge portion BT11 and the memory column MP is wider.

[0128] However, in the modification, it is preferable that the width L2 of the conductive portion EC formed in the first bridge portion BT11 in the y direction is larger than the width of the upper end portion of the conductive portion EC formed in the second plate-shaped portion ST12 in the y direction.

[0129] Next, refer to Fig.13 , while explaining a method for forming the cell array region CA of a variation example. Fig.13 FIG. 1 is a diagram illustrating a part of the sequence of a method for manufacturing a semiconductor memory device 2 according to a variation of the first embodiment. Fig.13 Before the processing of Figure 4 (Aa)~ Figure 5 At the above point in time, the lower structure BTB11 and the opening OPC above the lower structure BTB11 are formed at the position where the first bridge portion BT11 is formed.

[0130] exist Fig.13 In (a), a sidewall layer 35 such as an amorphous silicon layer is deposited on the insulating layer 33. The sidewall layer 35 is deposited on the bottom surface and sidewalls of the opening OPC. When the sidewall layer 35 is deposited on the above-mentioned parts and reaches a predetermined film thickness, the opening OPC is filled with the sidewall layer 35.

[0131] exist Fig.13In (b), when the sidewall layer 35 is etched back until the bottom of the opening OPC is exposed, the bottom surface of the opening OPC is exposed, and a portion of the sidewall layer 35 remains on the side of the opening OPC, forming a sidewall 35w. Due to the sidewall 35w covering the side of the opening OPC, the exposed width of the bottom surface of the opening OPC in the y direction is narrower than the original width of the opening OPC in the y direction.

[0132] exist Fig.13 In (c), after the insulating layer 33 is fully etched, the side wall 35w becomes a mask, and the bottom surface of the opening OPC exposed from the side wall 35w is etched away. Thus, an opening OPF extending from the bottom of the opening OPC in the depth direction is formed. In addition, the thickness of the insulating layer 33 is reduced as a whole.

[0133] exist Fig.13 In (d), the sidewall 35w is removed by wet etching, and the Figure 5 The amorphous carbon layer CB is filled in the opening OPE by a process corresponding to (Ag) in the above embodiment. Figure 6 The processing corresponding to the processing after (Ah) forms the first bridge portion BT11 of the semiconductor memory device 2 of the modified example.

[0134] According to the semiconductor memory device 2 of the variation, the width L2 of the conductive portion EC formed in the first bridge portion BT11 in the y direction is less than the width L1 of the conductive portion EC formed in the upper end portion of the first plate-like portion ST11 in the y direction. As a result, it is possible to ensure that the distance between the conductive portion EC formed in the first bridge portion BT11 and the memory column MP is wide, thereby improving the withstand voltage performance between the memory column MP and the conductive portion EC of the first bridge portion BT11. According to the semiconductor memory device 2 of the variation, in addition, the same effects as those of the semiconductor memory device 1 of the first embodiment are achieved.

[0135] (Implementation Method 2)

[0136] Next, refer to Figures 14A to 20 , a semiconductor memory device according to Embodiment 2 will be described. The semiconductor memory device according to Embodiment 2 is different from the above-described Embodiment and Modification Examples in the shape of the plate-like portion, the timing of forming the plate-like portion, the material of the bridge portion, and the like.

[0137] Fig.14A FIG. 1 is a partial top view illustrating a configuration example of a semiconductor memory device 10 according to Embodiment 2. More specifically, Fig.14A is a partial top view showing a schematic configuration of a semiconductor storage device 10 according to a second embodiment. Figure 1 The corresponding figure of the example. In addition, Fig. 14B2 is a cross-sectional view illustrating a configuration example of a semiconductor memory device 10 according to Embodiment 2. More specifically, Fig. 14B (a) is a diagram showing the detailed structure of the step area SA of the second embodiment, and is along Fig.14A The yz cross-sectional view of the L5a-L5a line. In addition, Fig. 14B (b) is along Fig.14A yz cross-sectional view of the L5b-L5b line.

[0138] like Fig.14A As shown, a plurality of plate-like portions STJ are formed in the cell array region CA and the step region SA to divide them. Each of the plurality of plate-like portions STJ crosses the cell array region CA and the step region SA in the x direction, extends in the z direction in the figure, and terminates in the source line (described later). In each of the plurality of plate-like portions STJ, the side surfaces on both sides of the y direction are formed into a periodic waveform shape in the x direction. In addition, the plate-like portion STJ has a plurality of second bridge portions BT22 intermittently arranged in the length direction (x direction) of the plate-like portion STJ.

[0139] like Fig. 14B As shown in (a), the plate-like portion STJ includes: a first plate-like portion ST21, which extends along the x direction and penetrates the first stacked body LM1, the insulating layers 31, 32, 34 and 36 along the z direction; and a second plate-like portion ST22, which extends along the x direction and penetrates the second stacked body LM2 and the second interlayer insulating film 40 along the z direction and is connected to the upper end portion of the first plate-like portion ST21.

[0140] In addition, the first plate-like portion ST21 and the second plate-like portion ST22 each have a first bridge portion BT21 and a second bridge portion BT22 at a portion of the upper end. The first bridge portion BT21 includes at least one of polycrystalline silicon and silicon carbonitride. The second bridge portion BT22 includes at least one of silicon oxide, polycrystalline silicon and silicon carbonitride. In this case, the first bridge portion BT21 and the second bridge portion BT22 may be made of the same material or different materials.

[0141] In contrast, Fig. 14B As shown in (b) in FIG. 1 , the first bridge portion BT21 and the second bridge portion BT22 are not formed in other parts of the upper end portions of the first plate-like portion ST21 and the second plate-like portion ST22. This is because the first bridge portion BT21 and the second bridge portion BT22 are respectively arranged intermittently in the x direction.

[0142] Fig.15 This is a diagram for explaining the positional relationship between the first bridging portion BT21 and the second bridging portion BT22 according to the second embodiment. Fig.15 (a) is along Fig. 14B The L7-L7 line in (a) Fig.15 (b) is along Fig. 14B The xy cross-sectional view of line L8-L8 in (a). That is, Fig.15 (a) and (b) are top views of the first plate-like portion ST21 and the second plate-like portion ST22 in the extending direction. Fig.14A Similarly, along the L5a-L5a line shown Fig.15 The yz cross section of L5a-L5a shown in (a) and (b) is equivalent to Fig. 14B The surface shown in (a) in .

[0143] like Fig.15 As shown in (a) and (b) in the figure, the side surfaces of the first plate-like portion ST21 and the second plate-like portion ST22 in the y direction are formed into a periodic wavy shape in the x direction. Specifically, the first plate-like portion ST21 and the second plate-like portion ST22 are formed by connecting a plurality of roughly cylindrical columnar portions S extending in the z direction to each other in the x direction, and thus have side surfaces Sb having a shape in which the side surfaces on both sides of the y direction of each columnar portion S are connected in a wavy manner. In addition, since the liner layer LL of the first plate-like portion ST21 and the second plate-like portion ST22 is also formed along the side wall of this wavy shape, it also has a wavy shape. In addition, since the conductive portion EC of the first plate-like portion ST21 and the second plate-like portion ST22 is filled inside the wavy liner layer LL, the side walls on both sides of the y direction also have a wavy shape.

[0144] like Fig.15 As shown in (b) in FIG. 1 , the first bridge portions BT21 are arranged at equal intervals so as to cover the connecting portions of the respective columnar portions S in the first plate-like portion ST21. Fig.15 As shown in (a) in FIG. 1 , the second bridge portion BT22 is provided so as to continuously cover the plurality of columnar portions S in the second plate-like portion ST22 .

[0145] Below, while referring to Figures 16 to 20 , while describing a method for forming each structure in the cell array region CA and the step region SA according to the second embodiment. Figures 16 to 20 This is a diagram illustrating a part of the procedure of the method for manufacturing the semiconductor memory device 10 according to the second embodiment. Fig.16 (Aa) to Fig. 20 (Aj) is along Fig.14A yz cross-sectional view of line L6-L6. Fig.16 (Ba) to Fig. 20 (Bj) is along Fig.14A The yz cross-sectional view of the L5a-L5a line is equivalent to Fig. 14B The cross section shown in (a) in FIG. Fig.16 (Cb), (Cc), Fig.17 (Ce), Fig.19 The (Ch) in are Figure 16 to Figure 19 The corresponding part of the top view in the figure.

[0146] exist Fig.16 Before the processing of (Aa) and (Ba) in the embodiment 2, the same processing as that of the embodiment 1 is also performed. Figure 4 At the above point in time, the first layered body LMs1 has been formed.

[0147] exist Fig.16 In (Aa) of FIG. 1 , a memory hole MHA1 is formed to penetrate the first laminate body LMs1 and the insulating layer 31. Next, amorphous carbon is buried in the memory hole MHA1. Fig.16 In (Ba), unlike the first embodiment, the hole HRA1 is not formed.

[0148] Next, an insulating layer 32 is formed on the insulating layer 31 and the insulating layer 34. Fig.16 As shown in (Bb) in FIG. 1 , a hole STH1 and a hole HRA1 are formed that penetrate the first laminate LMs1, the insulating layers 31, 32, and 34. The holes STH1 and HRA1 are circular holes that terminate at the substrate SB2. The diameters of the holes STH1 and HRA1 are larger than the diameter of the memory hole MHA1. In addition, the diameter of the hole STH1 may be substantially equal to the diameter of the hole HRA1, or may be slightly larger than the diameter of the hole HRA1. Fig.16 As shown in (Cb) in FIG. 1 , a plurality of holes STH1 are arranged at predetermined intervals in the x direction. Then, amorphous carbon is buried in the holes STH1 and the holes HRA1.

[0149] In contrast, Fig.16 (Ab) in the figure represents a cross section between a plurality of holes STH1 arranged at predetermined intervals in the x direction. Fig.16 The cross section (Ab) in FIG. 1 does not have a hole STH1. Fig.16 As shown in (Cb) in FIG. 1 , since the holes STH1 are arranged at predetermined intervals in the x direction, when observing the yz cross section, as shown in FIG. Fig.16 As shown in (Ab) and (Bb) in FIG. 1 , a cross section with and without a hole STH1 is shown. The hole STH1 is provided in order to form the slit STA1 and the first plate-like portion ST21 later.

[0150] Then, if Fig.16As shown in (Ac) and (Bc) in FIG. 1 , an insulating layer 36 is formed to cover the hole STH1, the hole HRA1 and the insulating layer 32. The insulating layer 36 is, for example, a silicon oxide layer. Next, a photoresist film (not shown) is coated on the insulating layer 36 to open the photoresist film in such a way that the portions between the plurality of holes STH1 are exposed. Using the photoresist film as a mask, the insulating layers 32 and 36 are dry-etched to a depth that does not reach the lower surface of the insulating layer 31. At least one of polysilicon and silicon carbonitride is buried in the formed opening. Thus, the first bridge portion BT21 is formed. As shown in FIG. Fig.16 As shown in (Cc) in FIG. 1 , the first bridge portion BT21 is disposed between the plurality of holes STH1 and is not disposed above the hole STH1. Fig.16 As shown in the cross section shown in (Bc) in FIG. 1 , the first bridge portion BT21 is not formed at the arrangement position of the hole STH1.

[0151] At this time, the width L4 of the first bridge portion BT21 in the x direction of the portion disposed between the holes STH1 is preferably smaller. This is because the smaller the width L4, the lower the possibility that the first bridge portion BT21 overlaps the opening portion of the hole STH1, and the lower the possibility that the hole STH1 is almost or completely covered by the first bridge portion BT21. The reason is that if the first bridge portion BT21 covers most or all of the hole STH1, then when the hole STH2 is formed on the hole STH1, the first bridge portion BT21 will hinder dry etching, and sometimes the hole STH1 and the hole STH2 will not be connected. As a result, there is a case where the formation of the plate-like portion STJ is hindered.

[0152] Next, the second laminate body LMs2 and the insulating layer 41 are sequentially formed on the insulating layer 36. Fig.17 As shown in (Bd) in FIG. 1 , the second step portion SR2 and the insulating layer 43 covering the second step portion SR2 are formed. Fig.17 As shown in (Ad) in FIG. 1 , a memory hole (not shown) is formed through the second laminated body LMs2 and the insulating layer 41 to be connected to the memory hole MHA1 , and a memory pillar MP is formed through a predetermined process.

[0153] Next, an insulating layer 42 is formed to cover the insulating layers 41 and 43. Fig.17As shown in (Be) in the figure, a hole STH2 and a hole HRA2 are formed which penetrate the second laminated body LMs2 and the insulating layers 41 to 43. At this time, the etching conditions of the hole STH2 and the hole HRA2 have high selectivity with respect to the polysilicon or silicon carbonitride etc. which constitute the first bridge portion BT21. However, as described above, since the first bridge portion BT21 is formed so as not to completely block the hole STH1, the hole STH2 and the hole HRA2 are connected to the upper ends of the hole STH1 and the hole HRA1, respectively. The diameters of the hole STH2 and the hole HRA2 are substantially equal to the diameters of the hole STH1 and the hole HRA1, respectively. The hole STH2 is provided in order to form the slit STA2 and the second plate-like portion ST22 later. In contrast, in Fig.17 In the cross section (Ae), the hole STH2 is not formed.

[0154] Next, amorphous carbon filled in the hole STH1 and the hole HRA1 is removed by ashing or the like.

[0155] Then, if Fig.18 As shown in (Bf) in FIG. 1 , an insulating layer 70 is formed to cover the side walls of the holes STH1 and STH2 and the holes HRA1 and HRA2. The insulating layer 70 is, for example, a silicon oxide layer. Next, a silicon nitride layer NA is formed to cover the hole STH2. The silicon nitride layer NA is formed to have a covering property to the extent that it does not fill the inside of the hole STH2. Next, an insulating layer 44 is buried in the holes HRA1 and HRA2 that are not covered by the silicon nitride layer NA. The insulating layer 44 is, for example, a silicon oxide layer. In addition, the silicon nitride layer NA is formed into a plate-like shape that covers the hole STH2 in the step area SA and the cell array area CA. Therefore, as shown in FIG. Fig.18 As shown in the cross section of (Af) in FIG. 1 , the silicon nitride layer NA is formed even in the cross section where the hole STH2 is not formed, and the insulating layer 44 is further deposited.

[0156] exist Fig.18 In the (Ag) and (Bg) of FIG. 1 , the insulating layer 44 deposited on the insulating layer 42 is removed by, for example, a CMP method, and then the silicon nitride layer NA is removed by a wet etching process. Thus, a hole STH2 is opened on the surface of the insulating layer 42. In addition, at this time, the sacrificial layers SN1 and SN2 are protected by the insulating layer 70 and are not affected by the processing liquid.

[0157] exist Fig.19In (Ah) and (Bh), a silicon nitride layer NB having an opening OPG above the hole STH2 is formed on the insulating layer 42, so that the processing liquid of the wet etching process penetrates from the opening OPG. The processing liquid enters from the opening OPG, passes through the hole STH2, and penetrates to the lower end of the hole STH1. At this time, as described above, since the first bridge portion BT21 is formed so as not to completely block the hole STH1, the processing liquid can penetrate from the lower end of the hole STH2 to the hole SRH1. In the wet etching process, by selecting a processing liquid with high selectivity for polysilicon and silicon carbonitride, the dissolution of the first bridge portion BT21 can be prevented.

[0158] As a result, the insulating layer 70, the sacrificial layers SN1, SN2, and the insulating layers OL1, OL2, etc., which are exposed on the sidewalls of the holes STH1 and STH2, are dissolved, and the diameters of the holes STH1 and STH2 are expanded in the xy direction. Fig.19 As shown in (Ch) in FIG. 1 , the holes STH1 and STH2 adjacent to each other in the x direction are connected to each other to form slits STA21 and STA22 extending in the x direction.

[0159] Furthermore, as described above, since the first bridge portion BT21 is formed so as not to completely block the hole STH1 , the upper end of the slit STA21 and the lower end of the slit STA22 are connected from the lower end of the hole STH2 to the hole STH1 .

[0160] At this time, the silicon nitride layer NB can be formed thickly. Thus, the silicon nitride layer NB remains on the insulating layer 42 until the slits STA21 and STA22 are formed, so that the insulating layer 42 can be protected from the treatment liquid. Fig.19 The first bridge portion BT21 in (Ah) is resistant to the processing liquid and therefore remains until the slits STA21 and STA22 are formed.

[0161] exist Fig.19In (Ai) and (Bi), amorphous carbon is buried in the slits STA21 and STA22, and then the slits STA21 and STA22, and the insulating layer NC covering the silicon nitride layer NB are formed. The insulating layer NC is formed of at least one material selected from silicon oxide, polycrystalline silicon and silicon carbonitride. Next, a photoresist film not shown is coated on the insulating layer NC, and the photoresist film is opened at a position overlapping with the slit STA22 in the z direction. The opening of the photoresist film extends along the x direction in a manner overlapping with the plurality of holes STH2 constituting the slit STA22. Using the photoresist film as a mask, the insulating layer NC is dry-etched to a depth that does not reach the lower surface of the insulating layer NC, and then the photoresist film is removed by ashing. At this time, in the opening of the insulating layer NC, since a portion of the insulating layer NC remains on the upper surface of the slit STA22, the amorphous carbon buried in the slits STA21 and STA22 is protected by the insulating layer NC and does not disappear due to ashing.

[0162] Next, the residual film of the insulating layer NC is dry-etched until the amorphous carbon buried in the slit STA22 is exposed, and then the etching gas is switched, and the insulating layer NC in the area after the opening is removed is used as a mask to dry-etch the silicon nitride layer NB, the insulating layer 42, and the amorphous carbon to a depth that does not reach the lower surface of the insulating layer 42. Fig.19 As shown in (Bi) in FIG. 1 , an opening OPH is formed at the upper end of the slit STA22. Fig.19 In the cross section (Ai) in FIG. 1 , the opening OPH is not formed in the region where the second bridge portion BT22 is not formed. At this time, by using the insulating layer NC, which is a material different from the silicon nitride layer NB, as a mask, for example, even if the switching timing of the etching gas after the amorphous carbon is exposed is deviated, and etching is continued with the gas before switching for a short time after the amorphous carbon is exposed, the risk of over-etching the silicon nitride layer NB can be reduced.

[0163] exist Fig. 20 In (Bj), at least one of silicon oxide, polysilicon and silicon carbonitride is used to bury the same material as the insulating layer NC in the opening OPH. The deposits deposited on the insulating layer NC and the insulating layer NC are removed simultaneously by, for example, CMP. Thus, the second bridge portion BT22 is formed. In contrast, as described above, Fig. 20 (Aj) in FIG. 1 is a cross section where the second bridge portion BT22 is not formed. In the portion where the second bridge portion BT22 is not formed, amorphous carbon is exposed at the upper end portion of the slit STA2.

[0164] Next, although not shown in the figure, Fig. 20 After (Aj) and (Bj) in FIG. 1 , the silicon nitride layer NB is removed by dry etching, and the amorphous carbon filled in the slits STA21 and STA22 is removed by ashing or the like. Fig. 9The semiconductor storage device 10 of the second embodiment is formed by the processing corresponding to the processing after (An) and (Bn).

[0165] According to the semiconductor memory device 10 of the second embodiment, the side surfaces of the first and second plate-like portions ST21 and ST22 in the y direction have a periodic waveform shape in the x direction. As described above, by configuring the first and second plate-like portions ST21 and ST22 to connect a plurality of holes STH1 and STH2 and having a waveform shape in the y direction, the holes STH1 and STH2 that form the bases of the first and second plate-like portions ST21 and ST22 and the holes HRA1 and HRA2 that form the bases of the columnar portions HR can be formed together.

[0166] Here, the memory holes MHA1 and MHA2 are processed under etching conditions suitable for processing the first and second stacked bodies LMs1 and LMs2 formed by stacking the sacrificial layers SN1 and SN2 and the insulating layers OL1 and OL2. On the other hand, when forming slits by penetrating not only the first and second stacked bodies LMs1 and LMs2 but also the first and second interlayer insulating films 30 and 40, as in the slits STA1 and STA2 of the first embodiment, etching conditions different from those for the memory holes MHA1 and MHA2 are required. In addition, the columnar portion HR has the function of supporting the first and second stacked bodies LMs1 and LMs2 during the replacement process, and does not contribute to the function of the semiconductor memory device 10, and therefore does not require precision processing like the memory holes MHA1 and MHA2.

[0167] Therefore, by separately forming the memory holes MHA1 and MHA2 that require precision processing of the first and second stacked bodies LMs1 and LMs2, and forming the holes STH1 and STH2 for processing the first and second plate-like parts ST21 and ST22 in parallel with the holes HRA1 and HRA2 for processing the columnar parts HR, the manufacturing load of the semiconductor storage device 10 can be reduced and the manufacturing cost can be cut.

[0168] In addition, in the present embodiment, the first bridge portion BT21 includes at least one material selected from polysilicon and silicon carbonitride, and the second bridge portion BT22 includes at least one material selected from silicon oxide, polysilicon and silicon carbonitride. However, the materials used for the first bridge portion BT21 and the second bridge portion BT22 are not limited to the above examples. For example, the first bridge portion BT21 can be any combination as long as it is resistant to the processing liquid used when forming the slits STA21 and STA22.

[0169] (Variation 1)

[0170] In the configuration of the first modification of the second embodiment, a first plate-shaped portion ST31 and a first bridging portion BT31 are used instead of the first plate-shaped portion ST21 and the first bridging portion BT21 of the second embodiment. Fig.21 An example of arrangement of the first bridging portion BT31 according to Modification 1 of Embodiment 2 is shown. The first bridging portion BT31 is arranged at an upper end portion of the first plate-like portion ST31 at a different interval from that of the first bridging portion BT21 .

[0171] like Fig.21 As shown, the first bridge portion BT31 includes a plurality of first bridge portions BT31 arranged along the x direction. At least a portion of the plurality of first bridge portions BT31 is arranged at different intervals. Specifically, for example, the first bridge portion BT31 may be arranged in a manner such that a plurality of columnar portions S are sandwiched therebetween and a portion of the upper end of the first plate-like portion ST31 is covered, rather than being arranged at equal intervals in a manner such that the connecting portion of each columnar portion S is covered.

[0172] In this way, the arrangement density of the first bridge portions BT31 is appropriately varied according to the bridge strength required of the first bridge portions BT31 , thereby preventing the first bridge portions BT31 from being excessively formed, reducing the manufacturing load of the semiconductor memory device 10 and reducing the manufacturing cost.

[0173] (Variation 2)

[0174] In the second embodiment, the hole STH2 and the hole HRA2 are formed using etching conditions having selectivity with the first bridge portion BT21. However, the hole STH2 and the hole HRA2 may be formed using etching conditions not having selectivity with the first bridge portion BT21.

[0175] In the above case, when the first bridge portion BT21 is initially formed, the first bridge portion BT21 may be formed so as to block the upper end of the hole STH1. This is because when the hole STH2 is formed at a position overlapping with the hole STH1 in the z direction, the lower end of the hole STH2 passes through the first bridge portion BT21 blocking the upper end of the hole STH1 and is connected to the hole STH1.

[0176] In the configuration of the second modification of the second embodiment, a first plate-shaped portion ST41 and a first bridging portion BT41 are used instead of the first plate-shaped portion ST21 and the first bridging portion BT21 of the second embodiment. Fig. 22 1 is a diagram showing an example of arrangement of the first bridge portion BT41 according to Modification 2. The first bridge portion BT41 covers not only the connecting portion of the columnar portion S but also the columnar portion S at the upper end portion of the first plate-like portion ST41.

[0177] like Fig. 22As shown, the first bridge portion BT41 is configured in a manner spanning across a plurality of columnar portions S. Here, the hole STH1 in the layer of the first bridge portion BT41 is not connected in the x direction even after the hole STH1 and the hole STH2 are connected. This is because the material constituting the first bridge portion BT41 does not dissolve in the wet etching process that connects the hole STH1 and the hole STH2. Therefore, after forming a plurality of columnar portions S having a liner layer LL and a conductive portion EC inside thereof, the portion of the hole STH1 extending in the layer of the first bridge portion BT41 becomes a plurality of columnar portions Z that are not connected to each other. The columnar portion Z, like the columnar portion S, has a liner layer LL and a conductive portion EC inside thereof. However, unlike the liner layer LL and the conductive portion EC of the columnar portion S, the liner layer LL of the columnar portion Z has a shape that is independently closed into an annular shape, and the conductive layer EC exists independently of each other in the annular shape of the liner layer LL. The columnar portion Z is connected to the first plate-shaped portion ST21 at its lower end, and is connected to the lower end of the second plate-shaped portion ST22 at its upper end.

[0178] In this way, as the processing conditions for the hole STH2 and the hole HRA2, an etching condition that is not selective to the first bridge portion BT21 is adopted, thereby reducing the positioning accuracy of the first bridge portion BT21 relative to the hole STH1, reducing the manufacturing load of the semiconductor storage device 10, and reducing the manufacturing cost.

[0179] In addition, compared with the first bridge portion BT21 of the second embodiment that covers the side portions Sb, the first bridge portion BT41 that is arranged so as to span a plurality of columnar portions S has a larger installation volume, thereby improving the support strength of the insulating layer 32. As a result, the bending and tilting of the layer can be further suppressed.

[0180] in addition, Fig. 20 , 21 The arrangement example of the first bridge portions BT31 and BT41 is merely an example and is not limited thereto. The x-direction length, adjacent interval, number, etc. of the first bridge portions BT31 and BT41 can be appropriately determined.

[0181] (Other embodiments)

[0182] In the first and second embodiments and their variations, the semiconductor memory device has a two-layer (Tier) stacked structure including a first stacked body LM1 and a second stacked body LM2. However, the semiconductor memory device may also have a stacked structure of more than three layers. In addition, in a multi-tier semiconductor memory device, it is easy to further increase the number of stacked layers of the conductive layer WL.

[0183] In the above-mentioned embodiments 1 and 2 and their variations, the plate-like parts STL and STJ have the conductive parts EC, but are not limited thereto. For example, the plate-like parts STL and STJ may be entirely formed of insulating materials such as silicon oxide. In the above-mentioned case, such plate-like parts STL and STJ do not function as source line contacts.

[0184] Specifically, the first plate-like portion ST21 extends along the x direction and penetrates the laminated body LM1 along the z direction, and has silicon oxide. The second plate-like portion ST22 extends along the x direction and penetrates the laminated body LM2 along the z direction and is connected to the upper end of the first plate-like portion ST21, and has silicon oxide. The first bridge portion BT21 is arranged at the upper end of the first plate-like portion ST21, has a material different from silicon oxide, and connects the first interlayer insulating film 30 on both sides of the first plate-like portion ST21. Silicon oxide is an example of the first insulating material.

[0185] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the present invention. These novel embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the subject matter of the invention. These embodiments or their variations are included in the scope or subject matter of the invention, and are included in the invention described in the claims and their equivalents.

[0186] [Explanation of Symbols]

[0187] 1,1x,2,10 Semiconductor storage device

[0188] 30 1st interlayer insulating film

[0189] 40 Second interlayer insulating film

[0190] 31,32,33.34,41,42,43,44,50,51,52,70 insulation layer

[0191] 35 Sidewall layer

[0192] BTx Bridging Department

[0193] BT1, BT11, BT21 1st bridge section

[0194] BT2, BT22 Second Bridge Section

[0195] CA cell array area

[0196] CC Contact

[0197] HRA1,HRA2 holes

[0198] LMs1, LM1 1st laminated body

[0199] LMs2,LM2 2nd laminated body

[0200] MP Memory Column

[0201] NA,NB Silicon Nitride Layer

[0202] NC Insulation

[0203] OL1, OL2 insulation layer

[0204] PER Peripheral Circuit Department

[0205] SA Step Area

[0206] SB1,SB2 substrate

[0207] SN1 Sacrificial Layer

[0208] SN2 Sacrificial Layer

[0209] SR Step

[0210] SR1 1st step

[0211] SR2 2nd step

[0212] ST1, ST21 1st plate-shaped part

[0213] ST2, ST22 2nd plate-shaped part

[0214] STA1,STA2,STA21,STA22,STAx slit

[0215] Tr Transistor

[0216] V,V1,V2 vias

[0217] WL1 Conductive layer

[0218] WL2 conductive layer.

Claims

1. A semiconductor storage device comprising: A first laminated body, wherein a plurality of first conductive layers and a plurality of first insulating layers are alternately laminated layer by layer, and the plurality of first conductive layers are processed into a first stepped portion extending in a first direction intersecting with a lamination direction of the first conductive layers; a first interlayer insulating film covering the first stepped portion; A second laminated body, disposed on the first laminated body, wherein a plurality of second conductive layers and a plurality of second insulating layers are laminated alternately layer by layer, and the plurality of second conductive layers are processed into a second stepped portion which is continuous with the first stepped portion in the first direction; a second interlayer insulating film covering the second stepped portion; a first plate-shaped portion extending along the first direction and penetrating the first stacked body along the stacking direction; a second plate-shaped portion extending along the first direction and penetrating the second laminated body along the lamination direction and connected to an upper end portion of the first plate-shaped portion; a first bridge portion disposed at an upper end portion of the first plate-shaped portion and connecting the first interlayer insulating film at both sides of the first plate-shaped portion; and a second bridge portion, disposed at an upper end portion of the second plate-shaped portion, connecting the second interlayer insulating film at both sides of the second plate-shaped portion; and The lower ends of the first and second bridge portions are located above the uppermost first and second conductive layers in each of the first and second laminated bodies.

2. The semiconductor memory device according to claim 1, wherein The first and second plate-shaped portions, and at least a portion of the first bridge portion have a conductive portion containing a conductive material; The width of the conductive portion of the first bridge portion in a second direction intersecting the first direction and the stacking direction is less than the width of the conductive portion of the first plate-shaped portion at the upper end portion in the second direction.

3. The semiconductor memory device according to claim 2, wherein The side surfaces of the first and second plate-shaped portions in the second direction have a wave shape that is periodic in the first direction.

4. The semiconductor memory device according to claim 3, wherein The first and second plate-like portions have a shape in which a plurality of columnar portions extending in the stacking direction are connected to each other in the first direction.

5. The semiconductor memory device according to claim 3, wherein The first bridge portion comprises at least one material selected from polysilicon and silicon carbonitride; The second bridge portion includes at least one material selected from silicon oxide, polysilicon, and silicon carbonitride.

6. The semiconductor memory device according to claim 1, wherein The first bridge portion includes a plurality of first bridge portions arranged along the first direction; The intervals between the plurality of first bridge portions are at least partially different from each other.

7. The semiconductor memory device according to claim 1, wherein At least a portion of the first bridging portion does not overlap with at least a portion of the second bridging portion in the stacking direction.

8. The semiconductor memory device according to claim 4, wherein The first bridge portion is arranged so as to straddle the plurality of columnar portions in the first direction, and includes a plurality of columnar portions that are connected to the first and second plate-like portions in the stacking direction and are not connected to each other.

9. A semiconductor storage device comprising: A first laminated body, wherein a plurality of first conductive layers and a plurality of first insulating layers are alternately laminated layer by layer, and the plurality of first conductive layers are processed into a first stepped portion extending in a first direction intersecting with a lamination direction of the first conductive layers; a first interlayer insulating film covering the first stepped portion; A second laminated body, disposed on the first laminated body, wherein a plurality of second conductive layers and a plurality of second insulating layers are laminated alternately layer by layer, and the plurality of second conductive layers are processed into a second stepped portion which is continuous with the first stepped portion in the first direction; a second interlayer insulating film covering the second stepped portion; a first plate-like portion extending along the first direction and penetrating the first laminated body along the lamination direction, and comprising a first insulating material; a second plate-like portion extending along the first direction, penetrating the second laminated body along the lamination direction and connected to an upper end portion of the first plate-like portion, and comprising the first insulating material; and a bridge portion, which is disposed at an upper end portion of the first plate-shaped portion, has a material different from the first insulating material, and connects the interlayer insulating film at both sides of the first plate-shaped portion; and The side surfaces of the first and second plate-like portions in a second direction intersecting the first direction and the stacking direction are in a periodic wave shape in the first direction; The lower end portion of the bridge portion is located above the first conductive layer which is the uppermost layer in the first laminate.

10. A method for manufacturing a semiconductor memory device, the method forming a first laminated body, wherein a plurality of first insulating layers and a plurality of second insulating layers are alternately laminated layer by layer, and the plurality of second insulating layers are processed into a first stepped portion extending in a first direction intersecting with a lamination direction of the second insulating layers; forming a first interlayer insulating film, wherein the first interlayer insulating film covers the first stepped portion; forming a first groove portion, the groove portion penetrating the first stacked body in the stacking direction and extending along the first direction; forming a first bridge portion at an upper end portion of the first groove portion, wherein the first bridge portion connects the first interlayer insulating film at both sides of the first groove portion and a lower end portion of the first bridge portion is located above the second insulating layer; A second laminate is formed on the first laminate, wherein a plurality of third insulating layers and a plurality of fourth insulating layers are alternately laminated one by one along the lamination direction, and the second laminate includes a second step portion in which the plurality of fourth insulating layers are processed into a step-shaped portion continuous with the first step portion in the first direction; forming a second interlayer insulating film, wherein the second interlayer insulating film covers the second stepped portion; forming a first groove portion, the first groove portion penetrating the first laminated body in the lamination direction and extending along the first direction; and A second bridge portion is formed at an upper end portion of the second groove portion, the second bridge portion connects the second interlayer insulating film at both sides of the second groove portion, and a lower end portion of the second bridge portion is located above the fourth insulating layer.

Images