A highly reliable trench-gate silicon carbide VDMOS and its manufacturing method

Abstract

The present invention provides a highly reliable trench-gate silicon carbide VDMOS and a preparation method thereof. The method includes: depositing metal on the lower side of a silicon carbide substrate to form a drain metal layer, epitaxially growing on the upper side of the silicon carbide substrate to form a drift layer; forming a blocking layer on the drift layer, etching, and ion implanting to form a first P-type well region, a protrusion, a first low-resistance region, a second low-resistance region, and a third low-resistance region, and the low-resistance regions include the first low-resistance region, the second low-resistance region, and the third low-resistance region; reforming the blocking layer, etching, and ion implanting to form a P-type source region, an N-type source region, a conductive region, and a protection region; reforming the blocking layer, etching, and oxidizing to form an insulating dielectric layer, and the insulating dielectric layer is provided with trenches; reforming the blocking layer, etching, and depositing metal to form a gate metal layer and a source metal layer, and removing the blocking layer to complete the preparation; by optimizing the design of the gate structure and the source structure, the purpose of improving the reliability of the device is achieved.

Description

Technical Field

[0001] The present invention relates to a highly reliable trench-gate silicon carbide VDMOS and a preparation method thereof. Background Art

[0002] Silicon carbide VDMOS is a typical representative of silicon carbide power devices and has wide applications in fields such as electric vehicles, aerospace, and power conversion. For silicon carbide power VDMOS, the performance requirements for devices vary in different fields, but generally, the overall requirements include higher breakdown voltage capability, lower on-resistance, faster switching speed, higher reliability (including gate reliability, drain voltage shock reliability, short-circuit reliability, etc.), and lower body diode conduction loss. In fields such as aerospace, the high reliability of silicon carbide VDMOS has become the key restricting its application. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a highly reliable trench-gate silicon carbide VDMOS and a preparation method thereof, which achieve the purpose of improving device reliability through the optimized design of the gate structure and the source structure.

[0004] In the first aspect, the present invention provides a preparation method of a highly reliable trench-gate silicon carbide VDMOS, including the following steps:

[0005] Step 1: Deposit metal on the lower side of the silicon carbide substrate to form a drain metal layer, and epitaxially grow on the upper side of the silicon carbide substrate to form a drift layer;

[0006] Step 2: Form a barrier layer on the drift layer, etch the barrier layer to form a through hole, and perform ion implantation on the drift layer to form a first P-type well region and a protrusion;

[0007] Step 3: Remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and perform ion implantation on the first P-type well region to form a low-resistance region I;

[0008] Step 4: Remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and perform ion implantation on the first P-type well region to form a low-resistance region II;

[0009] Step 5: Remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and perform ion implantation on the first P-type well region to form a low-resistance region III. The low-resistance region includes low-resistance region I, low-resistance region II, and low-resistance region III;

[0010] Step 6: Remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and perform ion implantation on the drift layer to form a P-type source region;

[0011] Step 7: Remove the original barrier layer, reform the barrier layer, etch the barrier layer to form a through hole, and perform ion implantation into the drift layer to form an N-type source region;

[0012] Step 8: Remove the original barrier layer, reform the barrier layer, etch the barrier layer to form a through hole, and perform ion implantation into the drift layer to form a conductive region;

[0013] Step 9: Remove the original barrier layer, reform the barrier layer, etch the barrier layer to form a through hole, and perform ion implantation into the drift layer to form a protection region;

[0014] Step 10: Remove the original barrier layer, reform the barrier layer, etch the barrier layer to form a through hole, etch the drift layer and the first P-type well region to form a groove and a second P-type well region, and oxidize to form an insulating dielectric layer, and the insulating dielectric layer is provided with a groove;

[0015] Step 11: Remove the original barrier layer, reform the barrier layer, etch the barrier layer to form a through hole, deposit metal to form a gate metal layer;

[0016] Step 12: Remove the original barrier layer, reform the barrier layer, etch the barrier layer to form a through hole, deposit metal to form a source metal layer, and remove the barrier layer to complete the preparation.

[0017] In a second aspect, the present invention provides a highly reliable trench-gate silicon carbide VDMOS, and the silicon carbide VDMOS is prepared by using the preparation method of a highly reliable trench-gate silicon carbide VDMOS described in the first aspect.

[0018] The advantages of the present invention are as follows:

[0019] First, the present invention leads the source metal layer current to the middle of the device, and after flowing to the middle through the conductive region and then flowing longitudinally, the gate control ability of the device is realized;

[0020] Second, the present invention wraps the gate structure and the source structure of the device in the direction close to the drain by the first P-type well region and the second P-type well region. Thus, when the drain bears a large voltage, the first P-type well region and the second P-type well region realize the protection of the gate and the source of the device, and the reliability of the device is improved;

[0021] Third, in the middle JFET region of the device, a two-layer structure of a conductive region and a protection region is constructed. The conductive region can introduce electrons from the gate structure of the device into the JFET region of the device, thereby reducing the on-resistance of the device. The protection region is to suppress the voltage from the drain of the device from being distributed at the top of the device, thereby avoiding the influence of the voltage of the intermediate electric field on the gate structure of the device and improving the reliability of the device;

[0022] IV. A second P-type well region is constructed directly below the insulating dielectric layer. This second P-type well region can protect the electric field concentration at the corners of the device gate, further improving the reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The present invention will be further described below with reference to the accompanying drawings in conjunction with embodiments.

[0024] Figure 1 It is a schematic diagram of a highly reliable trench-gated silicon carbide VDMOS of the present invention.

[0025] Figure 2 It is a process cross-section of a highly reliable trench-gated silicon carbide VDMOS of the present invention Figure 1 。

[0026] Figure 3 It is a process cross-section of a highly reliable trench-gated silicon carbide VDMOS of the present invention Figure 2 。

[0027] Figure 4 It is a process cross-section of a highly reliable trench-gated silicon carbide VDMOS of the present invention Figure 3 。

[0028] Figure 5 It is a process cross-section of a highly reliable trench-gated silicon carbide VDMOS of the present invention Figure 4 。

[0029] Figure 6 It is a process cross-section of a highly reliable trench-gated silicon carbide VDMOS of the present invention Figure 5 。

[0030] Figure 7 It is a process cross-section of a highly reliable trench-gated silicon carbide VDMOS of the present invention Figure 6 。

[0031] Figure 8 It is a process cross-section of a highly reliable trench-gated silicon carbide VDMOS of the present invention Figure 7 。

[0032] Figure 9 It is a process cross-section of a highly reliable trench-gated silicon carbide VDMOS of the present invention Figure 8 。

[0033] Figure 10 It is a process cross-section of a highly reliable trench-gated silicon carbide VDMOS of the present invention Figure 9 。

[0034] Figure 11 It is a process cross-section of a highly reliable trench-gated silicon carbide VDMOS of the present invention Figure 10 。

[0035] Figure 12 Process cross-section of a highly reliable trench-gate silicon carbide VDMOS according to the present invention Figure 10 I.

[0036] Figure 13 Process cross-section of a highly reliable trench-gate silicon carbide VDMOS according to the present invention Figure 10 II.

[0037] Figure 14 Process cross-section of a highly reliable trench-gate silicon carbide VDMOS according to the present invention Figure 10 III.

[0038] Figure 15 Process cross-section of a highly reliable trench-gate silicon carbide VDMOS according to the present invention Figure 10 IV. Specific embodiments

[0039] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs. The terms used in the specification of this application herein are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0041] It should be understood that when an element or layer is referred to as "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly on", "in contact with", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below may be denoted as the second element, component, region, layer or part.

[0042] Spatial relationship terms such as "under", "below", "beneath", "underneath", "above", "over", etc. can be used herein to describe the relationship of one element or feature described in the figures with other elements or features. It should be understood that, in addition to the orientations described in the figures, spatial relationship terms also include different orientations of the device during use and operation. For example, if the device in the drawings is flipped, an element or feature described as "under other elements" or "beneath them" or "underneath them" will be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "beneath" can include both upper and lower orientations. Additionally, the device may also have other orientations (such as rotated 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.

[0043] As used herein, the singular forms "a", "an", and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that terms such as "comprises / include" or "has" specify the presence of the stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the related listed items.

[0044] As Figures 1 to 15 shown, an embodiment of the present application provides a method for preparing a highly reliable trench-gate silicon carbide VDMOS, including the following steps:

[0045] Step 1: Deposit metal on the lower side of the silicon carbide substrate 101 to form a drain metal layer 112, and epitaxially grow on the upper side of the silicon carbide substrate 101 to form a drift layer 102;

[0046] Step 2: Form a blocking layer 113 on the drift layer 102, etch the blocking layer 113 to form a through hole, and perform ion implantation on the drift layer 102 to form a first P-type well region 103 and a protrusion 1021;

[0047] Step 3: Remove the original blocking layer 113, reform the blocking layer 113, etch the blocking layer 113 to form a through hole, and perform ion implantation on the first P-type well region 103 to form a low-resistance region I 114;

[0048] Step 4: Remove the original blocking layer 113, reform the blocking layer 113, etch the blocking layer 113 to form a through hole, and perform ion implantation on the first P-type well region 103 to form a low-resistance region II 115;

[0049] Step 5: Remove the original barrier layer 113, reform the barrier layer 113, etch the barrier layer 113 to form a through hole, perform ion implantation into the first P-type well region 103 to form a low-resistance three-region 116, and the low-resistance region 1031 includes a low-resistance first region 114, a low-resistance second region 115, and a low-resistance third region 116;

[0050] Step 6: Remove the original barrier layer 113, reform the barrier layer 113, etch the barrier layer 113 to form a through hole, perform ion implantation into the drift layer 102 to form a P-type source region 106;

[0051] Step 7: Remove the original barrier layer 113, reform the barrier layer 113, etch the barrier layer 113 to form a through hole, perform ion implantation into the drift layer 102 to form an N-type source region 107;

[0052] Step 8: Remove the original barrier layer 113, reform the barrier layer 113, etch the barrier layer 113 to form a through hole, perform ion implantation into the drift layer 102 to form a conductive region 108;

[0053] Step 9: Remove the original barrier layer 113, reform the barrier layer 113, etch the barrier layer 113 to form a through hole, perform ion implantation into the drift layer 102 to form a protection region 109;

[0054] Step 10: Remove the original barrier layer 113, reform the barrier layer 113, etch the barrier layer 113 to form a through hole, and etch the drift layer 102 and the first P-type well region 103 to form a groove 10311 and a second P-type well region 104, oxidize to form an insulating dielectric layer 105, and the insulating dielectric layer 105 is provided with a groove 1051;

[0055] Step 11: Remove the original barrier layer 113, reform the barrier layer 113, etch the barrier layer 113 to form a through hole, deposit metal to form a gate metal layer 110;

[0056] Step 12: Remove the original barrier layer 113, reform the barrier layer 113, etch the barrier layer 113 to form a through hole, deposit metal to form a source metal layer 111, remove the barrier layer 113, and complete the preparation.

[0057] In this embodiment, preferably, the silicon carbide substrate 101, the drift layer 102, the low-resistance region 1031, and the conductive region 108 are all N-type; the protection region 109 is P-type.

[0058] In this embodiment, preferably, the doping concentration of the first P-type well region 103 is equal to the doping concentration of the low-resistance region 1031.

[0059] In this embodiment, preferably, the doping concentration of the conductive region 108 is less than the doping concentration of the protection region 109.

[0060] In this embodiment, preferably, the doping concentration of the P-type source region 106 is greater than that of the N-type source region 107.

[0061] In this embodiment, preferably, the thickness of the conductive region 108 is 200 nm.

[0062] In this embodiment, preferably, the thickness of the protection region 109 is 300 nm.

[0063] As Figure 1 shown, the silicon carbide VDMOS obtained by the above manufacturing method includes:

[0064] A silicon carbide substrate 101,

[0065] A drift layer 102, the lower side of the drift layer 102 is connected to the upper side of the silicon carbide substrate 101; a convex portion 1021 is provided on the drift layer 102;

[0066] A first P-type well region 103, the lower side of the first P-type well region 103 is connected to the upper side of the drift layer 102, and the inner side of the first P-type well region 103 is connected to the outer side of the convex portion 1021; a low-resistance region 1031 is provided in the first P-type well region 103, and a groove 10311 is provided in the low-resistance region 1031;

[0067] A second P-type well region 104, the second P-type well region 104 is provided in the groove 10311;

[0068] An insulating dielectric layer 105, the lower side of the insulating dielectric layer 105 is connected to the upper side of the second P-type well region 104, and the lower part of the insulating dielectric layer 105 is provided in the groove 10311; a trench 1051 is provided in the insulating dielectric layer 105;

[0069] A P-type source region 106, the lower side of the P-type source region 106 is connected to the upper side of the first P-type well region 103;

[0070] An N-type source region 107, the lower side of the N-type source region 107 is connected to the upper side of the low-resistance region 1031, the outer side of the N-type source region 107 is connected to the inner side of the P-type source region 106, and the inner side of the N-type source region 107 is connected to the outer side of the insulating dielectric layer 105;

[0071] A conductive region 108, the lower side of the conductive region 108 is connected to the upper side of the first P-type well region 103 and the upper side of the convex portion 1021, and the outer side of the conductive region 108 is connected to the inner side of the insulating dielectric layer 105;

[0072] A protection region 109, the lower side surface of the protection region 109 is connected to the upper side surface of the conductive region 108, and the outer side surface of the protection region 109 is connected to the inner side surface of the insulating dielectric layer 105;

[0073] A gate metal layer 110, the gate metal layer 110 is disposed in the trench 1051;

[0074] A source metal layer 111, the source metal layer 111 is connected to the P-type source region 106 and the N-type source region 107;

[0075] And a drain metal layer 112, the drain metal layer 112 is connected to the lower side surface of the silicon carbide substrate 101.

[0076] In another embodiment of the present invention, the doping concentration of the N-type silicon carbide substrate 101 is 2 - 8e18 cm -3 , the doping concentration of the N-type drift layer 102 is 1 - 5e16 cm -3 , the doping concentration of the N-type low-resistance region 1031 is 1 - 5e17 cm -3 , the doping concentrations of the first P-type well region 103 and the second P-type well region 104 are both 1 - 5e17 cm -3 , the doping concentration of the N-type source region 107 is 2 - 8e18 cm -3 , the doping concentration of the P-type source region 106 is 1 - 5e19 cm -3 , the doping concentration of the N-type conductive region 108 is 5 - 9e17 cm -3 , the doping concentration of the P-type protection region 109 is 1 - 5e18 cm -3, the insulating dielectric layer 105 can be silicon dioxide; the doping concentration of the silicon carbide substrate 101 is to ensure a low-resistance ohmic contact with the drain metal layer 112 and reduce the overall on-resistance of the device; the doping concentration of the drift layer 102 is a compromise between the reverse breakdown voltage and the on-resistance of the device; the doping concentrations of the first P-type well region 103 and the second P-type well region 104 are mainly considered in two aspects. One is to protect the gate and source structures of the device, so a relatively high doping concentration is required. The other is to ensure a small amount of charge in the gate, so a relatively low concentration is required. A compromise is made between the two, and this concentration is selected; the doping concentration of the low-resistance region 1031 is mainly to reduce the on-resistance of the device without affecting the protection effect of the first P-type well region 103 and the second P-type well region 104 on the device structure; the N-type source region 107 and the P-type source region 106 are to reduce the ohmic contact resistance of the device source, and at the same time, the device lattice will not be damaged by ion implantation due to too high a concentration, affecting the device stability; the concentration of the conductive region 108 is to guide the electrons from the source of the device to the JFET region and reduce the on-resistance of the device. However, too high a concentration will affect the gate inversion region of the device, thereby affecting the gate control ability of the device; the doping concentration of the protection region 109 is to prevent the electric field from diffusing to the gate structure when the device is reverse biased and protect the gate structure;

[0077] The thickness of the N-type silicon carbide substrate 101 of the device is 1 μm, and the thickness of the N-type drift layer 102 is 30 - 100 μm, which is adjusted within the above range according to different requirements for the breakdown voltage characteristics of the device. The thickness of the first P-type well region 103 under the low-resistance region 1031 is 1 μm, the thickness under the P-type source region 106 is 2 μm, and the thickness under the N-type conductive region 107 is 2 μm; the thickness of the second P-type well region 104 is 100 nm, and the thickness of the first P-type well region 103 between the low-resistance region 1031 and the conductive region 108 is 200 nm; the thickness of the low-resistance region 1031 under the N-type source region 107 is 1 μm, the thickness in the region directly below the second P-type well region 104 is 300 nm, and the thickness in the region below the conductive region 108 is 900 nm; the bottom thickness of the insulating dielectric layer is 50 nm; the thicknesses of both the N-type source region 107 and the P-type source region 106 are 300 nm, the thickness of the source metal layer 111 is 200 nm; the thickness of the conductive region 108 is 200 nm; the thickness of the protection region 109 is 300 nm; the width of the first P-type well region 103 of the device accounts for 60 - 70% of the total width of the device, which is to ensure that the on-resistance of the low-resistance region 1031 of the device is small enough to ensure the on-performance of the device;

[0078] The present invention conducts the current of the source metal layers 111 on both sides of the device to the middle of the device. After flowing through the N-type conductive region 108 to the middle and then flowing longitudinally, the gate control ability of the device is realized. This method realizes the wrapping of the first P-type well region 103 and the second P-type well region 104 around the gate structure and the source structure of the device in the direction close to the drain. Thus, when the drain bears a large voltage, the first P-type well region 103 and the second P-type well region 104 protect the gate and source of the device, improving the reliability of the device.

[0079] In the middle JFET region of the device, a two-layer structure of an N-type conductive region 108 and a P-type protection region 109 is constructed. The N-type conductive region 108 can introduce electrons from the gate structure of the device into the JFET region of the device, thereby reducing the on-resistance of the device. The P-type protection region 109 suppresses the voltage distribution at the top of the device caused by the drain, thus avoiding the influence of the voltage of the intermediate electric field on the gate structure of the device and improving the reliability of the device. A second P-type well region 104 is constructed directly below the insulating dielectric layer 105 of the device. The second P-type well region 104 can protect the electric field concentration at the corner of the gate of the device, further improving the reliability of the device.

[0080] Through the design of the device structure, the first P-type well region 103 and the second P-type well region 104 achieve a wrapped protection of the gate and source structures of the device, thereby effectively suppressing the device damage caused by the drain voltage impact and improving the reliability of the device. At the same time, the P-type protection region 109 completes the protection of the gate structure of the device from the perspective of the conductive channel of the device, realizing the high-reliability characteristics of the device.

[0081] Although the specific embodiments of the present invention are described above, those skilled in the art of this technology should understand that the specific embodiments we described are illustrative rather than used to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be covered by the scope protected by the claims of the present invention.

Claims

1. A method for preparing a high-reliability trench gate silicon carbide VDMOS, characterized in that: The steps include: Step 1: depositing metal on the lower side of the silicon carbide substrate to form a drain metal layer, and epitaxially growing on the side of the silicon carbide substrate to form a drift layer; Step 2, forming a barrier layer on the drift layer, etching the barrier layer to form a through hole, and performing ion implantation into the drift layer to form a first P-type well region and a protruding portion, wherein the inner side surface of the first P-type well region is connected to the outer side surface of the protruding portion; Step 3, ion implantation is performed into the first P-type well region to form a low resistance first region; Step 4, ion implantation is performed into the first P-type well region to form a low-resistance second region; Step 5, performing ion implantation into the first P-type well region to form a low resistance region 3, wherein the low resistance region includes a low resistance region 1, a low resistance region 2 and a low resistance region 3; Step 6, ion implantation is performed into the drift layer to form a P-type source region on the upper side of the first P-type well region; Step 7, ion implantation is performed into the drift layer to form an N-type source region on the upper side of the low resistance region, wherein the outer side of the N-type source region is connected to the inner side of the P-type source region; Step 8, performing ion implantation into the drift layer to form a conductive region on the upper side of the first P-type well region and the upper side of the protruding portion; Step 9, implanting ions into the drift layer to form a protection zone on the upper side of the conductive zone; Step 10, etching the drift layer and the first P-type well region to form a groove and a second P-type well region, wherein the second P-type well region is located at the bottom of the groove, and an insulating dielectric layer is formed by oxidation on the sidewall and bottom of the groove, wherein a groove is provided in the insulating dielectric layer; Step 11: depositing metal to form a gate metal layer in the trench; Step 12: deposit metal to form a source metal layer on the upper side of the P-type source region and the N-type source region, remove the barrier layer, and complete the preparation; Before ion implantation in step 3-9, before etching the drift layer and the first P-type well region in step 10, and before metal deposition in steps 11-12, it is necessary to remove the original barrier layer, re-form the barrier layer, and etch the barrier layer to form a through hole; A groove is arranged in the low resistance area, the inner side of the N-type source area is connected to the outer side of the insulating dielectric layer, and the outer side of the conductive area and the outer side of the protection area are connected to the inner side of the insulating dielectric layer.

2. The method for preparing a high-reliability trench gate silicon carbide VDMOS according to claim 1, characterized in that: The silicon carbide substrate, drift layer, low resistance region and conductive region are all N-type; the protection region is P-type.

3. The method for preparing a high-reliability trench gate silicon carbide VDMOS according to claim 1, characterized in that: The doping concentration of the first P-type well region is equal to the doping concentration of the low resistance region.

4. The method for preparing a high-reliability trench gate silicon carbide VDMOS according to claim 1, characterized in that: The doping concentration of the conductive region is lower than the doping concentration of the protection region.

5. The method for preparing a high-reliability trench gate silicon carbide VDMOS according to claim 1, characterized in that: The doping concentration of the P-type source region is greater than the doping concentration of the N-type source region.

6. The method for preparing a high-reliability trench gate silicon carbide VDMOS according to claim 1, characterized in that: The thickness of the conductive region is 200 nm.

7. The method for preparing a high-reliability trench gate silicon carbide VDMOS according to claim 1, characterized in that: The thickness of the protection zone is 300 nm.

8. A high reliability trench gate silicon carbide VDMOS, characterized in that: The silicon carbide VDMOS is prepared by the preparation method described in any one of claims 1 to 7.

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