Surround-around gate gallium oxide MOSFET power device and fabrication method

Abstract

This invention discloses a four-sided surround-gate gallium oxide MOSFET power device and its fabrication method, mainly addressing the problems of weak gate control and poor heat dissipation in existing gallium oxide MOSFET devices. It includes a substrate, an unintentionally doped UID gallium oxide layer, a gallium oxide channel layer, an upper Al2O3 dielectric layer, a source ohmic electrode, a drain ohmic electrode, and a top gate electrode. The substrate is made of diamond material with high thermal conductivity. An Al2O3 dielectric layer and a Ni / Au metal layer are sequentially disposed between the unintentionally doped UID gallium oxide layer and the substrate. The Al2O3 dielectric layer is connected to the upper Al2O3 dielectric layer, together surrounding the gallium oxide channel layer. The Ni / Au metal layer is connected to the top gate electrode, together surrounding the upper Al2O3 dielectric layer and the Al2O3 dielectric layer. This invention effectively improves the heat dissipation capability and gate control capability of the channel in gallium oxide MOSFET devices, and can be used to fabricate high-voltage power transistor devices.

Description

Technical Field

[0001] This invention belongs to the field of microelectronics technology, and specifically relates to a gallium oxide MOSFET power device that can be used to fabricate high-voltage power transistor devices. Background Technology

[0002] Given the excellent material properties of gallium oxide (Ga2O3), an ultra-wide bandgap semiconductor, metal-oxide-semiconductor field-effect transistors (MOSFETs) fabricated from it are expected to become the core of next-generation power electronic systems. However, the low mobility of gallium oxide results in low output power density for gallium oxide transistors. Increasing the channel layer thickness is a common method to improve output power density, but this approach simultaneously reduces the gate control capability, leading to a more negative threshold voltage, higher off-state leakage current, and lower breakdown voltage, thus limiting the development of gallium oxide MOSFETs in high-voltage, high-power applications. Therefore, improving the gate control capability of gallium oxide MOSFETs to achieve low-state leakage current and high breakdown voltage is currently one of the key research focuses for gallium oxide power devices.

[0003] Furthermore, due to the extremely low thermal conductivity of gallium oxide (GaO), GaO power devices suffer from significant heat dissipation issues. To address this, GaO epitaxial thin film material is typically transferred to a substrate with high thermal conductivity to reduce heat accumulation during device operation. However, conventional transfer methods often cause considerable damage to the epitaxial layer, hindering subsequent device fabrication.

[0004] Patent document CN115472503 A discloses a gallium oxide-based power transistor with high breakdown voltage and its fabrication method. This method involves plasma treatment of the β-Ga2O3 channel layer near the drain to obtain a high-resistivity region, thereby improving the breakdown voltage. However, this method only improves the voltage division capability of the drain region and does not fundamentally improve the gate control capability. Furthermore, the presence of the high-resistivity region reduces the output current, making it difficult to apply in high-power applications.

[0005] Patent document CN117577518 A discloses a diamond-based gallium oxide semiconductor structure and its fabrication method. The semiconductor structure, from bottom to top, consists of a diamond substrate, a silicon carbide layer, and a gallium oxide layer. The fabrication process specifically employs a defect ion implantation method to achieve gallium oxide layer stripping. This method causes significant damage to the gallium oxide layer, which is detrimental to obtaining high-quality gallium oxide thin films. Summary of the Invention

[0006] The purpose of this invention is to address the shortcomings of the prior art by providing a gallium oxide MOSFET power device with a four-sided surrounding gate and a method for fabricating it, so as to improve the gate control capability of gallium oxide MOSFET, reduce the damage caused by the peeling of gallium oxide epitaxial film, and alleviate the heat dissipation problem of gallium oxide power device.

[0007] To achieve the above objectives, the technical solution of the present invention includes the following:

[0008] 1. A four-sided surround-gate gallium oxide MOSFET power device, comprising a substrate, an unintentionally doped UID gallium oxide layer, a gallium oxide channel layer, an upper Al2O3 dielectric layer, a source ohmic electrode, a drain ohmic electrode, and a top gate electrode, characterized in that:

[0009] The substrate is made of diamond material with high thermal conductivity to effectively improve the heat dissipation capability of gallium oxide MOSFET devices; an Al2O3 dielectric layer and a Ni / Au metal layer are sequentially disposed between the unintentionally doped UID gallium oxide layer and the substrate. The Al2O3 dielectric layer is connected to the upper Al2O3 dielectric layer and together surrounds the gallium oxide channel layer; the Ni / Au metal layer is connected to the top gate electrode and together surrounds the upper Al2O3 dielectric layer and the Al2O3 dielectric layer to improve the gate's control capability over the channel.

[0010] Furthermore, the unintentionally doped UID gallium oxide layer is located above the Al2O3 dielectric layer and has a thickness of 100nm to 500nm, with a carrier concentration of 1×10⁻⁶. 14 cm -3 ~1×10 16 cm -3 ;

[0011] Furthermore, the gallium oxide channel layer is located above the unintentionally doped UID gallium oxide layer and has a thickness of 200 nm to 600 nm, with a carrier concentration of 1 × 10⁻⁶. 16 cm -3 ~1×10 18 cm -3 ;

[0012] Furthermore, the upper Al2O3 dielectric layer has a thickness of 5–35 nm;

[0013] Furthermore, both the source ohmic electrode and the drain ohmic electrode are made of Ti / Au with a thickness of 20-40 nm / 400-600 nm, and are located in the two ohmic regions above the gallium oxide channel layer, respectively.

[0014] Furthermore, the top-layer gate electrode is made of Ni / Au and has a thickness of 35-55 nm / 350-450 nm;

[0015] Furthermore, the Ni / Au metal layer has a thickness of 35–55 nm / 350–450 nm;

[0016] Furthermore, the Al2O3 dielectric layer has a thickness of 5–35 nm.

[0017] 2. A method for fabricating a four-sided surround-gate gallium oxide MOSFET power device, characterized by comprising the following steps:

[0018] 1) Select and clean the epitaxial substrate;

[0019] 2) Using a Sputter apparatus, a thin film of iron oxide is grown on the surface of the cleaned substrate and then annealed.

[0020] 3) An Al2O3 dielectric layer of 5–35 nm was deposited on top of the iron oxide layer using an ALD device;

[0021] 4) The sample with the deposited Al2O3 dielectric layer was placed in the MOCVD reaction chamber, and a carrier concentration of 1×10⁻⁶ was sequentially grown on top of the Al2O3 dielectric layer using metal-organic chemical vapor deposition. 14 cm -3 ~1×10 16 cm -3 The first α-axis gallium oxide unintentionally doped layer has a thickness of 100nm to 500nm, and the carrier concentration is 1×10⁻⁶. 16 cm -3 ~1×10 18 cm -3 A second α-axis gallium oxide channel layer with a thickness of 200 nm to 600 nm;

[0022] 5) Use a mask to determine the location of the source / drain region of the sample, and perform ion implantation in the source / drain region to form an ohmic region;

[0023] 6) Deposit Ti / Au metal stacks above the source ohmic region and the drain ohmic region, and anneal them to complete the fabrication of the source ohmic electrode and the drain ohmic electrode;

[0024] 7) The gallium oxide layer outside the source / drain region is etched away using an ICP etching machine to complete the active region isolation;

[0025] 8) A nano-strip-shaped mask is formed by photolithography using an electron beam lithography machine, and then nanochannels are formed by etching using an ICP etching machine;

[0026] 9) Use a mask to determine the gate dielectric region of the sample, and use an ALD device to deposit a 5-35 nm upper Al2O3 dielectric layer in the gate dielectric region;

[0027] 10) Deposit a Ni / Au metal stack above the upper Al2O3 dielectric layer to complete the fabrication of the upper gate electrode;

[0028] 11) Use liquid phase stripping to remove the structure above the iron oxide layer from the epitaxial substrate;

[0029] 12) The structure above the iron oxide layer is transferred and bonded to a diamond substrate with Ni / Au multilayer metal deposited on the surface using the surface activation bonding method, and then annealed to complete the fabrication of the entire device.

[0030] Furthermore, the process of growing an iron oxide film on the cleaned substrate surface using a sputtering device and then annealing it involves first breaking the vacuum in the device, sending the cleaned sample into its chamber, and setting an iron oxide target. Then, the chamber is evacuated to a vacuum, and the process conditions are set to room temperature, power of 90–160 W, and an O2 to Ar ratio of 1:5–1:2. An iron oxide film with a thickness of 100 nm–5 μm is grown on the substrate surface by sputtering. Finally, the sample is placed in an annealing furnace and annealed for 20–60 minutes under a nitrogen atmosphere and at a temperature of 500–1100 °C.

[0031] Furthermore, the method of using liquid phase stripping to remove the structure above the iron oxide layer from the epitaxial substrate involves first immersing the sample in a hydrochloric acid solution with a concentration of 0.1–3 mol / L to dissolve the iron oxide until the four corners of the structure above the iron oxide layer lift up; then placing the sample in deionized water, using the surface tension of the water to detach the upper structure from the substrate, thus obtaining the stripped gallium oxide MOSFET device.

[0032] Compared with the prior art, the present invention has the following advantages:

[0033] First, the gate of the gallium oxide MOSFET power device designed in this invention surrounds the channel layer, which can effectively improve the gate electrode's control over the channel, help reduce the off-state leakage current of the channel, and improve the device's withstand voltage.

[0034] Secondly, since the present invention transfers the gallium oxide MOSFET device onto a diamond substrate, the high thermal conductivity of diamond can be utilized to effectively alleviate the heat dissipation problem of the gallium oxide MOSFET device.

[0035] Third, the present invention uses hydrochloric acid solution to dissolve iron oxide during the preparation process. Taking advantage of the characteristic that hydrochloric acid solution does not easily dissolve gallium oxide, low-damage stripping of gallium oxide MOSFET devices can be achieved, which is beneficial to improving the performance of gallium oxide MOSFET devices. Attached Figure Description

[0036] Figure 1 This is a schematic diagram of the structure of the device of the present invention;

[0037] Figure 2 This invention is made Figure 1 Schematic diagram of device implementation process. Detailed Implementation

[0038] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0039] Reference Figure 1 The device structure of the present invention includes a diamond substrate 1, an unintentionally doped UID gallium oxide layer 2, a gallium oxide channel layer 3, an upper Al2O3 dielectric layer 4, a source ohmic electrode 5, a drain ohmic electrode 6, a top gate electrode 7, a Ni / Au metal layer 8, and an Al2O3 dielectric layer 9, wherein:

[0040] The Ni / Au metal layer 8 is located on the diamond substrate 1, and its thickness is 35-55 nm / 350-450 nm.

[0041] The Al2O3 dielectric layer 9 is located on top of the Ni / Au metal layer 8, and its thickness is 5-35 nm.

[0042] The unintentionally doped UID gallium oxide layer 2 is located on top of the Al2O3 dielectric layer 9, with a thickness of 100 nm to 500 nm and a carrier concentration of 1 × 10⁻⁶. 14 cm -3 ~1×10 16 cm -3 .

[0043] The gallium oxide channel layer 3 is located above the unintentionally doped UID gallium oxide layer 2, and has a thickness of 200 nm to 600 nm and a carrier concentration of 1 × 10⁻⁶. 16 cm -3 ~1×10 18 cm -3 .

[0044] The upper Al2O3 dielectric layer 4 has a thickness of 5-35 nm and is connected to the Al2O3 dielectric layer 9, together surrounding the gallium oxide channel layer 3.

[0045] The source ohmic electrode 5 and the drain ohmic electrode 6 are both made of Ti / Au with a thickness of 20-40 nm and 400-600 nm, respectively, and are located on both sides of the ohmic region above the gallium oxide channel layer 3.

[0046] The top gate electrode 7 is made of Ni / Au with a thickness of 35-55nm / 350-450nm. It is connected to the Ni / Au metal layer 8 and together surrounds the upper Al2O3 dielectric layer 4 and Al2O3 dielectric layer 9 to improve the gate electrode's control over the channel.

[0047] Reference Figure 2The present invention provides the following three embodiments for fabricating a four-sided surrounding gate gallium oxide MOSFET power device.

[0048] Example 1: A diamond-based, all-around gate gallium oxide MOSFET power device was fabricated with a sapphire epitaxial substrate, a sputtered iron oxide layer thickness of 100 nm, a hydrochloric acid concentration of 0.1 mol / L for stripping, a gallium oxide channel layer width of 50 nm, and a depth of 305 nm.

[0049] Step 1: Select an epitaxial substrate and clean it.

[0050] Sapphire was selected as the epitaxial substrate material. The sapphire substrate was immersed in HF acid, acetone solution and ethanol solution in sequence, and then placed in a water bath for ultrasonic treatment for 3 minutes. After that, it was rinsed with deionized water for 3 minutes and finally dried with a nitrogen gun.

[0051] Step 2: A 100 nm thick iron oxide film is grown on the surface of a sapphire substrate using a Sputter device and then annealed.

[0052] First, break the vacuum in the Sputter equipment, then place the cleaned substrate inside and set the iron oxide target.

[0053] The chamber was then evacuated to a vacuum, and the process conditions were set to room temperature, 90W power, and O2 to Ar gas ratio of 1:5. A 100nm thick iron oxide film was then grown on the substrate surface by sputtering.

[0054] The sample with the iron oxide film was placed in an annealing furnace and annealed for 20 minutes at 500°C in a nitrogen atmosphere.

[0055] Step 3: Deposit a 5 nm Al2O3 dielectric layer on top of the iron oxide layer using an ALD device.

[0056] First, place the annealed sample in the ALD chamber, set the chamber pressure to 0.1 torr, and the temperature to 150℃;

[0057] Trimethylaluminum and H2O were selected as precursors. Trimethylaluminum 0.1, nitrogen gas for 10s, H2O gas for 3s, and nitrogen gas for 10s were sequentially introduced into the chamber. This process was repeated 100 times. An Al2O3 dielectric layer with a thickness of 5nm was grown on top of the iron oxide layer using atomic layer deposition.

[0058] Step 4: Using MOCVD, an unintentionally doped UID gallium oxide layer and a gallium oxide channel layer are sequentially grown on top of the Al2O3 dielectric layer.

[0059] The sample with the Al2O3 dielectric layer was placed in the MOCVD reaction chamber, and the pipeline and chamber were pumped in and out by a mechanical pump to reduce the impurities introduced from the environment.

[0060] The reaction chamber temperature was set at 400℃, and the pressure at 40 MPa; the oxygen source was high-purity oxygen, the gallium source was TEGa, and the carrier gas was argon; the process conditions were set at a TEGa to O2 molar flow ratio of 1:5000, and MOCVD was used to grow a carrier concentration of 1×10⁻⁶ on top of the Al₂O₃ dielectric layer. 14 cm -3 The first α-axis unintentionally doped UID gallium oxide layer;

[0061] Subsequently, the reaction chamber temperature was set to 400℃, the pressure to 200mba; the oxygen source was high-purity oxygen, the gallium source was TEGa, the doping source was silane, and the carrier gas was argon; the process conditions were: a TEGa to O2 molar flow rate ratio of 1:200 and a silane molar flow rate of 50μmol / min, to grow a carrier concentration of 1×10⁻⁶ on the unintentionally doped gallium oxide layer. 18 cm -3 The second α-axis gallium oxide channel layer;

[0062] During the sequential growth of two layers of α-gallium oxide, the growth rate of the α-gallium oxide layer during epitaxy was monitored in real time by means of the change in the reflectivity of the sample, and the growth time was modified accordingly to achieve the growth of an unintentionally doped α-gallium oxide layer with a thickness of 100 nm and an α-gallium oxide channel layer with a thickness of 200 nm by metal-organic chemical vapor deposition.

[0063] Step 5: Use a mask to determine the location of the source / drain region of the sample, and perform ion implantation in the source / drain region to form an ohmic region.

[0064] First, a mask is used to determine the source and drain regions, and a layer of SiO2 is deposited in the non-source and drain regions by sputtering to serve as a mask for ion implantation.

[0065] The masked sample was placed in an ion implanter, and the implanted ions were set to Si, the implantation angle to be 6°, and the beam current to be 15mA. Ion implantation conditions were then established: 10 [units of measurement missing - likely related to ion implantation] were performed in the source / drain region. 19 cm -3 Ion implantation doping creates an ohmic region.

[0066] Step 6: Deposit Ti / Au metal stacks above the source ohmic region and the drain ohmic region, and then anneal them.

[0067] The ion-implanted sample was placed in the E-beam evaporation stage, and the vacuum level was set to 10. -6The evaporation process conditions were as follows: the metal was Ti / Au, the temperature was 25°C, and the deposition rate was 1 Å / s. Ti / Au metal stacks with thicknesses of 20 nm and 400 nm were deposited in the ohmic region.

[0068] The Ti / Au metal stack sample after vapor deposition was placed in an annealing furnace and annealed under the following conditions: N2 atmosphere, 400℃ temperature, and 20s time, to complete the fabrication of the source ohmic electrode and the drain ohmic electrode.

[0069] The sample with the completed drain and source ohmic electrodes is then immersed in a buffer oxide etching solution until SiO2 is completely removed. It is then immersed in acetone solution and ethanol solution in sequence, and placed in a water bath for ultrasonic treatment for 3 minutes. After rinsing with deionized water for 3 minutes, it is finally dried with a nitrogen gun.

[0070] Step 7: Use an ICP etching machine to etch away the gallium oxide layer outside the source / drain region to complete the active region isolation.

[0071] Use a mask to determine the source and drain regions and the area surrounding the source and drain on the cleaned sample, and use photoresist to mask the above-mentioned areas.

[0072] The masked sample was placed in an ICP etching machine, and the etching process conditions were set to 200W upper power, 50W lower power, and 10mTorr pressure. The gallium oxide layer outside the source and drain regions was etched away by 300nm through the ICP etching process to complete the active region isolation.

[0073] The sample that achieves active region isolation is sequentially immersed in acetone solution and ethanol solution until the photoresist is completely removed, then rinsed with deionized water for 3 minutes, and finally dried with a nitrogen gun.

[0074] Step 8: Use an electron beam lithography machine to form a nano-strip-shaped mask, and then use an ICP etching machine to form a nanochannel with a width of 50nm and a depth of 305nm.

[0075] First, a mask is used to determine the channel area on the cleaned sample, and then an electron beam lithography machine is used to lithographically ...

[0076] The sample with the photoresist mask on its surface is then placed into the ICP etching machine. The etching process conditions are set to 200W upper power, 50W lower power, and 10mTorr pressure. A nanochannel with a width of 50nm and a depth of 305nm is etched in the gallium oxide channel layer.

[0077] Finally, the sample with etched nanochannels was immersed in acetone solution and ethanol solution in sequence until the photoresist was completely removed. Then it was rinsed with deionized water for 3 minutes and finally dried with a nitrogen gun.

[0078] Step 9: Use a mask to determine the gate dielectric region of the sample, and use an ALD device to deposit a 5nm upper Al2O3 dielectric layer in the gate dielectric region.

[0079] The gate dielectric region of the sample is determined using a mask, and the non-gate dielectric region is masked using photoresist.

[0080] The masked sample was placed in the ALD chamber, and the chamber pressure was set to 0.1 torr and the temperature to 150℃. Trimethylaluminum and H2O were selected as precursors. Trimethylaluminum was introduced into the chamber for 0.1s, nitrogen for 10s, H2O for 3s, and nitrogen for 10s in sequence. This process was repeated 100 times. An upper Al2O3 dielectric layer with a thickness of 5nm was grown in the gate dielectric region using atomic layer deposition.

[0081] Step 10: Deposit a Ni / Au metal stack on top of the upper Al2O3 dielectric layer.

[0082] The sample with the upper Al2O3 dielectric layer grown was placed in the E-beam evaporation stage, and the vacuum level was set to 10. -6 The metal torr is Ni / Au, the temperature is 25℃, and the deposition rate is 1 angstrom / second under E-beam evaporation conditions. Ni / Au metal stacks with thicknesses of 35nm and 350nm are deposited on the upper Al2O3 dielectric layer to complete the fabrication of the top gate electrode.

[0083] Step 11: Use liquid phase stripping method to peel the structure above the iron oxide layer from the epitaxial substrate.

[0084] The sample was immersed in a 0.1 mol / L hydrochloric acid solution to dissolve the iron oxide until the four corners of the structure above the iron oxide layer curled up.

[0085] The sample is then placed in deionized water, and the surface tension of the water causes the upper structure to detach from the substrate, resulting in the stripped gallium oxide MOSFET device.

[0086] Step 12: The stripped gallium oxide MOSFET device is transferred and bonded to a diamond substrate with Ni / Au multilayer metal deposited on its surface using the surface activation bonding method, and then annealed.

[0087] A Ni / Au multilayer metal with thicknesses of 35 nm and 350 nm was deposited on a diamond substrate by E-beam evaporation, and the E-beam evaporation process conditions were the same as those in step 10.

[0088] Apply adhesive material to the front side of the temporary carrier and spin it at a speed of 1000 rpm for 30 seconds. Place the temporary carrier with the adhesive material applied face up on a hot plate and bake it at 90°C for 2 minutes to ensure that the adhesive material is evenly and firmly attached to the temporary carrier.

[0089] The stripped gallium oxide MOSFET device is directly bonded to a temporary substrate coated with adhesive material, with the front sides facing each other.

[0090] Amorphous silicon nanolayers with a thickness of 5 nm were sputtered on the surface of a gallium oxide MOSFET device with a temporary carrier bonded together and on the surface of a diamond substrate with a Ni / Au multilayer metal grown thereon, respectively, using magnetron sputtering. The silicon nanolayers were then activated using an argon atom beam.

[0091] The two activated surfaces are placed face to face and then bonded in a bonding machine at a pressure of 3000 mba.

[0092] The bonded sample is immersed in the adhesive material removal solution until the temporary carrier is completely detached, thus completing the transfer of the stripped gallium oxide MOSFET device to the diamond substrate.

[0093] The transferred sample was placed in an annealing furnace and subjected to thermal annealing at 300°C in a N2 atmosphere for 4 minutes to obtain a gallium oxide MOSFET device with a surrounding gate, thus completing the fabrication of the entire device.

[0094] Example 2: A diamond-based, all-around gate gallium oxide MOSFET power device was fabricated with an epitaxial substrate of iron oxide, a sputtered iron oxide layer thickness of 5 μm, a hydrochloric acid concentration of 3 mol / L for stripping, a gallium oxide channel layer width of 300 nm, and a depth of 720 nm.

[0095] Step A: Select the epitaxial substrate and clean it.

[0096] Iron oxide was selected as the epitaxial substrate material. The iron oxide substrate was immersed in acetone solution and ethanol solution in sequence, and then ultrasonically treated in a water bath for 5 minutes. After rinsing with deionized water for 5 minutes, it was finally dried with a nitrogen gun.

[0097] Step B involves growing a 5 μm thick iron oxide film on the substrate surface using a Sputter apparatus and then annealing it.

[0098] B1) Remove the vacuum from the Sputter equipment and place the cleaned substrate inside, then set the iron oxide target.

[0099] B2) The chamber is evacuated to a vacuum. Under the process conditions of room temperature, power of 160W, and O2 to Ar gas ratio of 1:2, a 5μm thick iron oxide film is grown on the substrate surface by sputtering.

[0100] B3) The sample with the iron oxide film was placed in an annealing furnace and annealed for 60 min at 1100 °C in a nitrogen atmosphere.

[0101] Step C: A 35 nm Al2O3 dielectric layer is deposited on top of the iron oxide layer using an ALD device.

[0102] C1) Place the annealed sample in the ALD chamber, select trimethylaluminum and H2O as precursors, and sequentially introduce 0.3s of trimethylaluminum, 15s of nitrogen, 5s of H2O, and 15s of nitrogen into the chamber.

[0103] C2) Repeat the source-passing process in step C1) a total of 700 times. Under the process conditions of chamber pressure of 0.3 torr and temperature of 300℃, grow an Al2O3 dielectric layer with a thickness of 35nm on top of the iron oxide layer by atomic layer deposition.

[0104] Step D involves using MOCVD to sequentially deposit two α-axis gallium oxide thin films on top of the Al2O3 dielectric layer.

[0105] D1) The sample with the Al2O3 dielectric layer is placed in the MOCVD reaction chamber, and the pipeline and chamber are pumped in by a mechanical pump to reduce the impurities introduced from the environment.

[0106] D2) Under the process conditions of a reaction chamber temperature of 600℃, a pressure of 200mba, high-purity oxygen as the oxygen source, TEGa as the gallium source, and argon as the carrier gas, with a TEGa to O2 molar flow ratio of 1:200, the growth rate of the α-axis gallium oxide layer during epitaxy was monitored in real time by utilizing changes in the sample's reflectivity. The growth time was adjusted accordingly. A first layer with a thickness of 500nm was grown on an Al2O3 dielectric layer using metal-organic chemical vapor deposition (MOCVD) with a carrier concentration of 1×10⁻⁶. 14 cm -3 An unintentionally doped α-axis gallium oxide layer;

[0107] D3) Under the following process conditions: reaction chamber temperature 600℃, pressure 40mba; oxygen source: high-purity oxygen; gallium source: TEGa; doping source: silane; carrier gas: argon; TEGa to O2 molar flow rate ratio: 1:5000; silane molar flow rate: 5μmol / min; the growth rate of the α-axis gallium oxide layer during epitaxy was monitored in real time by utilizing changes in sample reflectivity, and the growth time was adjusted accordingly. A second layer with a thickness of 600nm and a carrier concentration of 1×10⁻⁶ was grown on the unintentionally doped gallium oxide layer using metal-organic chemical vapor deposition. 16 cm -3 α-axis gallium oxide channel layer.

[0108] Step E: Use a mask to determine the location of the source / drain region of the sample, and perform ion implantation in the source / drain region to form an ohmic region.

[0109] E1) First, use a mask to determine the source / drain region, and then deposit a layer of SiO2 in the non-source / drain region by sputtering to serve as a mask for ion implantation;

[0110] E2) The masked sample is placed in an ion implanter. Under the conditions of Si ions, an implantation angle of 7°, and a beam current of 20mA, ion implantation is performed in the source and drain regions for 10 minutes. 20 cm -3 Doping concentration creates an ohmic region.

[0111] Step F involves depositing a Ti / Au metal stack over the source ohmic region and the drain ohmic region, followed by annealing.

[0112] F1) Place the ion-implanted sample into the E-beam evaporation stage and set the vacuum level to 10. -7 torr, under the E-beam evaporation process conditions of Ti / Au metal evaporation at 90℃ and a deposition rate of 2 Å / s, Ti / Au metal stacks with thicknesses of 40 nm and 600 nm were deposited in the ohmic region.

[0113] F2) Place the deposited Ti / Au metal stack sample into an annealing furnace and anneal it under the conditions of N2 atmosphere, 450℃ temperature and 40s time to complete the fabrication of source ohmic electrode and drain ohmic electrode.

[0114] F3) Immerse the sample with the completed drain and source ohmic electrodes in a buffer oxide etching solution until SiO2 is completely removed. Then immerse it in acetone solution and ethanol solution in sequence, and place it in a water bath for ultrasonic treatment for 5 minutes. Rinse it with deionized water for 5 minutes, and finally dry it with a nitrogen gun.

[0115] Step G involves using an ICP etching machine to etch away the gallium oxide layer outside the source / drain regions, thus completing the active region isolation.

[0116] G1) Use a mask to determine the source and drain regions and the surrounding regions of the source and drain on the cleaned sample, and use photoresist to mask the above regions.

[0117] G2) Place the masked sample in the ICP etching machine and set the etching process conditions as follows: upper power 500W, lower power 150W, and pressure 20mTorr. Use the ICP etching process to etch away 1100nm of the gallium oxide layer outside the source and drain regions to complete the active region isolation.

[0118] G3) The sample with active region isolation is immersed in acetone solution and ethanol solution in sequence until the photoresist is completely removed, then rinsed with deionized water for 5 minutes, and finally dried with a nitrogen gun.

[0119] Step H involves etching nanochannels onto the gallium oxide channel layer.

[0120] H1) Use a mask to determine the channel region on the cleaned sample, and use an electron beam lithography machine to perform photolithography on the non-channel region to form a photoresist mask in the shape of a nano-strip.

[0121] H2) The sample with a photoresist mask on its surface is placed in an ICP etching machine. Under etching process conditions of 500W upper power, 150W lower power and 20mTorr pressure, a nanochannel with a width of 300nm and a depth of 720nm is etched in the gallium oxide channel layer.

[0122] H3) The sample with etched nanochannels was sequentially immersed in acetone solution and ethanol solution until the photoresist was completely removed. Then it was rinsed with deionized water for 5 minutes and finally dried with a nitrogen gun.

[0123] Step I: Use a mask to determine the gate dielectric region of the sample, and use an ALD device to deposit a 35nm upper Al2O3 dielectric layer in the gate dielectric region.

[0124] I1) Use a mask to determine the gate dielectric region of the sample, and use photoresist to mask the non-gate dielectric region;

[0125] I2) Place the masked sample into the ALD chamber, set the chamber pressure to 0.5 torr and the temperature to 450℃; select trimethylaluminum and H2O as precursors, and sequentially introduce 0.3s of trimethylaluminum, 15s of nitrogen, 8s of H2O, and 15s of nitrogen into the chamber.

[0126] I3) Repeat the source-passing step in I2) a total of 700 times, and grow an upper Al2O3 dielectric layer with a thickness of 35nm in the gate dielectric region using atomic layer deposition.

[0127] Step J: Deposit a Ni / Au metal stack on top of the upper Al2O3 dielectric layer.

[0128] The sample with the upper Al2O3 dielectric layer grown was placed in an E-beam evaporation stage under a vacuum of 10... -6 Under the evaporation process conditions of Ni / Au metal at 75°C and E-beam with a deposition rate of 2 Å / s, Ni / Au metal stacks with thicknesses of 55 nm and 450 nm are deposited on top of the upper Al2O3 dielectric layer to complete the fabrication of the top gate electrode.

[0129] Step K involves using a liquid phase stripping method to peel the structure above the iron oxide layer from the epitaxial substrate.

[0130] K1) Immerse the sample in a 3 mol / L hydrochloric acid solution to dissolve the iron oxide until the four corners of the structure above the iron oxide layer curl up;

[0131] K2) The sample is placed in deionized water, and the surface tension of the water causes the upper structure to detach from the substrate, resulting in a stripped gallium oxide MOSFET device.

[0132] Step L involves using a surface activation bonding method to transfer and bond the stripped gallium oxide MOSFET device onto a diamond substrate with a Ni / Au multilayer metal deposited on its surface, followed by annealing.

[0133] L1) A Ni / Au multilayer metal with thicknesses of 55 nm and 450 nm is deposited on a diamond substrate by E-beam evaporation, and the E-beam evaporation process conditions are the same as those in step J.

[0134] L2) Apply adhesive material to the front side of the temporary carrier and spin it at a speed of 3000 rpm for 30 seconds. Place the temporary carrier with the adhesive material applied face up on a hot plate and bake it at 110°C for 5 minutes to ensure that the adhesive material is evenly and firmly attached to the temporary carrier.

[0135] L3) The stripped gallium oxide MOSFET device is directly bonded to a temporary substrate coated with adhesive material, with the front sides facing each other.

[0136] L4) Amorphous silicon nanolayers with a thickness of 10 nanometers were sputtered on the surface of a gallium oxide MOSFET device with a temporary carrier bonded together and on the surface of a diamond substrate with a Ni / Au multilayer metal grown thereon, respectively, using magnetron sputtering, and the silicon nanolayers were activated using an argon atom beam.

[0137] L5) Place the two activated surfaces face to face and then bond them in a bonding machine at a pressure of 5000mba.

[0138] L6) The bonded sample is immersed in the adhesive material removal solution until the temporary carrier is completely detached, thus completing the transfer of the stripped gallium oxide MOSFET to the diamond substrate.

[0139] L7) The transferred sample was placed in an annealing furnace and subjected to thermal annealing at 400°C in a N2 atmosphere for 6 minutes to obtain a diamond-based all-around gate gallium oxide MOSFET, thus completing the fabrication of the entire device.

[0140] Example 3: A diamond-based, all-around gate gallium oxide MOSFET power device was fabricated with a sapphire epitaxial substrate, a sputtered iron oxide layer thickness of 2 μm, a hydrochloric acid concentration of 1 mol / L for stripping, a gallium oxide channel layer width of 500 nm, and a depth of 1135 nm.

[0141] Step 1: Select an epitaxial substrate and clean it.

[0142] Sapphire was selected as the epitaxial substrate material. The sapphire substrate was immersed in HF solution, acetone solution and ethanol solution in sequence, and then placed in a water bath for ultrasonic treatment for 5 minutes. After rinsing with deionized water for 5 minutes, it was finally dried with a nitrogen gun.

[0143] Step 2: A 2 μm thick iron oxide film is grown on the substrate surface using a Sputter device and then annealed.

[0144] 2.1) Break the vacuum in the Sputter equipment and place the cleaned substrate inside, then set the iron oxide target.

[0145] 2.2) The chamber was evacuated to a vacuum. Under the process conditions of room temperature, power of 100W, and O2 to Ar gas ratio of 1:5, a 2μm thick iron oxide film was grown on the substrate surface by sputtering.

[0146] 2.3) The sample with the iron oxide film was placed in an annealing furnace and annealed for 40 min in a nitrogen atmosphere at 800 °C.

[0147] Step 3: A 20 nm Al2O3 dielectric layer is deposited on top of the iron oxide layer using an ALD device.

[0148] 3.1) Place the annealed sample in the ALD chamber, select trimethylaluminum and H2O as precursors, and sequentially introduce 0.2s of trimethylaluminum, 12s of nitrogen, 8s of H2O, and 12s of nitrogen into the chamber.

[0149] 3.2) Repeat the power supply process in step 3.1) a total of 400 times. Under the process conditions of chamber pressure of 0.3 torr and temperature of 300℃, grow an Al2O3 dielectric layer with a thickness of 20nm on top of the iron oxide layer by atomic layer deposition.

[0150] Step 4: Use MOCVD to sequentially apply two α-axis gallium oxide thin films on top of the Al2O3 dielectric layer.

[0151] 4.1) The sample with the Al2O3 dielectric layer is placed in the MOCVD reaction chamber, and the pipeline and chamber are pumped in and out by a mechanical pump to reduce the impurities introduced by the environment.

[0152] 4.2) A first layer with a thickness of 200 nm and a carrier concentration of 1 × 10⁻⁶ was grown on an Al₂O₃ dielectric layer using metal-organic chemical vapor deposition. 16 cm -3 The unintentionally doped α-axis gallium oxide layer is fabricated under the following conditions:

[0153] The reaction chamber temperature is 500℃ and the pressure is 100mba.

[0154] The oxygen source is high-purity oxygen, the gallium source is TEGa, and the carrier gas is argon.

[0155] The molar flow ratio of TEGa to O2 was 1:400, and the growth rate of the α-axis gallium oxide layer during epitaxy was monitored in real time by using the change in the reflectivity of the sample, and the growth time was adjusted accordingly.

[0156] 4.3) A second layer with a thickness of 600 nm and a carrier concentration of 1 × 10⁻⁶ was grown on the unintentionally doped gallium oxide layer using metal-organic chemical vapor deposition. 18 cm -3 The α-axis gallium oxide channel layer has the following process conditions:

[0157] The reaction chamber temperature is 500℃ and the pressure is 50mba;

[0158] The oxygen source is high-purity oxygen, the gallium source is TEGa, the doping source is silane, and the carrier gas is argon.

[0159] The molar flow ratio of TEGa to O2 was 1:2000, the molar flow rate of silane was 50 μmol / min, and the growth rate of the α-axis gallium oxide layer during epitaxy was monitored in real time by using the change in the reflectivity of the sample, and the growth time was adjusted accordingly.

[0160] Step 5: Use a mask to determine the location of the source / drain region of the sample, and perform ion implantation in the source / drain region to form an ohmic region.

[0161] First, a mask is used to determine the source / drain region, and a layer of SiO2 is deposited in the non-source / drain region by sputtering to serve as a mask for ion implantation. Then, the masked sample is placed in an ion implanter, and ion implantation is performed in the source / drain region for 10 minutes. 21 cm -3 Doping at a certain concentration forms an ohmic region, and the implantation conditions are as follows:

[0162] The implanted ions were Si, the implantation angle was 8°, and the beam current was 25mA.

[0163] Step 6: Deposit Ti / Au metal stacks above the source ohmic region and the drain ohmic region, and then anneal them.

[0164] 6.1) The ion-implanted sample was placed in an E-beam evaporation stage, and Ti / Au metal stacks with thicknesses of 40 nm and 600 nm were deposited in the ohmic region under the following process conditions:

[0165] Vacuum degree is 10 -7 The torr, the evaporated metal is Ti / Au, the temperature is 70℃, and the plating rate is 1.5 angstroms / second;

[0166] 6.2) The deposited Ti / Au metal stack sample is placed in an annealing furnace for annealing to complete the fabrication of the source and drain ohmic electrodes. The annealing conditions are as follows:

[0167] The atmosphere was N2, the temperature was 430℃, and the annealing time was 40s;

[0168] 6.3) Immerse the sample with the completed drain ohmic electrode and source ohmic electrode in buffer oxide etching solution until SiO2 is completely removed, then immerse it in acetone solution and ethanol solution in sequence, and place it in a water bath for ultrasonic treatment for 5 minutes, then rinse it with deionized water for 5 minutes, and finally blow it dry with a nitrogen gun.

[0169] Step 7: Use an ICP etching machine to etch away the gallium oxide layer outside the source / drain region to complete the active region isolation.

[0170] 7.1) Use a mask to determine the source and drain regions and the surrounding regions of the source and drain on the cleaned sample, and use photoresist to mask the above regions;

[0171] 7.2) The masked sample is placed in an ICP etching machine, and the gallium oxide layer outside the source / drain region is etched away by 1100 nm using the ICP etching process to complete the active region isolation. The etching process conditions are as follows:

[0172] The upper power is 400W, the lower power is 100W, and the pressure is 15mTorr;

[0173] 7.3) Immerse the sample that achieves active region isolation in acetone solution and ethanol solution in sequence until the photoresist is completely removed, then rinse with deionized water for 5 minutes, and finally dry with a nitrogen gun.

[0174] Step 8: Etch to form nanochannels on the gallium oxide channel layer.

[0175] 8.1) Use a mask to determine the channel region on the cleaned sample, and use an electron beam lithography machine to perform photolithography on the non-channel region to form a photoresist mask in the shape of a nano-strip.

[0176] 8.2) The sample with a photoresist mask on its surface is placed in an ICP etching machine. A nanochannel with a width of 500 nm and a depth of 1135 nm is etched in the gallium oxide channel layer using the ICP etching process. The etching process conditions are as follows:

[0177] The upper power is 400W, the lower power is 100W, and the pressure is 15mTorr;

[0178] 8.3) Immerse the sample with etched nanochannels in acetone solution and ethanol solution in sequence until the photoresist is completely removed, then rinse with deionized water for 5 minutes, and finally dry with a nitrogen gun.

[0179] Step 9: Use a mask to determine the gate dielectric region of the sample, and use an ALD device to deposit a 35nm upper Al2O3 dielectric layer in the gate dielectric region.

[0180] 9.1) Use a mask to determine the gate dielectric region of the sample, and use photoresist to mask the non-gate dielectric region;

[0181] 9.2) The masked sample was placed in the ALD chamber and an upper Al2O3 dielectric layer with a thickness of 20 nm was grown in the gate dielectric region using atomic layer deposition. The atomic layer deposition conditions are as follows:

[0182] The pressure in the chamber is 0.3 torr, and the temperature is 400℃.

[0183] Trimethylaluminum and H2O were selected as precursors. Trimethylaluminum was introduced into the chamber for 0.3s, nitrogen for 15s, H2O for 8s, and nitrogen for 15s in sequence. This process was repeated 400 times.

[0184] Step 10: Deposit a Ni / Au metal stack on top of the upper Al2O3 dielectric layer.

[0185] The sample after the upper Al2O3 dielectric layer was grown was placed in an E-beam evaporation stage. Ni / Au metal stacks with thicknesses of 40 nm and 400 nm were deposited on top of the upper Al2O3 dielectric layer using the E-beam evaporation process to complete the fabrication of the top gate electrode. The E-beam evaporation process conditions are as follows:

[0186] Vacuum degree is 10 -6 The torr was used to evaporate Ni / Au metal at a temperature of 75°C, with a plating rate of 1.5 angstroms per second.

[0187] Step 11: Use liquid phase stripping to peel the structure above the iron oxide layer from the epitaxial substrate.

[0188] The sample was immersed in a 1 mol / L hydrochloric acid solution to dissolve the iron oxide until the four corners of the structure above the iron oxide layer curled up; then the sample was placed in deionized water, and the surface tension of the water caused the upper structure to detach from the substrate, resulting in the stripped gallium oxide MOSFET device.

[0189] Step 12: The stripped gallium oxide MOSFET device is transferred and bonded to a diamond substrate with Ni / Au multilayer metal deposited on its surface using the surface activation bonding method, and then annealed.

[0190] 12.1) A Ni / Au multilayer metal with thicknesses of 40 nm and 400 nm is deposited on a diamond substrate by E-beam evaporation, and the E-beam evaporation process conditions are the same as those in step ten.

[0191] 12.2) Apply adhesive material to the front side of the temporary carrier and spin coat it at a speed of 2000 rpm for 40 seconds. Place the temporary carrier with the adhesive material applied face up on a hot plate and bake it at 100°C for 4 minutes to ensure that the adhesive material is evenly and firmly attached to the temporary carrier.

[0192] 12.3) The stripped gallium oxide MOSFET device is directly bonded to a temporary substrate coated with adhesive material, with the front sides facing each other; then, an 8-nanometer-thick amorphous silicon nanolayer is sputtered on the surface of the gallium oxide MOSFET device with the temporary substrate bonded and on the surface of the diamond substrate with Ni / Au stacked metal, respectively, using magnetron sputtering, and the silicon nanolayer is activated using an argon atom beam.

[0193] 12.4) Place the two activated surfaces face to face and bond them together in a bonding machine at a pressure of 4000 mba. Immerse the bonded sample in an adhesive removal solution until the temporary carrier is completely removed, thus completing the transfer of the stripped gallium oxide MOSFET to the diamond substrate.

[0194] 12.5) The transferred sample was placed in an annealing furnace and subjected to thermal annealing at 400°C in a N2 atmosphere for 5 minutes to obtain a diamond-based gallium oxide MOSFET with a surrounding gate, thus completing the fabrication of the entire device.

[0195] The above descriptions are merely three specific examples of the present invention and do not constitute any limitation on the present invention. Obviously, those skilled in the art, after understanding the content and principles of the present invention, may make various modifications and changes in form and details without departing from the principles and structure of the present invention. For example, in the liquid phase stripping method, the iron oxide solution can be either hydrochloric acid solution or low-concentration hydrofluoric acid solution; in addition to using Ti / Au metal stack, the source and drain ohmic electrodes can also be Ti / Al / Ni / Au metal stacks. However, these modifications and changes based on the ideas of the present invention are still within the scope of protection of the claims of the present invention.

Claims

1. A method for fabricating a four-sided surround-gate gallium oxide MOSFET power device, characterized in that, Includes the following steps: 1) Select and clean the epitaxial substrate; 2) Using a Sputter apparatus, a thin film of iron oxide is grown on the surface of the cleaned substrate and then annealed. 3) An Al2O3 dielectric layer of 5-35 nm was deposited on top of the iron oxide layer using an ALD device; 4) The sample with the deposited Al2O3 dielectric layer was placed in the MOCVD reaction chamber, and a carrier concentration of 1×10⁻⁶ was sequentially grown on top of the Al2O3 dielectric layer using metal-organic chemical vapor deposition. 14 cm -3 ~1×10 16 cm -3 The first α-axis gallium oxide unintentionally doped layer has a thickness of 100nm~500nm, and the carrier concentration is 1×10⁻⁶. 16 cm -3 ~1×10 18 cm -3 A second α-axis gallium oxide channel layer with a thickness of 200nm~600nm; 5) Use a mask to determine the location of the source and drain regions of the sample, and perform ion implantation in the source and drain regions to form ohmic regions; 6) Deposit Ti / Au metal stacks above the source ohmic region and the drain ohmic region, and anneal them to complete the fabrication of the source ohmic electrode and the drain ohmic electrode; 7) The gallium oxide layer outside the source / drain region is etched away using an ICP etching machine to complete the active region isolation; 8) A nano-strip-shaped mask is formed by photolithography using an electron beam lithography machine, and then etched by an ICP etching machine until the iron oxide layer is exposed to form nanochannels; 9) Use a mask to determine the gate dielectric region of the sample, and use an ALD device to deposit a 5-35 nm upper Al2O3 dielectric layer in the gate dielectric region; the upper Al2O3 dielectric layer is in contact with the Al2O3 dielectric layer, and the upper Al2O3 dielectric layer is inverted U-shaped; 10) Deposit a Ni / Au metal stack above the upper Al2O3 dielectric layer to complete the fabrication of the top gate electrode; the top gate electrode is inverted U-shaped and contacts the iron oxide layer; 11) Use liquid phase stripping to remove the structure above the iron oxide layer from the epitaxial substrate; 12) The structure above the iron oxide layer is transferred and bonded to a diamond substrate with Ni / Au multilayer metal deposited on the surface using the surface activation bonding method, and then annealed to complete the fabrication of the entire device; the Ni / Au multilayer metal is connected to the top gate electrode.

2. The method according to claim 1, characterized in that: The epitaxial substrate in step 1) is made of materials with a corundum structure, such as sapphire or α-iron oxide. The cleaning in step 1) involves first immersing the substrate in acetone solution and ethanol solution in sequence, then placing it in a water bath for ultrasonic treatment for 3-5 minutes, rinsing it with deionized water for 3-5 minutes, and finally drying it with a nitrogen gun. In step 2), an iron oxide film is grown on the surface of the cleaned substrate using a sputtering device. First, the vacuum of the device is broken, the cleaned sample is sent into its chamber, and an iron oxide target is set. Then, the chamber is evacuated to a vacuum, and the process conditions are set to room temperature, power of 90~160W, and O2 to Ar ratio of 1:5~1:

2. An iron oxide film with a thickness of 100nm~5μm is grown on the substrate surface by sputtering. The annealing process in step 2) is performed in a nitrogen atmosphere at an annealing temperature of 500~1100℃ for 20~60 minutes on the sample with the grown iron oxide film.

3. The method according to claim 1, characterized in that, In step 3), an Al2O3 dielectric layer of 5-35 nm is deposited on top of the iron oxide layer using an ALD device, as follows: 3a) First, place the annealed sample in the ALD chamber, set the chamber pressure to 0.1~0.5 torr, and the temperature to 150~450℃; 3b) Using trimethylaluminum and H2O as precursors, trimethylaluminum is sequentially introduced into the chamber for 0.1–0.3 s, nitrogen for 10–15 s, H2O for 3–8 s, and nitrogen for 10–15 s. 3c) Repeat process 3b) 100 to 700 times to grow an Al2O3 dielectric layer with a thickness of 5 nm to 35 nm on top of the iron oxide layer using atomic layer deposition.

4. The method according to claim 1, characterized in that, In step 4), two α-gallium oxide layers are sequentially grown on top of the Al2O3 dielectric layer using metal-organic chemical vapor deposition (MOCVD). The process conditions are as follows: 4a) A first α-axis gallium oxide unintentionally doped layer is deposited above the Al2O3 dielectric layer, with the following process conditions: The reaction chamber temperature is 400~600℃, and the pressure is 40mba~200mba. The oxygen source is high-purity oxygen, the gallium source is TEGa, and the carrier gas is argon. The molar flow ratio of TEGa to O2 is 1:5000~1:200; 4b) The process conditions for depositing the second α-oriented gallium oxide channel layer on the first α-oriented gallium oxide layer are as follows: The reaction chamber temperature is 400~600℃, and the pressure is 40mba~200mba. The oxygen source is high-purity oxygen, the gallium source is TEGa, the doping source is silane, and the carrier gas is argon. The molar flow ratio of TEGa to O2 is 1:5000~1:200, and the molar flow rate of silane is 5~50 μmol / min.

5. The method according to claim 1, characterized in that, Step 5) uses a mask to determine the location of the source / drain region of the sample, and performs ion implantation in the source / drain region to form an ohmic region, achieving the following: 5a) Use a mask to determine the source / drain region location of the sample, and deposit a layer of SiO2 in the non-source / drain region by sputtering to serve as a mask for ion implantation; 5b) Place the masked sample into an ion implanter and set the ion implantation conditions as follows: implanted ions are Si, implantation angle is 6~8°, and beam current is 15~25mA. Achieve 10-1 ion implantation in the source / drain region using ion implantation. 19 ~10 21 cm -3 The doping concentration is adjusted to form an ohmic region.

6. The method according to claim 1, characterized in that, In step 6), a Ti / Au metal stack is deposited above the source ohmic region and the drain ohmic region, and then annealed to achieve the following: 6a) Place the ion-implanted sample into the E-beam evaporation stage and set the E-beam evaporation process conditions as follows: vacuum degree 10 -6 ~10 -7 torr, the evaporated metal is Ti / Au, the temperature is 25~90℃, the deposition rate is 1~2 angstroms / second, and Ti / Au metal stacks with thicknesses of 20~40nm / 400~600nm are deposited in the ohmic region; 6b) Place the deposited Ti / Au metal stack sample into an annealing furnace and anneal it under the following conditions: N2 atmosphere, 400~450℃ temperature, and 20~40s time to complete the fabrication of the source ohmic electrode and the drain ohmic electrode. 6c) Immerse the sample with the completed drain and source ohmic electrodes in a buffer oxide etching solution until SiO2 is completely removed. Then immerse it in acetone solution and ethanol solution in sequence, and place it in a water bath for ultrasonic treatment for 3-5 minutes. Rinse it with deionized water for 3-5 minutes, and finally dry it with a nitrogen gun.

7. The method according to claim 1, characterized in that, In step 7), the gallium oxide layer outside the source / drain region is etched away using an ICP etching machine, achieving the following: 7a) Use a mask to determine the source and drain regions and the surrounding regions of the source and drain on the cleaned sample, and use photoresist to mask the above regions; 7b) Place the masked sample in an ICP etching machine and set the etching process conditions as follows: upper power 200~500W, lower power 50~150W, and pressure 10~20mTorr. Use the ICP etching process to etch away 300~1100nm of the gallium oxide layer outside the source and drain regions to complete the active region isolation. 7c) Immerse the sample that achieves active region isolation in acetone solution and ethanol solution in sequence until the photoresist is completely removed, then rinse with deionized water for 3-5 minutes, and finally dry with a nitrogen gun.

8. The method according to claim 1, characterized in that, In step 8), an electron beam lithography machine is used to form a nano-elongated mask, and then an ICP etching machine is used to etch nanochannels, achieving the following: 8a) Use a mask to determine the channel region on the cleaned sample, and use an electron beam lithography machine to perform photolithography on the non-channel region to form a photoresist mask in the shape of a nano-strip; 8b) Place the sample with a photoresist mask on its surface into an ICP etching machine and set the etching process conditions to 200~500W upper power, 50~150W lower power, and 10~20mTorr pressure to etch nanochannels with a width of 50~500nm and a depth of 305~1135nm. 8c) Immerse the sample with etched nanochannels in acetone solution and ethanol solution in sequence until the photoresist is completely removed, then rinse with deionized water for 3-5 minutes, and finally dry with a nitrogen gun.

9. The method according to claim 1, characterized in that, In step 9), a mask is used to determine the gate dielectric region of the sample, and an upper Al2O3 dielectric layer of 5-35 nm is deposited in the gate dielectric region using an ALD device, as follows: 9a) Use a mask to determine the gate dielectric region of the sample, and use photoresist to mask the non-gate dielectric region; 9b) Place the masked sample into the ALD chamber, set the chamber pressure to 0.1~0.5 torr, and the temperature to 150~450℃; select trimethylaluminum and H2O as precursors, and sequentially introduce trimethylaluminum into the chamber for 0.1~0.3s, nitrogen for 10~15s, H2O for 3~8s, and nitrogen for 10~15s; 9c) Repeat step 9b) 100 to 700 times to grow an Al2O3 dielectric layer with a thickness of 5 nm to 35 nm in the gate dielectric region using atomic layer deposition.

10. The method according to claim 1, characterized in that: In step 10), depositing a Ni / Au metal stack above the upper Al2O3 dielectric layer involves placing the sample with the grown upper Al2O3 dielectric layer onto an E-beam evaporation stage and setting the vacuum level to 10. -6 ~10 -7 The metal torr is Ni / Au, the temperature is 25~90℃, and the deposition rate is 1~2 angstroms / second. Under the E-beam evaporation process conditions, Ni / Au metal stacks with thicknesses of 35~55nm / 350~450nm are deposited on the upper Al2O3 dielectric layer to complete the fabrication of the top gate electrode. In step 11), the structure above the iron oxide layer is peeled off from the epitaxial substrate using a liquid phase peeling method. This involves first immersing the sample in a hydrochloric acid solution with a concentration of 0.1~3 mol / L to dissolve the iron oxide until the four corners of the structure above the iron oxide layer lift up. The sample is then placed in deionized water, and the surface tension of the water causes the upper structure to detach from the substrate, resulting in the stripped gallium oxide MOSFET device.

11. The method according to claim 1, characterized in that, In step 12), the structure above the iron oxide layer is transferred and bonded to the diamond substrate with Ni / Au multilayer metal deposited on the surface using the surface activation bonding method, and then annealing is performed to achieve the following: 12a) A Ni / Au multilayer metal with thicknesses of 35~55nm / 350~450nm is deposited on a diamond substrate by E-beam evaporation, wherein the E-beam evaporation process conditions are the same as those in step 10). 12b) Apply adhesive material to the front side of the temporary carrier and spin coat it at a speed of 1000~3000 rpm for 30~60 seconds. Place the temporary carrier with the adhesive material applied face up on a hot plate and bake it at a temperature of 90~110℃ for 2~5 minutes to make the adhesive material adhere evenly and firmly to the temporary carrier. 12c) The stripped gallium oxide MOSFET device is directly bonded to a temporary substrate coated with adhesive material, with the front sides facing each other; 12d) Amorphous silicon nanolayers with a thickness of 5-10 nm were sputtered on the surface of a gallium oxide MOSFET device with a temporary carrier bonded together and on the surface of a diamond substrate with a Ni / Au multilayer metal grown thereon, respectively, and the silicon nanolayers were activated by an argon atom beam. 12e) Place the two activated surfaces face to face and then bond them in a bonding machine at a pressure of 3000~5000 mba; 12f) Immerse the bonded sample in the adhesive removal solution until the temporary carrier is completely detached; 12g) The sample was placed in an annealing furnace and subjected to thermal annealing in a N2 atmosphere at 300~400℃ for 4~6 minutes to complete the fabrication of a four-sided surrounding gate gallium oxide MOSFET device.

12. A four-sided surround-gate gallium oxide MOSFET power device prepared according to claim 1, comprising a substrate (1), an unintentionally doped UID gallium oxide layer (2), a gallium oxide channel layer (3), an upper Al2O3 dielectric layer (4), a source ohmic electrode (5), a drain ohmic electrode (6), and a top gate electrode (7), characterized in that: The substrate (1) is made of diamond material with high thermal conductivity to effectively improve the heat dissipation capability of gallium oxide MOSFET devices; An Al2O3 dielectric layer (9) and a Ni / Au metal layer (8) are sequentially disposed between the unintentionally doped UID gallium oxide layer (2) and the substrate (1). The Al2O3 dielectric layer (9) is connected to the upper Al2O3 dielectric layer (4) and together surrounds the gallium oxide channel layer (3). The Ni / Au metal layer (8) is connected to the top gate electrode (7) and together surrounds the upper Al2O3 dielectric layer (4) and the Al2O3 dielectric layer (9) to improve the gate's control over the channel.

13. The device according to claim 12, characterized in that: The unintentionally doped UID gallium oxide layer (2) is located above the Al2O3 dielectric layer (9) and has a thickness of 100 nm to 500 nm, with a carrier concentration of 1 × 10⁻⁶. 14 cm -3 ~1×10 16 cm -3 ; The gallium oxide channel layer (3) is located above the unintentionally doped UID gallium oxide layer (2) and has a thickness of 200 nm to 600 nm, with a carrier concentration of 1 × 10⁻⁶. 16 cm -3 ~1×10 18 cm -3 ; The upper Al2O3 dielectric layer (4) has a thickness of 5~35nm; The source ohmic electrode (5) and the drain ohmic electrode (6) are both made of Ti / Au with a thickness of 20~40nm / 400~600nm, and are located on both sides of the ohmic region above the gallium oxide channel layer (3); The top gate electrode (7) is made of Ni / Au and has a thickness of 35~55nm / 350~450nm; The Ni / Au metal layer (8) has a thickness of 35~55nm / 350~450nm; The Al2O3 dielectric layer (9) has a thickness of 5~35nm.

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