Pixel sensor and method for manufacturing the same

Abstract

The present application relates to a pixel sensor, a method for fabricating a pixel unit, and an electronic device. The method includes: providing a substrate, the substrate including an embedded isolation structure, a first region, and a second region sequentially arranged in a first direction parallel to the top surface of the substrate; the top surface of the substrate in the first region includes a gate structure; forming a first mask layer with a first thickness covering the exposed top surface of the substrate and the outer surface of the gate structure; the first thickness is related to the amplitude of the operating voltage of the pixel sensor; forming a pixel doping region in the substrate in the second region; the horizontal distance between the pixel doping region and the gate structure is related to the first thickness; removing a part of the first mask layer, and the first mask layer remaining on the top surface of the substrate has a second thickness; forming a second mask layer covering the first mask layer and the outer surface of the gate structure. By changing the thickness of the first mask layer to adjust the distance from the pixel doping region to the channel, better GIDL performance is achieved, and the influence caused by defects generated during the process is minimized as much as possible.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technologies, and particularly to a pixel sensor and a method for manufacturing the same. Background Art

[0002] With the continuous increase in the market demand for pixel integration, the feature size of pixel sensor chips has been continuously reduced. However, as the chip miniaturization progresses, after the feature size of traditional devices reaches the physical limit, problems such as poor imaging quality and high power consumption have become increasingly serious. Among them, the gate-induced drain leakage (GIDL) occurring in the gate-drain overlap region can cause problems such as white spots or defective pixels in the pixel sensor image. Therefore, when designing a pixel sensor, measures need to be taken to minimize the GIDL effect. Summary of the Invention

[0003] Based on this, in view of the technical problems in the prior art, it is necessary to provide a pixel sensor and a method for manufacturing the same, which can at least reduce GIDL leakage and reduce surface mask layer defects.

[0004] In a first aspect, this application provides a method for manufacturing a pixel unit, including: providing a substrate, the substrate including a buried isolation structure, a first region, and a second region sequentially arranged in a first direction parallel to the top surface of the substrate; the top surface of the substrate in the first region including a gate structure; forming a first mask layer with a first thickness covering the exposed top surface of the substrate and the outer surface of the gate structure; the first thickness being related to the amplitude of the operating voltage of the pixel sensor; performing an ion implantation process on the substrate in the second region to form a pixel doping region; the horizontal distance between the pixel doping region and the gate structure being related to the first thickness; removing a part of the first mask layer to expose the outer surface of the gate structure, and the first mask layer remaining on the top surface of the substrate having a second thickness; forming a second mask layer covering the first mask layer and the outer surface of the gate structure.

[0005] In the method for fabricating a pixel unit in the above embodiments, the ion implantation of the pixel doping region is defined after the process of the first mask layer of self-aligned silicide (Self Aligned Block, SAB). After the conventional ion implantation step is completed, the first mask layer is grown first, then the ion implantation of the pixel doping region is performed, and while stripping the first mask layer, a mask layer material with an appropriate thickness is retained on the surface of the active region; finally, a second mask layer covering the above structure is formed, and together with the remaining first mask layer, it serves as the SAB mask layer in the SAB process. This method can, according to the requirements of the operating voltage amplitude of different pixel sensors, control the horizontal spacing from the pixel doping region to the channel by adjusting the first thickness of the first mask layer, and can effectively reduce the leakage risk of GIDL in the pixel doping region and the dark current. Due to the high flexibility of adjusting the first thickness, the horizontal spacing between the pixel doping region and the gate structure can be precisely controlled. While improving the GIDL leakage, the problem of electron retention caused by insufficient transmission can be minimized.

[0006] In addition, the selected re-prepared SAB mask layer of this method can reduce the surface defects introduced by the rapid thermal annealing (Rapid Thermal Annealing, RTA) process, ensure its uniformity and consistency, ensure the smooth progress of subsequent processes, and improve the yield. And when stripping the first mask layer that is most affected by the RTA process, an appropriate thickness is retained in the active region to avoid the surface loss introduced into the active region by the etching process used, and ensure the overall performance of the chip.

[0007] In some embodiments, the gate structure includes sidewall structures arranged at intervals along a first direction, and a gate dielectric layer and a gate conductive layer that are located between adjacent sidewall structures, are in contact with the sidewall structures, and are stacked in sequence along a direction away from the substrate.

[0008] In some embodiments, the ratio range of the first thickness to the horizontal spacing is 0.15 - 0.45.

[0009] In some embodiments, before forming the second mask layer, the substrate is subjected to rapid thermal annealing.

[0010] In some embodiments, the first thickness is positively correlated with the operating voltage amplitude of the pixel sensor.

[0011] In some embodiments, the horizontal spacing is positively correlated with the first thickness.

[0012] In some embodiments, the substrate further includes a preset type device region. After forming the second mask layer: using the remaining first mask layer and the second mask layer as a mask, perform a self-aligned silicide process within the preset type device region.

[0013] In some embodiments, the substrate includes an LDD ion implantation region and a Halo ion implantation region provided on at least one side of the gate structure; the doping ions in the LDD ion implantation region and the Halo ion implantation region have opposite conduction types; the doping ions in the LDD ion implantation region and the pixel doping region have the same conduction type.

[0014] In some embodiments, the conduction type of the pixel doping region is N-type.

[0015] In a second aspect, the present application further provides a pixel sensor, including pixel units prepared by using the pixel unit preparation method in any of the above embodiments.

[0016] Configuring pixel units prepared by the above pixel unit preparation method, this pixel sensor can greatly improve the pixel white point problem caused by GIDL leakage, improve the image quality, and optimize the performance.

[0017] In a third aspect, the present application further provides an electronic device, including pixel units prepared by using the pixel unit preparation method in any of the above embodiments, or including the pixel sensor in the above embodiments.

[0018] An electronic device equipped with a pixel sensor with higher image quality can improve image clarity and details, enrich colors, and increase user satisfaction and product attractiveness. The unexpected technical effects that can be produced by the embodiments of the present disclosure include:

[0019] The present application provides a pixel sensor and a pixel unit preparation method. This method can control the horizontal distance from the pixel doping region to the channel by adjusting the first thickness of the first mask layer according to the different working voltage amplitude requirements of the pixel sensor, and indirectly expand the thickness of the sidewall structure by deposition, solving the problems of high difficulty and low quality in directly preparing a sidewall structure with a large lateral thickness in the existing sidewall process. At the same time, compared with the offset sidewall improvement technology combined with the lithography process, the method provided by the present application can be used commonly on the same platform, has high flexibility, better versatility and universality, effectively simplifies the process, and reduces the process cost.

[0020] In addition, the characteristic of accurately regulating the first thickness by the deposition method can reduce the leakage risk of GIDL in the pixel doping region and the dark current, while minimizing the problem of electron retention caused by insufficient transmission. It helps to improve the performance indicators of the pixel sensor prepared by this preparation method, meet the requirements of modern high-resolution and high-sensitivity devices, and is of great significance to image acquisition technology and data processing.

[0021] In addition, the re-prepared SAB mask layer selected by this method can reduce the surface defects introduced by the RTA process, ensure its uniformity and consistency, ensure the smooth progress of subsequent processes, and improve the yield rate. Moreover, when stripping the first mask layer most affected by the RTA process, an appropriate thickness is retained in the active region to avoid the surface loss introduced into the active region by the etching process used, and ensure the overall performance of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0023] Figure 1 It is a cross-sectional schematic diagram of the structure obtained after performing an ion implantation process on a pixel doping region after a sidewall process in the related art;

[0024] Figure 2 It is a cross-sectional schematic diagram of the structure obtained after performing an ion implantation process in the first mask layer in the related art;

[0025] Figure 3 It is a cross-sectional schematic diagram of the structure obtained after forming the first mask layer in the related art;

[0026] Figure 4 Is Figure 3 A cross-sectional schematic diagram of the structure obtained after performing a photolithography process on the structure in;

[0027] Figure 5 It is a cross-sectional schematic diagram of the structure obtained after forming source / drain doping regions in the related art;

[0028] Figure 6 It is a flowchart of a pixel unit manufacturing method provided in an embodiment;

[0029] Figure 7 It is a cross-sectional schematic diagram of a substrate provided in a pixel unit manufacturing method provided in an embodiment;

[0030] Figure 8 It is a cross-sectional schematic diagram of the structure obtained after forming the first mask layer in step S104 in a pixel unit manufacturing method provided in an embodiment;

[0031] Figure 9 It is a cross-sectional schematic diagram of the structure obtained after forming a pixel doping region in step S106 in a pixel unit manufacturing method provided in an embodiment;

[0032] Figure 10Schematic cross-sectional view of the resulting structure after removing a portion of the first mask layer in step S108 of the pixel unit fabrication method provided in an embodiment;

[0033] Figure 11 is Figure 10 Schematic cross-sectional view of the resulting structure when the structure in [reference] is subjected to a rapid thermal annealing process;

[0034] Figure 12 Schematic cross-sectional view of the resulting structure after forming the second mask layer in step S110 of the pixel unit fabrication method provided in the embodiment;

[0035] Figure 13 Schematic cross-sectional view of the chip morphology obtained without using and using the pixel unit fabrication method provided in the present application in an embodiment.

[0036] Explanation of reference numerals:

[0037] 1. Initial substrate; 10. Substrate; 20. Buried isolation structure; 30. Gate structure; 31. Gate dielectric layer; 32. Gate conductive layer; 33. Isolation layer; 34. Gate oxide layer; 35. Nitride layer; 40. SAB mask layer; 41. First mask layer; 42. Second mask layer; 50. Pixel doping region. Detailed implementation manners

[0038] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Preferred embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0039] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present application belongs. The terms used in the specification of the present application herein are only for the purpose of describing specific embodiments and are not intended to limit the present application.

[0040] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or portions, these elements, components, regions, layers, doping types and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or portion from another element, component, region, layer, doping type or portion. Thus, without departing from the teachings of the present application, the first element, component, region, layer, doping type or portion discussed below may be referred to as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0041] Spatial relationship terms such as "below", "beneath", "lower", "under", "above", "upper", etc. are used herein to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as "below" or "beneath" or "under" another element or feature will be oriented "above" the other element or feature. Thus, the exemplary terms "below" and "beneath" can include both an upper and a lower orientation. In addition, the device may also include additional orientations (such as, rotated 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.

[0042] As used herein, the singular forms "a", "an" and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that when the terms "comprises" and / or "comprising" are used in this specification, the presence of features, integers, steps, operations, elements and / or components can be identified, but one or more other features, integers, steps, operations, elements, components and / or groups are not excluded from the presence or addition. Also, as used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0043] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic illustrations of ideal embodiments (and intermediate structures) of the present application, so that variations in the shapes shown can be expected due to, for example, manufacturing techniques and / or tolerances. Accordingly, embodiments of the present application should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing techniques. For example, an implantation region shown as rectangular typically has rounded or curved features and / or an implantation concentration gradient at its edges, rather than a binary change from the implantation region to the non-implantation region. Similarly, a buried region formed by implantation can result in some implantation in the region between the buried region and the surface through which the implantation occurs. Accordingly, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of the regions of the device and do not limit the scope of the present application.

[0044] In the preparation process of a pixel sensor chip, it is often necessary to form a Pixel N+ region, i.e., a pixel doping region, by high-dose ion implantation. After annealing and diffusion, there will be an overlap between the high-dose region and its gate, which is one of the main reasons for GIDL leakage. Currently, there are mainly two methods for preparing the Pixel N+ region: one is to perform the sidewall process first, then form the Pixel N+ region, and then perform the SAB process; the other is to insert the Pixel N+ region into the SAB mask layer in order to achieve the effect of reducing leakage by moving the Pixel N+ region away from the channel region. However, the former will result in the Pixel N+ region being too close to the channel region, increasing the risk of GIDL leakage during the electron transport process in the device, and the leakage phenomenon of the Pixel N+ region will become more serious; although the latter can appropriately reduce GIDL leakage, it will cause defects in the surface mask layer during the subsequent annealing process, thus affecting the formation of self-aligned metal silicide.

[0045] There are certain limitations in the two existing pixel chip manufacturing processes. Therefore, it is necessary to explore a new process flow to reduce GIDL leakage and prevent the occurrence of increased surface mask layer defects while ensuring the performance and reliability of the pixel sensor chip. Figures 3 - 5 are schematic diagrams corresponding to the steps in a method for forming a semiconductor structure. Please refer to Figure 3 , a substrate 10 is provided, and a gate structure 30 and a first mask layer 41 are formed on the substrate 10. Please refer to Figure 4 , the first mask layer 41 is patterned to form sidewalls on the sidewalls of the gate structure 30. Please refer to Figure 5 , based on the sidewalls, an ion implantation process is performed on the substrate 10 to form source / drain doping regions.

[0046] However, due to the fixity and limitations of the photomask technology, during the adjustment process, the frequency of repeating the process and replacing the photomask significantly increases the production cost. In addition, the processes of film formation and exposure have extremely strict requirements on the process environment and parameters. Slight deviation may affect the final pattern quality, which undoubtedly increases the complexity of process control. In the process of modern microelectronics technology, this process complexity undoubtedly poses severe challenges to production efficiency and cost control. Therefore, there is an urgent need for a solution that can minimize the defects generated during the process while achieving better GIDL performance.

[0047] Please refer to Figure 6 , this application provides a method for preparing a semiconductor structure, including: step S102 - step S110.

[0048] In the embodiment of this application, the substrate may include a first surface on the front side and a back surface opposite to the front side, that is, a second surface. Ignoring the flatness of the first surface and the second surface, a first direction parallel to the first surface is defined, and the direction towards the substrate includes a second direction perpendicular to the first surface of the substrate. For example, the direction parallel to the top surface of the substrate is the first direction, and the direction towards the substrate is the second direction. Among them, the first direction and the second direction are perpendicular to each other. In the embodiment of this application, the first direction is defined as the Y-axis direction, and the second direction is defined as the X-axis direction. At the same time, the first region is defined as region A, and the second region is defined as region B.

[0049] Step S102: Provide a substrate 10, the substrate 10 includes buried isolation structures 20, a first region A, and a second region B arranged in sequence along the OY direction parallel to the top surface of the substrate; on the top surface of the substrate 10 in the first region A, there is a gate structure 30.

[0050] Exemplarily, the substrate 10 may be composed of a semiconductor material, an insulating material, a conductor material, or any combination thereof. The substrate 10 may be a single-layer structure or a multi-layer structure. For example, the substrate 10 may include a silicon (Si) substrate, a germanium (Ge) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Or, for another example, the substrate 10 may also include Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator. Therefore, the type of the substrate 10 should not limit the protection scope of the present disclosure. The substrate 10 may include word line structures and capacitor contact structures, etc., which are omitted because they have little relation to the inventive point of this solution. In this application, the substrate 10 mentioned is a silicon substrate.

[0051] As an example, the embedded isolation structure 20 can be a single-layer structure or a multi-layer structure. For example, the embedded isolation structure 20 can be a single-layer structure including insulating materials such as silicon dioxide (SiO2) and silicon nitride (Si3N4), or a multi-layer structure including doped polysilicon and high-k dielectric materials, etc., for isolating a plurality of spaced-apart active areas (Active Area, AA) within the substrate. Different active areas can be used to form different types of devices.

[0052] As an example, the cross-sectional shape of the embedded isolation structure 20 along the OY direction can include a right trapezoid, an inverted trapezoid, a rectangle, etc., or can also be a combination of shapes such as a right trapezoid, an inverted trapezoid, a rectangle, etc., for isolating from other devices within the substrate 10 and reducing the mutual interference between semiconductor devices. Of course, the substrate 10 also includes a plurality of embedded isolation structures 20. In this embodiment, the distance between adjacent embedded isolation structures 20 is not specifically limited and can be set according to actual needs.

[0053] In some embodiments, after performing an ion implantation process on the substrate 10 to form a highly doped isolation well region, an embedded isolation structure 20 can be formed within the isolation well region; wherein, the dimension of the isolation well region along the OY direction is greater than the dimension of the embedded isolation structure 20 along the OY direction, and the dimension of the isolation well region along the OX direction is greater than the dimension of the embedded isolation structure 20 along the OX direction. By establishing a built-in electric field, this structure can further improve the isolation effect, thereby improving the electrical performance of the pixel unit.

[0054] Step S104: Form a first mask layer 41 with a first thickness covering the exposed top surface of the substrate 10 and the outer surface of the gate structure 30; the first thickness D1 is related to the operating voltage amplitude of the pixel sensor.

[0055] Specifically, the gate structure 30 includes sidewall structures arranged at intervals along the OY direction, and a gate dielectric layer 31 and a gate conductive layer 32 that are located between adjacent sidewall structures, in contact with the sidewall structures, and stacked in sequence along the XO direction (the opposite direction of the OX direction).

[0056] The gate conductive layer 32 can be a polysilicon gate structure or a metal gate structure. The materials of the metal gate structure include, but are not limited to, metal conductive materials such as gold (Au), copper (Cu), silver (Ag), aluminum (Al), nickel (Ni), etc.

[0057] The gate dielectric layer 31 can be formed of a material with a high-k dielectric constant. For example, the materials of the gate dielectric layer 31 include: aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2), or strontium titanate oxide (SrTiO3), etc.

[0058] Specifically, the material of the first mask layer 41 may include, but is not limited to, silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), or a composition of the above materials, where x and y represent components. The first thickness is the dimension of the first mask layer 41 along the OX direction, and D1 is used to represent the first thickness of the first mask layer 41; V is used to represent the operating voltage amplitude of the pixel sensor.

[0059] Step S106: Perform an ion implantation process on the underlying substrate 10 of the second region B to form a pixel doping region 50; the horizontal spacing between the pixel doping region 50 and the gate structure 30 is related to the first thickness D1.

[0060] Specifically, D3 is used to represent the horizontal spacing between the pixel doping region 50 and the gate structure 30. It should be noted the correlation between the horizontal spacing and the transmission effect. If the horizontal spacing is too small, there will be an overlap between the pixel doping region and the gate structure, resulting in GIDL leakage; if the horizontal spacing is too large, the transmission efficiency will be reduced, and there will be an afterimage problem caused by electron retention. In some embodiments, the horizontal spacing D3 between the pixel doping region 50 and the gate structure 30 is in a certain proportion to the first thickness D1, and the ratio range is 0.15 - 0.45. For example, the ratio of the first thickness D1 to the horizontal spacing D3 is 0.15, 0.2, 0.25, 0.3, 0.35, 0.4, or 0.45, etc.

[0061] Step S108: Remove part of the first mask layer 41 to expose the outer surface of the gate structure 30, and the first mask layer 41 remaining on the top surface of the substrate 10 has a second thickness.

[0062] Specifically, the second thickness is the dimension of the remaining first mask layer along the OX direction, and D4 is used to represent the second thickness.

[0063] Step S110: Form a second mask layer 42 covering the first mask layer 41 and the outer surface of the gate structure 30.

[0064] Exemplarily, the material of the second mask layer 42 also includes, but is not limited to, SiN x , SiO x , SiO x N y , or a composition of the above materials. Together with the first mask layer 41 with the second thickness D4, it is used as the SAB mask layer 40 in the subsequent SAB process. In the SAB process, the metal layer used to form the self - aligned silicide will not react with the material of the SAB mask layer 40 it contacts. Therefore, the SAB mask layer 40 can be used to protect other non - metal silicide regions.

[0065] Among them, the semiconductor structure obtained after steps S102 - S110 can be referred to Figure 12 . To facilitate the understanding of this application, Figures 7 - 12 is a schematic diagram of each step of an exemplary pixel unit manufacturing method provided by an embodiment of this application. Among them, Figure 12 is an example of a pixel sensor fabricated using the manufacturing method of this application. There can be other suitable examples of pixel sensors fabricated using this application, and this application does not limit them here. The following combines Figures 7 - 12 to elaborate in detail on the pixel sensor provided by the embodiments of this application.

[0066] Please refer to Figure 7 , in some embodiments, providing the substrate 10 in step S102 further includes: steps S1022 - S1026.

[0067] Step S1022: Provide the initial substrate 1, and perform an ion implantation process in the initial substrate 1 to form a well region (not shown). Exemplarily, a well region is formed at a position away from the second surface of the initial substrate 1. The selection of the conductivity type of the well region is a well-known technique in the art, so it will not be elaborated here. It should be noted that the initial substrate 1 also includes a preset type device region. This figure only shows the first region B for forming the pixel doping region and the adjacent first region A in the substrate 10. If not otherwise specified in the subsequent processes, they are all carried out in the regions shown in the figure.

[0068] This application does not limit the structure and thickness of the initial substrate 1. For example, the initial substrate 1 may further include an epitaxial layer; the epitaxial layer can be a homoepitaxy with the same material and conductivity type as the initial substrate, or a heteroepitaxy with a different material from the initial substrate 1. This application does not limit this here.

[0069] Step S1024: Form a gate structure 30 on the top surface of the initial substrate 1 in the first region A.

[0070] Either dry etching or wet etching, which are familiar to those skilled in the art, can be used to form the gate structure 30. In this embodiment, the thickness D2 of the sidewall structure ranges from 450 Å to 480 Å, such as 450 Å, 460 Å, 470 Å, or 480 Å. In this embodiment, the dimension of the gate structure in the OY direction gradually increases in the OX direction.

[0071] Specifically, please refer to Figure 7, the sidewall structure includes an isolation layer 33 arranged in sequence along the OY direction, a gate oxide layer 34 with an "L-shaped" cross-section along the OY direction, and a nitride layer 35; wherein, the sidewall and bottom surface of the nitride layer 35 are in contact with the "L-shaped" sidewall of the gate oxide layer 34. The isolation layer 33 is used to protect the gate dielectric layer 31 and the gate conductive layer 32; the nitride layer 35 has a high density and strength and is used to prevent the diffusion of water vapor. The gate oxide layer 34 can serve as both an etch stop layer for the nitride layer 35 and a buffer layer between the semiconductor substrate 10 to reduce the stress on the semiconductor substrate 10.

[0072] Exemplarily, the material of the nitride layer includes but is not limited to silicon nitride (Si3N4), silicon oxynitride layer (SiON), boron nitride (BN), boron carbonitride (BNC), etc. or any combination of the above materials.

[0073] Step S1026: Using the gate structure 30 as a mask, perform an ion implantation process on the initial substrate 1 to form an LDD ion implantation region and a Halo ion implantation region (not shown) on at least one side of the gate structure 30.

[0074] Specifically, when the pixel unit is in the signal reading state, the gate structure 30 is connected to a low potential, and the pixel doping region 50 is connected to a high potential. At this time, there is a high voltage difference between the gate structure 30 and the pixel doping region 50. Lightly Doped Drain (LDD) and Halo doping are means to optimize the drain-induced barrier lowering (DIBL) in a conventional short channel. In this application, the LDD ion implantation region and the Halo ion implantation region are used to represent the corresponding technology doping regions.

[0075] The LDD ion implantation region formed using the gate structure 30 as a mask is covered or partially covered by the gate structure 30, which is used to prevent impurities from diffusing into the channel region under the gate structure 30 and improve the peak electric field; the vertical distance between the Halo ion implantation region and the channel region is generally not less than the vertical distance between the LDD ion implantation region and the trench region, forming a structure that surrounds or semi-surrounds the LDD ion implantation region. The conduction type is opposite to that of the LDD ion implantation region. For example, when the doping ion type of the LDD ion implantation region is N-type, the doping ion type of the Halo ion implantation region is P-type, and vice versa. When the doping ion type of the LDD ion implantation region is P-type, the doping type of the Halo ion implantation region is N-type, which is used to increase the local doping concentration, reduce the depletion region width near the channel region, and reduce the probability of leakage current generation.

[0076] The initial substrate 1 with the above-mentioned well region, LDD ion implantation region, and Halo ion implantation region forms the substrate 10 provided in this embodiment. Of course, the substrate 10 also includes other doped regions formed after performing other ion implantation processes, as long as the structure is reasonable, and should not be limited to the examples provided in this embodiment.

[0077] Please refer to Figure 8 , in some embodiments, forming the first mask layer 41 with a first thickness D1 that covers the exposed top surface of the substrate 10 and the outer surface of the gate structure 30 in step S104 further includes:

[0078] Exemplarily, any deposition process such as Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), High Density Plasma (HDP) process, etc. can be used to form the above structure. The first mask layer 41 covering the gate structure 30 increases the size of the sidewall structure in the OY direction. In the following description, the extended width ΔD is used to represent the increased size of the sidewall structure in the OY direction.

[0079] For example, the first mask layer 41 covering the outer surface of the gate structure 30 can be formed by atomic layer deposition to ensure that the first mask layer 41 has good thickness uniformity, so as to accurately control the extended width ΔD increased by the first mask layer 41.

[0080] The first thickness D1 and the extended width ΔD are in a certain proportion. The extended width ΔD can be predefined by including but not limited to the way of pre-slice, and the correlation between the two is established. For the same product, the extended width ΔD corresponding to different first thicknesses D1 is determined by conversion according to the correlation.

[0081] In this method, the first mask layer 41 obtained by deposition substantially provides an indirect extension of the sidewall structure thickness. While reducing the difficulty of directly preparing a sidewall structure with a large lateral thickness in the existing sidewall process, it improves the process flexibility and the actual quality of the sidewall structure with a large lateral thickness. At the same time, compared with the offset sidewall improvement technology combined with the lithography process, the method provided in this application can save at least one photomask. In addition, the deposition method can be commonly used on the same platform, and has better versatility and universality than the lithography process, thus effectively simplifying the manufacturing process, reducing the process cost, and better meeting the requirements of mass production.

[0082] Please refer to Figure 9, in some embodiments, in step S106, an ion implantation process is performed on the second region B inner substrate 10 to form a pixel doping region 50. The horizontal spacing D3 between the pixel doping region 50 and the gate structure 30 being associated with the first thickness D1 further includes:

[0083] Specifically, the conduction type of the doping ions in the pixel doping region is the same as that of the LDD ion implantation region. In this embodiment, the conduction type of the pixel doping region is N-type and is formed using doping ions such as phosphorus (P), arsenic (As), antimony (Sb), etc. It should be noted that the horizontal spacing D3 between the pixel doping region 50 and the gate structure 30 actually represents the distance from the pixel doping region 50 to the channel region. In addition, the horizontal spacing D3 is also associated with the type / dose / energy of ion implantation, and the corresponding distance needs to be defined by calculating the sensitivity through wafer testing (Chip probing, CP) using sampling inspection (Sampling Test).

[0084] In some embodiments, the first thickness D1 is positively correlated with the amplitude of the operating voltage of the pixel sensor.

[0085] In some embodiments, the horizontal spacing D3 is positively correlated with the first thickness D1.

[0086] Specifically, the first thickness D1 and the extended width ΔD are in a certain proportion. When the first thickness D1 is thicker, the indirect extension of the sidewall is greater, which means that the horizontal spacing between the pixel doping region formed based on this sidewall structure and the gate structure 30 is larger. Sufficient distance allows the depletion region to have sufficient space to expand, thereby consuming most of the voltage and avoiding electric field concentration near the gate, which may cause breakdown, and thus improving the tolerance of the operating voltage.

[0087] In some embodiments, the extended width ΔD can be predefined by means of pre-slice to establish the correlation between the two. For the same product, the extended width ΔD corresponding to different first thicknesses D1 is determined by conversion according to the correlation. After testing, the ratio range of the first thickness D1 to the horizontal spacing D3 is obtained as 0.15 - 0.45.

[0088] Specifically, please refer to Figure 9 , as described above, the first thickness D1 and the extended width ΔD are in a certain proportion. When the thickness D2 of the sidewall structure is constant, the larger the extended width ΔD, the larger the horizontal spacing D3 between the pixel doping region formed based on the first mask layer 41 and the gate structure 30.

[0089] Through preliminary slicing determination, the thickness D2 of the sidewall structure is 470 Å, and the ratio range of the first thickness D1 to the extension width ΔD is between 1.5 - 1.66, such as 1.5, 1.55, 1.60, or 1.66. When the first thickness D1 of the first mask layer 41 is 300 Å, the extension width ΔD is approximately 200 Å; when the first thickness D1 is 100 Å, the extension width ΔD is approximately 60 Å.

[0090] When the thickness D2 of the sidewall structure is fixed, through preliminary slicing determination, the ratio range of the first thickness D1 to the horizontal spacing D3 is 0.15 - 0.45, such as 0.15, 0.2, 0.25, 0.3, 0.35, 0.4, or 0.45. Since the horizontal spacing D3 is equal to the sum of the extension width ΔD and the sidewall structure thickness D2 (D3 = D2 + ΔD). Therefore, the ratio of the first thickness D1 to the horizontal spacing D3 is much smaller than the ratio of the first thickness D1 to the extension width ΔD.

[0091] When the thickness of the sidewall structure is 470 Å and the ratio of the first thickness D1 to the extension width ΔD is 1.65: It is measured under an operating voltage of 1.4V that an extension width ΔD of 60 Å can achieve a reduction of about 20 ppm in GIDL leakage in the pixel doping region 50; when the thickness of the sidewall structure is 470 Å and the ratio of the first thickness D1 to the extension width ΔD is 1.5, an extension width ΔD of 200 Å can achieve a reduction of about 30 ppm in GIDL leakage in the pixel doping region 50. The GIDL current in the pixel doping region formed based on the first mask layer 41 is significantly reduced, effectively improving the distortion and noise problems of the pixel unit signal.

[0092] Please refer to Figure 10 , in some embodiments, in step S108, part of the first mask layer 41 is removed to expose the outer surface of the gate structure 30, and the first mask layer 41 remaining on the top surface of the substrate 10 has a second thickness D4, further including:

[0093] Exemplarily, the above structure can be formed by dry etching, wet etching, or a combination of both. Dry etching includes at least any one of Reactive Ion Etching (RIE), Inductive Coupled Plasma Etching (ICP), or High Density Plasma Etching (HDP). The etching solution for the wet etching process used can be a mixed solution of hydrofluoric acid and hydrogen peroxide. Wet etching is often used in combination with dry etching to optimize the etching ability and efficiency, ensuring the manufacturing quality and consistency of the device. The specific selection should be based on different processing objects, requirements, and actual situations.

[0094] In some embodiments of the present application, the second thickness D4 is 12 Å - 35 Å, such as 12 Å, 15 Å, 20 Å, 25 Å, 30 Å, 35 Å, etc.

[0095] Please continue to refer to Figure 10 , specifically, half or one - third or less of the first thickness D1 is retained to obtain the second thickness D4, and the remaining first mask layer 41 covers the top surface of the active region to prevent the deterioration of the surface of the active region AA by ions during the etching process. When the second thickness D4 is 12 Å - 35 Å, on the one hand, it can avoid an increase in dark current caused by being too thin, affecting the reliability of the device; on the other hand, it can prevent the remaining first mask layer 41 from being too thick, resulting in unevenness in the device region of the preset type outside the substrate 10, affecting subsequent processes, and thus reducing the yield.

[0096] Please continue to refer to Figure 11 , in some embodiments, before step S110, that is, before forming the second mask layer 42, the substrate 10 is subjected to rapid thermal annealing.

[0097] Specifically, in this embodiment, mainly by using the rapid heating process and short duration in the RTA process, the doping elements in the substrate 10 are activated, and the lattice damage caused by ion implantation is repaired.

[0098] Please refer to Figure 12 , in some embodiments of the present application, the materials of the first mask layer 41 and the second mask layer 42 are the same or different. Considering the complexity of the manufacturing process, when the first mask layer 41 and the second mask layer 42 are made of the same material, corresponding to the same removal method, it can simplify the manufacturing process; considering the requirements for defects or filling capabilities, the first mask layer 41 and the second mask layer 42 are made of different types of materials (any combination of common materials). Specific selection is made according to the product, requirements, and actual situation.

[0099] Please refer to Figure 12 , in some embodiments, after step S110, it further includes: using the remaining first mask layer 41 and the second mask layer 42 as a mask, performing a self - aligned silicide process within the device region of the preset type.

[0100] When implementing the RTA process, it is required to reach a relatively high temperature in a short time. Since the thermal expansion coefficients of the first mask layer 41 and the substrate 10 are different, rapid cooling may cause separation or non - uniform shrinkage between the two layers, forming cracks, protrusions, or voids; or cause the accumulation of internal stress, which cannot be released in time during the cooling process, thus causing cracks or depressions on the surface of the first mask layer 41. Therefore, compared with directly using the first mask layer 41, the re - deposited second mask layer 42 and the remaining first mask layer 41 are jointly used for the subsequent SAB process, which is more conducive to reducing the generation of surface defects in the silicidation self - alignment process.

[0101] Specifically, Figure 13 Figure (1) shows a cross-sectional view of the chip morphology obtained without using the pixel unit preparation method provided in the present application, and a cross-sectional view of the chip morphology obtained by using the pixel unit preparation method provided in the present application ( Figure 13 Figure (2). By comparison Figure 13 It can be seen that the surface quality of the SAB mask layer 40 obtained by the preparation method provided in the present application is higher, smoother, and the defects are almost completely eliminated.

[0102] For example, performing the SAB process in the preset type device region includes: forming a photoresist layer covering the SAB mask layer 40, and performing exposure, development, and patterning the SAB mask layer 40 to expose the salicide region; sequentially forming a metal layer and a protective layer covering the SAB mask layer 40 and the salicide region; performing a rapid thermal annealing process on the metal layer; removing the protective layer and the unreacted metal layer; performing a second rapid thermal annealing process to react the substrate 10 with the metal to form a self-aligned metal silicide layer. The self-aligned metal silicide layer can be determined according to the metal used in the actual process, including but not limited to nickel (Ni), cobalt (Co), platinum (Pt), etc.

[0103] It should be understood that although Figure 6 The steps in the flowchart are shown in sequence as indicated by the arrows, but the steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of the steps, and the steps can be executed in other orders. Moreover, Figure 6 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0104] In some embodiments, the present application provides a pixel sensor, comprising a pixel unit prepared by the pixel unit preparation method in any of the above embodiments.

[0105] In some embodiments, the present application provides an electronic device, including a pixel unit prepared by the pixel unit preparation method in any of the above embodiments, or including a pixel sensor in the above embodiments.

[0106] In the pixel unit of the above pixel sensor, arranging the ion implantation process of the pixel doping region 50 after the first mask layer 41 of the SAB process can precisely control the lateral distance between the pixel doping region 50 and the channel according to the specific working voltage requirements of the pixel sensor by adjusting the thickness of the first mask layer 41. The effective control of the GIDL leakage risk of the pixel sensor is realized, which can significantly reduce the occurrence probability of white pixels in the pixel unit prepared by the above pixel unit preparation method, improve its image resolution, stability and durability, reduce the product power consumption at the same time, and improve the chip usage performance.

[0107] The technical features of the above embodiments can be combined arbitrarily. For the sake of concise description, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope recorded in this specification.

[0108] The above embodiments only represent several implementation manners of the present application, and the description is relatively specific and detailed, but it should not be understood as a limitation to the scope of the patent application. It should be pointed out that for those of ordinary skill in the art, without departing from the concept of the present application, several deformations and improvements can still be made, and these all belong to the protection scope of the present application.

Claims

1. A method for preparing a pixel unit, characterized in that: include: Providing a substrate, the substrate comprising a buried isolation structure, a first region, and a second region sequentially arranged along a first direction parallel to a top surface of the substrate; The top surface of the substrate in the first region includes a gate structure; forming a first mask layer having a first thickness covering the exposed top surface of the substrate and the outer surface of the gate structure; The first thickness is associated with an operating voltage amplitude of the pixel sensor; Performing an ion implantation process on the substrate in the second region to form a pixel doping region; The horizontal distance between the pixel doping region and the gate structure is associated with the first thickness; removing a portion of the first mask layer to expose the outer surface of the gate structure, and the first mask layer remaining on the top surface of the substrate has a second thickness; forming a second mask layer covering the first mask layer and the outer surface of the gate structure; Wherein, the substrate further includes a preset type device region, and after forming the second mask layer: The remaining first mask layer and the second mask layer are used as masks to perform a self-aligned metal silicide process in the predetermined type device region.

2. The method for preparing a pixel unit according to claim 1, characterized in that: The gate structure includes spacer structures arranged at intervals along the first direction, and a gate dielectric layer and a gate conductive layer located between adjacent spacer structures, contacting the spacer structures, and stacked in sequence along a direction away from the substrate.

3. The method for preparing a pixel unit according to claim 1, characterized in that: include: The ratio of the first thickness to the horizontal spacing is in the range of 0.15-0.

45.

4. The method for preparing a pixel unit according to claim 1, characterized in that: Before forming the second mask layer, the substrate is subjected to rapid thermal annealing.

5. The method for preparing a pixel unit according to any one of claims 1 to 4, characterized in that: Also includes: The first thickness is positively correlated with the operating voltage amplitude of the pixel sensor.

6. The method for preparing a pixel unit according to any one of claims 1 to 4, characterized in that: Also includes: The horizontal spacing is positively correlated with the first thickness.

7. The method for preparing a pixel unit according to any one of claims 1 to 4, characterized in that: The substrate includes an LDD ion implantation region and a Halo ion implantation region disposed on at least one side of the gate structure; The conductivity types of the doped ions in the LDD ion implantation region and the Halo ion implantation region are opposite; The conductivity type of the doped ions in the LDD ion implantation region and the pixel doping region is the same.

8. The method for preparing a pixel unit according to any one of claims 1 to 4, characterized in that: The conductivity type of the pixel doping region is N type.

9. A pixel sensor, characterized in that: include: A pixel unit manufactured by the pixel unit manufacturing method according to any one of claims 1 to 8.

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