Light detection device and distance measuring device

Abstract

The invention provides a light detection apparatus and a distance measuring apparatus. A light detection device according to the present invention comprises: a first chip including a first semiconductor substrate and a first wiring layer, the first semiconductor substrate including a plurality of pixels including avalanche photodiodes; a separation unit for separating the plurality of avalanche photodiodes from each other; and a plurality of concavo-convex portions, each of which is provided on the light incident side of the first semiconductor substrate with respect to each of the plurality of pixels. And a second chip including a second semiconductor substrate and a second wiring layer; wherein the first chip is bonded to the second chip, such that the first chip and the second chip face each other; moreover, each of the plurality of concave-convex parts is divided into four parts in a plan view.

Description

[0001] This application is a divisional application of a patent application with a filing date of February 6, 2020, an invention name of “Avalanche photodiode sensor and ranging device”, and an application number of 202080008797.3. Technical Field

[0002] The invention relates to an avalanche photodiode sensor and a distance measuring device. Background Art

[0003] In recent years, ranging image sensors that use time-of-flight (ToF) technology to measure distance have attracted much attention. For example, in ranging image sensors, a pixel array formed by arranging multiple single-photon avalanche diode (SPAD) pixels in a plane using CMOS (Complementary Metal Oxide Semiconductor) semiconductor integrated circuit technology can be used. In a SPAD pixel, if a photon enters a PN junction region with a high electric field while a voltage much higher than the breakdown voltage is being applied, avalanche amplification occurs. At this time, by detecting the time when the current flows instantaneously, the distance can be measured with high precision.

[0004] [Citation list]

[0005] [Patent Document]

[0006] [Patent Document 1] Japanese Patent Laid-Open JP 2018-88488A

[0007] [Patent Document 2] Japanese Patent Laid-Open JP 2017-108062 A

[0008] [Patent Document 3] International Application Publication No. WO 2018 / 074530 Summary of the invention

[0009] [Technical issues to be solved]

[0010] When the distance to an object is measured using a ranging image sensor as described above, the distance to the object is calculated based on the reflected light reflected by the object. Therefore, when the amount of reflected light (for example, the amount of reflected light from a distant object, etc.) is small, the reflected light may be submerged in the ambient light (also called interference light), and the ranging accuracy may be reduced.

[0011] Therefore, the present invention proposes an avalanche photodiode sensor and a distance measuring device capable of improving distance measurement accuracy.

[0012] [Technical solution to the problem]

[0013] In order to solve the above-mentioned problems, an avalanche photodiode sensor according to one aspect of the present invention includes: a first semiconductor substrate; and a second semiconductor substrate, which is bonded to the first surface of the first semiconductor substrate. Here, the first semiconductor substrate includes: a plurality of photoelectric conversion parts arranged in a matrix; and an element separation part for separating the plurality of photoelectric conversion parts from each other. The plurality of photoelectric conversion parts includes a first photoelectric conversion part. The element separation part has a first element separation region and a second element separation region. The first photoelectric conversion part is arranged between the first element separation region and the second element separation region. The first semiconductor substrate also includes a plurality of concave-convex parts, and the plurality of concave-convex parts are arranged on a second surface on a side opposite to the first surface and arranged between the first element separation region and the second element separation region. In addition, the second semiconductor substrate includes a readout circuit connected to each of the plurality of photoelectric conversion parts. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a block diagram showing a schematic configuration example of a ToF sensor as a distance measuring device according to the first embodiment.

[0015] Figure 2 is a diagram for explaining an optical system of a ToF sensor according to the first embodiment.

[0016] Figure 3 is a block diagram showing a schematic configuration example of a light receiving section according to the first embodiment.

[0017] Figure 4 is a schematic diagram showing a schematic configuration example of an effective region in the SPAD array according to the first embodiment.

[0018] Figure 5 is a circuit diagram showing a schematic configuration example of a SPAD pixel according to the first embodiment.

[0019] Figure 6 is a block diagram showing a more detailed configuration example of the SPAD adding section according to the first embodiment.

[0020] Figure 7 is a diagram showing an example of a chip configuration of a light receiving section according to the first embodiment.

[0021] Figure 8 is a cross-sectional view showing an example of a cross-sectional configuration of the first chip according to the first embodiment.

[0022] Fig. 9 It is shown Figure 8Cross-sectional view of the cross-sectional structure of the AA surface.

[0023] Fig.10 is a diagram for explaining an example of the moth-eye structure according to the first embodiment.

[0024] Fig.11 is a diagram for explaining another example of the moth-eye structure according to the first embodiment.

[0025] Fig.12 is a cross-sectional view showing an example of a cross-sectional configuration of a first chip according to a first modification example of the first embodiment.

[0026] Fig.13 It is shown Fig.12 Cross-sectional view of the cross-sectional structure of the BB surface.

[0027] Fig.14 is a cross-sectional view showing an example of a cross-sectional configuration of a first chip according to a second modification example of the first embodiment.

[0028] Fig.15 It is shown Fig.14 Cross-sectional view of the cross-sectional structure of the CC plane.

[0029] Fig.16 is a cross-sectional view showing an example of a cross-sectional configuration of a first chip according to a third modification example of the first embodiment.

[0030] Fig.17 is a cross-sectional view showing an example of a cross-sectional configuration of a first chip according to a fourth modification example of the first embodiment.

[0031] Fig.18 is a cross-sectional view showing an example of a cross-sectional configuration of a first chip according to a fifth modification example of the first embodiment.

[0032] Fig.19 is a cross-sectional view showing an example of a cross-sectional configuration of a first chip according to the second embodiment.

[0033] Fig. 20 It is shown Fig.19 Cross-sectional view of the cross-sectional structure of the GG plane.

[0034] Fig.21 is a cross-sectional view showing an example of a cross-sectional configuration of a first chip according to a first modification example of the second embodiment.

[0035] Fig. 22 It is shown Fig.21 Cross-sectional view of the cross-sectional structure of the HH plane.

[0036] Fig.23is a cross-sectional view showing an example of a cross-sectional configuration of a first chip according to a second modification example of the second embodiment.

[0037] Fig.24 It is shown Fig.23 Cross-sectional view of the cross-sectional structure of the JJ plane.

[0038] Fig.25 is a cross-sectional view showing an example of a cross-sectional configuration of a first chip according to a third modification example of the second embodiment.

[0039] Fig.26 is a cross-sectional view showing an example of a cross-sectional configuration of a first chip according to a fourth modification example of the second embodiment.

[0040] Fig. 27 is a cross-sectional view showing an example of a cross-sectional configuration of a first chip according to a fifth modification example of the second embodiment.

[0041] Fig.28 is a block diagram showing a schematic configuration example of a vehicle control system.

[0042] Fig.29 1 is an explanatory diagram showing an example of the installation positions of the vehicle exterior information detector and the camera unit. DETAILED DESCRIPTION

[0043] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following embodiments, the same parts are denoted by the same reference numerals, and thus their repeated description will be omitted.

[0044] The present invention will be explained in the order of the items given below.

[0045] 1. First Implementation Method

[0046] 1.1 Distance measuring device (ToF sensor)

[0047] 1.2 Optical system

[0048] 1.3 Light receiving unit

[0049] 1.4 SPAD Array

[0050] 1.5SPAD pixels

[0051] 1.6 Schematic Operation Example of SPAD Pixel

[0052] 1.7 SPAD Addition Unit

[0053] 1.8 Sampling period

[0054] 1.9 Chip Construction Example

[0055] 1.10 Section construction examples

[0056] 1.11 Moth Eye Structure

[0057] 1.12 Function and Effect

[0058] 1.13 Modification

[0059] 1.13.1 First Modification

[0060] 1.13.2 Second Modification

[0061] 1.13.3 Third variant

[0062] 1.13.4 Fourth variant

[0063] 1.13.5 Fifth variant

[0064] 2. Second Implementation Method

[0065] 2.1 Section construction examples

[0066] 2.2 Function and Effect

[0067] 2.3 Variations

[0068] 2.3.1 First Modification

[0069] 2.3.2 Second Modification

[0070] 2.3.3 Third Modification

[0071] 2.3.4 Fourth Modification

[0072] 2.3.5 Fifth Modification

[0073] 3. Application examples

[0074] 1. First Implementation Method

[0075] First, the first embodiment will be described in detail below with reference to the drawings.

[0076] 1.1 Distance measuring device (ToF sensor)

[0077] Figure 1 1 is a block diagram showing a schematic configuration example of a ToF sensor as a distance measuring device according to the first embodiment. Figure 1 As shown, the ToF sensor 1 includes a controller 11 , a light emitting section 13 , a light receiving section 14 , an operation unit 15 , and an external interface (I / F) 19 .

[0078] The controller 11 is constituted by an information processing device such as a central processing unit (CPU), for example, and controls each component of the ToF sensor 1 .

[0079] For example, the external interface 19 may be a communication adapter capable of establishing communication with an external host 80 via a communication network conforming to any standard such as a wireless LAN (Local Area Network), a wired LAN, a controller area network (CAN), a local interconnect network (LIN), or FlexRay (registered trademark).

[0080] Here, for example, when the ToF sensor 1 is mounted on a car or the like, the host 80 may be an engine control unit (ECU: Engine Control Unit) mounted on the car or the like. For another example, when the ToF sensor 1 is mounted on an autonomous mobile body, the host 80 may be a control device capable of controlling the autonomous mobile body, such as an autonomous mobile robot such as a household pet robot, a robot vacuum cleaner, an unmanned aerial vehicle, or a tracking transport robot.

[0081] For example, the light emitting section 13 includes one or more semiconductor laser diodes as a light source, and emits a laser light L1 in the form of a pulse having a predetermined time width at a predetermined cycle (also referred to as a light emission cycle). For example, the light emitting section 13 emits a laser light L1 having a time width of 10 nanoseconds (ns) at a cycle of 100 MHz (megahertz). For example, when an object 90 exists within the ranging range, the laser light L1 emitted from the light emitting section 13 is reflected by the object 90, and the reflected light L2 is incident on the light receiving section 14.

[0082] The light receiving section 14 is an avalanche photodiode sensor, the details of which will be described later, and, for example, includes a plurality of SPAD pixels arranged in a matrix and outputs information (e.g., equivalent to the number of detection signals described later) about the number of SPAD pixels that have respectively detected the incidence of photons after the light emitting section 13 emits light (hereinafter, referred to as the detection number). For example, the light receiving section 14 detects the incidence of photons at a predetermined sampling period for one emission of light by the light emitting section 13 and outputs the detection number.

[0083] The operation unit 15 counts the number of detections output from the light receiving unit 14 for each of the plurality of SPAD pixels (e.g., corresponding to one or more macro pixels to be described later), and creates a histogram with the horizontal axis being the flight time and the vertical axis being the accumulated pixel value based on the pixel value obtained by the counting. For example, for each of the multiple light emission of the light emitting unit 13, the operation unit 15 repeatedly counts the number of detections for one light emission of the light emitting unit 13 at a predetermined sampling frequency to obtain the pixel value, thereby creating the following histogram: wherein the horizontal axis (bin of the histogram) is the sampling period corresponding to the flight time, and the vertical axis is the accumulated pixel value obtained by accumulating the pixel values ​​obtained in each sampling period.

[0084] In addition, the operation unit 15 performs a predetermined filtering process on the created histogram, and then determines the flight time when the cumulative pixel value reaches a peak from the filtered histogram. Then, the operation unit 15 calculates the distance from the ToF sensor 1 or the device equipped with the ToF sensor 1 to the object 90 existing in the ranging range based on the determined flight time. For example, the information of the distance calculated by the operation unit 15 can be output to the host 80 or the like via the external interface 19.

[0085] 1.2 Optical system

[0086] Figure 2 is a diagram for explaining an optical system of a ToF sensor according to the first embodiment. Figure 2 However, the optical system of the ToF sensor is not limited thereto, and may be, for example, a so-called flash ToF sensor optical system in which the viewing angle of the light receiving section 14 is fixed.

[0087] like Figure 2 As shown, the optical system of the ToF sensor 1 includes a light source 131, a collimating lens 132, a half mirror 133, a galvanometer mirror 135, a light receiving lens 146, and a SPAD array 141. For example, the light source 131, the collimating lens 132, the half mirror 133, and the galvanometer mirror 135 are included in Figure 1 For example, the light receiving lens 146 and the SPAD array 141 are included in the light emitting section 13. Figure 1 In the light receiving unit 14.

[0088] exist Figure 2In the structure shown, the laser light L1 emitted from the light source 131 is converted into a rectangular parallel light whose cross-sectional intensity spectrum is long in the vertical direction by the collimating lens 132, and then is incident on the half mirror 133. The half mirror 133 reflects a part of the incident laser light L1. The laser light L1 reflected by the half mirror 133 is incident on the galvanometer mirror 135. For example, by the driving unit 134 operating under the control of the controller 11, the galvanometer mirror 135 is vibrated in the horizontal direction with a predetermined rotation axis as the vibration center. Thereby, the laser light L1 is horizontally scanned, so that the viewing angle SR of the laser light L1 reflected by the galvanometer mirror 135 is reciprocated in the horizontal direction across the distance measurement range AR. In addition, as the driving unit 134, a micro-electromechanical system (MEMS: Micro-Electro-Mechanical System) or a micro-motor or the like can be used.

[0089] The laser light L1 reflected by the galvanometer mirror 135 is reflected by the object 90 present in the ranging range AR, and the reflected light L2 is incident on the galvanometer mirror 135. A portion of the reflected light L2 incident on the galvanometer mirror 135 is transmitted through the half mirror 133 and is incident on the light receiving lens 146, thereby forming an image on a specific area (hereinafter, referred to as an effective area) 142 in the SPAD array 141. In addition, the effective area 142 may be all or part of the SPAD array 141.

[0090] 1.3 Light receiving unit

[0091] Figure 3 1 is a block diagram showing a schematic configuration example of a light receiving section according to the first embodiment. Figure 3 As shown, the light receiving section 14 includes a SPAD array 141, a timing control circuit 143, a drive circuit 144, and an output circuit 145. In the following description, the timing control circuit 143, the drive circuit 144, and the output circuit 145 may sometimes be referred to as peripheral circuits.

[0092] The SPAD array 141 includes a plurality of SPAD pixels 20 arranged in a matrix. Pixel drive lines LD (which extend in the vertical direction in the figure) are connected to each column of the plurality of SPAD pixels 20, and output signal lines LS (which extend in the horizontal direction in the figure) are connected to each row of the plurality of SPAD pixels 20. One end of each pixel drive line LD is connected to an output terminal of the drive circuit 144 corresponding to each column, and one end of each output signal line LS is connected to an input terminal of the output circuit 145 corresponding to each row.

[0093] In the present embodiment, all or part of the SPAD array 141 is used to detect the reflected light L2. When the laser light L1 is all reflected as the reflected light L2, the effective area 142 in the SPAD array 141 may be a vertically long rectangle similar to the image of the reflected light L2 imaged on the SPAD array 141. However, the effective area 142 in the SPAD array 141 is not limited thereto, and various modifications may be made, such as being a larger area or a smaller area than the image of the reflected light L2 imaged on the SPAD array 141, etc.

[0094] The driving circuit 144 includes a shift register and an address decoder, etc., and drives all pixels simultaneously or in columns or in other ways for each SPAD pixel 20 in the SPAD array 141. Therefore, the driving circuit 144 includes at least: a circuit for applying a quenching voltage V_QCH described later to each SPAD pixel 20 in a selected column of the SPAD array 141; and a circuit for applying a selection control voltage V_SEL described later to each SPAD pixel 20 in the selected column. Then, the driving circuit 144 selects the SPAD pixel 20 used to detect the incidence of photons in columns by applying the selection control voltage V_SEL to the pixel driving line LD corresponding to the column to be read out.

[0095] The signal (referred to as a detection signal) V_OUT output from each SPAD pixel 20 in the column selected and scanned by the drive circuit 144 is input to the output circuit 145 through each output signal line LS. The output circuit 145 outputs the detection signal V_OUT input from each SPAD pixel 20 to the SPAD adder 40 provided for each macro pixel described later.

[0096] The timing control circuit 143 includes a timing generator and the like for generating various timing signals, and controls the driving circuit 144 and the output circuit 145 based on the various timing signals generated by the timing generator.

[0097] 1.4 SPAD Array

[0098] Figure 4 1 is a schematic diagram showing a schematic configuration example of an active region in a SPAD array according to the first embodiment. Figure 4 As shown, for example, the active area 142 has a structure in which a plurality of SPAD pixels 20 are arranged in a matrix. The plurality of SPAD pixels 20 are grouped into a plurality of macro pixels 30, each of which is composed of a predetermined number of SPAD pixels 20 arranged in a row and / or column direction. The area defined by connecting the outer edges of the SPAD pixels 20 located on the outermost periphery of each macro pixel 30 has a predetermined shape (e.g., a rectangle).

[0099] For example, the active region 142 is composed of a plurality of macro pixels 30 arranged in the vertical direction (equivalent to the column direction). In the present embodiment, for example, the active region 142 is divided into a plurality of regions (hereinafter referred to as SPAD regions) in the vertical direction. Figure 4 In the example shown, the active area 142 is divided into four SPAD regions 142-1 to 142-4. The SPAD region 142-1 at the lowest position corresponds to, for example, the lowest quarter region in the viewing angle SR of the active area 142, the SPAD region 142-2 located above the SPAD region 142-1 corresponds to, for example, the second quarter region from the lowest in the viewing angle SR, the SPAD region 142-3 located above the SPAD region 142-2 corresponds to, for example, the third quarter region from the lowest in the viewing angle SR, and the SPAD region 142-4 at the highest position corresponds to, for example, the highest quarter region in the viewing angle SR.

[0100] 1.5SPAD pixels

[0101] Figure 5 1 is a circuit diagram showing a schematic configuration example of a SPAD pixel according to the first embodiment. Figure 5 As shown, the SPAD pixel 20 includes: a photoelectric conversion portion 21 as a light receiving element; and a readout circuit 22 for detecting that a photon has been incident on the photoelectric conversion portion 21 .

[0102] The readout circuit 22 includes a quenching resistor 23, a digital converter 25, an inverter 26, a buffer 27, and a selection transistor 24. For example, the quenching resistor 23 is composed of an N-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) (hereinafter, referred to as an NMOS transistor), whose drain is connected to the anode of the photoelectric conversion unit 21 and whose source is grounded via the selection transistor 24. In addition, a preset quenching voltage V_QCH is applied from the drive circuit 144 via the pixel drive line LD to the gate of the NMOS transistor constituting the quenching resistor 23, and the quenching voltage V_QCH is used to enable the NMOS transistor to function as a quenching resistor.

[0103] In this embodiment, the photoelectric conversion unit 21 is a SPAD. SPAD is an avalanche photodiode that operates in Geiger mode if a reverse bias voltage greater than the breakdown voltage is applied between its anode and cathode, and can detect the incidence of one photon. That is, when a photon is incident in a state where a reverse bias voltage V_SPAD greater than the breakdown voltage is applied between the anode and cathode of the photoelectric conversion unit 21, the photoelectric conversion unit 21 generates an avalanche current.

[0104] The digital converter 25 includes a resistor 251 and an NMOS transistor 252. The drain of the NMOS transistor 252 is connected to the power supply voltage VDD via the resistor 251, and the source of the NMOS transistor 252 is grounded. The voltage at the connection point N1 between the anode of the photoelectric conversion unit 21 and the quenching resistor 23 is applied to the gate of the NMOS transistor 252.

[0105] The inverter 26 includes a P-type MOSFET (hereinafter, referred to as a PMOS transistor) 261 and an NMOS transistor 262. The drain of the PMOS transistor 261 is connected to the power supply voltage VDD, and the source of the PMOS transistor 261 is connected to the drain of the NMOS transistor 262. The drain of the NMOS transistor 262 is connected to the source of the PMOS transistor 261, and the source of the NMOS transistor 262 is grounded. The voltage at the connection point N2 between the resistor 251 and the drain of the NMOS transistor 252 is applied to the gate of the PMOS transistor 261 and the gate of the NMOS transistor 262. The output of the inverter 26 is input to the buffer 27.

[0106] The buffer 27 is a circuit for impedance conversion. When the output signal is input from the inverter 26 to the buffer 27, the buffer 27 performs impedance conversion on the input output signal and outputs the converted signal as the detection signal V_OUT.

[0107] For example, the selection transistor 24 is an NMOS transistor, the drain of the selection transistor 24 is connected to the source of the NMOS transistor constituting the quenching resistor 23, and the source of the selection transistor 24 is grounded. The selection transistor 24 is connected to the drive circuit 144. When the selection control voltage V_SEL from the drive circuit 144 has been applied to the gate of the selection transistor 24 via the pixel drive line LD, the selection transistor 24 changes from the off state to the on state.

[0108] 1.6 Schematic Operation Example of SPAD Pixel

[0109] For example, Figure 5The readout circuit 22 shown operates as follows: First, while the selection control voltage V_SEL is applied from the drive circuit 144 to the selection transistor 24 and the selection transistor 24 is turned on, a reverse bias voltage V_SPAD equal to or higher than the breakdown voltage is applied to the photoelectric converter 21. Thus, the operation of the photoelectric converter 21 is permitted.

[0110] On the other hand, while the selection control voltage V_SEL is not applied from the drive circuit 144 to the selection transistor 24 and the selection transistor 24 is in the off state, the reverse bias voltage V_SPAD is not applied to the photoelectric converter 21 and the operation of the photoelectric converter 21 is prohibited.

[0111] If a photon is incident on the photoelectric conversion unit 21 when the selection transistor 24 is in the on state, an avalanche current is generated in the photoelectric conversion unit 21. Therefore, the avalanche current flows through the quenching resistor 23, and the voltage at the connection point N1 rises. When the voltage at the connection point N1 becomes higher than the on voltage of the NMOS transistor 252, the NMOS transistor 252 becomes the on state, and the voltage at the connection point N2 changes from the power supply voltage VDD to 0V. Then, when the voltage at the connection point N2 changes from the power supply voltage VDD to 0V, the PMOS transistor 261 changes from the off state to the on state, the NMOS transistor 262 changes from the on state to the off state, and the voltage at the connection point N3 changes from 0V to the power supply voltage VDD. As a result, a high-level detection signal V_OUT is output from the buffer 27.

[0112] Thereafter, when the voltage at the connection point N1 continues to rise, the voltage applied between the anode and cathode of the photoelectric conversion unit 21 becomes lower than the breakdown voltage, whereby the avalanche current stops and the voltage at the connection point N1 drops. Then, when the voltage at the connection point N1 becomes lower than the turn-on voltage of the NMOS transistor 252, the NMOS transistor 252 becomes turned off, and the output of the detection signal V_OUT from the buffer 27 stops (becomes low level).

[0113] In this way, the readout circuit 22 outputs a high-level detection signal V_OUT during the period from when a photon is incident on the photoelectric conversion unit 21 and an avalanche current is generated, thereby turning the NMOS transistor 252 into an on state, to when the avalanche current stops and the NMOS transistor 252 turns into an off state. The output detection signal V_OUT is input to the SPAD adder 40 provided for each macro pixel 30 via the output circuit 145. Therefore, the same number of detection signals V_OUT as the number of SPAD pixels 20 (detection number) that detect the incidence of photons among the plurality of SPAD pixels 20 constituting one macro pixel 30 is input to each SPAD adder 40.

[0114] 1.7 SPAD Addition Unit

[0115] Figure 6 1 is a block diagram showing a more detailed configuration example of the SPAD adding section according to the first embodiment. The SPAD adding section 40 may be configured to be included in the light receiving section 14 or configured to be included in the arithmetic unit 15.

[0116] like Figure 6 As shown, for example, the SPAD adding section 40 includes a pulse shaping unit 41 and a light reception number counting unit 42 .

[0117] The pulse shaping unit 41 shapes the pulse waveform of the detection signal V_OUT input from the SPAD array 141 via the output circuit 145 into a pulse waveform having a time width corresponding to the operation clock of the SPAD adder 40 .

[0118] The light receiving number counting unit 42 counts the detection signal V_OUT input from the corresponding macro-pixel 30 in each sampling cycle, thereby counting the number of SPAD pixels 20 that detect the incidence of photons (detection number) in each sampling cycle, and outputs the count value as the pixel value of the macro-pixel 30.

[0119] 1.8 Sampling period

[0120] Here, the sampling period refers to a period for measuring the time (flight time) from the emission of the laser light L1 by the light emitting unit 13 to the detection of the incidence of the photon by the light receiving unit 14. Regarding this sampling period, it is set to a period shorter than the light emission period of the light emitting unit 13. For example, by shortening the sampling period, the flight time of the photon emitted from the light emitting unit 13 and reflected by the object 90 can be calculated with a higher time resolution. This means that by increasing the sampling frequency, the distance to the object 90 can be calculated with a higher ranging resolution.

[0121] For example, assuming that t is the flight time from when the laser L1 is emitted from the light emitting unit 13 and then reflected by the object 90 until the reflected light L2 is incident on the light receiving unit 14, since the speed of light C is constant (C≈300,000,000 meters / second (m / s)), the distance L from the object 90 can be calculated by the following formula (1).

[0122] L = C × t / 2 (1)

[0123] Therefore, when the sampling frequency is 1 GHz, the sampling period is 1 nanosecond (ns). In this case, one sampling period is equivalent to 15 centimeters (cm). This shows that when the sampling frequency is 1 GHz, the ranging resolution is 15 cm. In addition, when the sampling frequency is doubled to 2 GHz, the sampling period is 0.5 nanoseconds (ns), so one sampling period is equivalent to 7.5 centimeters (cm). This shows that when the sampling frequency is doubled, the ranging resolution can be halved. Therefore, by increasing the sampling frequency and shortening the sampling period, the distance to the object 90 can be calculated with higher accuracy.

[0124] 1.9 Chip Construction Example

[0125] Figure 7 1 is a diagram showing an example of a chip configuration of a light receiving portion according to the first embodiment. Figure 7 As shown, for example, the ToF sensor 1 has a structure of a bonded chip 50 in which a first chip 51 and a second chip 52 are bonded up and down to form. For example, the first chip 51 is a semiconductor chip in which the photoelectric conversion parts 21 of the SPAD pixels 20 are arranged in a matrix, and for example, the second chip 52 is a semiconductor chip in which the readout circuit 22 of the SPAD pixels 20 is formed and peripheral circuits and the like are formed.

[0126] For example, the bonding of the first chip 51 and the second chip 52 can use so-called direct bonding. In so-called direct bonding, the bonding surfaces of the first chip 51 and the second chip 52 are flattened and then the first chip 51 and the second chip 52 are bonded together by electron force. However, the present invention is not limited to this, and for example, the above-mentioned bonding can use so-called Cu-Cu bonding or bump bonding other than this. In so-called Cu-Cu bonding, electrode pads made of copper (Cu) formed on the bonding surfaces of the first chip 51 and the second chip 52 are bonded together.

[0127] For example, the first chip 51 and the second chip 52 are electrically connected to each other via a connection portion such as a through-silicon via (TSV: Through-Silicon Via) that penetrates the semiconductor substrate. For example, the connection achieved using TSV can adopt the so-called double TSV method, or the so-called shared TSV method, etc. In the so-called double TSV method, the TSV set in the first chip 51 and the TSV set from the first chip 51 to the second chip 52 are connected to each other at the outer surfaces of these chips. In the so-called shared TSV method, the first chip 51 and the second chip 52 are connected to each other using the TSV that penetrates from the first chip 51 to the second chip 52.

[0128] However, when Cu-Cu bonding or bump bonding is used for bonding the first chip 51 and the second chip 52 , the first chip 51 and the second chip 52 are electrically connected to each other via the Cu-Cu bonding portion or the bump bonding portion.

[0129] Figure 7 The bonded chip 50 shown may include, in addition to the light receiving unit 14 , an operation unit 15 , a light emitting unit 13 , a controller 11 , and the like.

[0130] 1.10 Example of cross-section construction

[0131] Figure 8 is a cross-sectional view showing an example of a cross-sectional configuration of the first chip according to the first embodiment. Fig. 9 It is shown Figure 8 Cross-sectional view of the cross-sectional structure of the AA surface. Figure 8 FIG. 2 shows an example of a cross-sectional configuration of the photoelectric conversion unit 21 in one SPAD pixel 20. However, in reality, Fig. 9 As shown, in the first chip 51, there is Figure 8 The photoelectric conversion units 21 of the illustrated cross-sectional structure are arranged in a matrix. Figure 8 In the embodiment, the lower surface of the first chip 51 is the light incident surface.

[0132] like Figure 8 As shown, the first chip 51 includes a semiconductor substrate 150 , a wiring layer 170 , a planarization film 161 , and an on-chip lens 162 .

[0133] The semiconductor substrate 150 may be a semiconductor substrate made of a semiconductor material such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), gallium phosphide (GaP), or indium phosphide (InP), or a compound semiconductor material.

[0134] In the semiconductor substrate 150 , the photoelectric conversion unit 21 including an N− type semiconductor region 151 , a P type semiconductor region 153 , a P+ type semiconductor region 154 , and a contact layer 156 is formed.

[0135] For example, the N-type semiconductor region 151 is a well region and may be a region containing low-concentration donors. For example, the N-type semiconductor region 151 may be a rectangular parallelepiped region whose cross section parallel to the back surface of the semiconductor substrate 150 is a square or rectangular shape.

[0136] For example, the P-type semiconductor region 153 is a region including acceptors at a predetermined concentration, and may be a region surrounding at least the side surface and the bottom surface of the N-type semiconductor region 151 .

[0137] For example, the N+ type semiconductor region 155 is a region containing a high concentration of donors, and is arranged on the front surface of the semiconductor substrate 150. For example, the P+ type semiconductor region 154 is a region containing a higher concentration of acceptors than the P type semiconductor region 153, and is arranged near the front surface of the semiconductor substrate 150, and the P+ type semiconductor region 154 contacts the N+ type semiconductor region 155.

[0138] The P+ type semiconductor region 154 and the N+ type semiconductor region 155 form a PN junction that generates an avalanche current. Therefore, the charge generated by photoelectric conversion in the N-type semiconductor region 151 is captured in the P+ type semiconductor region 154, and then amplified (avalanche amplification) due to the relatively large potential difference given between the P+ type semiconductor region 154 and the N+ type semiconductor region 155.

[0139] The N+ type semiconductor region 155 also functions as a cathode of the photoelectric conversion unit 21, and as a contact layer for extracting the generated avalanche current to the outside of the semiconductor substrate 150. On the other hand, in the P type semiconductor region 153, a contact layer 156 is also formed in a region which is on the front surface of the semiconductor substrate 150 and is separated from the N+ type semiconductor region 155. For example, the contact layer 156 is a P++ type region containing a higher concentration of acceptors, and also functions as an anode of the photoelectric conversion unit 21. For example, in the case of observing the front surface of the semiconductor substrate 150 on which the contact layer 156 is formed in a plan view (for example, see the later-described Fig. 9 ), the contact layer 156 is formed on the front surface of the semiconductor substrate 150 along the inner and outer peripheries of the region surrounded by the element separation portion 157. Figure 8 As shown, when the cross-sectional structure is observed in which the element separation portion 157 is regarded as being divided into two left and right regions (which will be referred to as element separation regions) 157A and 157B, the contact layer 156 is formed in the following two regions among the regions divided by the two left and right element separation regions 157A and 157B: these two regions are on the front side of the semiconductor substrate 150 and are close to the element separation regions 157A and 157B, respectively.

[0140] The N+ type semiconductor region 155 may also function as an anode of the photoelectric conversion portion 21. In this case, the contact layer 156 functions as a cathode of the photoelectric conversion portion 21.

[0141] As described above, the photoelectric conversion unit 21 having the above-mentioned configuration is divided by the element separation unit 157. For example, Figure 8 and Fig. 9 As shown, when viewed from the front surface or the back surface side of the semiconductor substrate 150 , the element separation portion 157 is provided in the grooves formed in a lattice shape.

[0142] For example, each element separation portion 157 includes an insulating film 159 covering the inner side surface of a groove formed in the semiconductor substrate 150, and a reflective film 158 embedded in the groove having the insulating film 159 formed on the inner side surface. Here, the groove does not necessarily have to be completely embedded by the reflective film 158, and a gap may be left in a part of the groove.

[0143] For example, the reflective film 158 is a film for reflecting light incident on the element separation portion 157. For example, as the reflective film 158, not only a reflective material such as tungsten (W) that can reflect visible light or infrared light, but also a reflective material such as silicon (Si), germanium (Ge), gallium phosphide (GaP), aluminum oxide (Al2O3) and the like can be used. 2 O 3 ), cerium oxide (CeO 2 ), hafnium oxide (HfO 2 ), indium oxide (In 2 O 3 ), tin oxide (SnO 2 ), niobium pentoxide (Nb 2 O 5 ), magnesium oxide (MgO), tantalum pentoxide (Ta 2 O 5 ), titanium pentoxide (Ti 3 O 5 ), other titanium oxides (such as TiO or TiO 2 etc.), tungsten oxide (WO 3 ), yttrium oxide (Y 2 O 3 )、ZnO、ZrO 2 ), cerium fluoride (CeF 3 ), Gadolinium fluoride (GdF 3 ), lanthanum fluoride (LaF 3 ) or neodymium fluoride (NdF 3 ) and other high refractive index materials. The so-called high refractive index material may be a material having a refractive index higher than the refractive index of the substrate material of the semiconductor substrate 150.

[0144] For example, the insulating film 159 is a film for preventing electrical contact between the semiconductor substrate 150 and the reflective film 158. For example, as the insulating film 159, a material such as silicon oxide (SiO 2 ) or an insulating material such as silicon nitride (SiN). However, in the case where the reflective film 158 is made of an insulating material, the insulating film 159 can be omitted.

[0145] In this manner, by optically isolating adjacent SPAD pixels 20 using the element isolation section 157 , leakage of light into adjacent SPAD pixels 20 can be reduced, thereby suppressing color mixing between adjacent pixels.

[0146] Figure 8 A so-called forward full trench isolation (FFTI: Front Full Trench Isolation) type element separation portion 157 extending from the front side to the back side of the semiconductor substrate 150 is shown. However, the structure of the element separation portion 157 is not limited to the FFTI type. For example, various modifications can be made, such as a so-called deep trench isolation (DTI: Deep Trench Isolation) type element separation portion extending from the front side to the middle of the semiconductor substrate 150, or a so-called reverse deep trench isolation (RDTI: Reverse Deep Trench Isolation) type element separation portion extending from the back side to the middle of the semiconductor substrate 150, and the like.

[0147] In addition, if Figure 8 and Fig. 9 As shown, on the back side of the semiconductor substrate 150, a plurality of regularly or randomly arranged concave-convex portions 181 are provided over the entire area of ​​each region 180 divided by the element separation portion 157, that is, on the effective light incident surface of the semiconductor substrate 150.

[0148] For example, each concave-convex portion 181 may have various shapes such as the following: a polygonal prism such as a quadrangular prism, a triangular prism, or a hexagonal prism; a polygonal pyramid such as a quadrangular pyramid, a triangular pyramid, or a hexagonal pyramid; a polygonal pyramid such as a quadrangular pyramid, a triangular pyramid, or a hexagonal pyramid; a cone (including an elliptical cone); or a truncated cone. For example, by setting a shape in which the diameter decreases as it approaches the front end, the refractive index change along the traveling direction of the light can be made more gentle. In addition, the shape also includes a shape in which the front end is an obtuse angle or a shape in which the front end is flat (such as a polygonal pyramid or a truncated cone).

[0149] The interior of the concavo-convex portion 181 may be made of a material such as silicon oxide (SiO 2 ) or an insulating film such as silicon nitride (SiN). The size of each concavoconvex portion 181 can be variously modified as long as it is a size such as several micrometers (μm) or several nanometers (nm) that can reduce the reflectivity of the back surface of the semiconductor substrate 150.

[0150] By forming the back surface of the semiconductor substrate 150 into a moth-eye structure including a plurality of concavoconvex portions 181 in this way, the reflectivity of the back surface of the semiconductor substrate 150 can be reduced. Thus, the incident efficiency of light toward the photoelectric conversion unit 21 can be improved, and as a result, the quantum efficiency of the photoelectric conversion unit 21 can be improved.

[0151] Furthermore, by combining the reflective film 158 in the element isolation unit 157 with the moth-eye structure, the light scattered or diffracted by the moth-eye structure can be reflected by the reflective film 158. This can lengthen the flight distance of the light incident on the semiconductor substrate 150 in the photoelectric conversion unit 21, and as a result, the quantum efficiency of the photoelectric conversion unit 21 can be improved.

[0152] On the back surface of the semiconductor substrate 150, an on-chip lens 162 is provided via a planarization film 161 made of a silicon oxide film or a silicon nitride film, etc. The planarization film 161 may include a pinning layer, etc., provided at a boundary portion between the planarization film 161 and the semiconductor substrate 150. For example, the surface of the on-chip lens 162 is given a curvature that causes incident light to be focused near the center of the photoelectric conversion unit 21.

[0153] On the other hand, the above-mentioned wiring layer 170 is provided on the front side of the semiconductor substrate 150. The wiring layer 170 includes an insulating film 171 such as a silicon oxide film or a silicon nitride film. For example, a via wiring 172 in contact with the N+ type semiconductor region 155 also serving as a cathode of the photoelectric conversion unit 21 and a via wiring 176 in contact with the contact layer 156 also serving as an anode of the photoelectric conversion unit 21 are provided in the insulating film 171.

[0154] In addition, for example, an electrode pad 173 made of copper (Cu) in contact with the via wiring 172 and an electrode pad 177 made of copper (Cu) in contact with the via wiring 176 are provided on the front side (the surface on the side opposite to the semiconductor substrate 150) of the insulating film 171. These electrode pads 173 and 177 are used as electrode pads when the first chip 51 and the second chip 52 are Cu-Cu bonded. Therefore, when the first chip 51 and the second chip 52 are electrically and mechanically bonded in other bonding forms, the electrode pads 173 and 177 can be replaced with components that can be used for the bonding.

[0155] exist Figure 8 Although the detailed illustration of the second chip 52 is omitted, it shows: electrode pads 191 and 195 made of copper (Cu) for Cu-Cu bonding; terminal 192 for applying a potential (e.g., +3 volts (V)) to the cathode of the photoelectric conversion unit 21; and terminal 196 for applying a potential (e.g., -20 volts (V)) to the anode of the photoelectric conversion unit 21.

[0156] For example, when +3V is applied to the cathode (N+ semiconductor region 155) of the photoelectric conversion unit 21 via the terminal 192, and -20V is applied to the anode (contact layer 156) of the photoelectric conversion unit 21 via the terminal 196, a reverse bias voltage V_SPAD of 23V is theoretically applied between the N+ semiconductor region 155 and the P+ semiconductor region 154. Since the reverse bias voltage V_SPAD is a potential difference greater than the breakdown voltage of the N+ semiconductor region 155 and the P+ semiconductor region 154, the charges generated by the photoelectric conversion are moved and captured in the P+ semiconductor region 154 due to the electric field formed in the N-type semiconductor region 151, thereby generating an avalanche current in the PN junction region composed of the N+ semiconductor region 155 and the P+ semiconductor region 154. The avalanche current is input to the readout circuit 22 via the terminal 192.

[0157] In the above configuration, the P type and the N type can be interchanged. In this case, the N-type semiconductor region 151 is replaced by the P-type semiconductor region, the P-type semiconductor region 153 is replaced by the N-type semiconductor region, the P+ type semiconductor region 154 is replaced by the N+ type semiconductor region, and the N+ type semiconductor region 155 is replaced by the P+ type semiconductor region. In addition, the contact layer 156 is replaced by the N++ type region.

[0158] 1.11 Moth Eye Structure

[0159] Here, we will refer to Fig.10 The moth-eye structure is described below. The moth-eye structure is a region in which fine concavoconvex portions 181 are formed. However, the concavoconvex portions and the convex portions may vary depending on where a plane serving as a reference (hereinafter, referred to as a reference plane) is provided.

[0160] The moth-eye structure is a region having a fine concavo-convex structure formed at the interface (interface on the light receiving surface side) of the P-type semiconductor region 153 above the N-type semiconductor region 151 as a charge storage region. The concavo-convex structure is formed on the P-type semiconductor region 153, that is, on the light receiving surface side of the semiconductor substrate 150. Therefore, the reference plane may be a specific plane of the semiconductor substrate 150. The description will be continued with reference to the case where a part of the semiconductor substrate 150 is used as the reference plane as an example.

[0161] Fig.10 It is an enlarged view of the vicinity of the concavo-convex portion 181. In this specification, a case will be shown where the planarizing film 161 includes the pinning layer 163 as its bottom layer (on the semiconductor substrate 150 side) and the transparent insulating film 164 at the upper layer of the pinning layer 163.

[0162] exist Fig.10In the example shown, it is assumed that the interface between the pinning layer 163 and the transparent insulating film 164 in the concavo-convex portion 181 is the upper surface 181-1. In addition, the interface between the pinning layer 163 and the semiconductor substrate 150 is the lower surface 181-2.

[0163] In addition, it is assumed that reference plane A is a surface at a position where upper surface 181-1 is formed, and reference plane C is a surface at a position where lower surface 181-2 is formed. Reference plane B is assumed to be a surface located between reference plane A and reference plane C, that is, a surface located between upper surface 181-1 and lower surface 181-2.

[0164] When the reference plane A is used as a reference, the shape of the concavoconvex part 181 is a shape of a concave part relative to the reference plane A. That is, when the reference plane A is used as a reference, the lower surface 181-2 is located at a position recessed toward the bottom relative to the reference plane A (=upper surface 181-1), and the concavoconvex part 181 is a region where a fine concave part is formed. In other words, when the reference plane A is used as a reference, a concave part is formed between the upper surface 181-1 and the upper surface 181-1, and therefore, the concavoconvex part 181 can be said to be a region where a fine concave part is formed.

[0165] When the reference plane C is used as a reference, the shape of the concavoconvex part 181 is a shape of a convex part relative to the reference plane C. That is, when the reference plane C is used as a reference, the upper surface 181-1 is located at a position protruding upward relative to the reference plane C (=lower surface 181-2), and the concavoconvex part 181 is a region where a fine convex part is formed. In other words, when the reference plane C is used as a reference, a convex part is formed between the lower surface 181-2 and the lower surface 181-2, and therefore, the concavoconvex part 181 can be said to be a region where a fine convex part is formed.

[0166] When the reference plane B is used as a reference, the shape of the concavoconvex part 181 is a shape of concave and convex parts with respect to the reference plane B. That is, when the reference plane B is used as a reference, the lower surface 181-2 is located at a position recessed toward the lower side with respect to the reference plane B (= a surface located at a midway position between the upper surface 181-1 and the lower surface 181-2), and therefore, the concavoconvex part 181 can be said to be a region in which fine concave parts are formed.

[0167] Moreover, when the reference plane B is used as a reference, the upper surface 181 - 1 is located at a position protruding toward the upper side relative to the reference plane B, and therefore, the concavoconvex portion 181 can be said to be a region in which fine convex portions are formed.

[0168] As described above, the moth-eye structure may be a region where, in the cross-sectional view of the SPAD pixel 20, the region may appear as a region where fine recesses are formed, a region where fine protrusions are formed, or a region where fine recesses and protrusions are formed, depending on where the reference plane is set.

[0169] In the following description, the concavoconvex portion 181 will be described with reference to the case where the reference surface A (ie, the upper surface 181 - 1 ) is used as a reference surface as an example, and the description will be continued assuming that the concavoconvex portion 181 is a region in which fine recesses are formed.

[0170] For example, the concave-convex portion 181 has a concave-concave pitch corresponding to the concave-concave period set to 250 nm or more.

[0171] exist Fig.10 In the example shown, the case where the concavoconvex portion 181 has a shape formed by combining the planes of the upper surface 181-1 and the lower surface 181-2 is shown as an example, but the concavoconvex portion 181 to which the present technology is applicable also includes a shape having Fig.11 Those concave and convex parts of the shape shown.

[0172] Fig.11 The concavoconvex part 181 shown is formed into a triangular shape in the cross-sectional view. Even with such a shape, a reference plane can be set, and the concave part or the convex part can be defined based on the reference plane.

[0173] because Fig.11 The illustrated concavoconvex portion 181 is formed in a triangular shape in a cross-sectional view, and therefore, as an example of a reference plane, a surface connecting vertices is set as a reference plane.

[0174] In the cross-sectional view, a plane including a line connecting the vertices on the transparent insulating film 164 side among the vertices of the triangle of the concavo-convex portion 181 is defined as a reference plane A. A plane including a line connecting the vertices on the base side (that is, the vertices on the N-type semiconductor region 151 side) among the vertices of the triangle of the concavo-convex portion 181 is defined as a reference plane C. A plane between the reference plane A and the reference plane C is defined as a reference plane B.

[0175] Therefore, even when the reference surface is set at the position of the vertex of the triangle of the concave-convex portion 181, Fig.10 Similar to the above-described case, the shape of the concavo-convex portion 181 may be expressed differently depending on where the reference surface is set.

[0176] That is, when the reference plane A is used as a reference, the shape of the concavoconvex part 181 is a shape having a triangular (valley-shaped) concave part facing downward relative to the reference plane A. That is, when the reference plane A is used as a reference, the inter-valley area is located below relative to the reference plane A, and the inter-valley area is equivalent to the concave part, and therefore, the concavoconvex part 181 is a region in which a fine concave part is formed. In other words, when the reference plane A is used as a reference, a concave part is formed between the vertex of a triangle and the vertex of an adjacent triangle, and therefore, the concavoconvex part 181 can be said to be a region in which a fine concave part is formed.

[0177] When the reference plane C is used as a reference, the shape of the concavoconvex part 181 is a shape having a triangular (peak-shaped) convex part facing upward relative to the reference plane C. That is, when the reference plane C is used as a reference, the peak region is located upward relative to the reference plane C, and the peak region is equivalent to the convex part, and therefore, the concavoconvex part 181 is a region in which a fine convex part is formed. In other words, when the reference plane C is used as a reference, a convex part is formed between the vertices of the base of the triangle, and therefore, the concavoconvex part 181 can be said to be a region in which a fine convex part is formed.

[0178] When the reference plane B is used as a reference, the shape of the concavoconvex portion 181 is a shape having concave portions and convex portions (valleys and peaks) relative to the reference plane B. That is, when the reference plane B is used as a reference, since there are concave portions forming valleys below relative to the reference plane B and there are convex portions forming peaks above relative to the reference plane B, the concavoconvex portion 181 can be said to be a region in which fine concave portions and convex portions are formed.

[0179] like Fig.11 As shown, even in the case where the shape of the concave-convex portion 181 is a sawtooth shape having peaks and valleys, the concave-convex portion 181 can be defined as a region where, in the cross-sectional view of the SPAD pixel 20, the region can appear as a region where fine concave portions are formed, a region where fine convex portions are formed, or a region where fine concave portions and convex portions are formed, depending on where the reference plane is set as described above.

[0180] In addition, for example, in Fig.10 or Fig.11 In the shown convex-concave portion 181, when the reference plane is set as the interface between the layer above the transparent insulating film 164 in the planarizing film 161 and the transparent insulating film 164, since the shape of the convex-concave portion 181 has a concave area (valley), the convex-concave portion 181 can be said to be an area where fine concave portions are formed.

[0181] Furthermore, when the reference plane is set as the interface between the P-type semiconductor region 153 and the N-type semiconductor region 151 , since the shape of the concavoconvex portion 181 has a protruding region (peak), the concavoconvex portion 181 can be said to be a region where fine convex portions are formed.

[0182] In this way, in the cross-sectional view of the SPAD pixel 20 , by setting a predetermined flat surface as a reference surface, and depending on whether it is formed in a valley shape or a peak shape with respect to the reference surface, the shape of the concavoconvex portion 181 can be expressed as described above.

[0183] Furthermore, the region between the SPAD pixels 20, that is, the region corresponding to the element separation portion 157 may be formed as a flat region in which the concavoconvex portion 181 is not formed. In this case, a plane including the flat region may also be set as the reference plane.

[0184] When a plane including a flat area is set as a reference plane, since the concavoconvex portion 181 can be said to have a shape having a portion sunken below the reference plane, that is, a shape having a valley-shaped portion, the concavoconvex portion 181 can be said to be a region in which fine recesses are formed.

[0185] As described above, the concave-convex portion 181 can be a region where, in the cross-sectional view of the SPAD pixel 20, the region can appear as a region where fine concave portions are formed, a region where fine convex portions are formed, or a region where fine concave portions and convex portions are formed, depending on where the reference plane is set.

[0186] In addition, depending on the method of forming the concavo-convex portion 181 , the concavo-convex portion 181 may be expressed as: forming a region formed of fine concave portions, forming a region formed of fine convex portions, or forming a region formed of fine concave portions and convex portions.

[0187] For example, in the formation Fig.10 In the case of the convex-concave portion 181 shown, if the convex-concave portion 181 is formed to have a shape in which the upper surface 181-1 is formed larger than the lower surface 181-2, it can be said that the portion that becomes the concave portion is formed by cutting the substrate (semiconductor substrate 150), or it can be said that the portion that becomes the convex portion is retained.

[0188] When the amount of substrate cutting exceeds 50%, the concave portion is formed to have a larger area than the convex portion, and the amount of substrate (silicon) cut away is greater than the amount of substrate remaining. That is, in this forming method, the concave portion and the convex portion are formed so that the concave portion dominates, and therefore, it can be expressed as forming the concave-convex portion 181 by providing a plurality of convex portions.

[0189] In addition, when the amount of substrate cutting is 50% or less, the area of ​​the concave portion is formed to be smaller than the area of ​​the convex portion, and the amount of substrate (silicon) cut away is less than the amount of substrate remaining. That is, in this formation method, the concave portion and the convex portion are formed so that the convex portion dominates, and therefore, it can be expressed that the concave-convex portion 181 is formed by providing a plurality of concave portions.

[0190] From these facts, it can be seen that, depending on the method of forming the concavo-convex portion 181, when the concave portion is dominant, it can appear that a plurality of convex portions are provided, and when the convex portion is dominant, it can appear that a plurality of concave portions are provided.

[0191] Thus, depending on the method of forming the convex-concave portion 181 as described above, the convex-concave portion 181 can be a region that, in the cross-sectional view of the SPAD pixel 20, can appear as a region where fine concave portions are formed, a region where fine convex portions are formed, or a region where fine concave portions and convex portions are formed.

[0192] In the following description, although it will be assumed that the concave-convex portion 181 is a region where fine concave portions are formed, as described above, the concave-convex portion 181 also includes a region that is expressed as a region where fine convex portions are formed or a region where fine concave portions and convex portions are formed.

[0193] 1.12 Function and Effect

[0194] According to the present embodiment, by providing the above configuration, it is possible to reduce the reflectivity of the back surface of the semiconductor substrate 150. Thus, the efficiency of light incident on the photoelectric conversion unit 21 can be improved, and as a result, the quantum efficiency of the photoelectric conversion unit 21 can be improved.

[0195] In addition, by combining the reflective film 158 and the moth-eye structure in the element separation unit 157, the reflective film 158 can be used to reflect the light scattered or diffracted by the moth-eye structure, thereby increasing its flight distance and, as a result, improving the quantum efficiency of the photoelectric conversion unit 21.

[0196] 1.13 Modification

[0197] In the first embodiment described above, the case where the concavoconvex portion 181 is provided on the entire effective light incident surface (region 180) on the back side of the semiconductor substrate 150 to form the moth-eye structure is shown. However, the region in which the concavoconvex portion 181 is formed is not limited to the entire effective light incident surface (region 180) on the back side of the semiconductor substrate 150. Therefore, modifications of the region 180 in which the concavoconvex portion 181 is formed will be described below with reference to some examples.

[0198] 1.13.1 First Modification

[0199] Fig.12 is a cross-sectional view showing an example of a cross-sectional configuration of a first chip according to a first modification example. Fig.13 It is shown Fig.12 The cross-sectional view of the cross-sectional structure of the BB surface in FIG. Figure 8 resemblance, Fig.12FIG. 2 shows an example of a cross-sectional configuration of the photoelectric conversion unit 21 in one SPAD pixel 20. However, in reality, Fig.13 As shown, in the first chip 51, there is Fig.12 The photoelectric conversion units 21 of the cross-sectional structure shown are arranged in a matrix. Fig.12 In the embodiment, the lower surface of the first chip 51 is the light incident surface.

[0200] like Fig.12 and Fig.13 As shown, the region 180B in which the concavo-convex portion 181 is formed may be a region on the back side of the semiconductor substrate 150 located at the central portion of the region divided by the element separation portion 157 (hereinafter, referred to as the pixel region), for example, a region located above the N+ type semiconductor region 155 and the P+ type semiconductor region 154. In other words, for example, at the periphery of the pixel region, for example, above the contact layer 156, there may be a region (flat portion) in which the concavo-convex portion 181 is not formed. In the present specification, “above” may be a direction in the substrate thickness direction of the semiconductor substrate 150 and from the back side of the semiconductor substrate 150 to the front side.

[0201] 1.13.2 Second Modification

[0202] Fig.14 is a cross-sectional view showing an example of a cross-sectional configuration of a first chip according to a second modification. Fig.15 It is shown Fig.14 The cross-sectional view of the cross-sectional structure of the CC surface in FIG. Figure 8 resemblance, Fig.14 FIG. 2 shows an example of a cross-sectional configuration of the photoelectric conversion unit 21 in one SPAD pixel 20. However, in reality, Fig.15 As shown, in the first chip 51, there is Fig.14 The photoelectric conversion units 21 of the cross-sectional structure shown are arranged in a matrix. Fig.14 In the embodiment, the lower surface of the first chip 51 is the light incident surface.

[0203] like Fig.14 and Fig.15 As shown, the region 180C in which the concavo-convex portion 181 is formed may be a peripheral portion in the pixel region, for example, a region located above the contact layer 156. In other words, in the center of the pixel region, for example, above the N+ type semiconductor region 155 and the P+ type semiconductor region 154, there may be a region (flat portion) in which the concavo-convex portion 181 is not formed.

[0204] 1.13.3 Third variant

[0205] Fig.16 is a cross-sectional view showing an example of a cross-sectional configuration of a first chip according to a third modification example. Fig.16 For example, Figure 8 The cross-sectional configuration example of the first chip 51 shown is a cross-sectional configuration example of a plane corresponding to the AA plane.

[0206] like Fig.16 As shown, the region 180D in which the concavoconvex portion 181 is formed may be a cross-shaped region that divides the pixel region into a 2×2 matrix. In other words, at the four corners of the pixel region, there may be regions in which the concavoconvex portion 181 is not formed.

[0207] 1.13.4 Fourth variant

[0208] Fig.17 1 is a cross-sectional view showing an example of a cross-sectional configuration of a first chip according to a fourth modification. Fig.16 resemblance, Fig.17 For example, Figure 8 The cross-sectional configuration example of the first chip 51 shown is a cross-sectional configuration example of a plane corresponding to the AA plane.

[0209] like Fig.17 As shown, the region 180E in which the concavoconvex portion 181 is formed may be the four corners of the pixel region. In other words, in the cross-shaped region that divides the pixel region into a 2×2 matrix, there may be a region in which the concavoconvex portion 181 is not formed.

[0210] 1.13.5 Fifth variant

[0211] Fig.18 1 is a cross-sectional view showing an example of a cross-sectional configuration of a first chip according to a fifth modification. Fig.16 or Fig.17 resemblance, Fig.18 For example, Figure 8 The cross-sectional configuration example of the first chip 51 shown is a cross-sectional configuration example of a plane corresponding to the AA plane.

[0212] like Fig.18 As shown, the region 180F in which the concavo-convex portion 181 is formed may be a cross-shaped region located at the center of the pixel region, for example, located above the N+ type semiconductor region 155 and the P+ type semiconductor region 154 .

[0213] As in the first to fifth modifications described above, the concavoconvex portion 181 according to the first embodiment does not need to be formed in the entire pixel region as long as it is formed in at least a portion of the pixel region. The above-described first embodiment and its modifications are merely examples, and various modifications are possible.

[0214] 2. Second Implementation Method

[0215] Next, the second embodiment will be described in detail below with reference to the drawings.

[0216] In the first embodiment and its modified example, the region for photoelectric conversion, that is, the case where the N-type semiconductor region 151 is a rectangular parallelepiped is shown. However, for example, since the distance from the P+ type semiconductor region 154 is long near the back side of the semiconductor substrate 150, especially near the element separation portion 157 in the pixel region, the time taken until the charge generated in the region is captured by the P+ type semiconductor region 154 becomes long. Therefore, there is a possibility that time jitter occurs due to the difference in the time taken until the charge generated on the front side of the semiconductor substrate 150 or near the P+ type semiconductor region 154 is captured by the P+ type semiconductor region 154, and there is a possibility that the distance measurement accuracy is reduced.

[0217] Therefore, in this embodiment, a solid-state imaging device and a distance measuring device capable of reducing time jitter and thus limiting the reduction in distance measurement accuracy will be described with reference to an example. In the following description, the same components as those in the above-mentioned embodiment or its modified example will be represented by the same reference numerals, and their detailed description will be omitted.

[0218] The basic configuration and operation of the solid-state imaging device and the distance measuring device according to this embodiment can be the same as the configuration and operation in the above-mentioned embodiment or its modified example. However, in this embodiment, the cross-sectional configuration of the photoelectric conversion unit 21 formed on the first chip 51 is replaced by the cross-sectional configuration example described later.

[0219] 2.1 Example of cross-section construction

[0220] Fig.19 is a cross-sectional view showing an example of a cross-sectional configuration of a first chip according to the second embodiment. Fig. 20 It is shown Fig.19 Cross-sectional view of the cross-sectional structure of the GG plane. Fig.19 FIG. 2 shows an example of a cross-sectional configuration of the photoelectric conversion unit 21 in one SPAD pixel 20. However, in reality, Fig. 20 As shown, in the first chip 51, there is Fig.19 The photoelectric conversion units 21 of the cross-sectional structure shown are arranged in a matrix. Fig.19 In the embodiment, the lower surface of the first chip 51 is the light incident surface.

[0221] like Fig.19 and Fig. 20 As shown, the first chip 51 according to the present embodiment has the following structure (hereinafter referred to as "elevated portion"): that is, in the first modification example of the first embodiment, the first chip 51 is Fig.12 and Fig.13In the cross-sectional structure identical to the cross-sectional structure of the first chip 51 described, a groove 202G is provided in the periphery of the pixel area on the back side of the semiconductor substrate 150 (for example, the area 280G located above the contact layer 156), so that the light incident surface 203G of this part (i.e., the bottom surface of the groove 202G) is close to the P+ type semiconductor region 154.

[0222] A step is provided in a portion corresponding to the region 280G in the N-type semiconductor region 151 and the P-type semiconductor region 153 to ensure an area for arranging the trench 202G.

[0223] For example, a light-transmitting film 201G for guiding light incident through the planarization film 161 to the photoelectric conversion unit 21 may be provided inside the groove 202G. For example, a material that transmits visible light or infrared light, such as a silicon oxide film or a silicon nitride film, may be used as the light-transmitting film 201G.

[0224] At the bottom surface (light incident surface 203G) of the groove 202G, similar to the center of the pixel area on the back side of the semiconductor substrate 150 (for example, the area 180B located above the N+ type semiconductor region 155 and the P+ type semiconductor region 154), a plurality of regularly or randomly arranged concave-convex portions 181 may be provided.

[0225] 2.2 Function and Effect

[0226] According to this embodiment, by providing the above-mentioned structure, the difference in the movement distance of the charge generated by photoelectric conversion can be reduced, thereby reducing the time jitter caused by the difference in the time taken until the charge is captured into the P+ type semiconductor region 154, and thereby suppressing the reduction in distance measurement accuracy.

[0227] Other configurations, operations, and effects may be the same as those of the above-described embodiment or its modified examples, so their detailed descriptions will be omitted here.

[0228] 2.3 Variations

[0229] In the second embodiment described above, the peripheral portion of the pixel region on the back side of the semiconductor region 150 (for example, the region above the contact layer 156) is raised, and the concavo-convex portion 181 is provided in each of the raised region 280G and the center of the pixel region (for example, the region 180B above the N+ type semiconductor region 155 and the P+ type semiconductor region 154). However, the raised region and the region in which the concavo-convex portion 181 is formed are not limited thereto. Therefore, modified examples of the region in which the grooves are formed and the region in which the concavo-convex portion is formed will be described below with reference to some examples.

[0230] 2.3.1 First Modification

[0231] Fig.21 is a cross-sectional view showing an example of a cross-sectional configuration of a first chip according to a first modification example. Fig. 22 It is shown Fig.21 The cross-sectional view of the cross-sectional structure of the HH plane in FIG. Figure 8 resemblance, Fig.21 FIG. 2 shows an example of a cross-sectional configuration of the photoelectric conversion unit 21 in one SPAD pixel 20. However, in reality, Fig. 22 As shown, in the first chip 51, there is Fig.21 The photoelectric conversion units 21 of the cross-sectional structure shown are arranged in a matrix. Fig.21 In the embodiment, the lower surface of the first chip 51 is the light incident surface.

[0232] like Fig.21 and Fig. 22 As shown, the first chip 51 according to the present embodiment has the following structure (hereinafter referred to as "elevated portion"): that is, in contrast to the reference chip 51 in the second modification of the first embodiment, Fig.14 and Fig.15 In the cross-sectional structure identical to the cross-sectional structure of the first chip 51 described, a groove 202H is provided in the center of the pixel area on the back side of the semiconductor substrate 150 (for example, an area 280H located above the N+ type semiconductor region 155 and the P+ type semiconductor region 154), so that the light incident surface 203H of this part (i.e., the bottom surface of the groove 202H) is close to the P+ type semiconductor region 154.

[0233] A recessed portion is provided in a portion corresponding to the region 280H in the N-type semiconductor region 151 and the P-type semiconductor region 153 to ensure an area for arranging the trench 202H.

[0234] For example, a light-transmitting film 201H for guiding light incident through the planarization film 161 to the photoelectric conversion unit 21 may be provided inside the groove 202H, similar to the first modification. For example, a material that allows visible light or infrared light to pass therethrough, such as a silicon oxide film or a silicon nitride film, may be used as the light-transmitting film 201H.

[0235] On the bottom surface (light incident surface 203H) of the groove 202H, similar to the periphery of the pixel area on the back side of the semiconductor substrate 150 (for example, the area 180C located above the contact layer 156), a plurality of regularly or randomly arranged concave-convex portions 181 may be provided.

[0236] 2.3.2 Second Modification

[0237] Fig.23is a cross-sectional view showing an example of a cross-sectional configuration of a first chip according to a second modification. Fig.24 It is shown Fig.23 The cross-sectional view of the cross-sectional structure of the JJ plane in FIG. Figure 8 resemblance, Fig.23 FIG. 2 shows an example of a cross-sectional configuration of the photoelectric conversion unit 21 in one SPAD pixel 20. However, in reality, Fig.24 As shown, in the first chip 51, there is Fig.23 The photoelectric conversion units 21 of the cross-sectional structure shown are arranged in a matrix. Fig.23 In the embodiment, the lower surface of the first chip 51 is the light incident surface.

[0238] In the first modification example described above, a case where a plurality of regularly or randomly arranged concave-convex portions 181 are provided in both the periphery of the pixel region on the back side of the semiconductor substrate 150 (e.g., the region 180C located above the contact layer 156) and the center of the pixel region (e.g., the region 280H located above the N+ type semiconductor region 155 and the P+ type semiconductor region 154) is shown. However, the present invention is not limited to this configuration, and, for example, Fig.23 and Fig.24 As shown in FIG. 1 , a configuration may be provided in which the concavo-convex portion 181 is not formed in one of the region 180C and the region 280H. Fig.23 and Fig.24 2 shows a case where the concavo-convex portion 181 of the region 180C has been omitted.

[0239] 2.3.3 Third Modification

[0240] Fig.25 is a cross-sectional view showing an example of a cross-sectional configuration of a first chip according to a third modification example. Fig.25 For example, Fig.19 The cross-sectional configuration example of the first chip 51 shown is a cross-sectional configuration example of a plane corresponding to the GG plane.

[0241] like Fig.25 As shown, the elevated region 280K may be a cross-shaped region that divides the pixel region into a 2×2 matrix. The concavoconvex portion 181 may be formed in the elevated region 280K, or may be formed in a non-elevated region (a region other than the region 280K in each pixel region), or may be formed in all of these regions.

[0242] 2.3.4 Fourth Modification

[0243] Fig.26 1 is a cross-sectional view showing an example of a cross-sectional configuration of a first chip according to a fourth modification. Fig.25 Similarly, Fig.26 For example, Fig.19 The cross-sectional configuration example of the first chip 51 shown is a cross-sectional configuration example of a plane corresponding to the GG plane.

[0244] like Fig.26 The concavoconvex portion 181 may be formed in each of the four elevated regions 280L, or may be formed in a non-elevated region (a region other than the region 280L in each pixel region), or may be formed in all of these regions.

[0245] 2.3.5 Fifth Modification

[0246] Fig. 27 1 is a cross-sectional view showing an example of a cross-sectional configuration of a first chip according to a fifth modification. Fig.25 or Fig.26 Similarly, Fig. 27 For example, Fig.19 The cross-sectional configuration example of the first chip 51 shown is a cross-sectional configuration example of a plane corresponding to the GG plane.

[0247] like Fig. 27 As shown, the elevated region 280M may be the center of the pixel region, for example, a cross-shaped region located above the N+ type semiconductor region 155 and the P+ type semiconductor region 154. The concavoconvex portion 181 may be formed in the elevated region 280M, or may be formed in a non-elevated region (a region other than the region 280M in each pixel region), or may be formed in all of these regions.

[0248] As in the first to fifth modifications described above, the raised region is not limited to the periphery of the pixel region (eg, near the region above the contact layer 156), and various modifications are possible. The second embodiment described above and its modifications are merely examples, and various modifications are possible.

[0249] 3. Application examples

[0250] The technology according to the present invention can be applied to various products. For example, the technology according to the present invention can be implemented as a device installed on any type of mobile body, such as a car, an electric car, a hybrid car, a motorcycle, a bicycle, a personal mobile vehicle, an airplane, a drone, a ship, a construction machine or an agricultural machine (tractor), etc.

[0251] Fig.28 7000 is a block diagram showing a schematic configuration example of a vehicle control system 7000 as an example of a mobile body control system to which the technology according to the present invention can be applied. The vehicle control system 7000 includes a plurality of electronic control units connected to each other via a communication network 7010. Fig.28In the example shown, the vehicle control system 7000 includes a drive system control unit 7100, a body system control unit 7200, a battery control unit 7300, an external information detection unit 7400, an internal information detection unit 7500, and an integrated control unit 7600. The communication network 7010 that connects these control units to each other may be an in-vehicle communication network that conforms to any standard such as a controller area network (CAN), a local interconnect network (LIN), a local area network (LAN), or FlexRay (registered trademark).

[0252] Each control unit includes: a microcomputer that performs calculations according to various programs; a storage unit that stores programs run by the microcomputer or parameters for various calculations; and a drive circuit that drives various devices that are controlled. Each control unit also includes: a network interface for communicating with other control units via the communication network 7010; and a communication interface for communicating with devices or sensors inside and outside the vehicle through wired or wireless communication. Fig.28 76, as the functional configuration of the integrated control unit 7600, a microcomputer 7610, a general communication interface 7620, a dedicated communication interface 7630, a positioning unit 7640, a beacon receiving unit 7650, an in-vehicle device interface 7660, a sound / image output unit 7670, an in-vehicle network interface 7680, and a storage unit 7690 are shown. Other control units also include a microcomputer, a communication interface, a storage unit, and the like.

[0253] The drive system control unit 7100 controls the operation of the devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 7100 functions as a control device for the following devices: a drive force generating device such as an internal combustion engine or a drive motor for generating the drive force of the vehicle; a drive force transmitting mechanism for transmitting the drive force to the wheels; a steering mechanism for adjusting the steering angle of the vehicle; and a braking device for generating the braking force of the vehicle, etc. The drive system control unit 7100 can function as a control device for an antilock brake system (ABS), an electronic stability control system (ESC), etc.

[0254] The vehicle condition detector 7110 is connected to the drive system control unit 7100. For example, the vehicle condition detector 7110 may include at least one of the following: a gyro sensor for detecting the angular velocity of the shaft rotational motion of the vehicle body; an acceleration sensor for detecting the acceleration of the vehicle; and a sensor for detecting the operation amount of the accelerator pedal, the operation amount of the brake pedal, the steering angle of the steering wheel, the engine speed or the wheel speed, etc. The drive system control unit 7100 performs arithmetic processing using the signal input from the vehicle condition detector 7110 to control the internal combustion engine, the drive motor, the electric power steering device or the brake device, etc.

[0255] The body system control unit 7200 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 7200 functions as a control device for the following devices: a keyless entry system; a smart key system; a power window device; or various lights such as headlights, taillights, brake lights, turn signals, or fog lights. In this case, radio waves sent from a portable device that replaces the key or signals of various switches may be input to the body system control unit 7200. The body system control unit 7200 receives input of these radio waves or signals and controls the door lock device, power window device, and lights of the vehicle.

[0256] The battery control unit 7300 controls the secondary battery 7310 as a power source for driving the motor according to various programs. For example, information such as battery temperature, battery output voltage, or remaining battery power is input to the battery control unit 7300 from a battery device including the secondary battery 7310. The battery control unit 7300 performs arithmetic processing using these signals, and performs temperature adjustment control of the secondary battery 7310 or control of a cooling device or the like mounted in the battery device.

[0257] The vehicle exterior information detection unit 7400 detects information of the exterior of the vehicle in which the vehicle control system 7000 is installed. For example, at least one of the camera unit 7410 and the vehicle exterior information detector 7420 is connected to the vehicle exterior information detection unit 7400. The camera unit 7410 includes at least one of a time of flight (ToF) camera, a stereo camera, a monocular camera, an infrared camera, and other cameras. For example, the vehicle exterior information detector 7420 includes at least one of the following: an environmental sensor for detecting current weather or meteorology; and an environmental information detection sensor for detecting other vehicles, obstacles, pedestrians, etc. around the vehicle in which the vehicle control system 7000 is installed.

[0258] For example, the environmental sensor may be at least one of a raindrop sensor for detecting rainy days, a fog sensor for detecting fog, a sunshine sensor for detecting the degree of sunshine, and a snow sensor for detecting snowfall. The environmental information detection sensor may be at least one of an ultrasonic sensor, a radar device, and a LIDAR (e.g., light detection and ranging and laser imaging detection and ranging) device. The camera unit 7410 and the vehicle exterior information detector 7420 may be configured as independent sensors or devices, or may be configured as a device in which a plurality of sensors or devices are integrated.

[0259] here, Fig.29 An example of the installation position of the camera unit 7410 and the vehicle exterior information detector 7420 is shown. For example, the camera units 7910, 7912, 7914, 7916, and 7918 are arranged at the positions of the front nose, side mirrors, rear bumper, tailgate, and the upper part of the windshield in the vehicle compartment of the vehicle 7900. The camera unit 7910 arranged at the front nose and the camera unit 7918 arranged at the upper part of the windshield in the vehicle compartment mainly acquire images in front of the vehicle 7900. The camera units 7912 and 7914 arranged at the side mirrors mainly acquire images on the side of the vehicle 7900. The camera unit 7916 arranged at the rear bumper or tailgate mainly acquires images behind the vehicle 7900. The camera unit 7918 arranged at the upper part of the windshield in the vehicle compartment is mainly used to detect the front vehicle, pedestrians, obstacles, traffic lights, traffic signs, lane lines, etc.

[0260] Fig.29 Also shown are examples of imaging ranges of the imaging units 7910, 7912, 7914, and 7916. Imaging range a represents the imaging range of the imaging unit 7910 disposed at the front nose, imaging ranges b and c represent the imaging ranges of the imaging units 7912 and 7914 disposed at the side mirrors, respectively, and imaging range d represents the imaging range of the imaging unit 7916 disposed at the rear bumper or tailgate. For example, by superimposing the image data captured by the imaging units 7910, 7912, 7914, and 7916, an overhead image of the vehicle 7900 seen from above can be obtained.

[0261] For example, the vehicle exterior information detectors 7920, 7922, 7924, 7926, 7928, and 7930 disposed at the front, rear, side, corner, and upper portion of the windshield in the vehicle compartment of the vehicle 7900 may be ultrasonic sensors or radar devices, respectively. For example, the vehicle exterior information detectors 7920, 7926, and 7930 disposed at the front nose, rear bumper, tailgate, and upper portion of the windshield in the vehicle compartment of the vehicle 7900 may be LIDAR devices, respectively. These vehicle exterior information detectors 7920 to 7930 are mainly used to detect vehicles ahead, pedestrians, or obstacles, etc.

[0262] return Fig.28 The description continues. The vehicle exterior information detection unit 7400 enables the camera unit 7410 to capture images of the exterior of the vehicle and receive the captured image data. The vehicle exterior information detection unit 7400 also receives detection information from the connected vehicle exterior information detector 7420. When the vehicle exterior information detector 7420 is an ultrasonic sensor, a radar device, or a LIDAR device, respectively, the vehicle exterior information detection unit 7400 sends ultrasonic waves, or electromagnetic waves, etc., and receives information of the received reflected waves. The vehicle exterior information detection unit 7400 can perform object detection processing or distance detection processing on pedestrians, vehicles, obstacles, signs, or text on the road surface based on the received information. The vehicle exterior information detection unit 7400 can perform environmental recognition processing for identifying rainfall, fogging, or road surface conditions based on the received information. The vehicle exterior information detection unit 7400 can calculate the distance to objects outside the vehicle based on the received information.

[0263] In addition, the vehicle exterior information detection unit 7400 can perform image recognition processing or distance detection processing for identifying pedestrians, vehicles, obstacles, signs, or text on the road surface based on the received image data. The vehicle exterior information detection unit 7400 can perform processing such as distortion correction or position alignment on the received image data, and can synthesize image data captured by different camera units 7410 to generate a bird's-eye view image or a panoramic image. The vehicle exterior information detection unit 7400 can use the image data captured by different camera units 7410 to perform viewpoint conversion processing.

[0264] The in-vehicle information detection unit 7500 detects in-vehicle information. For example, a driver state detector 7510 for detecting the state of the driver is connected to the in-vehicle information detection unit 7500. The driver state detector 7510 may include a camera for photographing the driver, a biosensor for detecting the driver's biological information, or a microphone for collecting sounds in the vehicle compartment. For example, the biosensor is set on a seat surface or a steering wheel, etc., and detects the biological information of a passenger sitting on the seat or a driver holding the steering wheel. The in-vehicle information detection unit 7500 can calculate the driver's fatigue or concentration based on the detection information input from the driver state detector 7510, and can determine whether the driver is dozing off. The in-vehicle information detection unit 7500 can perform processing such as noise removal processing on the collected audio signal.

[0265] The integrated control unit 7600 controls the overall operation within the vehicle control system 7000 according to various programs. The input unit 7800 is connected to the integrated control unit 7600. For example, the input unit 7800 is implemented by a device such as a touch panel, a button, a microphone, a switch, or a joystick on which a passenger can perform input operations. Data obtained by performing voice recognition on audio input via a microphone can be input to the integrated control unit 7600. For example, the input unit 7800 can be a remote control device using infrared or other radio waves, or can be an external device such as a mobile phone or a personal digital assistant (PDA: Personal Digital Assistant) that supports operations on the vehicle control system 7000. For example, the input unit 7800 can be a camera, in which case the passenger can input information through gestures. Alternatively, data obtained by detecting the action of a wearable device worn by the passenger can be input. In addition, for example, the input unit 7800 may include an input control circuit that generates an input signal based on information input by a passenger or the like using the input unit 7800, and outputs the input signal to the integrated control unit 7600. By operating the input unit 7800, a passenger or the like can input various data to the vehicle control system 7000, and can instruct the vehicle control system 7000 to perform a processing operation.

[0266] The storage unit 7690 may include a read only memory (ROM) for storing various programs executed by the microcomputer and a random access memory (RAM) for storing various parameters, operation results, sensing values, etc. The storage unit 7690 may be implemented by a magnetic storage device such as a hard disk drive (HDD), a semiconductor storage device, an optical storage device, a magneto-optical storage device, etc.

[0267] The universal communication interface 7620 is a universal communication interface for coordinating communication with various devices present in the external environment 7750. The universal communication interface 7620 may implement cellular communication protocols such as GSM (global system of mobile communications, registered trademark), WiMAX (registered trademark), LTE (long term evolution, registered trademark) or LTE-A (LTE-Advanced) or other wireless communication protocols such as wireless LAN (also known as Wi-Fi (registered trademark)) or Bluetooth (registered trademark). For example, the universal communication interface 7620 may be connected to a device (e.g., an application server or a control server) present on an external network (e.g., the Internet, a cloud network, or an operator's inherent network) via a base station or an access point. For example, the universal communication interface 7620 may also be connected to a terminal (e.g., a driver, a pedestrian, or a store terminal or a machine type communication (MTC: Machine Type Communication) terminal) present near the vehicle using a point-to-point (P2P: peer to peer) technology.

[0268] The dedicated communication interface 7630 is a communication interface that supports a communication protocol developed for use on a vehicle. For example, the dedicated communication interface 7630 may implement standard protocols such as WAVE (wireless access in vehicle environment), which is a combination of the lower layer IEEE802.11p and the upper layer IEEE1609, DSRC (dedicated short range communications), or a cellular communication protocol. The dedicated communication interface 7630 typically performs V2X communication, which is a concept that includes one or more of vehicle-to-vehicle communication, vehicle-to-infrastructure communication, vehicle-to-home communication, and vehicle-to-pedestrian communication.

[0269] For example, the positioning unit 7640 receives a GNSS signal from a GNSS (global navigation satellite system) satellite (e.g., a GPS signal from a GPS (global positioning system) satellite) and performs positioning to generate position information including the latitude, longitude, and altitude of the vehicle. The positioning unit 7640 may identify the current position by exchanging signals with a wireless access point, or may acquire position information from a terminal having a positioning function such as a mobile phone, a PHS (personal handy-phone system), or a smart phone.

[0270] For example, the beacon receiving unit 7650 receives radio waves or electromagnetic waves transmitted from a radio station installed on the road, etc., and acquires information such as the current position, traffic congestion, road closure, or required time. The function of the beacon receiving unit 7650 may be included in the above-mentioned dedicated communication interface 7630.

[0271] The vehicle-mounted device interface 7660 is a communication interface for coordinating the connection between the microcomputer 7610 and various vehicle-mounted devices 7760 present in the vehicle. The vehicle-mounted device interface 7660 can use wireless communication protocols such as wireless LAN, Bluetooth (registered trademark), NFC (near field communication) or WUSB (wireless USB) to establish a wireless connection. The vehicle-mounted device interface 7660 can also establish a wired connection such as USB (universal serial bus), HDMI (high-definition multimedia interface) (registered trademark) or MHL (mobile high-definition link) via a connection terminal (and a cable if necessary) (not shown). For example, the vehicle-mounted device 7760 may include at least one of a mobile device or wearable device owned by a passenger or an information device moved into or installed in a vehicle. The vehicle-mounted device 7760 may also include a navigation device capable of searching for a route to any destination. The vehicle-mounted device interface 7660 exchanges control signals or data signals with these vehicle-mounted devices 7760.

[0272] The in-vehicle network interface 7680 is an interface for coordinating communication between the microcomputer 7610 and the communication network 7010. The in-vehicle network interface 7680 follows a predetermined protocol supported by the communication network 7010 to transmit and receive signals and the like.

[0273] The microcomputer 7610 of the integrated control unit 7600 controls the vehicle control system 7000 according to various programs based on information acquired via at least one of the general communication interface 7620, the dedicated communication interface 7630, the positioning unit 7640, the beacon receiving unit 7650, the vehicle device interface 7660, and the vehicle network interface 7680. For example, the microcomputer 7610 can calculate the control target value of the driving force generating device, the steering mechanism, or the braking device based on the acquired information inside and outside the vehicle, and output the control command to the driving system control unit 7100. For example, the microcomputer 7610 can perform coordinated control to realize the functions of an advanced driver assistance system (ADAS: advanced driver assistance system) including collision avoidance or collision mitigation of the vehicle, following driving based on the distance between vehicles, vehicle speed control, vehicle collision warning, or vehicle lane departure warning. Microcomputer 7610 can also coordinate control by controlling the driving force generating device, steering mechanism, or braking device based on the information obtained about the vehicle's surroundings, so as to achieve automatic driving, etc., in which the vehicle can travel autonomously without relying on the driver's operation.

[0274] The microcomputer 7610 can generate three-dimensional distance information between the vehicle and objects such as buildings or pedestrians around the vehicle based on information obtained via at least one of the general communication interface 7620, the dedicated communication interface 7630, the positioning unit 7640, the beacon receiving unit 7650, the vehicle-mounted device interface 7660, and the vehicle-mounted network interface 7680, and create regional map information including surrounding information about the current position of the vehicle. The microcomputer 7610 can also predict dangers such as vehicle collision, pedestrians approaching the vehicle, or about to enter a closed road based on the information obtained, and generate a warning signal. For example, the warning signal can be a signal for generating a warning sound or lighting a warning light.

[0275] The sound / image output unit 7670 transmits an output signal as at least one of sound and image to an output device capable of visually or auditorily notifying information to a vehicle passenger or the outside of the vehicle. Fig.28In the example of , as output devices, an audio speaker 7710, a display unit 7720, and a dashboard 7730 are shown. For example, the display unit 7720 may include at least one of an onboard display and a heads-up display. The display unit 7720 may have an augmented reality (AR: Augmented Reality) display function. The output device may be other devices such as headphones, wearable devices such as glasses-type displays worn by passengers, projectors, or lights in addition to these devices. When the output device is a display device, the display device visually displays the results obtained by the microcomputer 7610 performing various processes or information received from other control units in various forms such as text, images, tables, or graphs. When the output device is an audio output device, the audio output device converts an audio signal containing the played audio data or sound data into an analog signal and outputs the analog signal audibly.

[0276] exist Fig.28 In the example shown, at least two control units interconnected via the communication network 7010 can be integrated into one control unit. Alternatively, each control unit can be composed of multiple control units. In addition, the vehicle control system 7000 may include other different control units (not shown). In the above description, part or all of the functions responsible for any control unit may be included in another control unit. That is, the predetermined operation processing can be performed by any control unit, as long as the information is sent and received via the communication network 7010. Similarly, a sensor or device connected to any control unit can be connected to another control unit, and multiple control units can send and receive detection information to each other via the communication network 7010.

[0277] To achieve the reference Figure 1 The computer program of each function of the ToF sensor 1 of the present embodiment described can be installed in any control unit, etc. A computer-readable recording medium in which such a computer program is stored can be provided. For example, the recording medium is a magnetic disk, an optical disk, a magneto-optical disk, or a flash memory. For example, the computer program can be distributed via a network without using a recording medium.

[0278] In the above vehicle control system 7000, according to the reference Figure 1 The ToF sensor 1 of the present embodiment described above can be applied to Fig.28The integrated control unit 7600 in the exemplary application shown. For example, the controller 11, the operation unit 15, and the external interface 19 of the ToF sensor 1 are equivalent to the microcomputer 7610, the storage unit 7690, and the vehicle network interface 7680 of the integrated control unit 7600. However, the present invention is not limited thereto, and the vehicle control system 7000 may be equivalent to Figure 1 Host 80 in.

[0279] In addition, according to the reference Figure 1 At least a part of the components of the ToF sensor 1 of the present embodiment described above may be Fig.28 7600 (e.g., an integrated circuit module made of one wafer). Figure 1 The ToF sensor 1 of the present embodiment described above can be composed of Fig.28 The vehicle control system 7000 shown is implemented by multiple control units.

[0280] Although the embodiments of the present invention have been described above, the technical scope of the present invention is not limited to the above embodiments, and various modifications can be made without departing from the gist of the present invention. The constituent elements in different embodiments and modifications can also be appropriately combined.

[0281] Furthermore, the effects in the respective embodiments described in this specification are merely examples and are not restrictive, and other effects may also be achieved.

[0282] This technology can also adopt the following technical solutions.

[0283] (1) An avalanche photodiode sensor, comprising:

[0284] a first semiconductor substrate; and

[0285] a second semiconductor substrate bonded to the first surface of the first semiconductor substrate,

[0286] Wherein, the first semiconductor substrate comprises:

[0287] a plurality of photoelectric conversion sections arranged in a matrix; and

[0288] an element separation unit for separating the plurality of photoelectric conversion units from each other;

[0289] The plurality of photoelectric conversion units include a first photoelectric conversion unit,

[0290] The element isolation portion includes a first element isolation region and a second element isolation region,

[0291] The first photoelectric conversion unit is arranged between the first element isolation region and the second element isolation region,

[0292] The first semiconductor substrate further includes a plurality of concave-convex portions, the plurality of concave-convex portions being arranged on a second surface opposite to the first surface and arranged between the first element isolation region and the second element isolation region, and

[0293] The second semiconductor substrate includes a readout circuit connected to each of the plurality of photoelectric conversion portions.

[0294] (2) An avalanche photodiode sensor according to (1), wherein the first photoelectric conversion unit includes: a cathode region disposed on the first surface of the first semiconductor substrate and having a first conductivity type; and an anode region disposed on the first surface of the first semiconductor substrate and having a second conductivity type opposite to the first conductivity type.

[0295] (3) The avalanche photodiode sensor according to (2), wherein the plurality of concavo-convex portions are arranged at least in a region corresponding to the cathode region or the anode region in a substrate thickness direction of the first semiconductor substrate.

[0296] (4) The avalanche photodiode sensor according to any one of (1) to (3), wherein the first photoelectric conversion unit is an avalanche photodiode.

[0297] (5) The avalanche photodiode sensor according to any one of (1) to (4), wherein each of the first element isolation region and the second element isolation region includes a reflective film or a high refractive index film.

[0298] (6) The avalanche photodiode sensor according to any one of (1) to (5), wherein each of the first element isolation region and the second element isolation region penetrates the first semiconductor substrate from the first surface to the second surface.

[0299] (7) The avalanche photodiode sensor according to any one of (1) to (6), wherein the plurality of concavo-convex portions are arranged in an entire region partitioned by the first element isolation region and the second element isolation region on the second surface.

[0300] (8) The avalanche photodiode sensor according to (2), wherein the plurality of concavo-convex portions are arranged in a region on the second face corresponding to the cathode region in a substrate thickness direction of the first semiconductor substrate.

[0301] (9) The avalanche photodiode sensor according to (2), wherein the plurality of concavo-convex portions are arranged in a region on the second face corresponding to the anode region in a substrate thickness direction of the first semiconductor substrate.

[0302] (10) The avalanche photodiode sensor according to (2), wherein the element separation portion further includes a third element separation region and a fourth element separation region, the third element separation region and the fourth element separation region dividing the first photoelectric conversion portion in a direction different from the first element separation region and the second element separation region, and

[0303] The plurality of concavo-convex portions are arranged in a cross-shaped region on the second surface that divides a rectangular region divided from the first element isolation region to the fourth element isolation region into four parts.

[0304] (11) The avalanche photodiode sensor according to (2), wherein the element separation portion further includes a third element separation region and a fourth element separation region, the third element separation region and the fourth element separation region dividing the first photoelectric conversion portion in a direction different from the first element separation region and the second element separation region, and

[0305] The plurality of concavo-convex portions are arranged at each of four corners of a rectangular region partitioned by the first to fourth element isolation regions on the second surface.

[0306] (12) The avalanche photodiode sensor according to (2), wherein the plurality of concavoconvex portions are arranged in a cross-shaped region on the second face corresponding to the cathode region in a substrate thickness direction of the first semiconductor substrate.

[0307] (13) An avalanche photodiode sensor according to any one of (1) to (12), wherein a groove is provided in at least a portion of a region partitioned by the first element isolation region and the second element isolation region on the second surface of the first semiconductor substrate.

[0308] (14) The avalanche photodiode sensor according to (13), wherein the plurality of concavo-convex portions are provided on a bottom surface of the groove.

[0309] (15) The avalanche photodiode sensor according to (13), wherein the first semiconductor substrate further includes a plurality of concavo-convex portions provided on a bottom surface of the trench.

[0310] (16) The avalanche photodiode sensor according to any one of (13) to (15), wherein the first semiconductor substrate further includes a light-transmitting film provided inside the groove.

[0311] (17) A distance measuring device comprising:

[0312] a light emitting portion configured to emit light of a predetermined wavelength;

[0313] an avalanche photodiode sensor configured to generate a pixel signal based on received light; and

[0314] an operation unit configured to calculate a distance to an object based on the pixel signal generated by the avalanche photodiode sensor,

[0315] Wherein, the avalanche photodiode sensor comprises:

[0316] a first semiconductor substrate; and

[0317] A second semiconductor substrate is bonded to the first surface of the first semiconductor substrate, wherein the first semiconductor substrate comprises:

[0318] a plurality of photoelectric conversion sections arranged in a matrix; and

[0319] an element separation unit for separating the plurality of photoelectric conversion units from each other;

[0320] The plurality of photoelectric conversion units include a first photoelectric conversion unit,

[0321] The element isolation portion includes a first element isolation region and a second element isolation region,

[0322] The first photoelectric conversion unit is arranged between the first element isolation region and the second element isolation region,

[0323] The first semiconductor substrate further includes a plurality of concave-convex portions, the plurality of concave-convex portions being arranged on a second surface opposite to the first surface and arranged between the first element isolation region and the second element isolation region, and

[0324] The second semiconductor substrate includes a readout circuit connected to each of the plurality of photoelectric conversion portions.

[0325] [Explanation of Reference Numerals]

[0326] 1: ToF sensor

[0327] 11: Controller

[0328] 13: Light emitting unit

[0329] 14: Light receiving unit

[0330] 15: Arithmetic unit

[0331] 19: External interface

[0332] 20: SPAD pixels

[0333] 21: Photoelectric conversion unit

[0334] 22: Readout circuit

[0335] 23: Quench resistor

[0336] 24: Select transistor

[0337] 25: Digital Converter

[0338] 251: Resistor

[0339] 252: NMOS transistor

[0340] 26: Inverter

[0341] 261: PMOS transistor

[0342] 262: NMOS transistor

[0343] 27: Buffer

[0344] 30: macro-pixel

[0345] 40: SPAD addition unit

[0346] 41: Pulse shaping unit

[0347] 42: Light receiving number counting unit

[0348] 50: Bonded chip

[0349] 51: First Chip

[0350] 52: Second chip

[0351] 80: Host

[0352] 90: Object

[0353] 131: Light Source

[0354] 132: Collimator lens

[0355] 133: Half mirror

[0356] 134: Drive unit

[0357] 135: Galvanometer mirror

[0358] 141: SPAD Array

[0359] 142: Valid area

[0360] 142-1 to 142-4: SPAD area

[0361] 143: Timing control circuit

[0362] 144: Driving circuit

[0363] 145: Output circuit

[0364] 146: Light receiving lens

[0365] 150: Semiconductor substrate

[0366] 151: N-type semiconductor region

[0367] 153: P-type semiconductor region

[0368] 154: P+ semiconductor region

[0369] 155: N+ type semiconductor region

[0370] 156: Contact layer

[0371] 157: Component separation unit

[0372] 157A, 157B: Component separation area

[0373] 158: Reflective film

[0374] 159: Insulation film

[0375] 161: Flattening film

[0376] 162: On-chip lens

[0377] 163: Pinning layer

[0378] 164: Transparent insulating film

[0379] 170: Wiring layer

[0380] 171: Insulation film

[0381] 172, 176: via wiring

[0382] 173, 177, 191 and 195: Electrode pads

[0383] 180, 180B, 180C, 180D, 180E, 180F, 280G, 280H, 280K, 280L, 280M: Area

[0384] 181: concave-convex portion

[0385] 192, 196: Terminal

[0386] 201G, 201H: light-transmitting film

[0387] 202G, 202H: Groove

[0388] 203G, 203H: Incident surface

[0389] AR: Ranging range

[0390] L1: Laser

[0391] L2: reflected light

[0392] LD: pixel drive line

[0393] LS: Output signal line

[0394] SR: Perspective

Claims

1. A light detection device, comprising: A first chip, the first chip comprising a first semiconductor substrate and a first wiring layer, the first semiconductor substrate comprising a plurality of pixels including avalanche photodiodes; A separation unit, used for separating the plurality of avalanche photodiodes from each other; and a plurality of concavo-convex portions, each of the plurality of concavo-convex portions being provided on a light incident side of the first semiconductor substrate for each of the plurality of pixels; as well as a second chip, the second chip comprising a second semiconductor substrate and a second wiring layer; wherein the first chip is bonded to the second chip so that the first chip and the second chip face each other; and, Each of the plurality of concave-convex portions is divided into four parts in a plan view.

2. The light detection device according to claim 1, wherein: The four portions are formed to be respectively located at four corners of a pixel region of the pixel in a plan view.

3. The light detection device according to claim 2, wherein: The concavo-convex portion is not formed in at least a portion of a pixel region of the pixel.

4. The light detection device according to claim 2, wherein: In a plan view, the four portions are spaced apart from each other in a pixel region of the pixel.

5. The light detection device according to claim 1, wherein: The concavo-convex portion is formed in a polygonal column shape, a polygonal pyramid shape, a polygonal truncated pyramid shape, a cone shape, or a truncated cone shape.

6. The light detection device according to claim 1, wherein: The isolation portion includes a first element isolation region and a second element isolation region, and the plurality of concavo-convex portions are arranged between the first element isolation region and the second element isolation region.

7. The light detection device according to claim 6, wherein: Each of the first element isolation region and the second element isolation region includes a reflective film or a high refractive index film.

8. The light detection device according to claim 6, wherein: Each of the first element isolation region and the second element isolation region extends from the front surface of the first semiconductor substrate to the back surface of the first semiconductor substrate.

9. The light detection device according to claim 1, wherein: The first chip and the second chip are bonded to each other by Cu-Cu bonding or bump bonding.

10. A distance measuring device, comprising: a light emitting portion configured to emit light of a predetermined wavelength; The light detection device according to any one of claims 1 to 9, configured to generate a pixel signal based on the received light; and An operation unit is configured to calculate a distance to an object based on the pixel signal generated by the light detection device.

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