Superconducting quantum chip and preparation method thereof

Abstract

The invention relates to the field of superconductive quantum chip 3D integration, and discloses a superconductive quantum chip and a preparation method thereof, and the superconductive quantum chip comprises a first chip and a second chip which are oppositely arranged; the first superconducting layer and the read-out control part are located on the surface, opposite to the second chip, of the first chip; the second superconducting layer and the Josephson junction are located on the surface, opposite to the first chip, of the second chip; the superconducting cylinder and the photoresist gasket are located between the first superconducting layer and the second superconducting layer, and the superconducting cylinder is located on the inner side of the photoresist gasket. The photoresist gasket is used as the supporting gasket between the first chip and the second chip, the thickness uniformity of the photoresist gasket is good, the thickness is easy to control, the problem of inclination caused by pure superconducting cylinder supporting can be avoided, and the distance between the first chip and the second chip can be better controlled. The photoresist gasket is simple to manufacture, can adapt to wafer-level processing, and is compatible with a manufacturing process of a low-loss chip.

Description

Technical Field

[0001] The present application relates to the field of 3D integration of superconducting quantum chips, and in particular to a superconducting quantum chip and a method for preparing the same. Background Art

[0002] The 3D integrated superconducting quantum chip is connected through the Flip-Chip mode, which divides the quantum bit and readout control into two separate planes, placed on two chips respectively, and then coupled and connected using capacitors and inductors, while using superconducting metals as mechanical support and signal connection. Among them, superconducting metals usually use indium, which has good ductility and is easy to cold weld.

[0003] The distance between the two chips affects the frequency of the resonant characteristics, the impedance matching between different signal lines, and the capacitive and inductive coupling rates between components. The relative tilt of the two chips will affect the change in the distance between the two chips in the local area, which will lead to local frequency shift. Since indium is soft, it is easy to tilt during flip-chip bonding. In order to solve this problem, a hard stop gasket can be added between the two chips. The hard stop gasket can use a silicon spacer or a large indium pad. The large indium pad can significantly increase the surface area of ​​​​indium and dilute the bonding force. However, there are the following defects. For obtaining silicon spacers, uniformly etching a large silicon substrate without increasing the surface roughness or loss rate is a major manufacturing challenge and is very difficult to make. The large indium pad needs to be deposited at a very high thickness, and the height is difficult to control, which also poses a problem of great difficulty in manufacturing.

[0004] Therefore, how to solve the above technical problems should be the focus of technical personnel in this field. Summary of the invention

[0005] The purpose of this application is to provide a superconducting quantum chip and a method for preparing the same, which can reduce the difficulty of production while achieving good control of the distance between two chips.

[0006] In order to solve the above technical problems, the present application provides a superconducting quantum chip, comprising:

[0007] A first chip and a second chip arranged opposite to each other;

[0008] a first superconducting layer and a readout control unit located on a surface of the first chip opposite to the second chip;

[0009] A second superconducting layer and a Josephson junction located on a surface of the second chip opposite to the first chip;

[0010] A superconducting column and a photoresist pad are located between the first superconducting layer and the second superconducting layer, wherein the superconducting column is located inside the photoresist pad.

[0011] Optionally, also include:

[0012] A bottom metal layer is located between the first superconducting layer and the superconducting column and between the second superconducting layer and the superconducting column, the bottom metal layer including an adhesion barrier layer and an anti-oxidation layer stacked in a direction away from the surface of the first chip and the second chip.

[0013] Optionally, the adhesion barrier layer includes any one or any combination of a chromium layer, a titanium layer, a nickel layer, and a tungsten layer; and / or the anti-oxidation layer includes a gold layer.

[0014] Optionally, the thickness of the photoresist spacer ranges from 5 microns to 10 microns.

[0015] Optionally, the first superconducting layer includes any one of an aluminum superconducting layer, a tantalum superconducting layer, and a niobium superconducting layer; and / or the second superconducting layer includes any one of a superconducting layer, a tantalum superconducting layer, and a niobium superconducting layer.

[0016] Optionally, the material of the photoresist pad includes SU-8 series photoresist.

[0017] The present application also provides a method for preparing a superconducting quantum chip, comprising:

[0018] Obtaining a pre-processed first wafer and a pre-processed second wafer; wherein the pre-processed first wafer comprises a first substrate, a first superconducting layer located on a surface of the first substrate, and a readout control unit, and the pre-processed second wafer comprises a second substrate, a second superconducting layer located on a surface of the second substrate, and a Josephson junction;

[0019] Making a photoresist pad on the surface of the first superconducting layer and / or the second superconducting layer;

[0020] Fabricating superconducting columns on the surfaces of the first superconducting layer and the second superconducting layer;

[0021] The pre-processed first wafer and the pre-processed second wafer are flip-chip bonded and cut through the superconducting column to obtain a superconducting quantum chip, wherein the photoresist gasket is located between the pre-processed first wafer and the pre-processed second wafer, and the superconducting column is located on the inner side of the photoresist gasket; the first substrate is cut to form a first chip, and the second substrate is cut to form a second chip.

[0022] Optionally, manufacturing a photoresist pad on the surface of the first superconducting layer and / or the second superconducting layer includes:

[0023] Spin coating a negative photoresist layer on the surface of the first substrate and / or the second substrate;

[0024] Pre-baking, exposing, post-baking and developing the negative photoresist layer in sequence;

[0025] The photoresist residue after development is removed to form the photoresist pad.

[0026] Optionally, before manufacturing superconducting columns on the surfaces of the first superconducting layer and the second superconducting layer, the method further includes:

[0027] Making a bottom metal layer on the surface of the first superconducting layer and the second superconducting layer, the bottom metal layer comprising an adhesion barrier layer and an anti-oxidation layer stacked in a direction away from the surface of the first substrate and the second substrate;

[0028] Accordingly, manufacturing superconducting columns on the surfaces of the first superconducting layer and the second superconducting layer includes:

[0029] Superconducting columns are fabricated on the surface of the bottom metal layer on the first superconducting layer and the second superconducting layer respectively.

[0030] Optionally, before flip-chip bonding the pre-processed first wafer and the pre-processed second wafer through the superconducting cylinder, the method further includes:

[0031] Spin-coating a protective glue on the surface of the pre-processed first wafer and the pre-processed second wafer;

[0032] cutting the pre-processed first wafer and the pre-processed second wafer;

[0033] The protective glue on the surfaces of the pre-processed first wafer and the pre-processed second wafer is removed.

[0034] A superconducting quantum chip provided by the present application includes: a superconducting quantum chip including: a first chip and a second chip arranged opposite to each other; a first superconducting layer and a readout control unit located on a surface of the first chip opposite to the second chip; a second superconducting layer and a Josephson junction located on a surface of the second chip opposite to the first chip; a superconducting column and a photoresist gasket located between the first superconducting layer and the second superconducting layer, wherein the superconducting column is located on the inner side of the photoresist gasket.

[0035] It can be seen that the superconducting quantum chip in this application uses a photoresist gasket as a supporting gasket between the first chip and the second chip. The photoresist gasket has good thickness uniformity and is easy to control, which can avoid the problem of tilting caused by simple superconducting column support, and can better control the spacing between the first chip and the second chip, so as to achieve large-scale expansion of superconducting quantum bits. In addition, the photoresist gasket is simple to make, can be adapted to wafer-level processing, and is compatible with the manufacturing process of low-loss chips.

[0036] In addition, the present application also provides a method for preparing a quantum chip having the above advantages. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the embodiments of the present application or the technical solutions of the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0038] Figure 1 A process for preparing a superconducting quantum chip provided in an embodiment of the present application Figure 1 ;

[0039] Figures 2 to 7 A process for preparing a superconducting quantum chip provided in the embodiment of the present application Figure 1 ;

[0040] Figure 8 A process for preparing a superconducting quantum chip provided in an embodiment of the present application Figure 2 ;

[0041] Figures 9 to 11 A process for preparing a superconducting quantum chip provided in the embodiment of the present application Figure 2 ;

[0042] Fig.12 A process for preparing a superconducting quantum chip provided in an embodiment of the present application Figure 3 ;

[0043] In the figure, 1, first substrate, 2, first superconducting layer, 3, readout control unit, 4, second substrate, 5, second superconducting layer, 6, Josephson junction, 7, photoresist pad, 8, superconducting column, 9, bottom metal layer, 1', first chip, 4', second chip. DETAILED DESCRIPTION

[0044] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below in conjunction with the accompanying drawings and specific implementation methods. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present application.

[0045] In the following description, many specific details are set forth to facilitate a full understanding of the present invention, but the present invention may also be implemented in other ways different from those described herein, and those skilled in the art may make similar generalizations without violating the connotation of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0046] As described in the background technology section, currently a silicon spacer or a large indium pad is disposed between two chips to control the distance between the two chips, but both have the problem of being difficult to manufacture.

[0047] In view of this, the present application provides a method for preparing a superconducting quantum chip, please refer to Figure 1 , the method may include:

[0048] Step S101: obtaining a preprocessed first wafer and a preprocessed second wafer; wherein the preprocessed first wafer comprises a first substrate, a first superconducting layer located on a surface of the first substrate, and a readout control unit, and the preprocessed second wafer comprises a second substrate, a second superconducting layer located on a surface of the second substrate, and a Josephson junction.

[0049] The schematic diagram of pre-processing the first wafer is as follows Figure 2 As shown, the first substrate 1 may be a silicon substrate, and the first superconducting layer 2 and the readout control unit 3 are directly located on the surface of the first substrate 1. The readout control unit 3 may include an XY control line, a Z control line, a readout resonant cavity, and a readout line. The surface where the first superconducting layer 2 and the readout control unit 3 are located is the inner surface of the first substrate 1.

[0050] The schematic diagram of pre-processing the second wafer is as follows Figure 3 As shown, the second substrate 4 may be a silicon substrate, and the second superconducting layer 5 and the Josephson junction 6 are directly located on the surface of the second substrate 4. The surface where the second superconducting layer 5 and the Josephson junction 6 are located is the inner surface of the second substrate 4.

[0051] The first superconducting layer 2 and the second superconducting layer 5 include but are not limited to any one of an aluminum (Al) superconducting layer, a tantalum (Ta) superconducting layer, and a niobium (Nb) superconducting layer. The first superconducting layer 2 and the second superconducting layer 5 may be the same or different, both within the protection scope of the present application.

[0052] Step S102: forming a photoresist pad on the surface of the first superconducting layer and / or the second superconducting layer.

[0053] It is understandable that the photoresist pad can be made in three positions: the first is to make the photoresist pad only on the first superconducting layer; the second is to make the photoresist pad only on the second superconducting layer; and the third is to make the photoresist pad on both the first superconducting layer and the second superconducting layer.

[0054] For example, when the photoresist pad 7 is formed only on the first superconducting layer 2, as shown in FIG. Figure 4 shown.

[0055] The photoresist pad 7 is a negative photoresist pad 7. In this embodiment, the specific type of the photoresist pad 7 is not limited and can be set at will. For example, the material of the photoresist pad 7 can be SU-8 series photoresist, such as SU-8 3010, SU-83000, SU-8 2000, etc.

[0056] SU-8 photoresist is a commonly used negative photoresist based on epoxy resin. It can reach a thickness of several hundred microns and has good mechanical properties, chemical corrosion resistance and thermal stability.

[0057] It should be noted that in this embodiment, the number of photoresist pads 7 in each quantum chip is not limited and can be set at will. For example, the number of photoresist pads 7 in each quantum chip can be 2, 3, 4, etc.

[0058] It should also be noted that in this embodiment, the size of each photoresist spacer 7 is not limited and can be set at will. For example, the size of each photoresist spacer 7 can be 14.3 μm×14.3 μm.

[0059] In this embodiment, the manufacturing process of the photoresist spacer 7 is not specifically limited, as long as the photoresist spacer 7 can be manufactured on the surface of the first superconducting layer 2 and / or the second superconducting layer 5 .

[0060] As an implementation method, manufacturing a photoresist pad on the surface of the first superconducting layer and / or the second superconducting layer includes:

[0061] Step S1021: spin-coating a negative photoresist layer on the surface of the first substrate and / or the second substrate.

[0062] It should be noted that the coating speed during spin coating is not limited in this embodiment and can be set at will. As an implementation method, when spin coating negative photoresist, the coating speed ranges from 1500r / min to 3000r / min. For example, the coating speed can be 1500r / min, 2000r / min, 2500r / min, 3000r / min, etc.

[0063] Step S1022: pre-baking, exposing, post-baking and developing are performed on the negative photoresist layer in sequence.

[0064] The functions of pre-baking include: first, removing the solvent in the photoresist and reducing the residual solvent concentration; second, enhancing the adhesion between the photoresist and the first substrate and / or the second substrate; third, during the process of coating the photoresist, stress may be generated inside the film, and pre-baking helps to release this stress.

[0065] The functions of post-baking include: completing the photochemical reaction that has not completely reacted after exposure; and enhancing the etching resistance of the photoresist.

[0066] It should be pointed out that in this embodiment, there is no limitation on the baking temperature, time, and exposure dose, which can be set by oneself.

[0067] As an implementation method, the pre-baking temperature ranges from 90°C to 100°C, and the pre-baking time ranges from 180s to 300s. For example, the pre-baking temperature may be 90°C, 95°C, 100°C, etc., and the pre-baking time may be 180s, 200s, 250s, 280s, 300s, etc.

[0068] It should be pointed out that the exposure dose is not limited in this embodiment and depends on the circumstances.

[0069] As an embodiment, the wavelength of the light used for exposure can be 365nm, and the exposure dose range is 180mJ / cm 2 ~300mJ / cm 2 For example, the exposure dose can be 180 mJ / cm 2 、200mJ / cm 2 、250mJ / cm 2 、300mJ / cm 2 wait.

[0070] It should be noted that the post-baking process is not limited in this embodiment.

[0071] As an implementable method, post-baking includes normal pressure baking and vacuum baking, wherein the temperature range of normal pressure baking is 60℃~75℃, and the time range is 90s~120s; the temperature range of vacuum baking is 80℃~100℃, and the time range is 250s~400s.

[0072] For example, the temperature of normal pressure baking can be 60°C, 65°C, 70°C, 75°C, etc., and the time of normal pressure baking can be 90s, 100s, 110s, 120s, etc. The temperature of vacuum baking can be 80°C, 90°C, 95°C, 100°C, etc., and the time of vacuum baking can be 250s, 300s, 350s, 400s, etc.

[0073] Atmospheric pressure baking can promote photochemical reactions, and vacuum baking can remove residual solvents and enhance adhesion. This post-baking can improve the quality of photoresist graphics and reduce defects.

[0074] During development, mr-Dev 600 developer can be used for rinsing, and the rinsing time can be 90s.

[0075] Step S1023: removing the photoresist residue after development to form a photoresist pad.

[0076] When removing photoresist residue, you can use isopropyl alcohol and mr-Dev 600 to wash alternately several times until the residue is completely removed.

[0077] Step S103: manufacturing superconducting columns on the surfaces of the first superconducting layer and the second superconducting layer.

[0078] like Figure 5 and Figure 6 As shown, superconducting columns 8 are respectively made on the surfaces of the first superconducting layer 2 and the second superconducting layer 5 .

[0079] The material of the superconducting column 8 may be indium. The manufacturing process of the superconducting column 8 may include defining the pattern of the superconducting column 8 by photolithography, and then plating indium by thermal evaporation.

[0080] The shape of the superconducting column 8 includes but is not limited to any one of a cylinder, a prism, a truncated cone, and a frustum.

[0081] The superconducting column 8 may have a thickness of 10 μm and a diameter of 25 μm, and a distance between two adjacent superconducting columns 8 may be 100 μm.

[0082] It should be noted that the order of making the photoresist gasket and the superconducting column is not limited in this application. In this embodiment, the photoresist gasket is made first, and then the superconducting column is made. In other embodiments of this application, the superconducting column can also be made first, and then the photoresist gasket.

[0083] Step S104: The pre-processed first wafer and the pre-processed second wafer are flip-bonded and cut through a superconducting column to obtain a superconducting quantum chip, wherein the photoresist gasket is located between the pre-processed first wafer and the pre-processed second wafer; the superconducting column is located on the inner side of the photoresist gasket; the first substrate is cut to form a first chip, and the second substrate is cut to form a second chip.

[0084] The inner side of the photoresist pad refers to the side of the photoresist pad close to the center of the superconducting quantum chip, that is, the side away from the surroundings of the superconducting quantum chip.

[0085] The pre-processed first wafer and the pre-processed second wafer can be placed in a flip-chip bonding machine (model FC150) for flip-chip bonding. The positions of the pre-processed first wafer and the pre-processed second wafer are adjusted and aligned by a CCD (charge coupled device) camera, and then flip-chip pressure is applied for bonding to bond the pre-processed first wafer and the pre-processed second wafer together. The schematic diagram of the superconducting quantum chip after bonding is shown in FIG. Figure 7 shown.

[0086] Bonding pressure range can be 10N / mm 2 ~40N / mm 2, for example, the bonding pressure may be 10 N / mm 2 , 20N / mm 2 , 30 N / mm 2 , 40 N / mm 2 Etc. Avoid too little bonding pressure, which may result in a loose bond, and avoid too much bonding pressure, which may easily damage the pre-treated first wafer and the pre-treated second wafer. The bonding pressure is preferably 20 N / mm 2 .

[0087] After the first substrate and the second substrate are cut, a plurality of first chips and a plurality of second chips are formed correspondingly.

[0088] In order to facilitate the alignment of the pre-processed first wafer and the pre-processed second wafer, alignment mark points may be respectively set on the pre-processed first wafer and the pre-processed second wafer.

[0089] In the present embodiment, when preparing the superconducting quantum chip, after obtaining the pre-processed first wafer and the pre-processed second wafer, a photoresist gasket and a superconducting cylinder are made, and then the pre-processed first wafer and the pre-processed second wafer are flip-chip bonded. The photoresist gasket is used as a supporting gasket between the pre-processed first wafer and the pre-processed second wafer. The photoresist gasket made by photoresist has good thickness uniformity and easy thickness control, which can avoid the problem of tilting caused by simple superconducting cylinder support, and can better control the spacing between the first substrate and the second substrate, and can realize large-scale expansion of superconducting quantum bits. In addition, the photoresist gasket is simple to make, can be adapted to wafer-level processing, and is compatible with the manufacturing process of low-loss chips.

[0090] On the basis of the above embodiments, in one embodiment of the present application, after the negative photoresist layer is pre-baked, exposed, post-baked and developed in sequence, the following steps may also be included:

[0091] The developed negative photoresist layer is baked again.

[0092] Rebaking the photoresist after development can improve the mechanical resilience of the photoresist pad.

[0093] In this embodiment, the time and temperature for baking the developed photoresist again are not limited and can be set by oneself. As an implementation method, the temperature range for baking the developed photoresist again can be 150° C. to 200° C., and the baking time can be 800s to 1200s.

[0094] For example, the temperature for baking the developed photoresist again may be 150° C., 180° C., 200° C., etc., and the baking time may be 800 s, 900 s, 1000 s, 1200 s, etc.

[0095] Please refer to Figure 8Based on any of the above embodiments, in one embodiment of the present application, a method for preparing a superconducting quantum chip may include:

[0096] Step S201: obtaining a preprocessed first wafer and a preprocessed second wafer; wherein the preprocessed first wafer comprises a first substrate, a first superconducting layer located on a surface of the first substrate, and a readout control unit, and the preprocessed second wafer comprises a second substrate, a second superconducting layer located on a surface of the second substrate, and a Josephson junction.

[0097] Step S202: forming a photoresist pad on the surface of the first superconducting layer and / or the second superconducting layer.

[0098] Step S203: forming a bottom metal layer on the surfaces of the first superconducting layer and the second superconducting layer, wherein the bottom metal layer includes an adhesion barrier layer and an anti-oxidation layer stacked in a direction away from the surfaces of the first substrate and the second substrate.

[0099] like Fig. 9 and Fig.10 As shown, the position of the bottom metal layer 9 corresponds to the position of the superconducting column to be manufactured subsequently. By providing the bottom metal layer 9, the adhesion between the superconducting column and the first superconducting layer and the second superconducting layer can be enhanced, thereby improving the stability of the superconducting column.

[0100] The material of the adhesion barrier layer includes, but is not limited to, metals such as chromium (Cr), titanium (Ti), nickel (Ni), and tungsten (W); the anti-oxidation layer may be gold (Au) or the like.

[0101] The thickness of the adhesion barrier layer may be 20 nm to 50 nm, and the thickness of the anti-oxidation layer may be 80 nm to 100 nm.

[0102] Step S204: Superconducting columns are fabricated on the surfaces of the bottom metal layer on the first superconducting layer and the second superconducting layer respectively.

[0103] Step S205: The pre-processed first wafer and the pre-processed second wafer are flip-bonded and cut through a superconducting column to obtain a superconducting quantum chip, wherein the photoresist gasket is located between the pre-processed first wafer and the pre-processed second wafer; the superconducting column is located on the inner side of the photoresist gasket; the first substrate is cut to form a first chip, and the second substrate is cut to form a second chip.

[0104] The first substrate and the second substrate are cut to form a plurality of first chips 1' and a second chip 4' respectively. The superconducting quantum chips obtained after cutting are as follows: Fig.11 shown.

[0105] On the basis of any of the above embodiments, in one embodiment of the present application, a pre-processed first wafer and a pre-processed second wafer are obtained; wherein the pre-processed first wafer includes a first substrate, a first superconducting layer located on a surface of the first substrate, and a readout control unit, and the pre-processed second wafer includes a second substrate, a second superconducting layer located on a surface of the second substrate, and a Josephson junction, and a manufacturing process of the pre-processed first wafer and the pre-processed second wafer may be included, and the process may include:

[0106] Depositing a first superconducting layer on a surface of a first substrate;

[0107] Fabricating a readout control unit on a surface of a first substrate;

[0108] depositing a second superconducting layer on the surface of the second substrate;

[0109] A Josephson junction is fabricated on the surface of the second substrate.

[0110] The order of manufacturing the first superconducting layer and the readout control unit on the first substrate is not limited in this embodiment. Similarly, the order of manufacturing the second superconducting layer and the Josephson junction on the second substrate is not limited in this embodiment.

[0111] The first superconducting layer and the second superconducting layer may be manufactured by electron beam evaporation.

[0112] The manufacturing process of the readout control unit and the Josephson junction can refer to the prior art and will not be described in detail in this embodiment.

[0113] The readout control unit can be obtained by manufacturing a first wiring layer on the surface of a first substrate. The first substrate is patterned by photolithography and then subjected to a wet etching process to obtain the first wiring layer.

[0114] The Josephson junction can be obtained by forming a second wiring layer on the surface of the second substrate, wherein the second wiring layer includes a structure for forming the Josephson junction. The Josephson junction is formed by using EBL (electron beam lithography) technology and cross evaporation method.

[0115] It should be noted that, in order to improve the bonding stability between the first substrate and the first superconducting layer and the readout control unit, and the bonding stability between the second substrate and the second superconducting layer and the Josephson junction, a process of cleaning the first substrate and the second substrate may be further included. The cleaning process includes:

[0116] Soaking the first substrate and the second substrate in a mixture of an ammonium hydroxide solution and a hydrogen peroxide solution to remove organic pollutants on the surfaces of the first substrate and the second substrate;

[0117] Using a hydrofluoric acid solution at room temperature to soak the first substrate and the second substrate to remove organic pollutants, so as to remove the silicon dioxide oxide layer on the surface of the first substrate and the second substrate;

[0118] The cleaned first substrate and the second substrate are rinsed clean with deionized water.

[0119] The purity of the ammonium hydroxide solution can be 25%, the purity of the hydrogen peroxide solution can be 30%, the ratio of the ammonium hydroxide solution to the hydrogen peroxide solution can be 1:1, the immersion temperature when removing organic pollutants can be 80°C, and the immersion time can be 10 minutes. The purity of the hydrofluoric acid solution can be 7%, and the silicon dioxide layer can be removed at room temperature for 60 seconds.

[0120] After the first substrate and the second substrate are rinsed, it is best to proceed to the next step within 10 minutes, for example, sending the first substrate and the second substrate to an electron beam evaporation system to deposit a first superconducting layer and a second superconducting layer.

[0121] The first substrate and the second substrate may be high-resistance silicon (>20 KΩ.cm).

[0122] Please refer to Fig.12 Based on any of the above embodiments, in one embodiment of the present application, a method for preparing a superconducting quantum chip may include:

[0123] Step S301: obtaining a preprocessed first wafer and a preprocessed second wafer; wherein the preprocessed first wafer comprises a first substrate, a first superconducting layer located on a surface of the first substrate, and a readout control unit, and the preprocessed second wafer comprises a second substrate, a second superconducting layer located on a surface of the second substrate, and a Josephson junction.

[0124] Step S302: spin-coating a negative photoresist layer on the surface of the first substrate and / or the second substrate.

[0125] Step S303: pre-baking, exposing, post-baking and developing are performed on the negative photoresist layer in sequence.

[0126] Step S304: baking the developed negative photoresist layer again.

[0127] Step S305: removing the photoresist residue after development to form a photoresist pad.

[0128] Step S306: forming a bottom metal layer on the surfaces of the first superconducting layer and the second superconducting layer, wherein the bottom metal layer includes an adhesion barrier layer and an anti-oxidation layer stacked in a direction away from the surfaces of the first substrate and the second substrate.

[0129] Step S307: Superconducting columns are fabricated on the surfaces of the bottom metal layer on the first superconducting layer and the second superconducting layer respectively.

[0130] Step S308: spin-coating a protective glue on the surface of the pre-processed first wafer and the pre-processed second wafer.

[0131] The types of protective glue include but are not limited to any one of AZ4620, SPR220, and AZ9260.

[0132] When the sizes of the first substrate and the second substrate are relatively large, the structures required for multiple superconducting quantum chips can be manufactured on the first substrate and the second substrate, and then cut according to the required size of each superconducting quantum chip, which can improve the manufacturing efficiency of the superconducting quantum chips.

[0133] For example, when the diameters of the first substrate and the second substrate are 50.8 cm, and the size of the pre-processed first wafer in the final superconducting quantum chip is 14.3 mm×14.3 mm, and the size of the pre-processed second wafer is 12 mm×12 mm, cutting is required.

[0134] By coating protective glue on the processed first wafer and the pre-processed second wafer, structures such as the first superconducting layer, the readout control unit, the second superconducting layer, the Josephson junction and the superconducting column can be protected during the subsequent cutting process, thereby improving the yield of the superconducting quantum chip.

[0135] Step S309: cutting the pre-processed first wafer and the pre-processed second wafer.

[0136] Step S310: removing the protective glue on the surfaces of the pre-processed first wafer and the pre-processed second wafer after cutting.

[0137] When removing the protective glue, you can use solutions such as acetone and isopropyl alcohol.

[0138] It should be noted that after the protective glue spin coating and removal process, the photoresist pad may have residual solvent used to remove the protective glue. The pre-treated first wafer and the pre-treated second wafer can be placed in a temperature range of 40℃~60℃ and a pressure of 2×10 4 Pa in a vacuum oven for 12 to 15 hours to remove solvent residues.

[0139] Step S311: flip-chip bonding the cut pre-processed first wafer and the pre-processed second wafer through a superconducting column to obtain a superconducting quantum chip, wherein a photoresist pad is located between the pre-processed first wafer and the pre-processed second wafer; and the superconducting column is located on the inner side of the photoresist pad.

[0140] The superconducting quantum chip obtained after flip-chip bonding in the present application was scanned by a profilometer, and the average spacing of the superconducting quantum chip was calculated to be 9.6±0.8μm, and the average inclination was (76±36) μrad. This indicates that the SU-8 photoresist gasket in the present application can accurately control the spacing of the superconducting quantum chip and improve the inclination of the superconducting quantum chip.

[0141] The present application also provides a superconducting quantum chip, such as Figure 7 and Fig.11 As shown, it may include:

[0142] A first chip 1' and a second chip 4' are arranged opposite to each other, and the first chip 1' and the second chip 4' are flip-chip connected;

[0143] A first superconducting layer 2 and a readout control unit 3 located on a surface of the first chip 1' opposite to the second chip 4';

[0144] A second superconducting layer 5 and a Josephson junction 6 located on a surface of the second chip 4' opposite to the first chip 1';

[0145] A superconducting column 8 and a photoresist spacer 7 are located between the first superconducting layer 2 and the second superconducting layer 5 , wherein the superconducting column 8 is located inside the photoresist spacer 7 .

[0146] The inner side of the photoresist pad 7 refers to the side of the photoresist pad 7 close to the center of the superconducting quantum chip, that is, the side away from the surrounding of the superconducting quantum chip.

[0147] The first chip 1 ′ and the second chip 4 ′ may be silicon substrates.

[0148] The readout control section 3 may include an XY control line, a Z control line, a readout resonant cavity, and a readout line.

[0149] The first superconducting layer 2 and the second superconducting layer 5 include, but are not limited to, any one of an aluminum (Al) superconducting layer, a tantalum (Ta) superconducting layer, and a niobium (Nb) superconducting layer.

[0150] The superconducting column 8 may be an indium column.

[0151] The material of the photoresist pad 7 may include SU-8 series photoresist, such as SU-8 3010, SU-8 3000, SU-8 2000, etc. SU-8 series photoresist is a commonly used negative photoresist based on epoxy resin, with a thickness of up to several hundred microns, and has good mechanical properties, chemical corrosion resistance and thermal stability.

[0152] The superconducting quantum chip in this embodiment uses a photoresist gasket as a supporting gasket between the first chip and the second chip. The photoresist gasket has good thickness uniformity and is easy to control, which can avoid the problem of tilting caused by simple superconducting column support, and can better control the spacing between the first chip and the second chip, so as to achieve large-scale expansion of superconducting quantum bits. In addition, the photoresist gasket is simple to make, can be adapted to wafer-level processing, and is compatible with the manufacturing process of low-loss chips.

[0153] In the present application, there is no limitation on the thickness of the photoresist spacer 7 . Specifically, for example, the thickness of the photoresist spacer 7 is limited by simulating the chip spacing according to the design of the superconducting quantum chip architecture.

[0154] As an implementation method, the thickness of the photoresist spacer 7 can range from 5 micrometers to 10 micrometers. Exemplarily, the thickness of the photoresist spacer 7 can be 5 micrometers, 6 micrometers, 7 micrometers, 8 micrometers, 9 micrometers, 10 micrometers, etc.

[0155] like Fig.11 As shown, based on the above embodiment, in one embodiment of the present application, the superconducting quantum chip further includes:

[0156] A bottom metal layer 9 is located between the first superconducting layer 2 and the superconducting column 8 and between the second superconducting layer 5 and the superconducting column 8. The bottom metal layer 9 includes an adhesion barrier layer and an anti-oxidation layer stacked in a surface direction away from the first chip 1' and the second chip 4'.

[0157] The adhesion barrier layer includes, but is not limited to, any one or any combination of a chromium (Cr) layer, a titanium (Ti) layer, a nickel (Ni) layer, a tungsten (W) layer, etc.; the anti-oxidation layer may include a gold (Au) layer, etc. The thickness of the adhesion barrier layer may be 20nm to 50nm, and the thickness of the anti-oxidation layer may be 80nm to 100nm.

[0158] By providing the bottom metal layer 9 , the adhesion between the superconducting column 8 and the first superconducting layer 2 and the second superconducting layer 5 can be enhanced, thereby improving the stability of the superconducting column 8 .

[0159] The superconducting quantum chip is prepared, for example but not limited to, by the above-mentioned method for preparing the superconducting quantum chip.

[0160] Alternatively, in some embodiments, part of the circuits in the readout control unit 3 may also be fabricated on the second chip 4 ′.

[0161] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0162] The superconducting quantum chip and its preparation method provided by the present application are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the scheme and its core idea of ​​the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the present application.

Claims

1. A superconducting quantum chip, characterized in that: include: A first chip and a second chip arranged opposite to each other; a first superconducting layer and a readout control unit located on a surface of the first chip opposite to the second chip; A second superconducting layer and a Josephson junction located on a surface of the second chip opposite to the first chip; A superconducting column and a photoresist pad are located between the first superconducting layer and the second superconducting layer, wherein the superconducting column is located inside the photoresist pad.

2. The superconducting quantum chip according to claim 1, characterized in that: Also includes: A bottom metal layer is located between the first superconducting layer and the superconducting column and between the second superconducting layer and the superconducting column, the bottom metal layer including an adhesion barrier layer and an anti-oxidation layer stacked in a direction away from the surface of the first chip and the second chip.

3. The superconducting quantum chip according to claim 2, characterized in that: The adhesion barrier layer includes any one or any combination of a chromium layer, a titanium layer, a nickel layer, and a tungsten layer; And / or, the anti-oxidation layer includes a gold layer.

4. The superconducting quantum chip according to claim 1, characterized in that: The thickness of the photoresist pad ranges from 5 microns to 10 microns.

5. The superconducting quantum chip according to claim 1, characterized in that: The first superconducting layer includes any one of an aluminum superconducting layer, a tantalum superconducting layer, and a niobium superconducting layer; And / or, the second superconducting layer includes any one of a superconducting layer, a tantalum superconducting layer, and a niobium superconducting layer.

6. The superconducting quantum chip according to any one of claims 1 to 5, characterized in that: The material of the photoresist pad includes SU-8 series photoresist.

7. A method for preparing a superconducting quantum chip, characterized in that: include: Obtaining a pre-processed first wafer and a pre-processed second substrate; wherein the pre-processed first wafer comprises a first substrate, a first superconducting layer located on a surface of the first substrate, and a readout control unit, and the pre-processed second substrate comprises a second substrate, a second superconducting layer located on a surface of the second substrate, and a Josephson junction; Making a photoresist pad on the surface of the first superconducting layer and / or the second superconducting layer; Fabricating superconducting columns on the surfaces of the first superconducting layer and the second superconducting layer; The pre-processed first wafer and the pre-processed second wafer are flip-bonded and cut by the superconducting column to obtain a superconducting quantum chip. The photoresist pad is located between the pre-processed first wafer and the pre-processed second wafer, and the superconducting column is located on the inner side of the photoresist pad; the first substrate is cut to form a first chip, and the second substrate is cut to form a second chip.

8. The method for preparing a superconducting quantum chip according to claim 7, characterized in that: Producing a photoresist pad on the surface of the first superconducting layer and / or the second superconducting layer comprises: Spin coating a negative photoresist layer on the surface of the first substrate and / or the second substrate; Pre-baking, exposing, post-baking and developing the negative photoresist layer in sequence; The photoresist residue after development is removed to form the photoresist pad.

9. The method for preparing a superconducting quantum chip according to claim 7, characterized in that: Before manufacturing superconducting columns on the surfaces of the first superconducting layer and the second superconducting layer, the method further includes: Making a bottom metal layer on the surface of the first superconducting layer and the second superconducting layer, the bottom metal layer comprising an adhesion barrier layer and an anti-oxidation layer stacked in a direction away from the surface of the first substrate and the second substrate; Accordingly, manufacturing superconducting columns on the surfaces of the first superconducting layer and the second superconducting layer includes: Superconducting columns are fabricated on the surface of the bottom metal layer on the first superconducting layer and the second superconducting layer respectively.

10. The method for preparing a superconducting quantum chip according to any one of claims 7 to 9, characterized in that: Before flip-chip bonding the pre-processed first wafer and the pre-processed second wafer through the superconducting cylinder, the method further includes: Spin-coating a protective glue on the surface of the pre-processed first wafer and the pre-processed second wafer; cutting the pre-processed first wafer and the pre-processed second wafer; The protective glue on the surfaces of the pre-processed first wafer and the pre-processed second wafer is removed.

Images