Integrated package

Abstract

An integrated package includes an integrated control element. The integrated control element comprises a switch transistor unit, a driving transistor unit and an energy storage unit. The switch transistor unit comprises a first source electrode, a first drain electrode and a first grid electrode. The driving transistor unit comprises a second source electrode, a second drain electrode and a second grid electrode, wherein the second grid electrode is coupled to the first drain electrode. The energy storage unit is coupled between the second drain electrode and the second grid electrode. The integrated package also includes a shed terminal, a drain terminal, and a source terminal for coupling to the outside.

Description

Integrated packaging Technical Field

[0001] The present application relates to a semiconductor device, and more particularly to an integrated package. Background Art

[0002] In recent years, semiconductor devices have become increasingly smaller and more complex in structure.

[0003] Furthermore, display technology has become ubiquitous in our daily lives, with applications spanning smartphones, tablets, desktop monitors, and televisions. Light-emitting diodes (LEDs), such as micro-LEDs and mini-LEDs, have become the light-emitting components of next-generation displays.

[0004] Traditional LED displays include multiple LED sub-pixels, each of which includes at least one LED driven or controlled by a thin-film transistor (TFT) on a glass substrate. All LED sub-pixels are arranged together to form a pixel array. The drive systems for the pixel array in a display include passive matrix (PM) addressing, active matrix (AM) addressing, and semi-active matrix (semi-AM) addressing. Compared to active addressing systems, passive addressing systems have a relatively slow response time. Semi-active addressing systems have a response time between passive and active addressing systems. Furthermore, the thin-film transistors in the drive system are manufactured using amorphous silicon (amorphous silicon) and low-temperature polysilicon (LTPS) technologies on the glass backplane, but their low electron mobility further reduces system efficiency. Therefore, in the application of micro-LED / mini-LED displays, the integration of the LEDs and the display's drive system must be considered to achieve high efficiency and integration.

[0005] Summary of the Invention

[0006] The present application relates to an integrated package for manufacturing a transistor and an energy storage unit into an integrated control element and packaging the integrated control element on a carrier substrate for use in a driving system.

[0007] The present application relates to an integrated package for packaging transistors and light-emitting elements on a carrier substrate for use in a driving system.

[0008] According to one aspect of the present application, an integrated package is provided, comprising an integrated control element. The integrated control element includes a switching transistor unit, a driving transistor unit, and an energy storage unit. The switching transistor unit includes a first source, a first drain, and a first gate. The driving transistor unit includes a second source, a second drain, and a second gate, wherein the second gate is coupled to the first drain. The energy storage unit is coupled between the second drain and the second gate. The integrated package further includes a gate terminal, a drain terminal, and a source terminal for external coupling.

[0009] According to another aspect of the present application, an integrated package is provided, comprising an integrated control element and a light-emitting unit. The integrated control element includes a driving transistor unit. The driving transistor unit includes a source, a drain, and a gate. The light-emitting unit is coupled to the source. The integrated package also includes a gate terminal for external coupling, a drain terminal, and a ground terminal coupled to the light-emitting unit.

[0010] In order to better understand the above and other aspects of this application, the following embodiments are specifically described in detail with reference to the accompanying drawings: BRIEF DESCRIPTION OF THE DRAWINGS

[0011] FIG. 1 is a schematic diagram of an integrated package according to an embodiment of the present application.

[0012] FIG. 2 is a schematic diagram illustrating the integrated package shown in FIG. 1 being applied to an active addressing system.

[0013] FIG3 is a schematic diagram of an integrated control element according to an embodiment of the present application.

[0014] 4A to 4C are schematic cross-sectional views of a HEMT according to one embodiment of the present application.

[0015] FIG. 5 is a schematic diagram illustrating the integrated package shown in FIG. 1 being applied to an active addressing system.

[0016] FIG6 is a schematic diagram showing an integrated package according to another embodiment of the present application being applied in an active addressing system.

[0017] FIG. 7 is a schematic diagram illustrating the integrated package shown in FIG. 6 being applied to an active addressing system.

[0018] FIG8 is a schematic diagram of an integrated package according to another embodiment of the present application.

[0019] FIG. 9 is a schematic diagram illustrating the integrated package shown in FIG. 8 being applied to an active addressing system.

[0020] FIG. 10 is a schematic diagram of an integrated package according to another embodiment of the present application.

[0021] FIG. 11 is a schematic diagram illustrating the integrated package shown in FIG. 10 being applied to a semi-active addressing system.

[0022] FIG. 12 is a schematic diagram of an integrated package according to another embodiment of the present application.

[0023] FIG. 13 is a schematic diagram illustrating the integrated package shown in FIG. 12 being applied to a semi-active address selection system.

[0024] 14 and 15 are schematic diagrams respectively illustrating a packaging structure according to an embodiment of the present application.

[0025] [Description of symbols] 10: Active addressing system 20: Semi-active addressing system 100-104: Integrated package 1000: Carrier unit 1001, 1001': Integrated control element 1100: Backplane 1100a: Front surface 1100b: Back surface 1101: Conductive via 111: Data line 112: Scan line 113: Power line 200, 200', 200": HEMT element 202: Substrate 204: First buffer layer 206: Second buffer layer 208: Channel layer 209: Two-dimensional electron gas 210: Barrier layer 211: Buffer structure 212: Doping layer 213: Recess 300: Package Structure T1: switching transistor unit T2, T3: driving transistor unit C1: energy storage unit S1: first source S2: second source D1: first drain D2: second drain G1: first gate G2: second gate P1: source terminal P2: drain terminal P3: gate terminal Vdata1~VdataN: driving voltage SCAN1~SCANM: scanning signal VDD: drain voltage P4: control signal output terminal R1: red light emitting sub-unit G1: green light emitting sub-unit B1: blue light emitting sub-unit S3, S: source D3, D: drain G3, G: gate GN: ground terminal N1: cathode DETAILED DESCRIPTION

[0026] The following will be combined with the accompanying drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. The following description uses the same / similar symbols to represent the same / similar elements.

[0027] Please refer to Figures 1 to 3, where Figure 1 is a schematic diagram of an integrated package 100 according to an embodiment of the present application, Figure 2 is a schematic diagram of the integrated package 100 shown in Figure 1 being applied to an active addressing system 10, and Figure 3 is a schematic diagram of an integrated control element 1001 according to an embodiment of the present application. Integrated package 100 includes an integrated control element 1001. Integrated control element 1001 includes a switching transistor unit T1, a driving transistor unit T2, and an energy storage unit C1. Switching transistor unit T1 includes a first source S1, a first drain D1, and a first gate G1. Driving transistor unit T2 includes a second source S2, a second drain D2, and a second gate G2, wherein second gate G2 is coupled to first drain D1. Energy storage unit C1 is coupled between second drain D2 and second gate G2. Integrated package 100 may also include a carrier unit 1000, on which integrated control element 1001 is formed.

[0028] The switching transistor unit T1 and the driving transistor unit T2 may include a metal-oxide-semiconductor field-effect transistor (MOSFET) or a high electron mobility transistor (HEMT). The semiconductor material of the MOSFET includes silicon (Si) or germanium (Ge). The semiconductor material of the HEMT includes a III-V material or SiC material, wherein the III-V material includes a gallium nitride (GaN)-based or gallium arsenide (GaAs)-based III-V compound semiconductor material. HEMT devices inherently have the characteristics of high mobility and high frequency, and therefore can be used in the field of switching devices (such as the switching transistor unit T1 and the driving transistor unit T2 disclosed herein). In one embodiment, the GaN-based HEMT device has higher efficiency than traditional Si-based MOSFETs and is smaller in size, making it easier to integrate with other electronic components to form an integrated die, or to form an integrated package through die-level packaging. Therefore, integrated chips or integrated packages can replace TFTs wired on a glass backplane in traditional active, semi-active, or passive addressing systems to provide higher power driver efficiency for light-emitting units (EDs) (e.g., LED elements). Users can also simplify wiring and increase performance through integrated chips or integrated packages.

[0029] 4A to 4C illustrate cross-sectional views of HEMT devices 200, 200', and 200" according to an embodiment of the present application. HEMT devices 200, 200', and 200" are field-effect transistors (FETs) that utilize a heterojunction formed by two materials with different band gaps, creating a two-dimensional electron gas (2DEG) as a carrier channel, making the transistors suitable for high-voltage, high-frequency, or low-noise applications. Referring to FIG4A , in one embodiment, a gallium nitride-based depletion-mode HEMT (D-HEMT) 200 is used as an example for the switch transistor unit T1 or the driver transistor unit T2. This is a normally-on HEMT device. In one embodiment, HEMT device 200 includes a semiconductor stack including a buffer structure 211, a channel layer 208 disposed on the buffer structure 211, and a barrier layer 210. A two-dimensional electron gas 209 is present in the channel layer 208 near its interface with the barrier layer 210. The HEMT device 200 further includes a gate G, a drain D, and a source S disposed on a barrier layer 210. These correspond to the first source S1 / second source S2, first drain D1 / second drain D2, and first gate G1 / second gate G2 of the switching transistor unit T1 / driving transistor unit T2. In one embodiment, the HEMT device 200 further includes a substrate 202, which may be a growth substrate for epitaxial growth of semiconductor stacks and may be made of silicon or sapphire. The buffer structure 211 may include an AlGaN-based material, such as a first buffer layer 204 and a second buffer layer 206 stacked in sequence on the substrate 202. The first buffer layer 204 may be made of AlN, and the second buffer layer 206 may be made of AlGaN or GaN, but are not limited thereto. The channel layer 208 and the barrier layer 210 are undoped or unintentionally doped layers. Referring to FIG4B , in one embodiment, a gallium nitride-based enhancement-mode HEMT (E-HEMT) 200 ′ is used as an example for the switching transistor unit T1 or the driver transistor unit T2. This is a normally-off HEMT device. Unlike the depletion-mode HEMT device 200 , the E-HEMT device 200 ′ includes a doped layer 212 , such as a p-type doped GaN layer, between the gate G and the barrier layer 210 . In FIG4C , the HEMT device 200 ″ is also a normally-off HEMT device. Unlike the depletion-mode HEMT device 200 , the E-HEMT device 200 ″ includes a recess 213 in the barrier layer 210 below the gate G. The doped layer 212 or recess 213 blocks the two-dimensional electron gas 209 formed between the channel layer 208 and the barrier layer 210, thereby forming a normally-off E-HEMT device.

[0030] As shown in Figures 1 and 3, in one embodiment, the energy storage unit C1 of the integrated control device 1001 can be a capacitor. The switching transistor unit T1 and the driving transistor unit T2 are HEMT devices. One end of the energy storage unit C1 is connected to the node between the first drain D1 and the second gate G2 of the switching transistor unit T1, and the other end of the energy storage unit C1 is connected to the second drain D2. However, this is not limited to this embodiment. When the switching transistor unit T1 and the driving transistor unit T2 are other types of transistor devices, the other end of the energy storage unit C1 can also be connected to the second source S2.

[0031] In one embodiment, the switch transistor unit T1 and the driver transistor unit T2 in the integrated control device 1001 are selected from any two of the HEMT devices 200 ′, 200 ′, and 200 ″. The switch transistor unit T1, the driver transistor unit T2, and the energy storage unit C1 are each disposed on the carrier unit 1000 in the form of a bare chip or a package covered with protective adhesive. The integrated package 100 may include a packaging layer (not shown) covering the integrated control device 1001 and the carrier unit 1000 to form the integrated package 100. In another embodiment, the energy storage unit C1 may also be the same die or package as one of the switch transistor unit T1 and the driver transistor unit T2.

[0032] In one embodiment, the switching transistor unit T1 and the driving transistor unit T2 of the integrated control device 1001 can be formed on a common substrate 202 in the form of a monolithic substrate, integrating the switching transistor unit T1, the driving transistor unit T2, and / or the energy storage unit C1 into a single die. The method for forming the monolithic integrated control device 1001 includes: depositing a semiconductor stack on the substrate 202; selectively etching the semiconductor stack to expose a portion of the surface of the substrate 202 to separate the semiconductor stack into two active regions; forming a gate G, a drain D, and a source S on the two active regions to form the switching transistor unit T1 and the driving transistor unit T2; and forming the energy storage unit C1 on the substrate 202, the switching transistor unit T1, or the driving transistor unit T2. In this embodiment, the switching transistor unit T1, the driving transistor unit T2, and the energy storage unit C1 on the monolithic substrate can be disposed on a carrier unit 1000 and then covered with a packaging layer to form the integrated package 100. In another embodiment, the substrate 202 of the common substrate switch transistor unit T1, the driving transistor unit T2, and the energy storage unit C1 can replace the carrier unit 1000, that is, no additional carrier unit 1000 is required, and the packaging layer covers the common substrate switch transistor unit T1, the driving transistor unit T2, the energy storage unit C1 and the substrate 202 to form an integrated control device 1001. However, the transistors can also be bonded to the substrate 202 by wafer transfer to form the common substrate switch transistor unit T1 and / or the driving transistor unit T2. For example, the surface of the substrate 202 can include a bonding layer (not shown). The switch transistor unit T1 and / or the driving transistor unit T2 can be formed by forming a semiconductor stack on the same or different growth substrates, and then the semiconductor stack is transferred to the substrate 202 through one or more transfer, bonding and removal processes of the growth substrate, and then processed through subsequent processes to form the switch transistor unit T1 and / or the driving transistor unit T2. In one embodiment, the process may be performed to form the switch transistor unit T1 and / or the driver transistor unit T2 before the transfer bonding, and then the transfer bonding is performed to form the switch transistor unit T1 and / or the driver transistor unit T2 on the substrate 202 .

[0033] The integrated package 100 further includes a gate terminal P3, a drain terminal P2, and a source terminal P1 for external coupling. Furthermore, as shown in Figures 1 and 2, the integrated package 100 may further include a control signal output terminal P4. The control signal output terminal P4 is used to couple to the light-emitting unit ED. In Figure 2, each light-emitting unit ED may be a light-emitting diode die or a light-emitting diode package component. The semiconductor material of the light-emitting unit ED may be an AlInGaN series material AlxInyGa(1-xy)N or an AlInGaP series material AlxInyGa(1-xy)P, where 0≦x, y≦1; (x+y)≦1.

[0034] As shown in FIG2 , an integrated package 100 can be used in an active addressing system 10 for a display. The active addressing system 10 includes a gate driver 120, a source driver 110, a power supply 130, and a plurality of integrated packages 100. The source terminal of each integrated package 100 is coupled to the source driver 110 via a data line 111 to receive voltage data Vdata1-VdataN. The gate terminal P3 of each integrated package 100 is coupled to the gate driver 120 via a scan line 112 to receive scan signals SCAN1-SCANM, which enable the gate driver 120 to turn on or off the switching transistor unit T1 of each integrated package. The drain terminal P2 of each integrated package 100 is coupled to the power supply 130 via a power line 113, which provides a current and a drain voltage VDD to each integrated package 100. The integrated packages 100 can be arranged in an array on a backplane 1100 (see FIGS. 14 and 15 ), for example, and the number of integrated packages 100 is not limited. The switching transistor unit T1 of each integrated package 100 determines the switching of the driving transistor unit T2, thereby controlling the switching of the integrated control device 1001. Furthermore, when the driving transistor unit T2 is turned on, the energy storage unit C1 stores voltage data (Vdata) to stabilize the voltage of the second gate G2 of the driving transistor unit T2 during the switching process. Furthermore, after the scan signal (SCAN) pulse ends, the energy storage unit C1 can still keep the second gate G2 of the driving transistor unit T2 in the on state, thereby continuously providing current to the corresponding light-emitting unit ED.

[0035] In one embodiment, the light-emitting units ED corresponding to each integrated package 100 can emit different colors of light. For example, in FIG2 , the light-emitting units ED can emit red, green, or blue light. The control signal output terminal P4 of each integrated package 100 is electrically coupled to the light-emitting units ED of different colors to generate red, green, blue, or a combination thereof.

[0036] Specifically, the multiple integrated packages 100 can each introduce current through the drain terminal P2. The current then flows from the second drain D2 of the driving transistor unit T2 to the second source S2, and then through the second source S2 to the corresponding light-emitting unit ED, so that the multiple light-emitting units ED respectively generate corresponding red light, green light, blue light, or a combination of light colors.

[0037] Generally speaking, materials used to manufacture TFT backplanes include amorphous silicon (a-Si), low-temperature polysilicon (LTPS), and low-temperature polycrystalline oxide (LTPO). The main difference between the three is that a-Si TFT backplanes allow for large-area manufacturing using low-temperature processes, but their electron mobility is lower than the other two. While the electron mobility of LTPS and LTPO TFTs is higher than that of a-Si TFTs, it is lower than that of high electron mobility transistors (HEMTs). The electron mobility of the HEMT elements 200, 200', and 200" shown in Figures 4A to 4C is much higher than that of the aforementioned silicon-based transistors.

[0038] The switching transistor unit T1 and the driving transistor unit T2 can be two E-HEMT elements, two D-HEMT elements, or one E-HEMT element and one D-HEMT element. In this embodiment, an external IC controller can adjust signals, such as the signals of the scan line 112 and the data line 111, based on the types of the switching transistor unit T1 and the driving transistor unit T2. In one embodiment, the driving transistor unit T2 used for semi-active addressing can be an E-HEMT element. Please refer to Figures 14 and 15, which respectively illustrate a package structure according to an embodiment of the present application. Package structure 300 includes a backplate 1100, the integrated package 100 described above, and a light-emitting element ED. Package structure 300 can be a detailed partial structure of the active addressing system 10 of Figure 2. Backplate 1100 can be a circuit board or a glass substrate. In one embodiment, the integrated package 100 and the light-emitting element ED are disposed on opposite sides of the backplate 1100. Backplane 1100 includes a front surface 1100a and a back surface 1100b. Integrated package 100 is disposed on back surface 1100b of backplane 1100, and light-emitting element ED is disposed on front surface 1100a of backplane 1100. Integrated package 100 and light-emitting element ED are electrically connected via at least one conductive via 1101 extending through backplane 1100. For example, control signal output terminal P4 of integrated package 100 in FIG. 1 can be electrically connected to conductive via 1101. By disposing integrated package 100 and light-emitting element ED on opposite sides of backplane 1100, the number of light-emitting elements ED that can be configured on the front surface of backplane 1100 is increased, and the area unavailable for display is reduced, thereby improving the display quality.

[0039] As shown in FIG14 , the light-emitting unit ED can be an LED package component, comprising at least one LED die, or any number of LED dies connected in parallel or series to form an LED array light source. As shown in FIG15 , the LED package component of each light-emitting unit ED can comprise, for example, any number of LED dies connected in parallel or series, though the numbers can be the same or different, and each light-emitting unit ED can be controlled by an independent integrated device 100.

[0040] FIG5 illustrates a schematic diagram of an integrated package 100 according to FIG1 being applied to an active addressing system 10. Referring to FIG5 in conjunction with FIG1 , similar to the aforementioned embodiment, in this embodiment, each integrated package 100 includes a gate terminal P3, a drain terminal P2, a source terminal P1, and a control signal output terminal P4 for external coupling. The light-emitting unit ED includes multiple light-emitting sub-unit strings. The control signal output terminal P4 of each integrated package 100 is electrically connected to, for example, the anode of a light-emitting sub-unit string. Each light-emitting sub-unit string is connected in parallel, for example, with a common N-pole. In one embodiment, each light-emitting sub-unit string connected to each integrated package 100 includes three light-emitting sub-units, including a red light-emitting sub-unit R1, a green light-emitting sub-unit G1, and a blue light-emitting sub-unit B1, so that the light-emitting unit ED generates corresponding red, green, blue, or a combination thereof. The internal structure of the integrated package 100 and the active addressing system 10 are described in detail in FIG2 and will not be repeated here.

[0041] FIG6 illustrates a schematic diagram of an integrated package 101 employed in an active addressing system 10 according to another embodiment of the present application. Referring to FIG6 in conjunction with FIG1 , in this embodiment, the integrated package 101 is an all-in-one package, comprising a plurality of integrated control elements 1001. Similar to the aforementioned embodiment, each integrated control element 1001 comprises a switching transistor unit T1, a driving transistor unit T2, and an energy storage unit C1. For example, the integrated package 101 may be a four-in-one package, i.e., four integrated control elements 1001 are provided on the same carrier unit 1000. In other words, there are four switching transistor units T1, four driving transistor units T2, and four energy storage units C1. The integrated package 101 includes a common gate terminal P3 for external coupling, a common drain terminal P2, four source terminals P1, and four control signal output terminals P4. The shared gate terminal P3 is connected to the first gate G1 of each switching transistor unit T1 via a conductive wire. The shared drain terminal P2 is connected to the second drain D2 of each driving transistor unit T2 via a conductive wire. Each source terminal P1 is coupled to a data line 111 that provides a driving voltage. Each control signal output terminal P4 is coupled to a light-emitting unit ED. The internal structure of the integrated package 101 and the detailed description of the active addressing system 10 are similar to those in FIG2 and are not further described here.

[0042] Please refer to Figure 7, which is a schematic diagram of another embodiment of the integrated package 101 shown in Figure 6 being applied to the active addressing system 10. In this embodiment, the detailed structure of the all-in-one integrated package 101 has been described in detail in Figure 6 and will not be repeated here. The difference between this embodiment and Figure 6 is that the light-emitting unit ED is similar to Figure 5 and includes multiple light-emitting sub-unit strings. The difference between this embodiment and Figure 5 is that the control signal output terminal P4 of each integrated package 100 is electrically connected to multiple light-emitting sub-unit strings, for example, four light-emitting sub-unit strings. Thereby, the light-emitting unit ED generates corresponding red light, green light, blue light or a combination thereof. The detailed description of the internal structure of each integrated package 101 and the active addressing system 10 is similar to Figure 2 and will not be repeated here.

[0043] Please refer to FIG8 , which shows a schematic diagram of an integrated package 102 according to another embodiment of the present application. Unlike the integrated package 100 of FIG1 , the integrated package 102 further includes a light-emitting element ED disposed on the carrier unit 1000. The light-emitting element ED is coupled to the second source S2 of the driving transistor unit T2, and the integrated package 102 further includes a ground terminal GN coupled to the light-emitting element ED. The remaining internal structure of the integrated package 102 is similar to that of FIG1 and will not be further described here.

[0044] Similar to the aforementioned embodiment, the switch transistor unit T1 and the driver transistor unit T2 in the integrated control device 1001 are selected from any two of the HEMT devices 200 ′, 200 ′, and 200 ″ in FIG. 4A to FIG. 4C . Furthermore, the manner in which the switch transistor unit T1, the driver transistor unit T2, the light-emitting unit ED, and the energy storage unit C1 are integrated into the integrated package 102 , such as in the form of a bare die, a package, or a common substrate, is also similar to the aforementioned embodiment.

[0045] FIG9 is a schematic diagram illustrating an embodiment of the integrated package 102 shown in FIG8 being applied to an active addressing system 10. As shown in FIG9 and in conjunction with FIG8 , the integrated package 102 can be used in the active addressing system 10 for a display. Similar to FIG2 , the switching transistor unit T1 of each integrated package 102 can control the switching of the integrated control element 1001. Furthermore, the energy storage unit C1 can store voltage data to stabilize the voltage of the second gate G2 of the driving transistor unit T2 during switching, and maintain the second gate G2 of the driving transistor unit T2 in an on-state, thereby continuously providing current to the light-emitting unit ED in the integrated package 102 after the scan signal pulse ends. The internal structure of the integrated package 102 and the details of the active addressing system 10 are described in detail in FIG8 and will not be repeated here.

[0046] Please refer to Figures 10 and 11, where Figure 10 is a schematic diagram of an integrated package 103 according to another embodiment of the present application, and Figure 11 is a schematic diagram of an embodiment of the integrated package 103 shown in Figure 10 applied to a semi-active addressing system 20. Integrated package 103 includes an integrated control element 1001'. Integrated control element 1001' includes a driver transistor unit T3. Integrated package 103 may also include a carrier unit 1000, on which integrated control element 1001' and light-emitting unit ED are disposed. Driver transistor unit T3 includes a source S3, a drain D3, and a gate G3. Light-emitting unit ED is coupled to source S3. Integrated package 103 also includes a gate terminal P3 for external coupling, a drain terminal P2, and a ground terminal GN coupled to light-emitting unit ED. In Figure 11, each light-emitting unit ED may be a light-emitting diode die, including one or more light-emitting diode units.

[0047] As shown in FIG11 , the integrated package 103 can be used in a semi-active addressing system 20, which includes a gate driver 120 and a data bus 121. The drain terminal P2 of each integrated package 103 is coupled to the data bus 121, which provides voltage data Vdata1 to VdataN, via a data line 111. The gate terminal P3 of each integrated package 103 is coupled to the gate driver 120, which provides scan signals SCAN1 to SCANM, via a scan line 112. Multiple integrated packages 103 are arranged in an array on a backplane (not shown), for example, and the number of such packages is not limited. The gate driver 120 can turn on or off the driving transistor unit T3 of each integrated package via the gate terminal P3 to control the switching of the integrated control element 1001 ′, thereby determining the switching of the light-emitting unit ED. Furthermore, the light-emitting unit ED of each integrated package 103 is coupled to the ground terminal GN, allowing current to flow to the light-emitting unit ED via the driving transistor unit T3.

[0048] Similar to the aforementioned embodiment, the driving transistor unit T3 in the integrated control device 1001′ is selected from any one of the HEMT devices 200′, 200′, and 200″ in FIG. 4A to FIG. 4C . Furthermore, the manner in which the driving transistor unit T3 and the light-emitting element ED are integrated into the integrated package 103, such as in the form of a bare die, a package, or a common substrate, is also similar to the aforementioned embodiment.

[0049] As shown in Figure 11, in a semi-active matrix (semi-AM) addressing system 20 having the above-mentioned integrated package 103, the driving transistor unit T3 and the light emitting unit ED are respectively disposed on a carrier unit 1000. In Figure 11, the driving transistor unit T3 and the light emitting unit ED can be coupled in a one-to-one manner.

[0050] Please refer to Figures 12 and 13 in conjunction with Figure 11 . Figure 12 illustrates an integrated package 104 according to another embodiment of the present application. Figure 13 illustrates the integrated package 104 shown in Figure 12 being applied to a semi-active addressing system 20. In this embodiment, the integrated package 104 is an all-in-one package, comprising multiple integrated control elements 1001'. Similar to the above embodiment, each integrated control element 1001' includes a driving transistor unit T3. For example, the integrated package 104 may be a three-in-one package, that is, three integrated control elements 1001', namely, three switching transistor units T3, are provided on the same carrier unit 1000. The three switching transistor units T3 are coupled one-to-one to the three light-emitting units ED. The integrated package 104 includes a common drain terminal P2 for external coupling, a common ground terminal GN, and three gate terminals P3. The common drain terminal P2 is connected to the drain D3 of each driving transistor unit T3 via a conductive wire. The common ground terminal GN is connected to the cathode N1 of each light-emitting unit ED via a conductive wire. Each gate terminal P3 is coupled to a corresponding scan line 112 to turn one of the three light-emitting units ED on or off. The internal structure of the integrated package 104 and the semi-active addressing system 20 are described in detail in FIG. 11 above and will not be repeated here.

[0051] Furthermore, the plurality of light emitting units ED may include a red light emitting sub-unit R1 , a green light emitting sub-unit G1 , and a blue light emitting sub-unit B1 , so that the light emitting units ED generate corresponding red light, green light, blue light, or a combination thereof.

[0052] Because current glass metallization technology still faces technical bottlenecks, resulting in low yields and high costs, coupled with the high cost of TFT glass backplanes using LTPS switching technology, certain processes and parameters need to be adjusted to precisely control and drive the LED current. The integrated package of this application utilizes a new driver design to replace the traditional TFT glass backplane using LTPS switching technology, addressing these issues with traditional TFT backplanes. The integrated package of this application can be applied to drive systems with active (AM) matrix or semi-active (semi-AM) matrix selection, representing a new direction in display design.

[0053] In summary, although this application has been disclosed with reference to the embodiments described above, they are not intended to limit the present application. Persons skilled in the art will readily be able to make various modifications and alterations without departing from the spirit and scope of this application. Therefore, the scope of protection of this application shall be determined by the scope defined in the appended claims.

Claims

1. An integrated package comprising: Integrated control elements, including: A switch transistor unit, comprising a first source, a first drain and a first gate; a driving transistor unit comprising a second source, a second drain, and a second gate, wherein the second gate is coupled to the first drain; and an energy storage unit, coupled between the second drain and the second gate; The integrated package further includes a gate terminal, a drain terminal, and a source terminal for external coupling. 2 . The integrated package according to claim 1 , further comprising a carrier unit, wherein the switch transistor unit, the drive transistor unit and the energy storage unit are located on the carrier unit. 3 . The integrated package as claimed in claim 2 , further comprising a light emitting unit disposed on the carrier unit and coupled to the second source of the driving transistor unit, and the integrated package further comprising a ground terminal coupled to the light emitting element. 4 . The integrated package as claimed in claim 1 , further comprising a control signal output terminal, wherein the control signal output terminal is configured to be coupled to the light emitting unit. 5 . The integrated package as claimed in claim 4 , wherein the light emitting unit and the integrated package are respectively disposed on opposite sides of a back plate to form a package structure. The integrated package as claimed in claim 4 , wherein the light emitting unit comprises a plurality of light emitting sub-units.

7. The integrated package as described in claim 1, wherein the source terminal is used to couple to a data line providing a driving voltage, the gate terminal is used to couple to a scan line, and the drain terminal is used to couple to a power line providing a drain voltage, wherein there are multiple switching transistor units, multiple driving transistor units, and multiple energy storage units, respectively, the switching transistor units are coupled in parallel to the scan line, the driving transistor units are coupled to the power line, and each of the driving transistor units further includes a control signal output terminal for coupling to a light-emitting unit.

8. An integrated package comprising: An integrated control element, formed on the carrier unit, includes: a driving transistor unit, comprising a source, a drain, and a gate; and a light emitting unit coupled to the source; The integrated package further includes a gate terminal, a drain terminal and a terminal coupled to the emitter. Ground terminal of the optical unit. 9 . The integrated package according to claim 8 , further comprising a carrier unit, wherein the driving transistor unit and the light emitting unit are disposed on the carrier unit. 10 . The integrated package as claimed in claim 8 , wherein the driving transistor unit and the light emitting unit are coupled in a one-to-one manner.

11. The integrated package as claimed in claim 8, wherein the drain terminal is used to couple to a data line providing a driving voltage, the gate terminal is used to couple to a scan line, there are multiple driving transistor units and multiple light-emitting units, the driving transistor units are coupled in parallel to the data line, and the sources of the driving transistor units are respectively coupled to the light-emitting units.

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