Etching solution and preparation method of semiconductor device

Abstract

The invention discloses an etching solution and a preparation method of a semiconductor device, the etching solution is used for etching silicon nitride, the etching solution comprises a phosphoric acid solution and an organic solvent, and the organic solvent comprises one of an allyltrimethoxysilane organic solvent and a vinyltrimethoxysilane organic solvent. The yield and the performance of the semiconductor device prepared by applying the etching solution provided by the invention are remarkably improved.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and in particular relates to a method for preparing an etching solution and a semiconductor device. Background Art

[0002] In the transistor structure in the semiconductor device, a sidewall structure is usually provided. The sidewall structure usually uses a material with a low dielectric constant to isolate the gate and the source and drain to reduce the parasitic capacitance in the transistor structure, and air is considered to be the most ideal low dielectric constant material. Therefore, the use of air sidewalls can greatly reduce the parasitic capacitance of the device and effectively improve the operating speed of the device and circuit. However, during the preparation process, the air sidewalls are prone to over-etching other structures in the semiconductor device, thereby affecting the yield and performance of the semiconductor device. Summary of the invention

[0003] The purpose of this application is to at least solve the problem of how to improve the performance of semiconductor devices. This purpose is achieved through the following technical solutions:

[0004] The first aspect of the present application provides an etching solution for etching silicon nitride, the etching solution comprising:

[0005] A phosphoric acid solution and an organic solvent, wherein the organic solvent includes one of an allyltrimethoxysilane organic solvent and a vinyltrimethoxysilane organic solvent.

[0006] In the above embodiment, the etching liquid is used to etch silicon nitride. The etching liquid has a relatively high etching selectivity for silicon nitride and silicon dioxide, and the etching liquid has a relatively high etching selectivity for silicon nitride and hafnium dioxide, so that the etching rate of silicon dioxide and hafnium dioxide can be reduced while removing silicon nitride, thereby reducing the adverse effects on silicon dioxide and hafnium dioxide, and helping to maintain the thickness of the film layer made of silicon dioxide or hafnium dioxide.

[0007] The second aspect of the present application also provides a method for preparing a semiconductor device, comprising:

[0008] providing a substrate;

[0009] forming a transistor structure on one side of the substrate, the transistor structure comprising a sacrificial sidewall structure located on one side of the substrate, a first functional portion, and a second functional portion, wherein at least a portion of the sacrificial sidewall structure is located between the first functional portion and the second functional portion;

[0010] The etching solution provided in the first aspect of the present application is brought into contact with the sidewall sacrificial structure to remove the sidewall sacrificial structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present application. Moreover, the same reference numerals are used throughout the accompanying drawings to represent the same components. In the accompanying drawings:

[0012] Figure 1 It is a flow chart of a method for preparing a semiconductor device provided by the present application;

[0013] Figure 2 It is a schematic diagram of a transistor structure in a method for preparing a semiconductor device provided in the present application;

[0014] Figure 3 yes Figure 2 Section along N-N';

[0015] Figure 4 yes Figure 2 Section along the middle line M-M';

[0016] Figure 5 It is a cross-sectional view of a transistor structure along the N-N' viewing angle during an etching process in a method for preparing a semiconductor device provided in the present application;

[0017] Figure 6 It is a cross-sectional view of a transistor structure along the M-M' viewing angle during an etching process in a method for preparing a semiconductor device provided in the present application;

[0018] Figures 7 to 9 It is a schematic diagram of the structural changes of a transistor structure during the preparation process in a method for preparing a semiconductor device provided in the present application;

[0019] Figures 10 to 19 yes Fig. 9 Schematic diagram of the structural change of the cross section along the P-P' in step 412 to step 421;

[0020] Figures 20 to 29 yes Fig. 9 A schematic diagram of the structural change of the cross section along the line Q-Q' from step 412 to step 421;

[0021] Fig.30 yes Figure 5 The cross section shown is a schematic structural diagram after the side wall sacrificial structure is removed;

[0022] Fig.31 yes Figure 6 The cross section shown is a schematic structural diagram after the side wall sacrificial structure is removed;

[0023] Fig.32 yes Fig. 9A cross section along the PP' line is a schematic structural diagram of another method for preparing a semiconductor device provided in the present application after the sacrificial structure of the sidewall is removed;

[0024] Figure 33 to Figure 34 It is a schematic diagram of a top view of a structural change in another method for preparing a semiconductor device provided by the present application;

[0025] Fig.35 yes Fig. 9 A cross section along the PP' line is a schematic structural diagram of another method for preparing a semiconductor device provided in the present application after the sacrificial structure of the sidewall is removed;

[0026] Figure 36 to Figure 37 This is a schematic diagram of the structural changes of a transistor structure in another method for preparing a semiconductor device provided in the present application.

[0027] The reference numerals are as follows:

[0028] 1. Base; 10. Substrate; 101. First part; 102. Second part; 11. Source region; 12. Drain region; 13. Channel region; 14. Shallow trench isolation structure; 2. Transistor structure; 21. Sidewall sacrificial structure; 211. First sidewall sacrificial structure; 212. Second sidewall sacrificial structure; 22. First functional part; 23. Second functional part; 24. Channel layer stack; 241. Channel layer; 242. Sacrificial layer; x. First direction; y. Second direction; z. Third direction; 25. Source and drain function Energy part; 251, source part; 252, drain part; 26, gate functional part; 27, gate dielectric layer; 28, first dielectric layer; 29, first channel; 30, second dielectric layer; 31, second channel; 32, sacrificial layer; 33, dummy gate; 34, side wall sacrificial peripheral structure; B1, first surface; B2, second surface; 1021, source part formation area; 1022, drain part formation area; L1, first gap; L2, second gap; 35, inner side wall sacrificial structure; 36, air side wall; k, fourth direction. DETAILED DESCRIPTION

[0029] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0030] It should be understood that the terms used in the text are only for the purpose of describing specific example embodiments, and are not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms "one", "an" and "said" as used in the text may also be meant to include plural forms. The terms "include", "comprise", "contain", and "have" are inclusive, and therefore specify the existence of stated features, steps, operations, elements and / or parts, but do not exclude the existence or addition of one or more other features, steps, operations, elements, parts, and / or combinations thereof. The method steps, processes, and operations described herein are not interpreted as necessarily requiring them to be performed in the specific order described or illustrated, unless the execution order is clearly indicated. It should also be understood that additional or alternative steps may be used.

[0031] Although the terms first, second, third, etc. can be used in the text to describe multiple elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms can only be used to distinguish an element, component, region, layer or section from another region, layer or section. Unless the context clearly indicates, terms such as "first", "second" and other numerical terms do not imply order or sequence when used in the text. Therefore, the first element, component, region, layer or section discussed below can be referred to as the second element, component, region, layer or section without departing from the teaching of the example embodiments.

[0032] For ease of description, spatial relative terms may be used herein to describe the relationship of one element or feature relative to another element or feature as shown in the figure, such as "inside", "outside", "inner side", "outer side", "below", "below", "above", "above", etc. Such spatial relative terms are intended to include different orientations of the device in use or operation in addition to the orientation depicted in the figure. For example, if the device in the figure is turned over, then the elements described as "below other elements or features" or "below other elements or features" will subsequently be oriented as "above other elements or features" or "above other elements or features". Therefore, the example term "below..." can include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or in other directions) and the spatial relative descriptors used in the text are interpreted accordingly.

[0033] The present application provides an etching solution for etching silicon nitride, the etching solution comprising:

[0034] A phosphoric acid solution and an organic solvent, wherein the organic solvent includes one of an allyltrimethoxysilane organic solvent and a vinyltrimethoxysilane organic solvent.

[0035] In the above embodiment, the etching liquid is used to etch silicon nitride. The etching liquid has a relatively high etching selectivity for silicon nitride and silicon dioxide, and the etching liquid has a relatively high etching selectivity for silicon nitride and hafnium dioxide, so that the etching rate of silicon dioxide and hafnium dioxide can be reduced while removing silicon nitride, thereby reducing the adverse effects on silicon dioxide and hafnium dioxide, and helping to maintain the thickness of the film layer made of silicon dioxide or hafnium dioxide.

[0036] The etching solution can be used to etch and remove the sacrificial sidewall structure of silicon nitride in the semiconductor device, thereby forming an air sidewall. The dielectric constant of air is lower than that of silicon nitride, thereby further reducing the parasitic capacitance between the structures on both sides of the air sidewall, so as to further improve the yield of the semiconductor device. At the same time, when removing the sacrificial sidewall structure, the thickness of the film layer made of silicon dioxide and hafnium dioxide can be included to reduce the impact on other film layers in the semiconductor device, thereby improving the yield and performance of the semiconductor device.

[0037] Specifically, the etching solution may include a phosphoric acid solution, which has a high etching rate for silicon nitride, so hot phosphoric acid solution is used as the main material of the etching solvent for removing silicon nitride materials. Secondly, an organic solvent may be added to the etching solution so that when the etching solution etches and removes the sacrificial structure of the side wall, the etching rate of silicon dioxide, hafnium dioxide film layer, silicon and germanium silicon is low, thereby reducing the damage to silicon dioxide, hafnium dioxide film layer, silicon and germanium silicon when removing the silicon nitride film layer.

[0038] As shown in Table 1, when the organic solvent includes one of allyltrimethoxysilane organic solvent and vinyltrimethoxysilane organic solvent, the etching rate of the etching solution on silicon dioxide and hafnium dioxide can be reduced, so that the etching rate of the etching solution on silicon nitride is much greater than the etching rate on silicon dioxide and hafnium dioxide, thereby helping to ensure the thickness and yield of the silicon dioxide and hafnium dioxide film layers. Among them, the etching rate selectivity of the etching solution for silicon nitride and silicon dioxide can be as high as 2900, and the etching rate selectivity of the etching solution for silicon nitride and hafnium dioxide can be as high as 1800.

[0039]

[0040] Table 1: Etching rate or etching selectivity of etching solution for different materials

[0041] In a feasible implementation, the concentration of the phosphoric acid solution is in the range of 80%-90%, the purity of the organic solvent is in the range of 90%-99%, and the concentration is in the range of 0.1%-10%.

[0042] Specifically, the concentration of the phosphoric acid solution can be 80%, 82%, 83%, 85%, 89%, 90%, etc., which is not particularly limited in this application. The purity of the organic solvent can be 90%, 91%, 93%, 94%, 96%, 99%, and the concentration can be 0.1%, 0.5%, 0.8%, 1.0%, 1.5%, 2.6%, 3.9%, 5.8%, 6.7%, 7.5%, 8.8%, 9.0%, 10%, etc., which is not particularly limited in this application.

[0043] Preferably, the concentration range may be 0.1%-1%.

[0044] like Figure 1 As shown, according to an embodiment of the present application, a method for preparing a semiconductor device is also proposed, comprising:

[0045] S200 , providing a substrate 1 .

[0046] S400, such as Figure 2 , Figure 3 and Figure 4 As shown, a transistor structure 2 is formed on one side of a substrate 1 , and the transistor structure 2 includes a sidewall sacrificial structure 21 , a first functional portion 22 , and a second functional portion 23 located on one side of the substrate 1 , and at least a portion of the sidewall sacrificial structure 21 is located between the first functional portion 22 and the second functional portion 23 .

[0047] Specifically, the transistor structure 2 may be a main structure for forming a stacked gate-all-around nanosheet field effect transistor (GAA NSFET), or a main structure for forming a common transistor, which is not particularly limited in the present application.

[0048] S600, such as Figure 5 and Figure 6 As shown, any one of the etching solutions provided in the above embodiments of the present application is brought into contact with the sacrificial sidewall structure 21 to remove the sacrificial sidewall structure 21 .

[0049] In the method for preparing the semiconductor device provided by the present application, a sacrificial sidewall structure 21 is formed between the first functional part 22 and the second functional part 23 to achieve mutual isolation between the structures in the semiconductor device, thereby reducing the parasitic capacitance in the semiconductor device. The sacrificial sidewall structure 21 is subsequently removed by etching with an etching solution, thereby forming an isolation gap between the first functional part 22 and the second functional part 23, and there is air in the isolation gap. The isolation gap and the air inside it can form an air sidewall 36. Since the dielectric constant of air is low, the parasitic capacitance in the semiconductor device can be greatly reduced, and the working speed of the semiconductor device can be effectively improved. The etching liquid has a faster etching rate for silicon nitride and a slower etching rate for materials such as silicon dioxide and hafnium dioxide. Therefore, a side wall sacrificial structure 21 made of silicon nitride can be used, and the materials of the first functional part 22 and the second functional part 23 include silicon dioxide or hafnium dioxide. Under the etching action of the etching liquid, the etching selectivity of the side wall sacrificial structure 21 and the first functional part 22 and the second functional part 23 is relatively large, so that the damage to the internal structure of the semiconductor device can be greatly reduced in the process of removing the side wall sacrificial structure 21, which helps to further improve the preparation yield and performance of the semiconductor device.

[0050] In the method for preparing a semiconductor device provided in the present application, the existing preparation process of the semiconductor device can be continued to be used, and a process of removing the side wall sacrificial structure 21 using any one of the etching solutions provided in the above-mentioned embodiments of the present application can be added to the existing preparation process to form an air side wall 36. The preparation process is simple and low-cost.

[0051] In one possible implementation, the transistor may be a stacked gate-all-around nanosheet field effect transistor (GAANSFET).

[0052] Specifically, Figures 2 to 3 As shown, the transistor structure 2 includes a channel layer stack portion 24, a source-drain functional portion 25, a gate functional portion 26, a gate dielectric layer 27 and a first dielectric layer 28. The channel layer stack portion 24 is located on one side of the substrate 1. The channel layer stack portion 24 includes a plurality of channel layers 241 arranged along a first direction x. The channel layer 241 includes a first end A1, a middle section A2 and a second end A3 arranged along a second direction y. The first direction x is perpendicular to the second direction y. The source-drain functional portion 25 includes a source portion 251 and a drain portion 252 located on both sides of the channel layer stack portion 24 along the second direction y. The gate functional portion 26 surrounds the middle section A2 in a direction surrounding the second direction y, and the gate functional portion 26 is protruded from the source-drain functional portion 25 in a direction away from the substrate 1. The gate dielectric layer 27 is located between the middle section A2 and the gate functional portion 26 and between the source-drain functional portion 25 and the gate functional portion 26. The first dielectric layer 28 is located on the side of the source-drain functional portion 25 away from the substrate 1.

[0053] The stacked gate-all-around nanosheet field-effect transistor (GAA NSFET) can significantly suppress the short channel effect, has better gate control characteristics, and effectively improves the current driving performance of semiconductor devices.

[0054] In the above embodiment, the side wall sacrificial structure 21 includes a first side wall sacrificial structure 211 and a second side wall sacrificial structure 212 which are continuously arranged. The first side wall sacrificial structure 211 is located between the gate dielectric layer 27 and the source portion 251 and between the gate dielectric layer 27 and the drain portion 252; the second side wall sacrificial structure 212 is located on both sides of the gate functional portion 26 along the second direction y, and is located between the gate dielectric layer 27 and the first dielectric layer 28.

[0055] The first functional portion 22 includes a first dielectric layer 28 , and may further include a source portion 251 and a drain portion 252 , and the second functional portion 23 includes a gate dielectric layer 27 .

[0056] In the above embodiment, the material of the source portion 251 and the drain portion 252 may include silicon germanium or silicon, the material of the first dielectric layer 28 may include silicon dioxide, and the material of the gate dielectric layer 27 may include hafnium dioxide.

[0057] Since the etching liquid has a relatively high etching selectivity for silicon nitride and silicon dioxide, and the etching liquid has a relatively high etching selectivity for silicon nitride and hafnium dioxide, that is, under the action of the etching liquid, the etching selectivity for the side wall sacrificial structure 21 and the first functional part 22 is relatively high, and the etching selectivity for the side wall sacrificial structure 21 and the second functional part 23 is relatively high, and the etching selectivity for the side wall sacrificial structure 21 and the substrate 1 is relatively high. When removing the first side wall sacrificial structure 211, the etching liquid contacts and reacts with the first side wall sacrificial structure 211, and the reaction speed is greater than the reaction speed of the etching liquid with the substrate 1, the source and drain functional part 25, and the gate dielectric layer 27 arranged around the first side wall sacrificial structure 211. Therefore, in the process of removing the first side wall sacrificial structure 211, the etching liquid is not easy to cause damage to the substrate 1, the source and drain functional part 25, and the gate dielectric layer 27, which can improve the yield of the semiconductor device. In the process of removing the second side wall sacrificial structure 212, the etching liquid contacts and reacts with the second side wall sacrificial structure 212, and the reaction speed is greater than the reaction speed of the etching liquid with the first dielectric layer 28 and the gate dielectric layer 27 arranged around the second side wall sacrificial structure 212. Therefore, in the process of removing the second side wall sacrificial structure 212, the etching liquid is not easy to damage the first dielectric layer 28 and the gate dielectric layer 27, which can improve the yield of the semiconductor device.

[0058] In the conventional GAA NSFET, the area from the gate functional part 26 to the source-drain functional part 25 and from the gate functional part 26 to the first dielectric layer 28 is greatly increased, resulting in a sharp increase in the parasitic capacitance of the GAA NSFET, which will greatly reduce the operating speed of the circuit. The parasitic capacitance in the semiconductor device can be reduced by using a material with a lower dielectric constant as the sidewall structure. Therefore, in the present application, an air sidewall 36 is formed by forming a first sidewall sacrificial structure 211 and a second sidewall sacrificial structure 212, and removing the first sidewall sacrificial structure 211 and the second sidewall sacrificial structure 212 by etching liquid, that is, using air to isolate the gate functional part 26 from the source-drain functional part 25, and the gate functional part 26 from the first dielectric layer 28. Air is considered to be an ideal low dielectric constant material, which can reduce the parasitic capacitance in the semiconductor device, effectively improve the operating speed of the semiconductor device and the circuit using the semiconductor device, that is, improve the performance of the semiconductor device.

[0059] Specifically, Figure 2 and Figure 4 As shown, the base 1 includes a substrate 10 and a shallow trench isolation structure 14. The shallow trench isolation structure 14 includes a trench structure formed on the substrate 10 and an isolation material filled in the trench structure. The shallow trench isolation structure 14 can achieve mutual isolation between adjacent devices.

[0060] Specifically, Figure 2 As shown, the substrate 10 includes a first portion 101 and a second portion 102 , and the shallow trench isolation structure 14 and the second portion 102 are located on the same side of the first portion 101 and are adjacent to each other.

[0061] During the preparation of the transistor structure 2, forming a channel layer stack portion 24 on one side of the substrate 1 includes:

[0062] S411, such as Figure 7 As shown, a stacked epitaxy is formed on one side of the substrate 10, and the stacked epitaxy includes a channel layer 241 and a sacrificial layer 32 alternately arranged in a direction away from the substrate 10 (a first direction x). Then, the stacked epitaxy is patterned, as shown in FIG. Figure 8 As shown, at least one channel layer stack portion 24 is formed. At the same time, the substrate 10 can be patterned to form a first portion 101 and a second portion 102, wherein the second portion 102 is located on one side of the first portion 101, and the channel layer stack portion 24 is located on a side of the second portion 102 away from the first portion 101. Fig. 9 As shown, a shallow trench isolation structure 14 can be formed on one side of the substrate 10 at the same time, and the shallow trench isolation structure 14 is arranged around at least a portion of the edge of the second portion 102. The shallow trench isolation structure 14 can achieve electrical isolation of adjacent structures in the semiconductor device.

[0063] S412, the channel layer stack portion 24 includes a first end, a middle portion, and a second end arranged along the second direction y, and the middle portion includes a first surface and a second surface arranged along the third direction z. Fig.10 and Fig. 20 As shown, a dummy gate 33 is formed on the side of the channel layer stack portion 24 facing away from the substrate 10 , and the dummy gate 33 covers the side surface of the middle portion of the channel layer stack portion 24 facing away from the substrate 10 , as well as the first surface B1 and the second surface B2 .

[0064] S413, such as Fig.10 and Fig. 20 As shown, a sacrificial peripheral structure 34 is formed on both sides of the dummy gate 33 along the second direction y, and the sacrificial peripheral structure 34 exposes a portion in the first end and a portion in the second end. Fig.11 and Fig.21 As shown, the portion of the channel layer stack portion 24 not covered by the sacrificial peripheral structure 34 and the dummy gate 33 is removed, thereby forming a source forming region 1021 and a drain forming region 1022 on the surface of the second portion 102 away from the first portion 101 .

[0065] Specifically, the sidewall sacrificial peripheral structure 34 also covers a portion in the first end and a portion in the second end.

[0066] S414, such as Fig.12 and Fig. 22 As shown, a portion of the sacrificial layer 32 located at the first end is removed to form a first gap L1 , and a portion of the sacrificial layer 32 located at the second end is removed to form a second gap L2 .

[0067] S415, such as Fig.13 and Fig.23 As shown, an inner sidewall sacrificial structure 35 is formed in the first gap L1 and the second gap L2. The inner sidewall sacrificial structure 35 is continuously arranged with the sidewall sacrificial peripheral structure 34 to form a first sidewall sacrificial structure 211. The first sidewall sacrificial structure 211 includes a portion of the sidewall sacrificial peripheral structure 34 located on both sides of the channel layer stack portion 24 along the third direction z.

[0068] In the above steps, an outer sidewall sacrificial structure (not shown in the figure) may also be formed on both sides of the dummy gate 33 along the second direction y and on the side of the sidewall sacrificial peripheral structure 34 away from the substrate 10, and the outer sidewall sacrificial structure and the sidewall sacrificial peripheral structure 34 are continuously arranged to form a second sidewall sacrificial structure 212, and the second sidewall sacrificial structure 212 includes a portion of the sidewall sacrificial peripheral structure 34 located on the side of the channel layer stack portion 24 away from the substrate 10. Alternatively, a portion of the sidewall sacrificial peripheral structure 34 located on the side of the channel layer stack portion 24 away from the substrate 10 directly serves as the second sidewall sacrificial structure 212.

[0069] S416, such as Fig.14 and Fig.24 As shown, the source portion 251 is formed in the source portion formation region 1021 , and the drain portion 252 is formed in the drain portion formation region 1022 .

[0070] S417, such as Fig.15 and Fig.25 As shown, a first dielectric layer 28 is formed on the side of the dummy gate 33, the second sacrificial spacer structure 212, the source portion 251, and the drain portion 252 facing away from the substrate 10, and the dummy gate 33 and the second sacrificial spacer structure 212 are exposed on the surface of the first dielectric layer 28 facing away from the substrate 10. Specifically, the dummy gate 33 and the second sacrificial spacer structure 212 can be exposed on the surface of the first dielectric layer 28 facing away from the substrate 10 by a chemical mechanical polishing process (CMP).

[0071] S418, such as Fig.16 and Fig.26 As shown, the dummy gate 33 is removed.

[0072] S419, such as Fig.17 and Fig. 27 As shown, the sacrificial layer 32 located in the middle portion is removed.

[0073] S420, such as Fig.18 and Fig.28 As shown, a gate dielectric layer 27 is formed, and the gate dielectric layer 27 covers the surface of the channel layer 241 located in the middle portion and the surfaces of the second sacrificial spacer structure 212 and the first sacrificial spacer structure 211 facing the middle portion.

[0074] S421, such as Fig.19 and Fig.29 As shown, a gate functional portion 26 is formed, and a second dielectric layer 30 is formed on the gate functional portion 26 , the gate dielectric layer 27 , the second sacrificial spacer structure 212 , and the first dielectric layer 28 on a side facing away from the substrate 10 .

[0075] Specifically, the first sacrificial sidewall structure 211 and the second sacrificial sidewall structure 212 are disposed in a continuous manner at the sacrificial sidewall peripheral structure 34, that is, the sacrificial sidewall peripheral structure 34 includes the first sacrificial sidewall structure 211 at the first surface B1 and the second surface B2 of the channel layer stack 24, and also includes the second sacrificial sidewall structure 212 at the first surface B1 and the second surface B2 of the channel layer stack 24, and includes the second sacrificial sidewall structure 212 at the side of the channel layer stack 24 away from the substrate 10. Therefore, after any one of the first sacrificial sidewall structure 211 and the second sacrificial sidewall structure 212 fully reacts with a sufficient amount of etching solution, the other one can also gradually contact and react with the etching solution.

[0076] In a feasible implementation manner, step S600 includes:

[0077] S611, such as Figure 5 and Figure 6 As shown, a first channel 29 is formed in the substrate 1 , the first channel 29 penetrates the substrate 1 , and the first channel 29 exposes the sacrificial structure 21 of the sidewall.

[0078] S612, Figure 5 and Figure 6 The middle arrow shows the injection direction of the etching liquid. The etching liquid is injected into the first channel 29 so that the etching liquid contacts the side wall sacrificial structure 21. Fig.30 and Fig.31 shown.

[0079] In the above implementation mode, if Figure 5 As shown, the orthographic projection of the first channel 29 in the thickness direction of the substrate 1 at least partially overlaps with the orthographic projection of the sacrificial sidewall structure 21 in the thickness direction of the substrate 1. Specifically, the orthographic projection of the first channel 29 in the thickness direction of the substrate 1 can cover the orthographic projection of the sacrificial sidewall structure 21 in the thickness direction of the substrate 1, so that the first channel 29 exposes part of the sacrificial sidewall structure 21. By injecting etching liquid into the first channel 29, the etching liquid can react with the sacrificial sidewall structure 21 to remove the sacrificial sidewall structure 21. Since the first sacrificial sidewall structure 211 and the second sacrificial sidewall structure 212 are arranged continuously, after the etching liquid is injected into the first channel 29, the etching liquid can fully react with the first sacrificial sidewall structure 211 and the second sacrificial sidewall structure 212, so as to remove the sacrificial sidewall structure 21 and form an air sidewall 36.

[0080] In the above embodiment, the portion of the substrate 1 opposite to the channel layer stack portion 24 can be completely removed, that is, the portion of the substrate 1 covered by the positive projection of the channel layer stack portion 24 on the substrate 1 can be removed, thereby reducing the parasitic capacitance between the gate functional portion 26 and the underlying substrate 1 to further improve the performance of the semiconductor device.

[0081] Specifically, Fig.31 As shown, the first channel 29 penetrates the portion of the substrate 1 where the first portion 101 and the second portion 102 are stacked.

[0082] Specifically, the first channel 29 may completely remove the substrate 10, or Fig.31 As shown, a portion of the substrate 10 below the source / drain functional portion 25 may be retained.

[0083] In a feasible implementation manner, the first channel 29 is formed by using a dry etching process and / or a wet etching process.

[0084] Specifically, a part or all of the first portion 101 may be removed by a dry etching process, and the second portion 102 may be removed by a wet etching process. The etching solution used in the wet etching process may include a tetramethylammonium hydroxide solution.

[0085] In the process of removing the second portion 102 by the wet etching process, the source portion 251 , the drain portion 252 and the gate dielectric layer 27 are used as etching stop layers.

[0086] In a feasible implementation manner, the gate functional portion 26 and the second sacrificial spacer structure 212 are exposed on the surface of the first dielectric layer 28 facing away from the substrate 1; step S600 includes:

[0087] S621 , injecting etching liquid from the side of the second sacrificial spacer structure 212 facing away from the substrate 1 , so that the etching liquid contacts the second sacrificial spacer structure 212 .

[0088] In the above embodiment, the first dielectric layer 28 is used to achieve planarization of the semiconductor device.

[0089] In the above implementation mode, if Fig.15 and Fig.25 As shown, in step S417, the surface of the first dielectric layer 28 facing away from the substrate 10 exposes the dummy gate 33 and the second sacrificial spacer structure 212. Fig.16 and Fig.26 As shown, the dummy gate 33 is removed in step S418, and the gate functional portion 26 is formed at the position of the original dummy gate 33 in step S421, and the first dielectric layer 28 exposes the gate functional portion 26 and the second sacrificial spacer structure 212. Fig.19 and Fig.29 As shown, after the gate functional portion 26 is formed in step S421 and before the second dielectric layer 30 is formed, the side of the second sacrificial sidewall structure 212 facing away from the substrate 10 is exposed to the outside, so that the sacrificial sidewall structure 21 can be removed at this time, and it is only necessary to directly contact the etching liquid with the side of the second sacrificial sidewall structure 212 facing away from the substrate 10. Since the first sacrificial sidewall structure 211 and the second sacrificial sidewall structure 212 are continuously arranged, they can be removed together, thereby forming an air sidewall 36. The cross section is shown in FIG. Fig.32 shown.

[0090] In the above embodiment, the air sidewall 36 is formed first, and then the second dielectric layer 30 is formed. When the second dielectric layer 30 is formed, part of the second dielectric layer 30 may be located at an end of the sidewall of the air sidewall 36 away from the substrate 10, such as Fig.32 shown.

[0091] The above embodiment is simple to operate, thereby reducing the preparation cost. At this time, the substrate 1, the source-drain functional part 25, the first dielectric layer 28 and the gate dielectric layer 27 serve as etching stop layers. Since the material of the sidewall sacrificial structure 21 is usually made of silicon nitride, at this time, the material of the source part 251 and the drain part 252 includes germanium silicon or silicon, the material of the first dielectric layer 28 includes silicon dioxide, and the material of the gate dielectric layer 27 includes hafnium dioxide. The etching rate of the etching liquid for silicon nitride is greater than the etching rate for silicon dioxide, silicon and hafnium dioxide, which helps to ensure the thickness and yield of the silicon dioxide, silicon and hafnium dioxide film layers, that is, in the process of removing the sidewall sacrificial structure 21, the etching liquid is not easy to damage the substrate 1, the source-drain functional part 25, and the gate dielectric layer 27, which can improve the yield of the semiconductor device.

[0092] In a feasible implementation, a portion of the sacrificial spacer structure 21 is located on both sides of the channel layer stack portion 24 along the third direction z, the third direction z is perpendicular to the second direction y, and the third direction z is perpendicular to the first direction x. Fig.29 As shown, the preparation method further includes: forming a second dielectric layer 30 on the side of the first dielectric layer 28 away from the substrate 1, and the second dielectric layer 30 covers and wraps the transistor structure 2. Step S600 includes: S631, as shown in Fig.33 As shown, a second channel 31 is formed in the second dielectric layer 30 along the third direction z and penetrates the second dielectric layer 30. The second channel 31 exposes the sidewall sacrificial structure 21. Fig.33 and Fig.34 As shown, the etching liquid is injected into the second channel 31 so that the etching liquid contacts the sacrificial sidewall structure 21. After the sacrificial sidewall structure 21 is removed by etching, an air sidewall 36 is formed. Fig.35 shown.

[0093] The second dielectric layer 30 is made of silicon dioxide. Under the etching action of the etching solution, the etching selectivity between the sidewall sacrificial structure 21 and the second dielectric layer 30 is relatively large, so that the second dielectric layer 30 is not easily damaged when the sidewall sacrificial structure 21 is etched away.

[0094] In the above embodiment, the second dielectric layer 30 is used to cover the gate functional portion 26 , the gate dielectric layer 27 , the second spacer sacrificial structure 212 and the surface of the first dielectric layer 28 facing away from the substrate 10 , and is arranged around the circumference of the transistor structure 2 along the direction around the first direction x.

[0095] In the above embodiment, a second channel 31 is formed in the second dielectric layer 30 along the third direction z and penetrates the second dielectric layer 30, and the second channel 31 exposes the sidewall sacrificial structure 21, so that the etching liquid can be injected into the second channel 31 to make the etching liquid contact with the sidewall sacrificial structure 21. Specifically, the second channel 31 can be formed by a dry etching process.

[0096] In the above embodiment, the substrate 1, the source-drain functional portion 25, the gate dielectric layer 27 and the second dielectric layer 30 are used as etching barrier layers. Under the action of the etching liquid, the etching selectivity of the side wall sacrificial structure 21 and the substrate 1, the source-drain functional portion 25, the gate dielectric layer 27 and the second dielectric layer 30 is relatively large. Therefore, in the process of removing the side wall sacrificial structure 21, the etching liquid is not easy to cause damage to the substrate 1, the source-drain functional portion 25, the gate dielectric layer 27 and the second dielectric layer 30, which can improve the yield of the semiconductor device.

[0097] In the above embodiment, although an additional step of drilling is required to form the second channel 31, the etching process of the second channel 31 and the side wall sacrificial structure 21 can be performed after the semiconductor structure is prepared, without changing the original process, thereby reducing the difficulty and cost of preparation.

[0098] In another possible implementation, if Fig.36 As shown, the substrate 1 includes a source region 11 and a drain region 12 arranged along a fourth direction k, and a channel region 13 located between the source region 11 and the drain region 12;

[0099] S421, the step of forming a transistor structure 2 on one side of the substrate 1 includes: forming a gate functional portion 26 on one side of the channel region 13, forming a sidewall sacrificial structure 21 on two opposite sides of the gate functional portion 26 along the fourth direction k, and forming a first dielectric layer 28 on a side of the sidewall sacrificial structure 21 away from the substrate 1, forming a first via hole opposite to the source region and a second via hole opposite to the drain region on the first dielectric layer 28, forming a source portion 251 in the first via hole, and forming a drain portion 252 in the second via hole.

[0100] The first functional portion 22 includes at least one of a source portion 251 and a drain portion 252 , and the second functional portion 23 includes a gate functional portion 26 .

[0101] The above embodiment is a method for manufacturing a common transistor. In the above embodiment, the sacrificial spacer structure 21 may be in direct contact with the source portion 251 , the drain portion 252 , and the gate functional portion 26 .

[0102] Specifically, during the preparation process, a hard mask covering the gate functional portion 26 may be formed on the side of the gate functional portion 26 facing away from the substrate 1. The hard mask may be made of silicon dioxide.

[0103] In the above embodiment, under the etching action of the etching liquid, the etching selectivity between the side wall sacrificial structure 21 and the substrate 1 is relatively large, the etching selectivity between the side wall sacrificial structure 21 and the first functional part 22 is relatively large, and the etching selectivity between the side wall sacrificial structure 21 and the second functional part 23 is relatively large. Therefore, in the process of etching the side wall sacrificial structure 21 by the etching liquid, the damage to the source part 251, the drain part 252, the gate functional part 26 and the substrate 1 can be reduced, thereby improving the preparation yield of the semiconductor device and the performance of the semiconductor device. Specifically, the side wall sacrificial structure 21 is made of silicon nitride, the first dielectric layer 28 is made of silicon or silicon germanium, the gate functional part 26 is made of metal, and the etching liquid used in the above-mentioned embodiment of the present application can improve the etching selectivity of silicon nitride to silicon, the etching selectivity of silicon nitride to silicon germanium, and the etching selectivity of silicon nitride to metal, so that the etching rate of the etching liquid on the side wall sacrificial structure 21 is higher, and the etching rate of the first functional part 22 and the second functional part 23 is lower, which helps to improve the yield of semiconductor devices.

[0104] In the above embodiment, when forming the first dielectric layer 28 and the source portion 251 and the drain portion 252, the surface of the sidewall sacrificial structure 21 facing away from the substrate 1 may be covered, and the sidewall sacrificial structure 21 may be exposed by a chemical mechanical polishing process to facilitate contact between the sidewall sacrificial structure 21 and the etching solution.

[0105] In the above embodiment, the semiconductor device includes a second dielectric layer 30 located on the side of the source / drain functional portion 25 and the gate functional portion 26 away from the substrate. Before forming the second dielectric layer 30, as shown in FIG. Fig.36 and Fig.37 As shown, the etching liquid can directly contact the sacrificial sidewall structure 21 from the side of the sacrificial sidewall structure 21 away from the substrate 1, and remove the sacrificial sidewall structure 21 to form an air sidewall 36. The material of the second dielectric layer 30 can also include silicon dioxide.

[0106] In a feasible implementation manner, before step S600, the following steps are included:

[0107] The etching solution is formed, including: adding an organic solvent to a phosphoric acid solution, mixing and stirring evenly, and then standing for a preset time, which is greater than or equal to 30 minutes, and heating the mixed solution to a preset temperature, which is in the range of 120°C to 180°C.

[0108] In the above embodiment, an organic solvent is added to the phosphoric acid solution, mixed and stirred evenly, and then left to stand for more than or equal to 30 minutes, so that the phosphoric acid solution and the organic solvent can fully react, thereby achieving a good etching effect in the subsequent etching process.

[0109] In the above embodiment, the preset temperature may be 120° C., 130° C., 145° C., 160° C., 177° C., 180° C., etc., and this application does not specifically limit this.

[0110] Specifically, the preset temperature may be 160° C., which can achieve a better reaction effect between the etching solution and silicon nitride and reduce the adverse effects of the etching solution on silicon, silicon dioxide and hafnium dioxide (HfO 2 ).

[0111] In the above embodiment, the preset temperature can satisfy the reaction temperature of the etching solution and silicon nitride, thereby achieving etching of silicon nitride.

[0112] The above are only preferred specific implementations of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. An etching solution for etching silicon nitride, characterized in that: The etching solution comprises: A phosphoric acid solution and an organic solvent, wherein the organic solvent includes one of an allyltrimethoxysilane organic solvent and a vinyltrimethoxysilane organic solvent.

2. The etching solution according to claim 1, characterized in that The concentration range of the phosphoric acid solution is 80%-90%, the purity range of the organic solvent is 90%-99%, and the concentration range of the organic solvent is 0.1%-10%.

3. A method for preparing a semiconductor device, characterized in that: include: providing a substrate; forming a transistor structure on one side of the substrate, the transistor structure comprising a sacrificial sidewall structure located on one side of the substrate, a first functional portion, and a second functional portion, wherein at least a portion of the sacrificial sidewall structure is located between the first functional portion and the second functional portion; The etching solution as described in any one of claims 1 to 2 is brought into contact with the sidewall sacrificial structure to remove the sidewall sacrificial structure.

4. The method for preparing a semiconductor device according to claim 3, characterized in that: The transistor structure includes a channel layer stack portion located on one side of the substrate, the channel layer stack portion includes a plurality of channel layers arranged along a first direction, the channel layer includes a first end, a middle section and a second end arranged along a second direction, the first direction being perpendicular to the second direction; The transistor structure further includes a source-drain functional portion and a gate functional portion located on one side of the substrate, the source-drain functional portion includes a source portion and a drain portion located on both sides of the channel layer stack portion along a second direction, the gate functional portion surrounds the middle section along a direction surrounding the second direction, and the gate functional portion is protruded from the source-drain functional portion in a direction away from the substrate; The transistor structure further includes a gate dielectric layer, wherein the gate dielectric layer is located between the middle section and the gate functional portion and between the source-drain functional portion and the gate functional portion; The transistor structure further includes a first dielectric layer, wherein the first dielectric layer is located on a side of the source / drain functional portion away from the substrate; The sacrificial sidewall structure comprises a first sacrificial sidewall structure and a second sacrificial sidewall structure which are arranged continuously, wherein the first sacrificial sidewall structure is located between the gate dielectric layer and the source portion and between the gate dielectric layer and the drain portion; the second sacrificial sidewall structure is located at both sides of the gate functional portion along the second direction and between the gate dielectric layer and the first dielectric layer; The first functional portion includes at least one of the source portion, the drain portion, and the first dielectric layer, and the second functional portion includes the gate dielectric layer.

5. The method for preparing a semiconductor device according to claim 4, characterized in that: The step of contacting the etching solution with the sidewall sacrificial structure to remove the sidewall sacrificial structure comprises: forming a first channel in the substrate, wherein the first channel penetrates the substrate, and the first channel exposes the sacrificial structure of the sidewall; The etching liquid is injected into the first channel so that the etching liquid contacts the sidewall sacrificial structure.

6. The method for preparing a semiconductor device according to claim 5, characterized in that: The first channel is formed by using a dry etching process or a wet etching process.

7. The method for preparing a semiconductor device according to claim 4, characterized in that: A surface of the first dielectric layer facing away from the substrate exposes the gate functional portion and the second sacrificial spacer structure; The step of contacting the etching solution with the sidewall sacrificial structure to remove the sidewall sacrificial structure comprises: The etching liquid is injected from a side of the second sacrificial sidewall structure away from the substrate, so that the etching liquid contacts the second sacrificial sidewall structure.

8. The method for preparing a semiconductor device according to claim 4, characterized in that: Parts of the sacrificial sidewall structure are located on both sides of the channel layer stack along a third direction, wherein the third direction is perpendicular to the second direction and the third direction is perpendicular to the first direction; The method further includes forming a second dielectric layer on a side of the first dielectric layer facing away from the substrate, wherein the second dielectric layer covers and wraps the transistor structure; The step of contacting the etching solution with the sidewall sacrificial structure to remove the sidewall sacrificial structure comprises: forming a second channel penetrating the second dielectric layer along the third direction in the second dielectric layer, wherein the second channel exposes the sidewall sacrificial structure, and injecting the etching liquid into the second channel so that the etching liquid contacts the sidewall sacrificial structure; Wherein, under the etching action of the etching solution, the etching selectivity ratio between the sidewall sacrificial structure and the second dielectric layer is greater than 1.

9. The method for preparing a semiconductor device according to claim 3, characterized in that: The substrate comprises a source region and a drain region arranged along a fourth direction, and a channel region located between the source region and the drain region; The step of forming a transistor structure on one side of the substrate comprises: forming a gate functional part on one side of the channel region, forming the sidewall sacrificial structure on two opposite sides of the gate functional part along a fourth direction, and forming a first dielectric layer on a side of the sidewall sacrificial structure away from the substrate, forming a first via hole opposite to the source region and a second via hole opposite to the drain region on the first dielectric layer, forming a source part in the first via hole, and forming a drain part in the second via hole; The first functional portion includes at least one of the source portion and the drain portion, and the second functional portion includes the gate functional portion.

10. The method for preparing a semiconductor device according to claim 3, characterized in that: The step of contacting the etching solution with the sacrificial structure of the sidewall to remove the sacrificial structure of the sidewall comprises: The etching solution is formed, including: adding the organic solvent to the phosphoric acid solution, mixing and stirring evenly, and then standing for a preset time, the preset time is greater than or equal to 30 minutes, and heating the mixed solution to a preset temperature, the preset temperature is in the range of 120°C to 180°C.

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