Chip compression test circuit structure

Abstract

The invention relates to the technical field of chip testing, in particular to a chip compression testing circuit structure which comprises a serial input interface, M input triggers, M scrambling circuits, a decompression module, N scanning chains, a compression module, M output triggers and a serial output interface. An input pin of the A1 is connected with a serial input interface; an output pin of the Am is connected with an input pin of the Em, and data in the Am is scrambled by the Em to generate a corresponding preset value; the input end of each scanning chain is connected with the output pin of the decompression module, and the output end of each scanning chain is connected with the input pin of the compression module; the input pin of the BM is connected with the serial output interface, and the output trigger is connected with the digital output pin of the compression module. According to the invention, the test of the compression mode can be realized based on a group of serial data input interface and serial data output interface, the test coverage rate is improved, the clock frequency is improved, the chip test time is shortened, and the chip test cost is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of chip testing, and in particular to a chip compression testing circuit structure. Background Art

[0002] Chip Probing Test is mainly used to perform preliminary functional and performance tests on chips at the wafer level. At this stage, the chip test can usually be performed in compression mode in the automatic test equipment (ATE) based on multiple parallel input pins. The compression mode uses data compression technology to reduce test time and test costs. However, in some scenarios, there may be only one set of serial data input (Serial Data In, SDI) interface and serial data output (Serial Data Out, SDO) interface. For example, in the final inspection test stage, many pins are not packaged and cannot be detected, resulting in only one set of serial data input interface and serial data output interface remaining. In the prior art, all triggers can be constructed into a test chain for testing based on a set of serial data input interface and serial data output interface, and the compression mode test cannot be implemented, resulting in at least the following technical problems: low chip test coverage, limited chip test clock frequency, long chip test time, and high chip test cost. Summary of the invention

[0003] The purpose of the present invention is to provide a chip compression test circuit structure, which can realize compression mode testing based on a group of serial data input interfaces and serial data output interfaces, improve test coverage, increase clock frequency, reduce chip test time, and reduce chip test costs.

[0004] According to a first aspect of the present invention, a chip compression test circuit structure is provided, comprising a serial input interface, M input triggers {A1, A2, ..., A m ,...,A M}, M scrambling circuits {E1, E2, ..., E m ,...,E M}, decompression module, N scan chains, compression module and M output flip-flops {B1, B2, ..., B m ,...,B M}、Serial output interface, N≥M;

[0005] Among them, A mis the mth input trigger, the value range of m is 1 to M, M is the total number of input triggers, E m is the mth scrambling circuit, B m is the mth output flip-flop, A1, A2, ..., A m , ..., A M Connect in series, B1, B2, ..., B m ,...,B M Connect in series in sequence;

[0006] The input pin of A1 is connected to the serial input interface, and the serial input interface is used to serially transmit data to A1, A2, ..., A m , ..., A M Enter data in

[0007] A m The output pin and E m The input pins of E1, E2, ..., E m ,...,E M are connected to the input pins of the decompression module, A m The data in E m After scrambling, the corresponding preset values ​​are generated, E1, E2, ..., E m ,...,E M transmitting the corresponding preset values ​​to the decompression module in parallel;

[0008] The input end of each scan chain is connected to the output pin of the decompression module, and the decompression module is used to convert A1, A2, ..., A m , ..., A M The input data is decompressed into N output data and output to each scan chain respectively;

[0009] The output end of each scan chain is connected to the input pin of the compression module, and is used to compress the data output from all scan chains into M output data;

[0010] B M The input pins of are connected to the serial output interface, B1, B2, ..., B m , ..., B M They are all connected to the digital output pins of the compression module, and are used to parallely obtain the M-channel output data compressed by the compression module, and serially output the obtained M-channel output data to the serial output interface.

[0011] Compared with the prior art, the present invention has obvious advantages and beneficial effects. By means of the above technical solution, the chip compression test circuit structure provided by the present invention can achieve considerable technical advancement and practicality, and has wide industrial utilization value, and has at least the following beneficial effects:

[0012] The circuit structure of the present invention first converts the data input by the serial input interface into parallel input data through M input triggers, then adjusts the input data according to requirements through M scrambling circuits, and then implements the compression mode test through the decompression module. After passing through N scan chains, the data of the N scan chains are converted into M output data through the compression module, and then the M output data are serially output through the M input triggers, thereby implementing the compression mode test based on a group of serial data input interfaces and serial data output interfaces, improving the test coverage, increasing the clock frequency, reducing the chip test time, and reducing the chip test cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0014] Figure 1 A schematic diagram of the chip compression test circuit structure provided by an embodiment of the present invention;

[0015] Figure 2 A schematic diagram of a preset scrambling value generation circuit provided by an embodiment of the present invention;

[0016] Figure 3 Another circuit for generating a preset scrambling value provided by an embodiment of the present invention is intended;

[0017] Figure 4 Another preset scrambling value generating circuit is provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0018] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0019] The embodiment of the present invention provides a chip compression test circuit structure, such as Figure 1As shown, it includes a serial input interface, M input triggers {A1, A2, ..., A m ,...,A M}, M scrambling circuits {E1, E2, ..., E m ,...,E M}, decompression module, N scan chains, compression module and M output flip-flops {B1, B2, ..., B m ,...,B M}, serial output interface, N≥M.

[0020] Among them, A m is the mth input trigger, the value range of m is 1 to M, M is the total number of input triggers, E m is the mth scrambling circuit, B m is the mth output flip-flop. The total number of scrambling circuits and output flip-flops is also M. A1, A2, ..., A m , ..., A M Connect in series, B1, B2, ..., B m ,...,B M Connect in series one by one.

[0021] The input pin of A1 is connected to the serial input interface, and the serial input interface is used to serially transmit data to A1, A2, ..., A m , ..., A M Enter data in A m The output pin and E m The input pins of E1, E2, ..., E m ,...,E M are connected to the input pins of the decompression module, A m The data in E m After scrambling, the corresponding preset values ​​are generated, E1, E2, ..., E m ,...,E M The corresponding preset values ​​are transmitted to the decompression module in parallel.

[0022] It should be noted that the circuit structure works under the same clock, by setting M input triggers {A1, A2, ..., A m ,...,A M} can convert the data input from one serial input interface into data input from M parallel input interfaces. If the data input from M parallel input interfaces is directly transmitted to the decompression module, when a target sequence needs to be obtained, it usually takes multiple cycles to obtain it, and the target sequence will be mixed with many inefficient and invalid redundant codes, which are difficult to compress through test vector compression technology, resulting in longer test time and higher test cost. Based on this, the embodiment of the present invention adds M scrambling circuits {E1, E2, ..., E m ,...,E M}, A m The data in E m After scrambling, the corresponding preset value is generated, thereby shortening the target sequence construction cycle, reducing invalid redundant codes in the target sequence, shortening the chip testing time, and reducing the chip testing cost.

[0023] The input end of each scan chain is connected to the output pin of the decompression module, and the decompression module is used to convert A1, A2, ..., A m , ..., A M The input data is decompressed into N output data, which are output to each scan chain respectively; the output end of each scan chain is connected to the input pin of the compression module, which is used to compress the data output from all scan chains into M output data. It should be noted that each scan chain is composed of triggers in the chip connected in series. In order to improve the overall processing efficiency, it is preferred that all triggers in the chip are arranged in the N scan chains as evenly as possible.

[0024] B M The input pins of are connected to the serial output interface, B1, B2, ..., B m , ..., B M The M output triggers {B1, B2, ..., B m ,...,B M}Then convert the M-channel output data compressed by the compression module into serial output data and output it to the serial output interface.

[0025] The chip test circuit according to the embodiment of the present invention realizes compression test based on a group of serial input and output interfaces, improves test coverage, increases chip test clock frequency, reduces chip test time, and reduces chip test cost.

[0026] As an embodiment, the decompression module is a combinational logic circuit or a sequential circuit including a sequential unit, including M input pins and N output pins, and each input pin of the decompression module is connected to an A m Each output pin of the decompression module is connected to an input end of a scan chain. When the decompression module is a combinational logic circuit, it can be implemented based on an XOR gate. The specific combination of the XOR gates is set according to the specific decompression requirements. It can be understood that the implementation of the decompression module based on the XOR gate is only an example. The M-way parallel data can be further converted into N-way parallel data through the decompression module.

[0027] As an embodiment, the compression module is composed of logic gates arranged in multiple levels, including N input pins and M output pins, each input pin of the compression module is connected to the output end of a scan chain, and each output pin of the compression module is connected to a B m The logic gate may specifically use an XOR gate, and the specific combination of the logic gates is set according to specific compression requirements.

[0028] As an example, E m Consists of at least one logic gate, E m It includes two input pins and one output pin, E m The first input pin is used to receive the preset scrambling value K m , E m The second input pin is used to receive A m Input data, E m The output pin is used to convert E m The preset value generated after scrambling is transmitted to the decompression module. Preferably, the logic gate is an XOR gate.

[0029] As an embodiment, the circuit structure further includes a preset scrambling value generating circuit, such as Figure 2 As shown, the preset scrambling value generating circuit includes M scrambling triggers {D1, D2, ..., D m ,...,D M}, M-1 sub-scrambling circuits {F1, F2, ..., F m ,...,F M-1}, D m is the mth scrambling trigger, F m is the mth sub-scrambling circuit, F m It includes a first input pin, a second input pin and an output pin, D m The output pin is connected to the E m The first input pin is connected to D m For E m Transmit preset scrambling value Km When 1≤m≤M-1, D m The output pin is connected to the F m The first input pin is connected to F m The output pin is connected to D m+1 The input pin of D M The output pins are connected to each F m The second input pin is connected to D M The output pin of is connected to the input pin of D1. M The output value is fed back as an input to generate the value of each scrambling trigger in the next round. m Set the initial value and start running based on the initial value.

[0030] In order to further increase the possibility of generating the preset scrambling value, as an embodiment, the circuit structure further includes a preset scrambling value generating circuit, such as Figure 3 As shown, the preset scrambling value generating circuit includes M scrambling triggers {D1, D2, ..., D m ,...,D M}, M-1 sub-scrambling circuits {F1, F2, ..., F m ,...,F M-1}, M scrambling selectors {H1,H2,...,H m ,...,H M}, D m is the mth scrambling trigger, F m is the mth sub-scrambling circuit, H m is the mth scrambling selector, F m It includes a first input pin, a second input pin and an output pin, D m The output pin is connected to the E m The first input pin is connected to D m For E m Transmit preset scrambling value K m , H m It includes a first selection pin, a second selection pin and an output pin.

[0031] When 1≤m≤M-1, D m The output pin is connected to the F m The first input pin is connected to F m The output pin H m+1 The second selection pin is connected to H m+1 The first selection pin is used to input the preset random seed R m+1 , H m+1 The output pin is connected to D m+1、 The input pin is connected to D MThe output pins are connected to each F m The first selection pin of H1 is used to input the preset random seed R1, and the second selection pin of H1 is connected to D M connected to the output pin of the

[0032] H m Including the selection control signal, when the selection control signal is 1, the H m The first selection pin, when the selection control signal is 0, the strobe H m Specifically, the selection control signal can be set to 0 in the initial state, that is, in the initial state, H m The first selection pin is turned on by H m The first selection pin is D m Enter the preset random seed R m , so that the preset scrambling value generation circuit starts running based on the preset random seed, and in other states, the selection control signal is set to 1, H m The second selection pin of the D m The value of D m The value of .

[0033] In order to further increase the combination of generating the preset random seeds, as an embodiment, the preset scrambling value generating circuit further includes a coefficient adjustment unit {G1, G2, ..., G m ,...,G M+1},like Figure 4 In the example shown, G m is the mth coefficient adjustment unit, which is used to adjust the value after the coefficient adjustment unit. When 2≤m≤M, G m Set in F m-1 The first input pin is connected to the input circuit, G M Set in D M G1 is set on an output circuit connected to the output pin of H1, and G1 is set on an input circuit connected to the second selection pin of H1.

[0034] As an embodiment, the preset M triggers on one of the N scan chains are respectively connected one-to-one with the H m The first selection pin is connected to the trigger to transfer the value in the trigger to the corresponding H m First selection pin.

[0035] In order to enable the circuit structure to be used for testing at different stages, the circuit structure further includes M input selectors {C1, C2, ..., C m ,...,C M} and select control circuit, C mis the mth input selector, the value range of m is 1 to M, C m Including the first selection pin, the second selection pin, the enable pin and the output pin, C m The first selection pin is connected to the E m The second selection pin is used to connect the mth parallel input interface P m , C m The enable pin is connected to the selection control circuit.

[0036] As an example, during the chip wafer level testing phase, there are usually multiple P m When there are R parallel interfaces that can be detected in the chip to be tested, the selection control circuit controls all C m The second selection pin is selected by M P m Input data to the decompression module, and obtain output data from the decompression module through (RM) parallel output interfaces, R≥M+2, and the (RM) parallel output interfaces are specifically Q1, Q2, ..., Q i ,...,Q R-M , Q i is the i-th parallel output interface, the value range of i is 1 to Q i .

[0037] As an embodiment, during the finished product testing stage of the chip, many pins are not packaged and cannot be detected, which may result in only one set of serial data input interface and serial data output interface remaining and unable to implement compression testing. Or there are relatively few remaining input interfaces and output interfaces, and the coverage rate of directly performing compression testing is not high. In such cases, the circuit structure described in the present invention can greatly improve the test coverage rate. When there are no R parallel interfaces that can be detected in the chip to be tested, the selection control circuit controls all C m The first selection pin is selected by E1, E2, ..., E m ,...,E M Input data to the decompression module. By setting M input selectors {C1, C2, ..., C m ,...,C M} and selection control circuit, so that the circuit structure can be suitable for chip testing at different stages.

[0038] As an embodiment, the selection control circuit includes an OR gate and an inverter, wherein the first input pin of the OR gate is connected to the output pin of the inverter, the second input pin of the OR gate is connected to the parallel input enable signal, the first input pin of the inverter is connected to the control enable signal, and the output of the OR gate is connected to each A m When the output of the OR gate is 1, all C mThe second selection pin is selected, and the OR gate output is 0 when all C m The first select pin is selected.

[0039] When there are R detectable parallel interfaces in the chip to be tested, the parallel input enable signal is set to 1, and the control enable signal is set to 0.

[0040] When there are no R detectable parallel interfaces in the chip to be tested, the parallel input enable signal is set to 0, the control enable signal is set to 1, and the control enable signal is set to 1.

[0041] The circuit structure of the embodiment of the present invention first converts the data input by the serial input interface into parallel input data through M input triggers, then adjusts the input data according to requirements through M scrambling circuits, and then implements the compression mode test through the decompression module. After passing through N scan chains, the data of the N scan chains are converted into M output data through the compression module, and then the M output data are serially output through M input triggers, thereby implementing the compression mode test based on a group of serial data input interfaces and serial data output interfaces, improving the test coverage, increasing the clock frequency, reducing the chip test time, and reducing the chip test cost.

[0042] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with this profession can make some changes or modifications to equivalent embodiments of equivalent changes using the technical contents disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of the technical solution of the present invention.

Claims

1. A chip compression test circuit structure, characterized in that: It includes a serial input interface, M input triggers {A1, A2, ..., A m ,...,A M }, M scrambling circuits {E1, E2, ..., E m ,...,E M }, decompression module, N scan chains, compression module and M output flip-flops {B1, B2, ..., B m ,...,B M }、Serial output interface, N≥M; Among them, A m is the mth input trigger, the value range of m is 1 to M, M is the total number of input triggers, E m is the mth scrambling circuit, B m is the mth output flip-flop, A1, A2, ..., A m , ..., A M Connect in series, B1, B2, ..., B m ,...,B M Connect in series in sequence; The input pin of A1 is connected to the serial input interface, and the serial input interface is used to serially transmit data to A1, A2, ..., A m , ..., A M Enter data in A m The output pin and E m The input pins of E1, E2, ..., E m ,...,E M are connected to the input pins of the decompression module, A m The data in E m After scrambling, the corresponding preset values ​​are generated, E1, E2, ..., E m ,...,E M transmitting the corresponding preset values ​​to the decompression module in parallel; The input end of each scan chain is connected to the output pin of the decompression module, and the decompression module is used to convert A1, A2, ..., A m , ..., A M The input data is decompressed into N output data and output to each scan chain respectively; The output end of each scan chain is connected to the input pin of the compression module, and is used to compress the data output from all scan chains into M output data; B M The input pins of are connected to the serial output interface, B1, B2, ..., B m , ..., B M They are all connected to the digital output pins of the compression module, and are used to parallely obtain the M-channel output data compressed by the compression module, and serially output the obtained M-channel output data to the serial output interface.

2. The circuit structure according to claim 1, characterized in that: E m Consists of at least one logic gate, E m It includes two input pins and one output pin, E m The first input pin is used to receive the preset scrambling value K m , E m The second input pin is used to receive A m Input data, E m The output pin is used to convert E m The preset value generated after scrambling is transmitted to the decompression module.

3. The circuit structure according to claim 2, characterized in that: The logic gate is an XOR gate.

4. The circuit structure according to claim 1, characterized in that: The circuit structure further includes a preset scrambling value generating circuit, which includes M scrambling triggers {D1, D2, ..., D m ,...,D M }, M-1 sub-scrambling circuits {F1, F2, ..., F m ,...,F M-1 }, D m is the mth scrambling trigger, F m is the mth sub-scrambling circuit, F m It includes a first input pin, a second input pin and an output pin, D m The output pin is connected to the E m The first input pin is connected to D m For E m Transmit preset scrambling value K m ; When 1≤m≤M-1, D m The output pin is connected to the F m The first input pin is connected to F m The output pin is connected to D m+1 The input pin is connected to D M The output pins are connected to each F m The second input pin is connected to D M The output pin of is connected to the input pin of D1.

5. The circuit structure according to claim 1, characterized in that: The circuit structure further includes a preset scrambling value generating circuit, which includes M scrambling triggers {D1, D2, ..., D m ,...,D M }, M-1 sub-scrambling circuits {F1, F2, ..., F m ,...,F M-1 }, M scrambling selectors {H1,H2,...,H m ,...,H M-1 }, D m is the mth scrambling trigger, F m is the mth sub-scrambling circuit, H m is the mth scrambling selector, F m It includes a first input pin, a second input pin and an output pin, D m The output pin is connected to the E m The first input pin is connected to D m For E m Transmit preset scrambling value K m , H m comprising a first selection pin, a second selection pin and an output pin; When 1≤m≤M-1, D m The output pin is connected to the F m The first input pin is connected to F m The output pin H m+1 The second selection pin is connected to H m+1 The first selection pin is used to input the preset random seed R m+1 , H m+1 The output pin is connected to D m+1、 The input pin is connected to D M The output pins are connected to each F m The first selection pin of H1 is used to input the preset random seed R1, and the second selection pin of H1 is connected to D M connected to the output pin of the 6. The circuit structure according to claim 5, characterized in that: The preset scrambling value generating circuit further includes a coefficient adjustment unit {G1, G2, . . . , G m ,...,G M+1 }, G m is the mth coefficient adjustment unit, and the coefficient adjustment unit is used to adjust the value passing through the coefficient adjustment unit; When 2≤m≤M, G m Set in F m-1 The first input pin is connected to the input circuit, G M Set in D M G1 is set on an output circuit connected to the output pin of H1, and G1 is set on an input circuit connected to the second selection pin of H1.

7. The circuit structure according to claim 5, characterized in that: The preset M flip-flops on one of the N scan chains are respectively connected one-to-one with H m The first selection pin is connected to the trigger to transfer the value in the trigger to the corresponding H m First selection pin.

8. The circuit structure according to claim 5 or 6, characterized in that: H m Including the selection control signal, when the selection control signal is 1, the H m The first selection pin, when the selection control signal is 0, the strobe H m The second selection pin.

9. The circuit structure according to claim 8, characterized in that: The selection control signal is set to 0 in the initial state and to 1 in other states.

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