Chip temperature influence verification device and control method thereof

Abstract

The invention provides a chip temperature influence verification device and a control method thereof.The chip temperature influence verification device comprises a control device, a heat exchanger, a semiconductor cooler and a heat conduction structure, the heat conduction structure makes contact with a to-be-tested chip and corresponds to the to-be-tested chip in shape, and the heat exchanger and the heat conduction structure are arranged on the two side faces of the semiconductor cooler respectively; the control device is connected to the semiconductor cooler and the heat conduction structure. And the control device controls the current parameter of the semiconductor cooler according to the target temperature and the real-time temperature of the heat conduction structure so as to enable the real-time temperature to reach the target temperature, detects the current chip parameter of the to-be-detected chip, compares the current chip parameter with a preset parameter value, and determines the influence degree of the target temperature on the to-be-detected chip. The chip to be tested can be tested independently, more variables do not need to be introduced, the high requirement of an existing scheme for a testing machine is met, the fund, space and power requirements of environment verification are reduced, and desktop-level testing and portable requirements can be achieved by making a small device.

Description

Technical Field

[0001] The present application relates to the field of chip testing technology, and in particular to a chip temperature impact verification device and a control method thereof. Background Art

[0002] In related technologies, the underlying circuits of chips are easily affected by temperature. During chip verification and debugging, it is often necessary to adjust the working environment temperature of the chip to confirm whether the chip will be abnormal. The current solution is to place the chip in an environmental test chamber to create an adjustable temperature environment. However, the current solution usually has the following disadvantages: placing the chip in an environmental test chamber will bring other circuits except the target chip into the temperature chamber, which may introduce more variables and increase the difficulty of chip verification or debugging. In addition, the environmental test chamber requires more funds, space, electricity and other resources, and its use will be limited. Summary of the invention

[0003] The present application aims to solve at least one of the technical problems existing in the prior art. To this end, the present application proposes a chip temperature impact verification device and a control method thereof, which aims to solve the high requirements of the existing solution on the test machine, reduce the capital, space and power requirements of environmental verification, and make it into a small device to achieve desktop-level testing and portable requirements.

[0004] In a first aspect, an embodiment of the present application provides a control method for a chip temperature influence verification device, wherein the chip temperature influence verification device comprises a control device, a heat exchanger, a semiconductor refrigerator and a heat-conducting structure, wherein the heat-conducting structure is used to contact the chip to be tested, and the shape of the heat-conducting structure corresponds to the shape of the chip to be tested, the heat exchanger and the heat-conducting structure are respectively arranged on two sides of the semiconductor refrigerator, and the control device is respectively connected to the semiconductor refrigerator and the heat-conducting structure; the method is applied to the control device, and the method comprises: receiving a target temperature input by a user, and detecting a real-time temperature of the heat-conducting structure; Controlling the current parameters of the semiconductor refrigerator according to the target temperature and the real-time temperature, generating a Peltier effect through the semiconductor refrigerator, so that the real-time temperature of the heat-conducting structure reaches the target temperature, wherein the current parameters include current direction and / or current magnitude; When the real-time temperature reaches the target temperature, detecting a plurality of current chip parameters of the chip to be tested; Compare the multiple current chip parameters with multiple preset parameter values ​​respectively to obtain parameter deviation results, wherein each of the preset parameter values ​​is determined by sample chip parameters of multiple qualified sample chips at the target temperature; The degree of influence of the target temperature on the chip to be tested is determined according to the parameter deviation result.

[0005] According to some embodiments of the present application, the controlling the current parameter of the semiconductor refrigerator according to the target temperature and the real-time temperature includes at least one of the following: When the target temperature is higher than the real-time temperature, the current direction of the semiconductor refrigerator is controlled to be a first direction, so that the semiconductor refrigerator transfers heat to the heat-conducting structure, wherein the temperature difference between the target temperature and the real-time temperature is positively correlated with the current of the semiconductor refrigerator; When the target temperature is lower than the real-time temperature, the current direction of the semiconductor refrigerator is controlled to a second direction so that the semiconductor refrigerator absorbs heat from the heat-conducting structure, wherein the second direction and the first direction are opposite directions, and the temperature difference between the real-time temperature and the target temperature is positively correlated with the current size of the semiconductor refrigerator.

[0006] According to some embodiments of the present application, when the target temperature includes a first target temperature and a second target temperature, wherein the first target temperature is higher than the real-time temperature and the second target temperature is lower than the real-time temperature; controlling the current parameter of the semiconductor refrigerator according to the target temperature and the real-time temperature includes: By switching the current direction of the semiconductor refrigerator, the heat-conducting structure is periodically heated and cooled, so that the real-time temperature repeatedly reaches the first target temperature and the second target temperature; Until the number of round trips reaches a preset number of test times, stop controlling the semiconductor refrigerator; The cooling time required for the real-time temperature to drop from the first target temperature to the second target temperature, and the heating time required for the real-time temperature to rise from the second target temperature to the first target temperature are both less than the preset time.

[0007] According to some embodiments of the present application, when the real-time temperature reaches the target temperature, detecting multiple current chip parameters of the chip to be tested includes: When the real-time temperature reaches the target temperature, the chip temperature impact verification device is grasped by a mechanical arm and moved downward, so as to apply downward pressure to the chip to be tested through the heat-conducting structure; When the downward pressure applied by the heat-conducting structure to the chip to be tested is within a preset pressure test range, a plurality of current chip parameters of the chip to be tested are detected.

[0008] According to some embodiments of the present application, when the real-time temperature reaches the target temperature, detecting multiple current chip parameters of the chip to be tested includes: When the real-time temperature reaches the target temperature, the chip temperature influence verification device is grasped by a mechanical arm and moves back and forth, so as to collide with the chip to be tested multiple times through the heat-conducting structure; When the collision number is greater than or equal to the preset test number, multiple current chip parameters of the chip to be tested are detected.

[0009] According to some embodiments of the present application, the chip to be tested is arranged on a circuit board to be tested; before controlling the current parameter of the semiconductor refrigerator according to the target temperature and the real-time temperature, the method further comprises: Generating a virtual coordinate system corresponding to the circuit board to be tested according to the circuit board to be tested; Obtaining the coordinate position of the chip to be tested on the circuit board to be tested, and grabbing the chip temperature impact verification device by a mechanical arm to perform a planar movement in the virtual coordinate system; After the heat-conducting structure moves to the coordinate position, the chip temperature impact verification device is grasped by a mechanical arm and moved downward, so that the heat-conducting structure is pressed against the surface of the chip to be tested.

[0010] According to some embodiments of the present application, the preset parameter value is determined by the following steps: Obtaining sample chip parameters of each qualified sample chip at the target temperature; Performing concentration analysis on the plurality of sample chip parameters, and determining a parameter range whose concentration is higher than a preset degree, and determining the sample chip parameters within the parameter range as target sample chip parameters; An average value of the target sample chip parameters is calculated to obtain the preset parameter value.

[0011] In a second aspect, an embodiment of the present application provides a chip temperature impact verification device, and a control method of the chip temperature impact verification device based on the first aspect; the chip temperature impact verification device includes: A control device, a heat exchanger, a semiconductor refrigerator and a heat-conducting structure, wherein the heat-conducting structure is used to contact the chip to be tested, and the shape of the heat-conducting structure corresponds to the shape of the chip to be tested. The heat exchanger and the heat-conducting structure are respectively arranged on two sides of the semiconductor refrigerator, and the control device is respectively connected to the semiconductor refrigerator and the heat-conducting structure.

[0012] According to some embodiments of the present application, a first thermal insulation layer is provided on the surrounding side surfaces and the exposed bottom surface of the semiconductor refrigerator; and a second thermal insulation layer is provided on the surrounding side surfaces of the heat-conducting structure.

[0013] According to some embodiments of the present application, the semiconductor cooler and the heat-conducting structure are detachably arranged to replace the heat-conducting structure corresponding to the shape and size of the chip to be tested.

[0014] In a third aspect, an embodiment of the present application provides a control device, comprising: a memory, a processor, and a computer program stored on the memory and executable on the processor, wherein the processor executes the control method of the chip temperature impact verification device of the first aspect mentioned above when running the computer program.

[0015] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium storing computer-executable instructions, wherein the computer-executable instructions are used to execute the control method of the chip temperature impact verification device as described in the first aspect above.

[0016] In a fifth aspect, an embodiment of the present application provides a computer program product, comprising a computer program or computer instructions, wherein the computer program or the computer instructions are stored in a computer-readable storage medium, a processor of a computer device reads the computer program or the computer instructions from the computer-readable storage medium, and the processor executes the computer program or the computer instructions, so that the computer device executes the control method of the chip temperature impact verification device as described in the first aspect above.

[0017] According to the technical solution of the embodiment of the present application, at least the following beneficial effects are achieved: the embodiment of the present application designs a chip temperature influence verification device, comprising a control device, a heat exchanger, a semiconductor refrigerator and a heat-conducting structure, wherein the heat-conducting structure is used to contact the chip to be tested, the shape of the heat-conducting structure corresponds to the shape of the chip to be tested, the heat exchanger and the heat-conducting structure are respectively arranged on the two sides of the semiconductor refrigerator, and the control device is respectively connected to the semiconductor refrigerator and the heat-conducting structure; the control device receives the target temperature input by the user, and detects the real-time temperature of the heat-conducting structure; the current parameter of the semiconductor refrigerator is controlled according to the target temperature and the real-time temperature, and the Peltier effect is generated by the semiconductor refrigerator so that the real-time temperature of the heat-conducting structure reaches the target temperature, wherein the current parameter includes the current direction and / or the current magnitude; when the real-time temperature reaches the target temperature, a plurality of current chip parameters of the chip to be tested are detected; the plurality of current chip parameters are respectively compared with a plurality of preset parameter values ​​to obtain parameter deviation results, wherein each preset parameter value is determined by the sample chip parameters of a plurality of qualified sample chips at the target temperature; the influence of the target temperature on the chip to be tested is determined according to the parameter deviation results. Different from the existing testing scheme of placing the chip into an environmental test chamber, the embodiment of the present application can test the chip to be tested individually without introducing more variables, which solves the high requirements of the existing scheme on the test machine, reduces the capital, space and power requirements of environmental verification, and is made into a small device to meet desktop-level testing and portable requirements.

[0018] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying drawings are used to provide further understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0020] Figure 1 It is a structural schematic diagram of a chip temperature impact verification device provided by an embodiment of the present application; Figure 2 This is a schematic diagram of the use of a chip temperature impact verification device provided by an embodiment of the present application; Figure 3 This is a schematic diagram of performing a low temperature test on a chip to be tested provided by an embodiment of the present application; Figure 4 is a schematic diagram of performing a high temperature test on a chip to be tested provided by an embodiment of the present application; Figure 5 It is a schematic structural diagram of a chip temperature influence verification device provided with a first thermal insulation layer and a second thermal insulation layer provided in one embodiment of the present application; Figure 6 is a flow chart of a control method of a chip temperature impact verification device provided by an embodiment of the present application; Figure 7 yes Figure 6 Step S620 is a sub-step flow chart of heating the chip under test; Figure 8 yes Figure 6 Step S620 is a sub-step flow chart of cooling the chip under test; Fig. 9 yes Figure 6 Step S620 is a flowchart of the sub-steps of performing rapid heating and cooling treatments on the chip to be tested multiple times; Fig.10 yes Figure 6 The sub-step flow chart of step S630 performing pressure test and temperature test simultaneously; Fig.11 yes Figure 6 The sub-step flow chart of step S630 performing collision test and temperature test simultaneously; Fig.12 This is a flow chart of positioning a chip to be tested and moving a heat-conducting structure provided by an embodiment of the present application; Fig.13 is a flow chart of a process for determining a preset parameter value provided by an embodiment of the present application; Fig.14 It is a schematic diagram of a control device for executing a control method of a chip temperature impact verification device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0021] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0022] In the description of the present application, it should be understood that descriptions involving orientation, such as up, down, front, back, left, right, etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0023] In the description of this application, "several" means one or more, "more" means more than two, "greater than", "less than", "exceed", etc. are understood to exclude the number itself, and "above", "below", "within", etc. are understood to include the number itself. If there is a description of "first" or "second", it is only used for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

[0024] In the description of this application, unless otherwise clearly defined, terms such as setting, installing, connecting, etc. should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meanings of the above terms in this application based on the specific content of the technical solution.

[0025] In some cases, the underlying circuits of a chip are susceptible to temperature. During chip verification and debugging, it is often necessary to adjust the chip's working environment temperature to confirm whether the chip will be abnormal. The current solution is to place the chip in an environmental test chamber to create an adjustable temperature environment. However, the current solution usually has the following disadvantages: placing the chip in an environmental test chamber will bring other circuits besides the target chip into the temperature chamber, which may introduce more variables and increase the difficulty of chip verification or debugging. In addition, the environmental test chamber requires more funds, space, electricity and other resources, and its use will be limited.

[0026] Based on the above situation, the embodiment of the present application proposes a chip temperature impact verification device and a control method thereof, aiming to solve the high requirements of the existing solution on the test machine, reduce the capital, space and power requirements of environmental verification, and make it into a small device that can achieve desktop-level testing and portable requirements.

[0027] The following further describes various embodiments of the chip temperature impact verification device of the present application in conjunction with the accompanying drawings.

[0028] like Figure 1 to Figure 2 As shown, Figure 1 It is a structural schematic diagram of a chip temperature impact verification device provided by an embodiment of the present application; Figure 2 This is a schematic diagram of the use of a chip temperature impact verification device provided by an embodiment of the present application.

[0029] In one embodiment, the chip temperature impact verification device includes but is not limited to a control device 100, a heat exchanger 200, a semiconductor refrigerator 300 and a heat-conducting structure 400. The heat-conducting structure 400 is used to contact the chip to be tested 510. The shape of the heat-conducting structure 400 corresponds to the shape of the chip to be tested 510. The heat exchanger 200 and the heat-conducting structure 400 are respectively arranged on two sides of the semiconductor refrigerator 300. The control device 100 is respectively connected to the semiconductor refrigerator 300 and the heat-conducting structure 400.

[0030] In one embodiment, the control device 100 can input a target temperature and detect the real-time temperature of the heat-conducting structure 400 , and control the temperature of the heat-conducting structure 400 by controlling the current direction and current magnitude of the semiconductor refrigerator 300 .

[0031] In one embodiment, the heat exchanger 200 includes but is not limited to an air cooling device or a water cooling device, which is used to absorb or provide heat transferred by the semiconductor refrigerator 300, so that the semiconductor refrigerator 300 can work normally.

[0032] In one embodiment, for the semiconductor refrigerator 300 described above, when low-voltage direct current is passed, the heat from one side can be pumped to the other side through the Peltier effect, and the temperature difference can reach 60-70°C. In addition, by changing the direction of the direct current, the hot and cold sides can be exchanged.

[0033] In one embodiment, the heat-conducting structure 400 mentioned above has one side close to the chip under test 510 and the other side close to the semiconductor cooler 300, which can play a heat-conducting role; in addition, the heat-conducting structure 400 of different shapes can be replaced to avoid the influence of components around the chip under test 510.

[0034] It is understandable that the above-mentioned thermally conductive copper structure can be a metal thermally conductive material such as copper and aluminum, or a non-metal thermally conductive material such as aluminum oxide and silicon carbide, and the embodiments of the present application do not specifically limit this.

[0035] In one embodiment, the target value of the control device 100 is set to make the heat-conducting structure 400 at the target temperature, and then the heat-conducting structure 400 is in contact with the chip under test 510, so that the chip under test 510 approaches the target temperature through heat conduction.

[0036] In one embodiment, the chip temperature impact verification device is very small in size and has simple power requirements, and can be used as a tool for testing temperature impact.

[0037] In addition, if Figure 3 As shown, Figure 3 is a schematic diagram of performing a low temperature test on a chip to be tested 510 provided by an embodiment of the present application; In one embodiment, when the target temperature is lower than the real-time temperature, the current direction of the semiconductor cooler 300 is controlled to be the second direction, so that the semiconductor cooler 300 absorbs heat from the heat-conducting structure 400, thereby causing the real-time temperature of the heat-conducting structure 400 to drop to the target temperature, thereby realizing the verification of the low-temperature effect on the chip 510 to be tested.

[0038] It should be noted that the temperature difference between the real-time temperature and the target temperature is positively correlated with the current of the semiconductor refrigerator 300; specifically, if the target temperature is much lower than the real-time temperature, that is, the real-time temperature is much higher than the target temperature, in order to quickly cool the heat-conducting structure 400, the current value of the semiconductor refrigerator 300 can be appropriately increased.

[0039] In addition, if Figure 4 As shown, Figure 4 is a schematic diagram of performing a high temperature test on a chip to be tested 510 provided by an embodiment of the present application; In one embodiment, when the target temperature is higher than the real-time temperature, the current direction of the semiconductor cooler 300 is controlled to be a first direction, wherein the first direction and the second direction are opposite directions, so that the semiconductor cooler 300 transfers heat to the heat-conducting structure 400, thereby causing the real-time temperature of the heat-conducting structure 400 to rise to the target temperature, thereby realizing verification of the high-temperature impact on the chip 510 to be tested.

[0040] It should be noted that the temperature difference between the target temperature and the real-time temperature is positively correlated with the current of the semiconductor refrigerator 300. Specifically, if the target temperature is much higher than the real-time temperature, that is, the real-time temperature is much lower than the target temperature, in order to quickly heat up the heat-conducting structure 400, the current of the semiconductor refrigerator 300 can be appropriately increased.

[0041] In one embodiment, if Figure 5 As shown, Figure 5 6 is a schematic diagram of a chip temperature impact verification device provided with a first thermal insulation layer 610 and a second thermal insulation layer 620 according to an embodiment of the present application; Figure 5 It can be seen that when the heat-conducting structure 400 is in close contact with the chip to be tested 510 on the circuit board to be tested 500, since other components 520 may exist around it, in order to avoid affecting other surrounding components 520, the embodiment of the present application can set a first heat-insulating layer 610 on the surrounding sides and exposed bottom surface of the semiconductor refrigerator 300, and set a second heat-insulating layer 620 on the surrounding sides of the heat-conducting structure 400.

[0042] In one embodiment, the semiconductor cooler 300 and the heat-conducting structure 400 are detachably arranged to replace the heat-conducting structure 400 corresponding to the shape and size of the chip to be tested 510. Specifically, since the circuit board 500 to be tested is provided with multiple shapes and sizes of the chips to be tested 510, or the shapes and sizes of the chips to be tested 510 on different circuit boards 500 to be tested are different, in order to make the contact surface between the heat-conducting structure 400 and the chip to be tested 510 larger and not touch other peripheral components 520, the embodiment of the present application can be provided with heat-conducting structures 400 of multiple shapes and sizes, so that the appropriate corresponding heat-conducting structure 400 can be selected according to the shape and size of the chip to be tested 510.

[0043] It is understandable that the detachable manner between the semiconductor cooler 300 and the heat-conducting structure 400 may be a snap-on connection manner or a screw-fixed connection manner, and the embodiment of the present application does not specifically limit this.

[0044] Based on the hardware structure of the chip temperature impact verification device of each of the above-mentioned embodiments, various embodiments of the control method of the chip temperature impact verification device of the present application are respectively proposed below.

[0045] like Figure 6 As shown, Figure 6 It is a flowchart of a control method of a chip temperature impact verification device provided by an embodiment of the present application; the control method of the chip temperature impact verification device may include but is not limited to step S610, step S620, step S630, step S640 and step S650.

[0046] Step S610, receiving a target temperature input by a user, and detecting a real-time temperature of the heat-conducting structure; Step S620, controlling the current parameters of the semiconductor refrigerator according to the target temperature and the real-time temperature, and generating a Peltier effect through the semiconductor refrigerator so that the real-time temperature of the heat-conducting structure reaches the target temperature, wherein the current parameters include current direction and / or current magnitude; Step S630: when the real-time temperature reaches the target temperature, detecting multiple current chip parameters of the chip to be tested; Step S640, comparing the multiple current chip parameters with multiple preset parameter values ​​respectively to obtain parameter deviation results, wherein each preset parameter value is determined by sample chip parameters of multiple qualified sample chips at a target temperature; Step S650: Determine the influence of the target temperature on the chip to be tested according to the parameter deviation result.

[0047] In one embodiment, first, the control device receives a target temperature input by a user, which is the test temperature. At the same time, the control device also detects the real-time temperature of the heat-conducting structure in real time through a temperature sensor; then, the target temperature input by the user and the real-time temperature of the heat-conducting structure are compared in size, thereby determining the current direction and current size of the semiconductor refrigerator, and powering on the semiconductor refrigerator; wherein, during the power-on period, the semiconductor refrigerator will produce a Peltier effect, which can draw heat from one side of the semiconductor refrigerator to the other side of the semiconductor refrigerator, thereby adjusting the real-time temperature of the heat-conducting structure, and then adjusting the test temperature of the chip to be tested; then, when the real-time temperature reaches the target temperature, that is, when the test temperature to be tested is reached, multiple current chip parameters of the chip to be tested can be detected at this time, such as read or write efficiency, power consumption, reliability and other parameters; then, the current chip parameters are compared with preset parameter values ​​determined by sample chip parameters of multiple qualified sample chips at the target temperature, thereby obtaining parameter deviation results; finally, the degree of influence of the target temperature on the chip to be tested is determined based on the parameter deviation results.

[0048] It should be noted that the above-mentioned current chip parameters may be read and write efficiency, data transmission stability, electrical performance parameters such as frequency, power consumption, voltage, etc., or other parameters, and the embodiments of the present application do not specifically limit this.

[0049] In addition, it should be noted that, since each preset parameter value is determined by sample chip parameters of a plurality of qualified sample chips at a target temperature, the preset parameter value can represent a standard qualified level of a qualified chip at a target temperature.

[0050] In addition, it should be noted that if the parameter deviation result between the current chip parameters and the preset parameter values ​​is large, that is, the numerical deviation between the two is large, then the surface of the chip to be tested does not meet the standard qualified level at the target temperature; if the parameter deviation result between the current chip parameters and the preset parameter values ​​is small, that is, the numerical deviation between the two is small, then the surface of the chip to be tested meets the standard qualified level at the target temperature.

[0051] In addition, it should be noted that, when there are multiple types of parameter deviation results, if one parameter deviation result is unqualified, it is determined that the chip under test performs unqualified at this target temperature; that is, only when all parameter deviation results are qualified can it be determined that the chip under test performs qualified at this target temperature.

[0052] In addition, if Figure 7 As shown, Figure 7 yes Figure 6 The sub-step flow chart of step S620 in which the temperature of the chip under test is raised; the above-mentioned step S620 may include but is not limited to step S710 and step S720.

[0053] Step S710: When the target temperature is higher than the real-time temperature, the current direction of the semiconductor refrigerator is controlled to be a first direction; Step S720, using a semiconductor cooler to generate a Peltier effect to transfer heat to the heat-conducting structure so that the real-time temperature of the heat-conducting structure reaches a target temperature, wherein the temperature difference between the target temperature and the real-time temperature is positively correlated with the current of the semiconductor cooler.

[0054] In one embodiment, when the target temperature is higher than the real-time temperature, the current direction of the semiconductor cooler is controlled to a first direction, wherein the first direction and the second direction are opposite directions, so that the semiconductor cooler transfers heat to the heat-conducting structure, thereby causing the real-time temperature of the heat-conducting structure to rise to the target temperature, thereby realizing verification of the high-temperature impact on the chip to be tested.

[0055] It should be noted that the temperature difference between the target temperature and the real-time temperature is positively correlated with the current of the semiconductor refrigerator. Specifically, if the target temperature is much higher than the real-time temperature, that is, the real-time temperature is much lower than the target temperature, in order to quickly heat up the heat-conducting structure, the current value of the semiconductor refrigerator can be appropriately increased.

[0056] In addition, if Figure 8 As shown, Figure 8 yes Figure 6 Step S620 is a sub-step flow chart of cooling the chip under test; regarding the above-mentioned step S620, it may include but is not limited to step S810 and step S820.

[0057] Step S810: when the target temperature is lower than the real-time temperature, the current direction of the semiconductor refrigerator is controlled to be a second direction, wherein the second direction is opposite to the first direction; Step S820, using a semiconductor cooler to generate a Peltier effect to absorb heat from the heat-conducting structure so that the real-time temperature of the heat-conducting structure reaches a target temperature, wherein the temperature difference between the real-time temperature and the target temperature is positively correlated with the current of the semiconductor cooler.

[0058] In one embodiment, when the target temperature is lower than the real-time temperature, the current direction of the semiconductor cooler is controlled to a second direction so that the semiconductor cooler absorbs heat from the heat-conducting structure, thereby causing the real-time temperature of the heat-conducting structure to drop to the target temperature, thereby realizing verification of the low-temperature effect on the chip to be tested.

[0059] It should be noted that the temperature difference between the real-time temperature and the target temperature is positively correlated with the current of the semiconductor refrigerator; specifically, if the target temperature is much lower than the real-time temperature, that is, the real-time temperature is much higher than the target temperature, in order to quickly cool the heat-conducting structure, the current value of the semiconductor refrigerator can be appropriately increased.

[0060] In addition, if Fig. 9 As shown, Fig. 9 yes Figure 6 In step S620, a sub-step flowchart is provided for repeatedly performing rapid heating and cooling treatment on the chip under test; when the target temperature includes a first target temperature and a second target temperature, wherein the first target temperature is higher than the real-time temperature and the second target temperature is lower than the real-time temperature; regarding the above-mentioned step S620, it may include but is not limited to step S910 and step S920.

[0061] Step S910, by switching the current direction of the semiconductor refrigerator, the heat-conducting structure is periodically heated and cooled so that the real-time temperature repeatedly reaches the first target temperature and the second target temperature; Step S920, until the number of round trips reaches the preset number of tests, stop controlling the semiconductor refrigerator; wherein the cooling time required for the real-time temperature to drop from the first target temperature to the second target temperature, and the heating time required for the real-time temperature to rise from the second target temperature to the first target temperature are both less than the preset time.

[0062] In one embodiment, the embodiment of the present application can set up an extreme detection method, that is, to test the chip to be tested by repeatedly cycling between high temperature and low temperature. At the same time, it also takes into account the test of the rapid heating process and the test of the rapid cooling process, so as to test the performance parameters of the chip to be tested under extreme conditions.

[0063] It should be noted that the preset number of tests and the preset duration may be pre-set. If the preset number of tests is greater or the preset duration is shorter, the test environment is more severe.

[0064] In addition, if Fig.10 As shown, Fig.10 yes Figure 6 The sub-step flowchart of step S630 in which pressure test and temperature test are performed simultaneously; regarding the above-mentioned step S630, it may include but is not limited to step S1010 and step S1020.

[0065] Step S1010: When the real-time temperature reaches the target temperature, the temperature influence verification device of the chip is grasped by the mechanical arm and moves downward, so as to apply downward pressure to the chip to be tested through the heat-conducting structure; Step S1020 : When the downward pressure applied by the heat-conducting structure to the chip to be tested is within a preset pressure test range, a plurality of current chip parameters of the chip to be tested are detected.

[0066] In one embodiment, when the real-time temperature reaches the target temperature, the embodiment of the present application will also use a robotic arm to grab the chip temperature to affect the downward movement of the verification device, and apply downward pressure to the chip to be tested through the heat-conducting structure, so that the downward pressure applied by the heat-conducting structure to the chip to be tested is within a preset pressure test range. At this time, under the dual test environment of target temperature and preset pressure, multiple current chip parameters of the chip to be tested are detected.

[0067] It should be noted that the preset pressure test range can be pre-set, and the embodiments of the present application do not specifically limit this.

[0068] In addition, if Fig.11 As shown, Fig.11 yes Figure 6 Flow chart of sub-steps of performing collision test and temperature test simultaneously in step S630; regarding the above-mentioned step S630, it may include but is not limited to step S1110 and step S1120.

[0069] Step S1110, when the real-time temperature reaches the target temperature, the temperature impact verification device of the chip is grasped by the mechanical arm to move back and forth, so as to collide with the chip to be tested multiple times through the heat-conducting structure; Step S1120: When the collision number is greater than or equal to the preset test number, multiple current chip parameters of the chip to be tested are detected.

[0070] In one embodiment, when the real-time temperature reaches the target temperature, the embodiment of the present application will also use a robotic arm to grab the chip temperature to affect the reciprocating movement of the verification device, and use the heat-conducting structure to perform multiple collisions on the chip to be tested until the number of collisions is greater than or equal to the preset test number. At this time, under the dual test environment of the target temperature and the preset number of collisions, multiple current chip parameters of the chip to be tested are detected.

[0071] It should be noted that the preset number of tests may be pre-set, and the embodiments of the present application do not specifically limit this.

[0072] In addition, if Fig.12 As shown, Fig.12 This is a flowchart of positioning the chip to be tested and moving the heat-conducting structure provided by an embodiment of the present application; the chip to be tested is set on the circuit board to be tested; before controlling the current parameters of the semiconductor refrigerator according to the target temperature and the real-time temperature, the method includes but is not limited to step S1210, step S1220 and step S1230.

[0073] Step S1210, generating a virtual coordinate system corresponding to the circuit board to be tested according to the circuit board to be tested; Step S1220, obtaining the coordinate position of the chip to be tested on the circuit board to be tested, grabbing the chip by a mechanical arm, and moving the temperature impact verification device in a plane in a virtual coordinate system; Step S1230: After the heat-conducting structure moves to the coordinate position, the chip temperature influence verification device is grasped by the robot arm and moved downward, so that the heat-conducting structure is pressed against the surface of the chip to be tested.

[0074] In one embodiment, the embodiment of the present application can also automatically achieve precise positioning. Specifically, the embodiment of the present application can obtain a virtual coordinate system corresponding to the circuit board to be tested and the coordinate position of the chip to be tested on the circuit board to be tested, and then control the robotic arm to grab the chip temperature impact verification device to the above-mentioned coordinate position, that is, grab the heat-conducting structure above the chip to be tested, and then use the robotic arm to grab the chip temperature impact verification device and move it downward, so that the heat-conducting structure is pressed against the surface of the chip to be tested, thereby realizing automatic positioning and movement of the heat-conducting structure.

[0075] In addition, if Fig.13 As shown, Fig.13 It is a flowchart of a process for determining a preset parameter value provided by an embodiment of the present application; regarding the above-mentioned preset parameter value, its determination process may include but is not limited to step S1310, step S1320 and step S1330.

[0076] Step S1310, obtaining sample chip parameters of each qualified sample chip at a target temperature; Step S1320, performing concentration analysis on a plurality of sample chip parameters, and determining a parameter range where the concentration is higher than a preset degree, and determining the sample chip parameters within the parameter range as target sample chip parameters; Step S1330: Calculate the average value of the parameters of multiple target sample chips to obtain a preset parameter value.

[0077] In one embodiment, in order to determine a suitable preset parameter value, the embodiment of the present application can screen out a parameter range with a concentration higher than a preset degree from multiple sample chip parameters, that is, screen out a numerical interval that can include most of the sample chip parameters. The sample chip parameters within this parameter range are then used as target sample chip parameters. Subsequently, the average value of the target sample chip parameters within this parameter range is calculated to obtain the preset parameter value. In this way, a more suitable preset parameter value can be obtained.

[0078] Based on the control method of the chip temperature impact verification device of each of the above-mentioned embodiments, various embodiments of the control device, chip temperature impact verification device, computer-readable storage medium and computer program product of the present application are respectively proposed below.

[0079] like Fig.14 As shown, Fig.141 is a schematic diagram of a control device for executing a control method for a chip temperature influence verification device provided by an embodiment of the present application. The control device 100 implemented in the present application includes: a processor 110, a memory 120, and a computer program stored in the memory 120 and executable on the processor 110, wherein: Fig.14 In the figure, a processor 110 and a memory 120 are taken as an example.

[0080] The processor 110 and the memory 120 may be connected via a bus or other means. Fig.14 The example of connecting through bus is taken in the following.

[0081] The memory 120, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs and non-transitory computer executable programs. In addition, the memory 120 may include a high-speed random access memory, and may also include a non-transitory memory, such as at least one disk storage device, a flash memory device, or other non-transitory solid-state storage device. In some embodiments, the memory 120 may optionally include a memory 120 remotely arranged relative to the processor 110, and these remote memories 120 may be connected to the control device 100 via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0082] Those skilled in the art will understand that Fig.14 The device structure shown in the figure does not constitute a limitation on the control device 100, and may include more or less components than shown in the figure, or combine certain components, or arrange the components differently.

[0083] exist Fig.14 In the control device 100 shown, the processor 110 can be used to call the control program stored in the memory 120, so as to implement the control method of the chip temperature effect verification device described above. Specifically, the non-transient software program and instructions required to implement the control method of the chip temperature effect verification device described above are stored in the memory 120, and when executed by the processor 110, the control method of the chip temperature effect verification device described above is executed.

[0084] It is worth noting that since the control device 100 of the embodiment of the present application can execute the control method of the chip temperature impact verification device of any of the above-mentioned embodiments, the specific implementation manner and technical effects of the control device 100 of the embodiment of the present application can refer to the specific implementation manner and technical effects of the control method of the chip temperature impact verification device of any of the above-mentioned embodiments.

[0085] In addition, an embodiment of the present application further provides a chip temperature impact verification device, which includes the control device of the above embodiment.

[0086] It is worth noting that since the chip temperature impact verification device of the embodiment of the present application includes the control device of the above-mentioned embodiment, and the control device of the above-mentioned embodiment can execute the control method of the chip temperature impact verification device of any of the above-mentioned embodiments, the specific implementation manner and technical effects of the chip temperature impact verification device of the embodiment of the present application can refer to the specific implementation manner and technical effects of the control method of the chip temperature impact verification device of any of the above-mentioned embodiments.

[0087] In addition, an embodiment of the present application further provides a computer-readable storage medium, which stores computer-executable instructions, and the computer-executable instructions are used to execute the control method of the chip temperature impact verification device described above. Figures 6 to 13 The method steps in .

[0088] It is worth noting that since the computer-readable storage medium of the embodiment of the present application can execute the control method of the chip temperature impact verification device of any of the above-mentioned embodiments, the specific implementation manner and technical effects of the computer-readable storage medium of the embodiment of the present application can refer to the specific implementation manner and technical effects of the control method of the chip temperature impact verification device of any of the above-mentioned embodiments.

[0089] In addition, an embodiment of the present application further provides a computer program product, including a computer program or a computer instruction, the computer program or the computer instruction is stored in a computer-readable storage medium, the processor of the computer device reads the computer program or the computer instruction from the computer-readable storage medium, and the processor executes the computer program or the computer instruction, so that the computer device executes the control method of the chip temperature impact verification device described above. Exemplarily, the execution of the above-described Figures 6 to 13 The method steps in .

[0090] It is worth noting that since the computer program product of the embodiment of the present application can execute the control method of the chip temperature impact verification device of any of the above-mentioned embodiments, the specific implementation method and technical effects of the computer program product of the embodiment of the present application can refer to the specific implementation method and technical effects of the control method of the chip temperature impact verification device of any of the above-mentioned embodiments.

[0091] It will be appreciated by those skilled in the art that all or some of the steps and systems in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or transient medium). As known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically include computer readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0092] It should be understood that in the present application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0093] In several embodiments provided in the present application, it should be understood that the disclosed systems, apparatuses and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely schematic, for example, the division of units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of apparatuses or units, which can be electrical, mechanical or other forms. The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the scheme of this embodiment.

[0094] It should also be understood that the various implementations provided in the embodiments of the present application can be combined arbitrarily to achieve different technical effects.

[0095] The above is a specific description of the preferred implementation of the present application, but the present application is not limited to the above implementation mode. Technical personnel familiar with the field can also make various equivalent modifications or substitutions under the shared conditions without violating the spirit of the present application. These equivalent modifications or substitutions are all included in the scope defined by the claims of the present application.

Claims

1. A control method for a chip temperature impact verification device, characterized in that: The chip temperature influence verification device comprises a control device, a heat exchanger, a semiconductor refrigerator and a heat-conducting structure, wherein the heat-conducting structure is used to contact the chip to be tested, and the shape of the heat-conducting structure corresponds to the shape of the chip to be tested, the heat exchanger and the heat-conducting structure are respectively arranged on two sides of the semiconductor refrigerator, and the control device is respectively connected to the semiconductor refrigerator and the heat-conducting structure; The method is applied to the control device, and the method comprises: receiving a target temperature input by a user, and detecting a real-time temperature of the heat-conducting structure; Controlling the current parameters of the semiconductor refrigerator according to the target temperature and the real-time temperature, generating a Peltier effect through the semiconductor refrigerator, so that the real-time temperature of the heat-conducting structure reaches the target temperature, wherein the current parameters include current direction and / or current magnitude; When the real-time temperature reaches the target temperature, detecting a plurality of current chip parameters of the chip to be tested; Compare the multiple current chip parameters with multiple preset parameter values ​​respectively to obtain parameter deviation results, wherein each of the preset parameter values ​​is determined by sample chip parameters of multiple qualified sample chips at the target temperature; The degree of influence of the target temperature on the chip to be tested is determined according to the parameter deviation result.

2. The method according to claim 1, characterized in that The controlling of the current parameter of the semiconductor refrigerator according to the target temperature and the real-time temperature comprises at least one of the following: When the target temperature is higher than the real-time temperature, the current direction of the semiconductor refrigerator is controlled to be a first direction, so that the semiconductor refrigerator transfers heat to the heat-conducting structure, wherein the temperature difference between the target temperature and the real-time temperature is positively correlated with the current of the semiconductor refrigerator; When the target temperature is lower than the real-time temperature, the current direction of the semiconductor refrigerator is controlled to a second direction so that the semiconductor refrigerator absorbs heat from the heat-conducting structure, wherein the second direction and the first direction are opposite directions, and the temperature difference between the real-time temperature and the target temperature is positively correlated with the current size of the semiconductor refrigerator.

3. The method according to claim 1, characterized in that When the target temperature includes a first target temperature and a second target temperature, wherein the first target temperature is higher than the real-time temperature and the second target temperature is lower than the real-time temperature; the current parameter of the semiconductor refrigerator is controlled according to the target temperature and the real-time temperature, comprising: By switching the current direction of the semiconductor refrigerator, the heat-conducting structure is periodically heated and cooled, so that the real-time temperature repeatedly reaches the first target temperature and the second target temperature; Until the number of round trips reaches a preset number of test times, stop controlling the semiconductor refrigerator; The cooling time required for the real-time temperature to drop from the first target temperature to the second target temperature, and the heating time required for the real-time temperature to rise from the second target temperature to the first target temperature are both less than the preset time.

4. The method according to claim 1, characterized in that When the real-time temperature reaches the target temperature, detecting multiple current chip parameters of the chip to be tested includes: When the real-time temperature reaches the target temperature, the chip temperature impact verification device is grasped by a mechanical arm and moved downward, so as to apply downward pressure to the chip to be tested through the heat-conducting structure; When the downward pressure applied by the heat-conducting structure to the chip to be tested is within a preset pressure test range, a plurality of current chip parameters of the chip to be tested are detected.

5. The method according to claim 1, characterized in that When the real-time temperature reaches the target temperature, detecting multiple current chip parameters of the chip to be tested includes: When the real-time temperature reaches the target temperature, the chip temperature influence verification device is grasped by a mechanical arm and moves back and forth, so as to collide with the chip to be tested multiple times through the heat-conducting structure; When the collision number is greater than or equal to the preset test number, multiple current chip parameters of the chip to be tested are detected.

6. The method according to claim 1, characterized in that The chip to be tested is arranged on the circuit board to be tested; before controlling the current parameter of the semiconductor refrigerator according to the target temperature and the real-time temperature, the method further comprises: Generating a virtual coordinate system corresponding to the circuit board to be tested according to the circuit board to be tested; Obtaining the coordinate position of the chip to be tested on the circuit board to be tested, and grabbing the chip temperature impact verification device by a mechanical arm to perform a planar movement in the virtual coordinate system; After the heat-conducting structure moves to the coordinate position, the chip temperature impact verification device is grasped by a mechanical arm and moved downward, so that the heat-conducting structure is pressed against the surface of the chip to be tested.

7. The method according to claim 1, characterized in that The preset parameter value is determined by the following steps: Obtaining sample chip parameters of each qualified sample chip at the target temperature; Performing concentration analysis on the plurality of sample chip parameters, and determining a parameter range whose concentration is higher than a preset degree, and determining the sample chip parameters within the parameter range as target sample chip parameters; An average value of the target sample chip parameters is calculated to obtain the preset parameter value.

8. A chip temperature impact verification device, characterized in that: A control method for a chip temperature impact verification device based on any one of claims 1 to 7; The chip temperature impact verification device comprises: A control device, a heat exchanger, a semiconductor refrigerator and a heat-conducting structure, wherein the heat-conducting structure is used to contact the chip to be tested, and the shape of the heat-conducting structure corresponds to the shape of the chip to be tested. The heat exchanger and the heat-conducting structure are respectively arranged on two sides of the semiconductor refrigerator, and the control device is respectively connected to the semiconductor refrigerator and the heat-conducting structure.

9. The chip temperature influence verification device according to claim 8, characterized in that: The first heat insulation layer is arranged on the surrounding side surfaces and the exposed bottom surface of the semiconductor refrigerator; and the second heat insulation layer is arranged on the surrounding side surfaces of the heat-conducting structure.

10. The chip temperature influence verification device according to claim 8, characterized in that: The semiconductor cooler and the heat-conducting structure are detachably arranged to replace the heat-conducting structure corresponding to the shape and size of the chip to be tested.

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