V-groove optical fiber barrier

Abstract

An apparatus includes a silicon substrate and a waveguide on the silicon substrate. A recess is in the substrate, the recess having a sloped back wall adjacent the waveguide. A trench is in the substrate, the trench passing through the sloped back wall in a second direction generally orthogonal to the first direction, the trench having a vertical wall at an intersection with the sloped back wall. An optical fiber in the groove, wherein one end of the optical fiber abuts the vertical wall.

Description

Background Art

[0001] Today's consumer electronics market often requires complex functions that require very complex circuit modules. Scaling down to smaller and smaller basic building blocks (e.g., transistors) has enabled the incorporation of even more complex circuit modules on a single die with each progressive generation. Semiconductor packaging is used to protect the integrated circuit (IC) chip or die and provide the die with an electrical interface to external circuit modules. As the demand for smaller electronic devices increases, semiconductor packages are designed to be even more compact and must support greater circuit density.

[0002] For example, the trend in semiconductor packaging is to move optical interconnects into the package to interface directly with the logic chip for increased data transmission speeds using optical transmission. The optical interconnect can include a photonic integrated circuit (PIC) connected to a processor or memory, which is connected to an external component through an optical fiber array and a corresponding optical connector or ferrule. One problem is that the optical interconnect package requires less than sub-micron alignment accuracy to align the optical fiber to the on-chip photonic waveguide. The V-groove array is a passive alignment structure that has become a standard way to align the optical fiber to the photonic integrated circuit. However, there is a problem of how to ensure that the end of the optical fiber is in the optimal position relative to the optical input / output facet or waveguide of the PIC. The fiber array needs to be assembled simultaneously to achieve a large number of assemblies, which makes meeting the alignment accuracy requirements a major challenge for production. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Figures 1A-1E An example of a silicon v-groove structure for integrating an optical interconnect or fiber optic connector in an optical interconnect semiconductor package is shown.

[0004] Figure 2 and 3 A groove alignment structure according to the disclosed embodiments is shown, the groove alignment structure including a groove with an X-stop (Xs top) for integrating an optical interconnect or a fiber optic connector into an optical interconnect package.

[0005] Figure 4 Further shown is a wafer level sorting groove extending along a second direction through the set of grooves.

[0006] Figures 5A-5D is a cross-sectional diagram illustrating an exemplary process flow for fabricating a groove alignment structure according to the disclosed embodiments.

[0007] Fig. 6A and 6Bis a schematic diagram showing a wafer and one or more die having integrated circuit (IC) structures formed on a surface of the wafer.

[0008] Figure 7 A block diagram of an electronic system according to an embodiment of the present disclosure is shown.

[0009] Figure 8 is a cross-sectional side view of an integrated circuit (IC) device assembly that may include one or more recess alignment structures according to one or more of the embodiments disclosed herein.

[0010] Fig. 9 A computing device according to one implementation of the present disclosure is shown. DETAILED DESCRIPTION

[0011] A groove alignment structure and a manufacturing process for z-direction alignment of an optical fiber with a photonic integrated circuit are described. In the following description, many specific details, such as specific materials and processing systems, are set forth in order to provide a thorough understanding of the embodiments of the present disclosure. It will be apparent to those skilled in the art that embodiments of the present disclosure may be implemented without these specific details. In other instances, in order to avoid unnecessarily obscuring the embodiments of the present disclosure, well-known features, such as single or dual inlay processing, are not described in detail. In addition, it is to be understood that the various embodiments shown in the accompanying drawings are illustrative representations and are not necessarily drawn to scale. In some cases, various operations will be described sequentially as multiple discrete operations in a manner that is most helpful in understanding the present disclosure, however, the order of description should not be interpreted as implying that the operations are necessarily sequence-dependent. In particular, the operations do not need to be performed in the order presented.

[0012] Certain terms may also be used in the following description for reference purposes only, and thus are not intended to be limiting. For example, terms such as "upper," "lower," "above," "below," "bottom," and "top" refer to directions in the drawings to which reference is made. Terms such as "front," "back," "rear," and "side" describe the orientation and / or position of parts of a component within a consistent but arbitrary frame of reference, as made clear by reference to the text and associated drawings describing the component in question. Such terminology may include the words specifically mentioned above, derivatives thereof, and words of similar meaning.

[0013] There is an increasing need for techniques to integrate fiber optic connectors with flip chip packaging.One or more embodiments described herein are directed to groove alignment structures and fabrication processes for z-direction alignment of optical fibers with photonic integrated circuits.

[0014] To provide context, Figures 1A-1CAn example V-groove structure for integrating a fiber optic connector in an optical interconnect semiconductor package is shown. Figure 1A A top view of an optical interconnect package 100 is shown, which may include a logic die 104 mounted to a polymer substrate 102. A PIC 106 is mounted on the polymer substrate 102 and connected to the logic die 104 through the polymer substrate 102. The PIC 106 is also connected to external components through an optical fiber array 108 and a corresponding optical connector 110 (also referred to as a ferrule). The optical interconnect package 100 requires an alignment accuracy of less than 1 μm to align the optical fibers comprising the optical fiber array 108 to the PIC 106.

[0015] For example, in one embodiment, PIC 106 may provide a terabit / second optical physical layer to support high bandwidth, low latency connectivity. In one embodiment, PIC 106 refers to a single die. In another embodiment, PIC 106 may be included in a photonic multi-chip package with a laser and electronic control chip. PIC 106 may be mounted to substrate 102 via microbumps or other contacts and may be connected to logic die 104 via interconnects within substrate 102. In one embodiment, PIC 106 may have a body including a silicon substrate and a photonic device layer formed on the silicon substrate. In some embodiments, PIC 106 may include a silicon on insulator (SOI) substrate having a silicon substrate, a thick oxide layer on the substrate, and a silicon layer with a photonic device on the oxide layer. In one example, PIC 106 may have a thickness of approximately 75 μm.

[0016] Figure 1B A close-up front view of the edge of the PIC 106 is shown, illustrating that an existing solution uses a V-groove array 112 to guide and align the optical fiber array 108 into the PIC 106. The V-groove array 112 may be fabricated by wet non-isotropic etching of the silicon substrate of the PIC 106. Each groove or V-groove may have a U-shaped, square, or V-shaped cross-section.

[0017] Figure 1CA front view of one of the V-grooves is shown, showing the respective optical fibers in the optical fiber array 108 being inserted into the corresponding V-groove 112A. The sidewalls of each V-groove 112A are etched at an angle to a depth of approximately 80 μm deep, and each V-groove 112A may have a width approximately equal to the diameter of the optical fiber. After the optical fiber 108A is inserted, a compression plate (not shown) is then pressed on the top of the optical fiber 108A to push the optical fiber down into the V-groove 12A so that the center of the optical fiber 108A is aligned with the waveguide that emits light from the side of the PIC (PIC "facet") 106. In this example, each optical fiber 108A in the optical fiber array 108 may have a diameter of approximately 125 μm, and there may be a gap (e.g., ~17.5 μm) between the optical fiber 108A and the bottom of the V-groove 112A.

[0018] Figure 1D and 1E 112A. Figure 1D 112A is shown as transparent so that the bottom of the V-groove 112A is visible. Because the non-isotropic etching process for forming the V-groove uses the silicon substrate 106A of the PIC 106 <111> The crystal plane acts as an etching stop, so each V-groove 112A is formed with two inclined side walls 114A, an inclined rear wall 114B adjacent to the waveguide 116, and a bottom 114C. The optical fiber 108A is shown inserted into the V-groove 112A and facing the waveguide 116 on the PIC 106 at or near the top of the rear wall 114B. The waveguide 116 is a channel for guiding light, which is emitted by the waveguide end face called a facet. The waveguide 116 can be made of a variety of materials, including silicon, silicon nitride, and indium phosphide.

[0019] like Figure 1E As shown in FIG. 1 , due to the inclined rear wall 114B at the end of the V-groove 112A, once the optical fiber 108A is inserted and pushed toward the waveguide 116 in the x-direction (along the fiber axis), the optical fiber 108A hits the inclined rear wall 114B and stops. The distance between the facet of the PIC 106 and the inserted optical fiber 108A is about 60 μm. Unfortunately, at this distance, there is a loss of light entering the optical fiber 108A from the facet. To prevent light loss, the optical fiber 108A should be within a distance of 20 μm from the waveguide.

[0020] While V-grooves are well known for ensuring adequate xy alignment of optical fibers, what is needed is an improved groove alignment structure that ensures accurate positioning of the optical fiber near the waveguide in the x-direction. Such a groove alignment structure should also reduce the risk of optical fiber colliding with the PIC facet and damaging both the optical fiber and the PIC facet.

[0021] According to the disclosed embodiments, an improved groove alignment structure and manufacturing process for x-direction alignment of an optical fiber with a waveguide of a PIC are described. The embodiments disclose a groove alignment structure having a novel X-block built into the groove that effectively controls the x-direction alignment of the optical fiber with the PIC. In the embodiments, the X-block is formed by creating a fiber blocking groove through the inclined rear wall of the groove. The fiber blocking groove forms a vertical wall at the intersection with the inclined rear wall near the waveguide, which defines the X-block. The optical fiber inserted into the groove alignment structure abuts the X-block instead of the rear wall. The use of the X-block ensures that the optical fiber is at a distance of 10-20 μm from the waveguide. In addition, the fiber blocking ensures that the optical fiber is not pushed too far forward in the x-direction so that the optical fiber contacts the waveguide, which prevents potential damage to the waveguide and improves the yield of the PIC 106.

[0022] Figure 2 and 3 An example of a groove alignment structure is shown, which includes a groove with an X-block for integrating an optical interconnect or fiber optic connector into an optical interconnect package, such as optical interconnect package 100. Groove 212 represents a groove including a groove array, which is intended to replace Figure 1B The V-groove array 112 is provided. Figure 2 A cross-sectional view of the groove 212 holding the inserted optical fiber 208 is shown.

[0023] According to the disclosed embodiment, similar to Figure 1A and Figure 1B , a device such as a groove alignment structure 200 includes a substrate 206 (e.g., silicon) of a PIC. A waveguide 216 is on the substrate 206. A groove 212 is along a first direction, and the groove includes an inclined back wall 214B adjacent to the waveguide 216. A trench 220 is in the substrate 206 along a second direction that is generally orthogonal (±10%) to the first direction and passes through the inclined back wall 214B. The trench 220 forms a vertical wall at the intersection with the corresponding inclined back wall to produce an X-block 222. An optical fiber 208 is in the groove 212, wherein one end of the optical fiber 208 abuts the vertical wall.

[0024] Grooves 212 are part of an array of grooves, and bonding material (not shown) may be located at the bottom of grooves 212. Optical fibers 208 may include a portion of an array of optical fibers located in a set of grooves above the bonding material, with a portion of each of the optical fibers extending or rising above substrate 206.

[0025] In an embodiment, the X-stop 222 is designed to contact the cladding, rather than the optical core, of the optical fiber 208. This ensures that the optical fiber 208 can be repeatedly inserted from the waveguide 216 into a specified x-direction without hitting or damaging the core of the optical fiber 208.

[0026] X-block 222 also ensures that the longest fiber in the fiber array is always less than 60 μm from the facet of waveguide 216. Figure 2 As shown in FIG, the vertical wall defining the X-barrier 222 is located between 10-20 μm from the waveguide 216. Therefore, there is a distance of 10-20 μm between the optical fiber 208 and the waveguide 216, and a gap is maintained between the optical fiber 208 and the waveguide 216.

[0027] In one embodiment, the fiber blocking groove 220 forming the X-block 222 may include a single continuous fiber groove extending through each groove 212 of the plurality of grooves. In an alternative embodiment, the fiber blocking groove 220 may be discontinuous, such that each groove 212 of the plurality of grooves includes a corresponding fiber blocking groove 220.

[0028] According to the disclosed embodiment, the X-stop 222 provides effective x-direction alignment of the optical fiber with the waveguide 216 on the substrate 206. Even if the mechanical assembly dictates that the optical fiber 208 be pushed closer to the waveguide 216 than normal, the X-stop 222 will protect the facets of the waveguide 216 from being scratched or damaged by contact with the optical fiber 208, which also ensures that the optical quality of the optical fiber and the PIC facets will not be compromised.

[0029] Figure 3 A cross-sectional view of the groove 212 without the optical fiber 208 is shown, showing the groove 212 with the optical fiber blocking groove and the optional wafer level sorting groove 402 in the substrate 206 adjacent to the optical fiber blocking groove 220. The wafer level sorting groove is a groove etched into the substrate to define the boundaries of individual dies (e.g., PICs) and facilitate separation of the dies from the wafer after wafer level testing. In one embodiment, the wafer level sorting groove 402 is a single continuous groove extending through multiple grooves.

[0030] The optical fiber blocking groove 220 and the wafer-level sorting groove 402 can be formed simultaneously after the grooves are formed by a single dry etching process. In one embodiment, the wafer-level sorting groove 402 is etched to a deeper depth than the optical fiber blocking groove 220. For example, in one embodiment, the depth of the optical fiber blocking groove 220 can be between about 150-200 μm, while the depth of the wafer-level sorting groove 402 can be in the range of from 180-260 μm, wherein the area of ​​the wafer-level sorting groove 402 between the grooves is shallower than the area of ​​the wafer-level sorting groove 402 etched into the bottom of the groove 212.

[0031] Figure 4 An angled side view of the PIC 206 and a groove array including a set of grooves 404 adjacent to the waveguide 216 is shown. Figure 4Also shown is an enlarged view of groove 212 in the set of grooves 404 .

[0032] The PIC 206 includes a substrate, and the set of grooves 404 are aligned with the waveguide 216 along a first direction on the top surface of the substrate. As shown in the enlarged view, each groove 212 has two inclined side walls 414A and 414B, and an inclined rear wall 214B adjacent to the waveguide 216. A set of one or more fiber blocking grooves 220 extend through the inclined rear wall 214B of the groove 212 along a second direction generally orthogonal to the first direction. As described above, the one or more fiber blocking grooves 220 each form a vertical wall at the intersection with the inclined rear wall 214B of the groove 212 to produce a corresponding X-block. Once a corresponding optical fiber (not shown) is inserted into each groove 212, one end of the corresponding optical fiber abuts the vertical wall (X-block) of the groove 212. The vertical wall defines a distance of 10-20 μm between the optical fiber and the waveguide 216.

[0033] Figure 4 Also shown is a wafer-level sorting groove 402 that passes through the set of grooves 404 along the second direction. In this embodiment, the fiber blocking groove 220 is discontinuous so that the grooves in the set of grooves 404 include corresponding fiber blocking grooves. The wafer-level sorting groove 402 is shown as continuous and extends through the set of grooves 404. The wafer-level sorting groove 402 is positioned so that there is a gap between the wafer-level sorting groove 402 and the vertical wall. In one embodiment, the wafer-level sorting groove 402 can be located approximately 50-60 μm away from the fiber blocking groove 220. The wafer-level sorting groove 402 effectively divides the groove 212 into two parts to form a first groove 212A and a second groove 212B. In one embodiment, the length of the second groove 12B can be approximately 800 μm.

[0034] In one embodiment, the optical fiber may have a diameter of approximately 80-125 μm and a pitch of approximately 125-250 μm. The set of grooves 404 may each have a width approximately equal to the diameter of the optical fiber.

[0035] Figures 5A-5D is a cross-sectional view illustrating an exemplary process flow for fabricating a groove alignment structure according to the disclosed embodiments. Figure 5A It is shown that the process may begin by performing a first etching process through the dielectric stack (not shown) of the PIC 506 having the waveguide 516 to expose the substrate 506A of the PIC 506 where the grooves will be formed. In one embodiment, the substrate 506A comprises silicon (Si), but may comprise other materials including, but not limited to, silicon germanium (SiGe), silicon on insulator (SOI), and Group II IV semiconductors.

[0036] In an embodiment, the first etching process can be performed by dry etching (e.g., reactive ion etching) or a laser etching process. Laser etching (if used) can also allow the groove to be created after the PIC is attached to the package (e.g., package 100), which reduces the risk of PIC cracking. Any type of dry etching process, whether directional or anisotropic etching, can be used. Alternatively, wet etching can be used instead of dry etching. The etching process is performed after forming an etching mask using known photolithography methods. In some embodiments, the etching mask can be a hard mask of silicon dioxide or silicon nitride; and in other embodiments, the etching mask is made of known photoresist materials.

[0037] Figure 5B A second etching process is shown being performed through an etching mask to form openings in the substrate 506A that define the location, width, and length of a plurality of grooves along a first direction of the substrate (e.g., along the axis of the waveguide). The second etching process can be performed so that each groove 512 of the plurality of grooves has an inclined sidewall, a bottom, and an inclined back wall 514. The second etching process defines the X and Y alignment of the optical fiber array. Once inserted into the grooves, the optical fibers move within the plane (X) of the substrate 206A (see Figure 1D ).

[0038] In an embodiment, the second etching process may be performed by a crystalline silicon wet etching using tetramethylammonium hydroxide (TMAH) or a KOH etching process. The substrate 506A is wet etched for a predetermined amount of time to form the recesses to a desired depth, for example, 80 μm.

[0039] Figure 5C It is shown that after performing the second etching to form the groove 512, a third etching process is performed to create a fiber blocking groove 520 through the back wall 514 of the groove adjacent to the waveguide 516. The fiber blocking groove 520 forms a vertical wall at the intersection with the inclined back wall 514 to form an X-block 522. The vertical wall or X-block 522 of the fiber blocking groove formed in the back wall 514 defines the distance between the end of the waveguide 516 and the end of the optical fiber inserted into the corresponding groove. In an embodiment, the third etching process can be performed by dry etching (e.g., reactive ion etching) or a laser etching process. In an embodiment, the third etching process for creating the fiber blocking groove 520 can also be used to create Figure 4 Wafer-level sorting trenches shown in .

[0040] Figure 5DIt is shown that after the third etching process, bonding material 526 is optionally dispensed into the bottom of each of the grooves 512, and optical fibers 508 of the optical fiber array are inserted into corresponding grooves in the grooves 512 on the bonding material 526. Approximately half of each of the optical fibers 508 extends above the surface of the substrate 506A. The resulting groove alignment structure can then be covered with a polymer cap (not shown).

[0041] refer to Fig. 6A and Figure 6B , wafer 600 may be composed of semiconductor material and may include one or more dies 602 having integrated circuit (IC) structures formed on a surface of wafer 600. Each of dies 602 may be a repeating unit of a semiconductor product including any suitable IC (e.g., an IC including a substrate having a V-groove and corresponding fiber blocking grooves forming an X-block, such as described above). After fabrication of the semiconductor product is complete, wafer 600 may undergo a singulation process in which each of dies 602 is separated from one another to provide discrete "chips" of the semiconductor product. In particular, a structure including an embedded non-volatile memory structure having a substrate having a V-groove and corresponding fiber blocking grooves forming an X-block as disclosed herein may take the form of wafer 600 (e.g., unsingulated) or dies 602 (e.g., singulated). Dies 602 may include one or more embedded non-volatile memory structures and / or supporting circuit modules used to route electrical signals, as well as any other IC components. In some embodiments, wafer 600 or die 602 may include additional memory devices (e.g., static random access memory (SRAM) devices), logic devices (e.g., AND gates, OR gates, NAND gates, or NOR gates), or any other suitable circuit elements. Multiple of these devices may be combined on a single die 602. For example, a memory array formed from multiple memory devices may be formed on the same die 602 as a processing device or other logic configured to store information in the memory devices or to execute instructions stored in the memory array.

[0042] Embodiments disclosed herein can be used to manufacture various types of integrated circuits and / or microelectronic devices. Examples of such integrated circuits include, but are not limited to, processors, chipset components, graphics processors, digital signal processors, microcontrollers, etc. In other embodiments, semiconductor memories can be manufactured. In addition, integrated circuits or other microelectronic devices can be used in various electronic devices known in the art. For example, in computer systems (e.g., desktops, laptops, servers), cellular phones, personal electronic devices, etc. The integrated circuit can be coupled to buses and other components in the system. For example, a processor can be coupled to a memory, a chipset, etc. via one or more buses. Each of the processor, memory, and chipset can potentially be manufactured using the methods disclosed herein.

[0043] Figure 7 A block diagram of an electronic system 700 according to an embodiment of the present disclosure is shown. The electronic system 700 may correspond to, for example, a portable system, a computer system, a process control system, or any other system that utilizes a processor and associated memory. The electronic system 700 may include a microprocessor 702 (having a processor 704 and a control unit 706), a memory device 708, and an input / output device 710 (it is to be appreciated that in various embodiments, the electronic system 700 may have multiple processors, control units, memory device units, and / or input / output devices). In one embodiment, the electronic system 700 has a set of instructions that define operations to be performed on data by the processor 704, as well as other transactions between the processor 704, the memory device 708, and the input / output device 710. The control unit 706 coordinates the operations of the processor 704, the memory device 708, and the input / output device 710 by looping a set of operations that cause instructions to be retrieved and executed from the memory device 708. The memory device 708 may include a non-volatile memory unit as described in this specification. In an embodiment, the memory device 708 is embedded in the microprocessor 702, such as Figure 7 In an embodiment, the processor 704 or another component of the electronic system 700 includes a substrate having a V-groove and a corresponding fiber blocking trench forming an X-block, such as those described herein.

[0044] Figure 8 is a cross-sectional side view of an integrated circuit (IC) device assembly that may include a substrate having a V-groove and a corresponding fiber blocking trench forming an X-block according to one or more embodiments disclosed herein.

[0045] refer to Figure 8, the IC device assembly 800 includes a component having one or more integrated circuit structures described herein. The IC device assembly 800 includes a plurality of components disposed on a circuit board 802 (which may be, for example, a motherboard). The IC device assembly 800 includes components disposed on a first side 840 of the circuit board 802 and an opposite second side 842 of the circuit board 802. Generally, the components may be disposed on one or both of the sides 840 and 842. In particular, any suitable component of the components of the IC device assembly 800 may include a plurality of multilayer high-k gate dielectrics, such as disclosed herein.

[0046] In some embodiments, circuit board 802 may be a printed circuit board (PCB) including multiple metal layers separated from each other by layers of dielectric material and interconnected by conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals between components coupled to circuit board 802 (optionally in conjunction with other metal layers). In other embodiments, circuit board 802 may be a non-PCB substrate.

[0047] Figure 8 The IC device assembly 800 shown in FIG. 8 includes an interposer package structure 836 coupled to a first side 840 of a circuit board 802 via a coupling component 816. The coupling component 816 can electrically and mechanically couple the interposer package structure 836 to the circuit board 802 and can include solder balls (e.g., Figure 8 ), protrusions and recesses of the socket, adhesive, bottom fill material and / or any other suitable electrical and / or mechanical coupling structure.

[0048] The package-on-interposer structure 836 may include an IC package 820 coupled to the interposer 804 via a coupling assembly 818. The coupling assembly 818 may take any suitable form for the application, such as the forms discussed above with reference to the coupling assembly 816. Figure 8 804, but multiple IC packages may be coupled to the interposer 804. It is appreciated that additional interposers may be coupled to the interposer 804. The interposer 804 may provide an intermediate substrate for bridging the circuit board 802 and the IC package 820. The IC package 820 may be or include, for example, a die ( Figure 6B Typically, the interposer 804 can extend the connection to a wider spacing or reroute the connection to a different connection. For example, the interposer 804 can couple the IC package 820 (e.g., the die) to a ball grid array (BGA) of the coupling component 816 for coupling to the circuit board 802. Figure 8In the embodiment shown in FIG. 8 , IC package 820 and circuit board 802 are attached to opposite sides of interposer 804. In other embodiments, IC package 820 and circuit board 802 can be attached to the same side of interposer 804. In some embodiments, three or more components can be interconnected through interposer 804.

[0049] The interposer 804 may be formed of epoxy, glass fiber reinforced epoxy, ceramic material or polymer material such as polyimide. In some implementations, the interposer 804 may be formed of alternative rigid or flexible materials, which may include the same materials used in the semiconductor substrate, such as silicon, germanium and other II IV and IV materials. The interposer 804 may include metal interconnects 810 and through holes 808, including but not limited to through silicon vias (TSVs) 806. The interposer 804 may also include embedded devices, including both passive and active devices. Such devices may include but are not limited to capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices and memory devices. More complex devices such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors and micro-electromechanical systems (MEMS) devices may also be formed on the interposer 804. The interposer package structure 836 may take the form of any interposer package structure known in the art.

[0050] IC device assembly 800 may include an IC package 824 coupled to first side 840 of circuit board 802 via coupling assembly 822. Coupling assembly 822 may take the form of any of the embodiments discussed above with reference to coupling assembly 816, and IC package 824 may take the form of any of the embodiments discussed above with reference to IC package 820.

[0051] Figure 8 The IC device assembly 800 shown in the figure includes a package-on-package structure 834 coupled to the second side 842 of the circuit board 802 by a coupling component 828. The package-on-package structure 834 may include an IC package 826 and an IC package 832 coupled together by a coupling component 830, such that the IC package 826 is disposed between the circuit board 802 and the IC package 832. The coupling components 828 and 830 may take the form of any of the embodiments of the coupling component 816 described above, and the IC packages 826 and 832 may take the form of any of the embodiments of the IC package 820 described above. The package-on-package structure 834 may be configured according to any package-on-package structure known in the art.

[0052] Fig. 9A computing device 900 according to one implementation of the present disclosure is shown. The computing device 900 houses a board 902. The board 902 may include a plurality of components, including, but not limited to, a processor 904 and at least one communication chip 906. The processor 904 is physically and electrically coupled to the board 902. In some implementations, at least one communication chip 906 is also physically and electrically coupled to the board 902. In further implementations, the communication chip 906 is part of the processor 904.

[0053] Depending on its application, the computing device 900 may include other components that may or may not be physically and electrically coupled to the board 902. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, graphics processors, digital signal processors, cryptographic processors, chipsets, antennas, displays, touch screen displays, touch screen controllers, batteries, audio codecs, video codecs, power amplifiers, global positioning system (GPS) devices, compasses, accelerometers, gyroscopes, speakers, cameras, and mass storage devices (e.g., hard drives, compact disks (CDs), digital versatile disks (DVDs), etc.).

[0054] The communication chip 906 enables wireless communication for transmitting data to and from the computing device 900. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., which can transmit data using modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated device does not contain any wires, although in some embodiments they may not contain any wires. The communication chip 906 can implement any of a variety of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, its derivatives, and any other wireless protocols designated as 3G, 4G, 5G and higher levels. The computing device 900 may include multiple communication chips 906. For example, the first communication chip 906 may be dedicated to short-range wireless communications such as Wi-Fi and Bluetooth, while the second communication chip 906 may be dedicated to long-range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, etc.

[0055] The processor 904 of the computing device 900 includes an integrated circuit die packaged within the processor 904. According to implementations of embodiments of the present disclosure, in some implementations of the present disclosure, the integrated circuit die of the processor includes a substrate having a V-groove and a corresponding fiber blocking groove forming an X-block. The term "processor" may refer to any device or portion of a device that processes electronic data from a register and / or memory to convert that electronic data into other electronic data that may be stored in a register and / or memory.

[0056] The communication chip 906 also includes an integrated circuit die packaged within the communication chip 906. According to another implementation of an embodiment of the present disclosure, the integrated circuit die of the communication chip 906 includes a substrate having a V-groove and a corresponding fiber blocking groove forming an X-block.

[0057] In further implementations, another component housed within computing device 900 may include an integrated circuit die including a substrate having a V-groove and corresponding fiber blocking trenches forming an X-block, in accordance with implementations of embodiments of the present disclosure.

[0058] In various implementations, computing device 900 may be a laptop, a netbook, a notebook, an ultrabook, a smart phone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, computing device 900 may be any other electronic device that processes data.

[0059] Thus, embodiments described herein include V-groove fiber stops.

[0060] The above description of the illustrated implementation of the embodiments of the present disclosure (including the content described in the Abstract) is not intended to be exhaustive or limit the present disclosure to the exact form disclosed. Although specific implementations and examples of the present disclosure are described herein for illustrative purposes, as will be appreciated by those skilled in the relevant art, various equivalent modifications are possible within the scope of the present disclosure.

[0061] These modifications may be made to the present disclosure in light of the above detailed description. The terms used in the following claims should not be interpreted as limiting the present disclosure to the specific implementations disclosed in the specification and claims. Instead, the scope of the present disclosure will be determined entirely by the following claims, which will be interpreted in accordance with established principles of claim interpretation.

[0062] Example Embodiment 1: An apparatus comprising a silicon substrate and a waveguide on the silicon substrate. A groove is in the substrate, the groove having an inclined back wall adjacent to the waveguide. A trench is in the substrate, the trench passing through the inclined back wall along a second direction generally orthogonal to the first direction, the trench having a vertical wall at the intersection with the inclined back wall. An optical fiber in the groove, wherein one end of the optical fiber abuts the vertical wall.

[0063] Example embodiment 2: The device as described in embodiment 1, wherein the vertical wall is between 10-20 μm from the waveguide.

[0064] Example Embodiment 3: The device as described in Embodiment 1 or 2 further includes a plurality of grooves in the substrate, and wherein the groove includes a single continuous groove extending through the plurality of grooves.

[0065] Example Embodiment 4: The device as described in Embodiment 1, 2 or 3 further includes a plurality of grooves in the substrate, wherein the groove passes through each groove of the plurality of grooves discontinuously.

[0066] Example embodiment 5: The device as described in embodiment 1, 2, 3 or 4, wherein the depth of the optical fiber blocking groove is between 150-200μm.

[0067] Example embodiment 6: The device as described in embodiment 1, 2, 3, 4 or 5, wherein the groove includes a first groove, and the device also includes a second groove adjacent to the first groove in the substrate.

[0068] Example Embodiment 7: The device of Embodiment 1, 2, 3, 4, 5 or 6, wherein the depth of the second groove ranges from 180-260 μm.

[0069] Example Embodiment 8: A device as described in Embodiment 1, 2, 3, 4, 5, 6 or 7, wherein the groove has a U-shaped, square or V-shaped cross-section.

[0070] Example Embodiment 9: The device of Embodiment 1, 2, 3, 4, 5, 6, 7 or 8, wherein the depth of the groove is approximately 80 μm.

[0071] Example embodiment 10: A device includes a photonic integrated circuit (PIC) having a substrate. A set of grooves is in the substrate, wherein the grooves in the set of grooves have two inclined side walls and an inclined back wall. A set of one or more grooves passes through the inclined back wall of the groove along a second direction generally orthogonal to the first direction, and one or more grooves have a vertical wall at the intersection with the inclined back wall of the groove. A corresponding optical fiber is in the groove, wherein one end of the corresponding optical fiber abuts the vertical wall of the groove.

[0072] Example Embodiment 11: The device as described in Embodiment 10, wherein the groove includes a first groove and the device further includes a second groove passing through the set of grooves along a second direction.

[0073] Example Embodiment 12: The device as described in Embodiment 11, wherein there is a gap between the second groove and the vertical wall.

[0074] Example Embodiment 13: The device of Embodiment 11 or 12, wherein the second trench is located approximately 50-60 μm from the first trench.

[0075] Example Embodiment 14: The device as described in Embodiment 10, 11, 12 or 13, further comprising a waveguide on the substrate, wherein the vertical wall is between 10-20 μm from the waveguide.

[0076] Example Embodiment 15: A device as described in Embodiment 10, 11, 12, 13 or 14, wherein the groove includes a single continuous optical fiber groove extending through the set of grooves.

[0077] Example Embodiment 16: A device as described in Embodiment 10, 11, 12, 13, 14 or 15, wherein the grooves are discontinuous so that the grooves in the group of grooves include corresponding grooves.

[0078] Example embodiment 17: A method for manufacturing a device, comprising performing a first etching process through a dielectric stack to expose a substrate where grooves are to be formed. Performing a second etching process to form a plurality of grooves along a first direction of the substrate, so that some of the grooves in the plurality of grooves have inclined side walls, a bottom, and an inclined rear wall. Performing a third etching process to create grooves through the inclined rear walls of some of the grooves that form vertical walls at intersections with the inclined rear walls. An adhesive material is deposited into the bottom of the groove, and optical fibers of an optical fiber array are inserted into corresponding grooves in the grooves.

[0079] Example embodiment 18: The method as described in embodiment 17 also includes: performing a first etching process using dry etching.

[0080] Example embodiment 19: The method as described in embodiment 17 or 18 also includes: performing a second etching process using a wet etching process using tetramethylammonium hydroxide (TMAH) or a KOH etching process.

[0081] Example embodiment 20: The method as described in embodiment 17, 18 or 19 also includes: performing a third etching process using dry etching.

Claims

1. A device comprising: Silicon substrate; a waveguide on the silicon substrate; a groove in the substrate, the groove having an inclined rear wall adjacent the waveguide; a trench in the substrate, the trench extending through the inclined rear wall along a second direction generally orthogonal to the first direction, the trench having a vertical wall at an intersection with the inclined rear wall; and An optical fiber is in the groove, wherein one end of the optical fiber abuts the vertical wall.

2. The device according to claim 1, wherein: The vertical wall is located between 10-20 μm from the waveguide.

3. The apparatus of claim 1 or 2, further comprising a plurality of grooves in the substrate, and wherein the trench comprises a single continuous trench extending through the plurality of grooves.

4. The apparatus of claim 1 or 2, further comprising a plurality of grooves in the substrate, wherein the trench is discontinuous across each of the plurality of grooves.

5. The device according to claim 1 or 2, wherein: The depth of the groove is between 150-200 μm.

6. The device according to claim 1 or 2, wherein: The trenches include a first trench and the device further includes a second trench in the substrate adjacent to the first trench.

7. The device according to claim 6, wherein: The depth of the second trench ranges from 180-260 μm.

8. The device according to claim 1 or 2, wherein: The groove has a U-shaped, square-shaped or V-shaped cross section.

9. The device according to claim 1 or 2, wherein: The depth of the grooves was about 80 μm.

10. An apparatus comprising: A photonic integrated circuit (PIC) having a substrate; a set of grooves in the substrate, wherein the grooves in the set of grooves have two inclined side walls and an inclined back wall; a set of one or more grooves extending through the inclined rear wall of the groove in a second direction generally orthogonal to the first direction, the one or more grooves having vertical walls at intersections with the inclined rear wall of the groove; and A corresponding optical fiber in the groove, wherein one end of the corresponding optical fiber abuts the vertical wall of the groove.

11. The device according to claim 10, wherein: The grooves include a first groove, and the device further includes a second groove passing through the set of grooves along the second direction.

12. The device according to claim 11, wherein There is a gap between the second groove and the vertical wall.

13. The device according to claim 11 or 12, wherein: The second trench is located approximately 50-60 μm from the first trench.

14. The apparatus of claim 10, 11 or 12, further comprising a waveguide on the substrate, wherein the vertical wall is between 10-20 μm from the waveguide.

15. The device according to claim 10, 11 or 12, wherein: The groove comprises a single continuous groove extending through the set of grooves.

16. The device according to claim 10, 11 or 12, wherein: The grooves are discontinuous such that a groove in the set of grooves comprises a corresponding groove.

17. A method for manufacturing a device, comprising: performing a first etching process through the dielectric stack to expose the substrate where the recess will be formed; performing a second etching process to form a plurality of grooves along the first direction so that some of the grooves among the plurality of grooves have inclined sidewalls, a bottom, and an inclined rear wall; performing a third etching process to create trenches through the inclined rear walls of some of the recesses, the trenches forming vertical walls at intersections with the inclined rear walls; depositing an adhesive material into the bottoms of the plurality of recesses; and The optical fibers of the optical fiber array are inserted into corresponding grooves of the plurality of grooves.

18. The method according to claim 17 further comprises: performing the first etching process using dry etching.

19. The method according to claim 17 or 18, further comprising: performing the second etching process using a wet etching process using tetramethylammonium hydroxide (TMAH) or a KOH etching process.

20. The method according to claim 17 or 18 further comprises: performing the third etching process by dry etching.

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