Random number generator and random number generation method

Abstract

The invention provides a random number generator and a random number generation method, and relates to the technical field of computers, the random number generator comprises a random number generation module, a data acquisition module and a power supply module; the power supply module is used for supplying power to the random number generation module and the data acquisition module; the random number generation module is used for generating a random digital pulse signal based on the random response time delay and the random low-resistance-state resistance value of the memristor; and the data acquisition module is used for generating a random sequence according to the random digital pulse signal. Therefore, the random response time delay and the random low-resistance-state resistance value of the memristor are introduced at the same time to serve as entropy sources, random resources of the memristor are fully utilized, the circuit structure is simplified, the circuit reliability, the randomness and the random number rate are improved, and the application scene of the random number generator is expanded.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, and in particular to a random number generator and a random number generation method. Background Art

[0002] With the rapid development of new generation information and communication technologies represented by 5G (5th Generation Mobile Communication Technology), cloud, IoT (Internet of Things), etc., information security is facing great challenges due to the easy intrusion of traditional data encryption methods. In these encryption algorithms and cryptographic protocols, the quality of random number performance directly affects the performance of the cryptographic system. Therefore, encryption technology requires more unpredictable, secure and reliable random number sequences.

[0003] A random number generator (RNG) is an algorithm or device that can generate pseudo-random or truly random number sequences. The prior art provides a random number generator that designs a single-loop circuit based on a memristor, uses the random properties of the memristor to generate a random analog signal, and generates a random number sequence based on the analog signal. However, the above scheme generally requires a complex circuit structure to construct a random number generator, and only relies on the single random property of the memristor, resulting in low random resource utilization, unstable random performance, reduced reliability, and other problems. Summary of the invention

[0004] The present disclosure provides a random number generator and a random number generation method to at least solve the above technical problems existing in the prior art.

[0005] In a first aspect, an embodiment of the present disclosure provides a random number generator, the random number generator comprising: a random number generation module, a data acquisition module, and a power supply module; The power supply module is used to supply power to the random number generation module and the data acquisition module; The random number generation module is used to generate a random digital pulse signal based on the random response delay and random low-resistance state resistance of the memristor; The data acquisition module is used to generate a random number sequence according to the random digital pulse signal.

[0006] In the above scheme, the random number generation module includes: a memristor, a capacitor, and an adjustment circuit; the first end of the adjustment circuit is connected to the first end of the memristor, and the second end of the adjustment circuit is connected to the second end of the memristor; the first end and the third end of the adjustment circuit are respectively connected to the first end and the second end of the capacitor, and the second end of the capacitor is grounded; the output end of the adjustment circuit is connected to the input end of the data acquisition module; The capacitor is used to charge or discharge the memristor to adjust the first reference voltage of the memristor; The adjustment circuit is used to output a random digital pulse signal according to the first reference voltage of the memristor.

[0007] In the above scheme, the adjustment circuit includes: an integrated circuit, a triode; The integrated circuit is used to compare the first reference voltage of the memristor, the high threshold voltage and the low threshold voltage of the resistance state change of the memristor, output a random digital pulse signal according to the comparison result, and adjust the state of the triode, the state being on or off; The state of the capacitor changes with the state of the transistor, and the state of the capacitor is charging or discharging; and the first reference voltage changes with the state of the capacitor.

[0008] In the above solution, the integrated circuit includes: a first comparator, a second comparator, and an RS trigger; The first comparator is used to compare the first reference voltage with the high threshold voltage; The second comparator is used to compare the first reference voltage with the low threshold voltage; The RS trigger is used to output a random digital pulse signal and adjust the state of the transistor according to the comparison result of the first comparator and the comparison result of the second comparator.

[0009] In the above solution, the integrated circuit further includes: the first resistor, the second resistor, and the third resistor, which are used to provide the high threshold voltage for the first comparator and provide the low threshold voltage for the second comparator.

[0010] In the above solution, the integrated circuit further includes: a buffer, which is used to adjust the output result of the RS trigger and / or buffer the output result.

[0011] In the above scheme, the data acquisition module includes: a trigger and a clock; the input end of the trigger is respectively connected to the output end of the random number generation module and the clock; the output end of the trigger is connected to the input end of the counter.

[0012] In the above scheme, the trigger is used to receive the random pulse output by the random number generation module and the clock signal from the clock, perform logical AND based on the random pulse and the clock signal, and count based on the logical AND result to obtain a random number sequence.

[0013] In the above solution, the data acquisition module further includes: a counter, which is used to control the number of data bits of the random number sequence according to the data requirements of the target device.

[0014] In the above solution, the data acquisition module further includes: a serial port unit, which is used to output the random number sequence to the target device.

[0015] In a second aspect, an embodiment of the present disclosure provides a random number generation method, which is applied to a random number generator, wherein the random number generator includes: a random number generation module and a data acquisition module; the method includes: After the random number generator is powered on, the random number generation module generates a random digital pulse signal based on the random response delay and random low-resistance resistance of the memristor; The data acquisition module generates a random number sequence according to the random digital pulse signal.

[0016] In the above scheme, the random number generation module includes: a memristor, a capacitor, and an adjustment circuit; the adjustment circuit includes: an integrated circuit and a triode; The random number generation module generates a random digital pulse signal based on the random response delay and random low-resistance resistance of the memristor, including: The integrated circuit compares the first reference voltage of the memristor, the high threshold voltage and the low threshold voltage of the resistance state change of the memristor, outputs a random digital pulse signal according to the comparison result, and adjusts the state of the triode, the state being on or off; The state of the capacitor changes with the state of the transistor, and the state of the capacitor is charging or discharging; and the first reference voltage changes with the state of the capacitor.

[0017] In the above solution, the integrated circuit includes: a first comparator, a second comparator, and an RS trigger; The integrated circuit compares the first reference voltage of the memristor, the high threshold voltage and the low threshold voltage of the resistance state change of the memristor, outputs a random digital pulse signal according to the comparison result, and adjusts the state of the triode, including: The first comparator compares the first reference voltage and the high threshold voltage; The second comparator compares the first reference voltage and the low threshold voltage; The RS trigger outputs a random digital pulse signal and adjusts the state of the transistor according to the comparison result of the first comparator and the comparison result of the second comparator.

[0018] In the above scheme, the RS trigger outputs a random digital pulse signal according to the comparison result of the first comparator and the comparison result of the second comparator, and adjusts the state of the transistor, including: If the comparison result of the first comparator is a first value and the comparison result of the second comparator is a second value, the RS trigger outputs a random digital pulse signal as a first output value, and the transistor is turned off; If the comparison result of the first comparator is the second value and the comparison result of the second comparator is the second value, the RS trigger outputs a random digital pulse signal as the second output value, and turns on the transistor.

[0019] In the above scheme, the method further includes: The output result of the RS trigger is adjusted, and / or the output result is buffered.

[0020] The disclosed embodiment provides a random number generator and a random number generation method, wherein the random number generator includes: a random number generation module, a data acquisition module, and a power supply module; the power supply module is used to supply power to the random number generation module and the data acquisition module; the random number generation module is used to generate a random digital pulse signal based on the random response delay and random low-resistance resistance of the memristor; the data acquisition module is used to generate a random number sequence according to the random digital pulse signal. The design of the random number generator and the random number generation method can achieve at least the following beneficial effects: By simultaneously introducing the random response delay and random low-resistance resistance of the memristor as entropy sources, the random resources of the memristor are fully utilized, the circuit structure is simplified, and the circuit reliability, randomness and random number rate are improved. By designing the adjustment circuit in the random number generator, the rate control function is realized and the application scenarios of the random number generator are expanded.

[0021] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 A schematic diagram of the structure of a random number generator provided in an embodiment of the present disclosure; Figure 2 A schematic diagram of the structure of a random number generation module provided in an embodiment of the present disclosure; Figure 3 A structural diagram of a data acquisition module provided in an embodiment of the present disclosure; Figure 4 A schematic diagram of a random number generation method provided in an embodiment of the present disclosure; Figure 5 A schematic diagram of the structure of an electronic device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0023] In order to make the purpose, features, and advantages of the present disclosure more obvious and easy to understand, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present disclosure.

[0024] Random generators include pseudo-random number generators (PRNG) and true random number generators (TRNG).

[0025] Pseudo-random number generators are the most common type of random number generators. They generate random numbers through deterministic algorithms. These random numbers appear to be random, but are actually determined by the initial seed value and certain mathematical operations (such as linear congruential method, Mersenne rotation method, etc.). Since they are generated by algorithms, pseudo-random number generators are predictable. If the initial seed and algorithm are known, the subsequent "random" numbers can be inferred.

[0026] A true random number generator generates random numbers through physical processes such as radioactive decay, thermal noise, photon detection, etc. Since physical phenomena are unpredictable, the generated random numbers are completely random.

[0027] The key to a true random number generator lies in the entropy source. Traditional random number generators have many defects that are difficult to make up for due to the entropy source problem. The birth of memristors has brought opportunities for the development of random number generators. In the process of changing the resistance value of a memristor under the stimulation of an external electric field, there are multiple inherent random characteristics, including random resistance, random current noise (RTN, Random Telegraph Noise), periodic random voltage and random delay. This unique random characteristic can be used independently as an entropy source to make a new type of random number generator.

[0028] The true random number generator in the prior art generally adopts a simple single-loop circuit based on a memristor design, generates a random analog signal based on the random performance of the memristor itself during the resistance state change process, and then processes the analog signal to obtain a corresponding random digital signal, and further collects and processes the digital signal to obtain a random number sequence. Although the above design scheme simplifies the circuit structure to a certain extent, it also brings some defects, such as the complexity of the random number generator module, only using the single random performance of the device, resulting in low random resource utilization, unstable random performance, unstable circuit operation, and reduced reliability.

[0029] Therefore, the embodiment of the present disclosure provides a random number generator, the random number generator comprising: a random number generation module, a data acquisition module, and a power supply module; the power supply module is used to supply power to the random number generation module and the data acquisition module; the random number generation module is used to generate a random digital pulse signal based on the random response delay and random low-resistance resistance of the memristor; the data acquisition module is used to generate a random number sequence according to the random digital pulse signal. In this way, by simultaneously introducing the random response delay and random low-resistance resistance of the memristor as entropy sources, the random resources of the memristor are fully utilized, the circuit structure is simplified, the circuit reliability, randomness and random number rate are improved, and the application scenarios of the random number generator are expanded.

[0030] Figure 1 A schematic diagram of the structure of a random number generator provided in an embodiment of the present disclosure is shown in FIG. Figure 1 As shown, the random number generator includes: a random number generation module, a data acquisition module, and a power supply module; The power supply module is used to supply power to the random number generation module and the data acquisition module; The random number generation module is used to generate a random digital pulse signal based on the random response delay and random low-resistance state resistance of the memristor; The data acquisition module is used to generate a random number sequence according to the random digital pulse signal.

[0031] In some embodiments, the power supply module provides power for the entire random number generator, ensuring that the random number generation module and the data acquisition module can operate normally, and is the energy supply part.

[0032] The random number generation module includes a memristor, which uses the characteristics of the memristor to generate a random digital pulse signal. The memristor is a special electronic component whose resistance value is not only affected by the current, but also by the history of past currents (i.e., it has a memory effect). This characteristic enables the memristor to produce a certain random response when facing external stimuli. In the embodiment of the present disclosure, random response delay and random low-resistance state resistance are used.

[0033] Among them, random response delay refers to the fact that the reaction time of the memristor to the electrical signal has a certain randomness; random low-resistance state resistance value refers to the fact that the resistance of the memristor can also show a certain randomness in the low-resistance state; entropy source refers to the source of uncertainty in the system.

[0034] Here, the random number generation module utilizes these two characteristics at the same time, generates a random digital pulse signal based on the random response delay and the random low-resistance resistance as the entropy source; the data acquisition module converts the random digital pulse signal obtained from the random response of the memristor into a series of random number sequences, which improves the circuit reliability, randomness and random number rate, and expands the application scenarios of the random number generator.

[0035] In some embodiments, the random number generation module includes: a memristor, a capacitor, and an adjustment circuit; the first end of the adjustment circuit is connected to the first end of the memristor, and the second end of the adjustment circuit is connected to the second end of the memristor; the first end and the third end of the adjustment circuit are respectively connected to the first end and the second end of the capacitor, and the second end of the capacitor is grounded; the output end of the adjustment circuit is connected to the input end of the data acquisition module; The capacitor is used to charge or discharge the memristor to adjust the first reference voltage of the memristor; The adjustment circuit is used to output a random digital pulse signal according to the first reference voltage of the memristor.

[0036] Here, the memristor is one of the key components of the random number generation module. Its resistance value changes under a certain external current, and this change has memory, that is, its resistance value is not only affected by the current, but also by the previous current history. By utilizing this characteristic, the memristor can provide a certain degree of randomness.

[0037] In order to utilize this characteristic, an adjustment circuit and a capacitor are provided. The capacitor can store and release electrical energy and participate in the voltage change process. Together with the memristor, it constitutes a part of the circuit. The charging and discharging of the capacitor can affect the output random digital pulse signal.

[0038] Here, the adjustment circuit has three ports, among which, The first terminal is connected to the first terminal of the memristor, and the second terminal is connected to the second terminal of the memristor; The first end is connected to a first end of the capacitor, the third end is connected to a second end of the capacitor, and the second end of the capacitor is grounded.

[0039] The capacitor can change the voltage of the memristor through charging and discharging, thereby affecting the resistance value of the memristor and the first reference voltage. The adjustment circuit then outputs a digital pulse signal according to the first reference voltage.

[0040] In this way, the random digital pulse signal is generated through the synergistic effect of the memristor and the capacitor, which has the characteristics of low power consumption, high efficiency, and easy integration, and is suitable for use in random number generation, encryption, secure communications, etc. By precisely controlling the charging and discharging process of the capacitor, a highly adjustable and stable random signal output can be achieved.

[0041] In some embodiments, the adjustment circuit includes: an integrated circuit, a triode; The integrated circuit is used to compare the first reference voltage of the memristor, the high threshold voltage and the low threshold voltage of the resistance state change of the memristor, output a random digital pulse signal according to the comparison result, and adjust the state of the triode, the state being on or off; The state of the capacitor changes with the state of the transistor, and the state of the capacitor is charging or discharging; and the first reference voltage changes with the state of the capacitor.

[0042] Here, the integrated circuit can adjust the conduction or cutoff of the transistor, which will affect the charging or discharging of the capacitor, and the charging or discharging of the capacitor will affect the first reference voltage of the memristor, thereby affecting the comparison result, and the comparison result will continue to affect the state of the transistor, that is, the on or off switching will occur again.

[0043] That is to say, the integrated circuit realizes the conversion of charging and discharging of the capacitor by controlling the on and off states of the transistor, thereby affecting the first reference voltage of the memristor. The first reference voltage in turn affects the comparison results of the integrated circuit, and these comparison results further adjust the working state of the transistor, forming a feedback loop, causing the transistor to switch between on and off periodically. This feedback mechanism enables the circuit to continuously output uninterrupted digital pulse signals, and due to the uncertainty in the charging and discharging process of the memristor and capacitor, the signal has a high randomness. In this way, the integrated circuit not only maintains the stability of the signal output, but also enhances the randomness of the signal, meeting the demand for high-quality random signals.

[0044] In some embodiments, the integrated circuit includes: a first comparator, a second comparator, a set input and a reset input (RS, Reset-Set) trigger; The first comparator is used to compare the first reference voltage with the high threshold voltage; The second comparator is used to compare the first reference voltage with the low threshold voltage; The RS trigger is used to output a random digital pulse signal and adjust the state of the transistor according to the comparison result of the first comparator and the comparison result of the second comparator.

[0045] Here, the high threshold voltage may also be referred to as the first threshold voltage, and the low threshold voltage may also be referred to as the second threshold voltage, the high and the low are the difference between the two threshold voltages, and the low threshold voltage is less than the high threshold voltage. There is no limitation on the values ​​of the high threshold voltage and the low threshold voltage.

[0046] Here, the RS trigger is a digital logic circuit, which can also be called an RS latch, which has two input terminals, namely: R (reset) and S (set). In the embodiment of the present disclosure, the input of the RS trigger is the comparison result of the first comparator and the comparison result of the second comparator. Assume that the comparison result of the first comparator is the S input and the comparison result of the second comparator is the R input; when applied, it can include a variety of situations, for example: If the S input is 1 and the R input is 0, the random digital pulse signal output by the RS flip-flop is 1.

[0047] If the S input and R input are both 0 at the same time, the RS flip-flop maintains its current state, that is, no change occurs.

[0048] If the S input is 0 and the R input is 1, the random digital pulse signal output by the RS flip-flop is 0.

[0049] That is, if the comparison result of the first comparator is 1 and the comparison result of the second comparator is 0, it can output 1; if the comparison result of the first comparator is 0 and the comparison result of the second comparator is 1, it can output 0.

[0050] Of course, there may be other situations for the input and output settings here. For example, if the S input is 1 and the R input is 0, the random digital pulse signal output by the RS flip-flop is 0; if the S input and the R input are both 0, the flip-flop maintains its current state, that is, does not change; if the S input is 0 and the R input is 1, the random digital pulse signal output by the RS flip-flop is 1. There is no limitation on the setting of the RS flip-flop here.

[0051] In this way, the circuit design combining the comparator and the RS trigger can efficiently generate random digital pulse signals and has many advantages. First, the dual comparison mechanism enhances the stability of the system and the tolerance to noise, ensuring the reliability of the signal output. Secondly, the flexible trigger control enables the circuit to generate accurate random signals according to demand, and is widely used in encryption, communication and other fields. In addition, the design simplifies the circuit structure, reduces the dependence on external components, and improves the integration and cost-effectiveness. Overall, this design provides an efficient, reliable and low-power random number generation solution suitable for various digital applications.

[0052] In some embodiments, the integrated circuit further includes: the first resistor, the second resistor, and the third resistor, which are used to provide the high threshold voltage for the first comparator and the low threshold voltage for the second comparator.

[0053] Here, a connection relationship among a first resistor, a second resistor, and a third resistor is provided, as well as a connection relationship among a first comparator, a second comparator, a memristor, a capacitor, etc.

[0054] The first end of the first resistor is connected to the power supply (VCC), and the second end is connected to the first end of the second resistor; the second end of the second resistor is connected to the first end of the third resistor, and the second end of the third resistor is grounded.

[0055] The second end of the first resistor is also connected to the first input end of the first comparator, and the second input end of the first comparator is connected to the first reference voltage end; The second end of the second resistor, that is, the first end of the third resistor, is also connected to the second input end of the second comparator, and the first input end of the second comparator is connected to the first reference voltage end; One end of the capacitor is connected to the second end of the third resistor and grounded, and the other end is connected to the first input end of the second comparator; One end of the memristor (ie, the first reference voltage end) is connected to the first comparator and the second comparator, and the other end is connected to the second end of the transistor; the first end of the transistor is connected to the output end of the RS trigger, and the third end of the transistor is grounded.

[0056] Specifically, the first resistor, the second resistor, and the third resistor in the circuit are used to set the high threshold voltage and the low threshold voltage by voltage division. In addition, since the third resistor is connected between the capacitor and the comparator, it can also help adjust the charge and discharge rate of the capacitor, thereby controlling the working cycle of the integrated circuit.

[0057] The different resistance designs of the first resistor, the second resistor, and the third resistor can not only affect the specific values ​​of the high threshold voltage and the low threshold voltage, but also affect the working cycle of the integrated circuit, that is, the charging and discharging time of the capacitor, when the output result of the comparator changes, etc., and ultimately affect when the output signal of the random number generation module changes.

[0058] In this way, the first resistor, the second resistor, and the third resistor in the integrated circuit provide a high threshold voltage and a low threshold voltage for the first comparator and the second comparator, ensuring that the two comparators can accurately judge the state of the input signal, so that the comparator has higher accuracy and reliability when judging the input signal. The sensitivity and anti-interference ability of the circuit are enhanced, and misjudgment caused by voltage fluctuations is avoided. In addition, through the cooperation of the third resistor, the power consumption and response speed of the circuit can be further optimized, and the overall performance and stability of the system can be improved.

[0059] In some embodiments, the integrated circuit further includes: a buffer, wherein the buffer is used to adjust the output result of the RS trigger and / or buffer the output result.

[0060] Here, the buffer is used to adjust and / or buffer the output result of the RS trigger to ensure that the output result can be transmitted in a stable and reliable manner in the subsequent circuit.

[0061] The buffer can use a NOT gate, which reverses its input signal (i.e., the output result of the RS trigger), that is, when the RS trigger outputs a high level, the buffer outputs a low level, and vice versa. In this way, the NOT gate not only helps adjust the state of the signal, but also effectively reduces signal attenuation and noise interference, ensuring the stability and efficiency of the circuit.

[0062] like Figure 2 As shown, a schematic diagram of the structure of a random number generation module is provided; Figure 2 As shown, the random number generation module includes: a memristor (i.e. Figure 2 M in), capacitance (i.e. Figure 2 C) in the adjustment circuit; The adjustment circuit includes: a transistor (i.e. Figure 2 VT in), integrated circuits; For an integrated circuit, the present disclosure specifically provides a circuit structure, which includes: a first comparator (i.e. Figure 2 U1 in the second comparator (i.e. Figure 2 U2 in), RS trigger (i.e. Figure 2 The device with R and S in the first resistor (i.e. Figure 2 R1 in the figure), the second resistor (i.e. Figure 2 R2 in the figure), the third resistor (i.e. Figure 2 R3 in), NOT gate (i.e. Figure 2 in (N).

[0063] in addition, Figure 2 Ui represents the first reference voltage terminal, VDD represents the power module, Uo represents the output terminal, and R4 represents a voltage dividing resistor, one end of which is connected to VDD and the other end is connected to the output terminal Uo.

[0064] The random number generation model is explained in conjunction with this structure.

[0065] The high threshold voltage when the memristor M undergoes resistance state conversion is V H , low threshold voltage is V L .

[0066] When the voltage is higher than V HThe external voltage excitation of , the memristor M changes from a high resistance state to a low resistance state, at which time the memristor M is “turned on”; When the voltage is lower than V L When stimulated by an external voltage, the memristor M changes from a low-resistance state to a high-resistance state, and the memristor M is “off” at this time.

[0067] After the resistance change of the memristor M from a high resistance state to a low resistance state is completed, it can be regarded as a low resistance resistor with a stable resistance value.

[0068] Assume the voltage of capacitor C is Vi (combined with Figure 2 , Vi also represents the voltage of the first reference voltage terminal Ui) to analyze the relationship between the voltage of capacitor C and the output terminal (i.e., Uo) of the integrated circuit. After the power supply (i.e., VDD) is connected, the memristor M is in a high-resistance state, where the voltage across the memristor is V M1 , the high impedance value is R H , the low resistance value is R L , when the voltage across capacitor C is 0, the voltage across memristor M is V M1 =V DD -V R4 , at this time V M1 Greater than V H After a short random delay, the memristor M changes from a high-resistance state to a low-resistance state. VDD charges the capacitor C through R4 and the memristor M. V i Start from 0 and gradually increase.

[0069] The basic working principle of integrated circuits is as follows: 1. When V i <V L <V H When V U1 =0,V U2 =1,U O =1, the transistor is cut off, VDD charges capacitor C through resistor R4 and memristor M, V i Gradually increases; among them, V U1 is the output result of comparator U1 (i.e., the first comparator), V U2 is the output result of comparator U2 (i.e., the second comparator), and Uo is the output terminal; 2. As Vi is gradually generated, V i 、V L 、V H The relationship between will also change. When it changes to V L <V i <V H When V U1 =0,V U2 =0,U Ounchanged, at this time the transistor VT is cut off, VDD continues to charge the capacitor C through the resistor R4 and the memristor M, V i Continue to gradually rise; 3. V i 、V L 、V H The relationship between V i changes with the change of V L <V H <V i When V U1 =1, V U2 =0,U O =0, at this time, the transistor VT is turned on, and the memristor M is turned on in reverse phase. At this time, the capacitor C discharges through the memristor M and the transistor VT. As the capacitor discharges, V i gradually decrease; 4. As Vi gradually decreases, V i 、V L 、V H The relationship between will also change. When it changes to V L <V i <V H When V U1 =0,V U2 =0,U O unchanged, at this time, the transistor VT is turned on, the memristor M is turned on in reverse phase, and the capacitor C is discharged through the memristor M and the transistor, V i Continue to lower; 5. V i 、V L 、V H The relationship between V i changes with the change of V i <V L <V H When V U1 =0,V U2 =1,U O =1, the transistor is cut off, VDD charges the capacitor C through R4 and memristor M, V i Gradually increase.

[0070] Through the above principle, it can be found that the voltage of capacitor C is V L and V H The output terminal Uo of the integrated circuit is high during the charging period of the capacitor C and low during the discharging period of the capacitor. When the capacitor C is charged, the resistance value of the memristor M is R4+R L , when the capacitor C is discharged, the resistance value of the memristor M is R L , the charging and discharging time is proportional to the resistance value of the memristor M.

[0071] Through the above design, a time domain pulse width of the output terminal Uo outputting a high level, a response delay of the memristor, and a low resistance value R are obtained. L The design of the circuit, that is, the random performance of the circuit has been improved by introducing two random quantities, random response delay and random low-resistance resistance. This means that the behavior of the circuit is no longer completely determined by deterministic factors, but adds a certain degree of uncertainty and variability, which brings better anti-interference ability and adaptability, especially in complex or changing working environments.

[0072] It should be noted that the integrated circuit may also adopt other circuit structures having the above functions, such as any 555 timer, etc., which is not limited here.

[0073] In some embodiments, the data acquisition module includes: a trigger and a clock; the input end of the trigger is respectively connected to the output end of the random number generation module and the clock; the output end of the trigger is connected to the input end of the counter.

[0074] In some embodiments, the trigger is used to receive the random pulse output by the random number generation module and the clock signal from the clock, perform a logical AND operation on the random pulse and the clock signal, and count according to the logical AND operation result to obtain a random number sequence.

[0075] Here, the random number generation module outputs a random digital pulse signal (Uo), the trigger performs a logical AND operation on the clock signal (clk) and Uo, the trigger counts on the falling edge, counts "1" when the output is high, and counts "0" when the output is low, thereby obtaining a random number sequence.

[0076] In some embodiments, the data acquisition module further includes: a counter, which is used to control the number of data bits of the random number sequence according to the data requirements of the target device.

[0077] Here, the counter is used to control the number of data bits generated to fit the upper limit of the FPGA's register.

[0078] In some embodiments, the data acquisition module further includes: a serial port unit, used to output the random number sequence to a target device.

[0079] Here, the random number sequence is output to the target device, ie, the signal receiving device, through the serial port unit.

[0080] Here, the data acquisition module may further include a state controller, and the entire process of the data acquisition module is controlled by the state controller.

[0081] Here, the data acquisition module can be designed through FPGA (Field Programmable Gate Array), which has independent input / output (I / O) ports. It has a built-in adjustable clock signal, integrated triggers, clocks, counters, serial ports, state controllers and other units, and can realize the shift storage of binary data.

[0082] Figure 3 A structural diagram of a data acquisition module provided in an embodiment of the present disclosure; Figure 3 As shown, the data acquisition module may include: a trigger, a counter, a serial port, a clock, and a state controller; Among them, the random number generation module outputs a random digital pulse signal (i.e., Uo), the trigger receives the clock signal clk and Uo for logical AND, the trigger counts on the falling edge, counts "1" when the output is high, and counts "0" when the output is low, thereby obtaining a random number sequence; then, it is output to the signal receiving device through the serial port unit.

[0083] In some embodiments, the random number generator further includes: a control unit; At least one of the first resistor, the second resistor, and the third resistor is a variable resistor; The control unit is used to adjust the resistance value of at least one of the first resistor, the second resistor, and the third resistor.

[0084] Here, each resistor in the integrated circuit can be a variable resistor. In the design of the random number generator, a control unit can be provided. Using the control unit to adjust the resistance value of the variable resistor can change the current flow mode or noise characteristics of the circuit, thereby affecting the output of the random number generation. The change in resistance value can make the generated random number more unpredictable, increasing the randomness and security of the system.

[0085] In addition, the control unit can adjust the resistance value to make the random number generator have flexible performance. In different application scenarios, the resistance value can be adjusted as needed to optimize the random number generation characteristics. For example, under different working conditions (such as temperature changes, power supply fluctuations, etc.), adjusting the resistance value can maintain the stability and quality of the random number. Different resistance settings can compensate for the impact of environmental changes on the random number generation process and ensure the stable quality of the generated random numbers.

[0086] In some embodiments, the random number generator further includes: a control unit; The capacitor is a variable capacitor; The control unit is used to adjust the capacitance value of the capacitor.

[0087] Here, the change in capacitance value will directly affect the characteristics of current and voltage fluctuations in the circuit, thereby changing the random number generation process. By adjusting the capacitance, the time constant, charge and discharge characteristics of the circuit can be changed, thereby increasing the unpredictability of the generated random numbers. By using variable capacitance, changes can be made in a wider range, making the generated random numbers more random and difficult to predict.

[0088] Here, in the design of the random number generator, a control unit can be provided, and the control unit can be used to accurately adjust the capacitance value to optimize the performance of the random number generator. Different capacitance values ​​will affect the noise characteristics, stability and randomness of the circuit. The introduction of the control unit makes the adjustment more flexible, and the capacitance can be adjusted according to the needs in different working environments to obtain the best random number quality and adapt to different application scenarios.

[0089] By adjusting the capacitance value through the control unit, the influence of these environmental factors on the circuit performance can be compensated, ensuring the quality and stability of the generated random numbers. Under different working environments, the change of capacitance can adjust the response of the circuit, thereby adapting to the changes in external conditions and maintaining the stability of the system. The capacitance value can be easily adjusted through the control unit, so as to flexibly adjust the performance of the random number generator according to the needs. For example, in some specific occasions, higher randomness or stability may be required. The control unit can adjust the capacitance according to actual needs, avoiding the problem of unstable performance caused by capacitance mismatch. In addition, the design of variable capacitors makes the system more flexible during maintenance and upgrades.

[0090] In some embodiments, the control unit is used to periodically adjust the resistance value of at least one of the first resistor, the second resistor, and the third resistor; and / or adjust the capacitance value of the capacitor.

[0091] The control unit is further used to adjust the resistance value of at least one of the first resistor, the second resistor, and the third resistor according to application requirements; and / or adjust the capacitance value of the capacitor.

[0092] Here, by adjusting the values ​​of resistance and capacitance periodically or according to application requirements, the control unit can improve the flexibility and adaptability of the system so that it can maintain excellent performance under different working conditions. This adjustment helps to optimize the response speed, filtering characteristics and stability of the circuit, and can enhance the robustness of the circuit to cope with environmental changes and load fluctuations. In addition, by reducing hardware requirements and simplifying the design, it is possible to reduce costs, improve the energy efficiency, accuracy and maintainability of the system, extend the service life of the equipment, and support future upgrade requirements. In addition, by adjusting the resistance value of at least one of the first resistor, the second resistor, and the third resistor, and the capacitance value of the capacitor, the duty cycle of the integrated circuit can also be changed.

[0093] In some embodiments, the random number generator can be applied to electronic devices such as computers, Internet of Things devices, automotive electronics, wireless communication devices, quantum computers, etc.; of course, it can also be applied to any other electronic devices that require high security, encryption processing and unpredictability. This is not limited here.

[0094] The true random number generator based on memristor provided by the embodiment of the present disclosure introduces the random response delay of the memristor and the random low-resistance state resistance as entropy sources, and comprehensively utilizes the two random resources of device response delay and low-resistance state resistance. It can make full use of the random resources of the memristor, simplify the circuit structure, improve the circuit reliability, randomness and random number rate, and add a rate control function to expand the application scenarios of the random number generator.

[0095] Figure 4 A flow chart of a random number generation method provided by an embodiment of the present disclosure; Figure 4 As shown, the method is applied to a random number generator, and the random number generator includes: a random number generation module and a data acquisition module; the method includes: Step 401: After the random number generator is powered on, the random number generation module generates a random digital pulse signal based on the random response delay and random low-resistance resistance of the memristor; Step 402: The data acquisition module generates a random number sequence according to the random digital pulse signal.

[0096] In some embodiments, the random number generator may use the above Figure 1 The specific structure of the random number generator shown is as described above and will not be repeated here.

[0097] In some embodiments, the random number generation module includes: a memristor, a capacitor, and an adjustment circuit; the adjustment circuit includes: an integrated circuit and a triode; The random number generation module generates a random digital pulse signal based on the random response delay and random low-resistance resistance of the memristor, including: The integrated circuit compares the first reference voltage of the memristor, the high threshold voltage and the low threshold voltage of the resistance state change of the memristor, outputs a random digital pulse signal according to the comparison result, and adjusts the state of the triode, the state being on or off; The state of the capacitor changes with the state of the transistor, and the state of the capacitor is charging or discharging; and the first reference voltage changes with the state of the capacitor.

[0098] Here, the integrated circuit realizes the conversion of charging and discharging of the capacitor by controlling the on and off states of the transistor, thereby affecting the first reference voltage of the memristor. The first reference voltage in turn affects the comparison results of the integrated circuit, and these comparison results further adjust the working state of the transistor, forming a feedback loop, causing the transistor to switch between on and off periodically. This feedback mechanism enables the circuit to continuously output uninterrupted digital pulse signals, and due to the uncertainty in the charging and discharging process of the memristor and capacitor, the signal has a high randomness. In this way, the integrated circuit not only maintains the stability of the signal output, but also enhances the randomness of the signal, meeting the demand for high-quality random signals.

[0099] In some embodiments, the integrated circuit includes: a first comparator, a second comparator, and an RS trigger; The integrated circuit compares the first reference voltage of the memristor, the high threshold voltage and the low threshold voltage of the resistance state change of the memristor, outputs a random digital pulse signal according to the comparison result, and adjusts the state of the triode, including: The first comparator compares the first reference voltage and the high threshold voltage; The second comparator compares the first reference voltage and the low threshold voltage; The RS trigger outputs a random digital pulse signal and adjusts the state of the transistor according to the comparison result of the first comparator and the comparison result of the second comparator.

[0100] In some embodiments, the RS trigger outputs a random digital pulse signal according to a comparison result of the first comparator and a comparison result of the second comparator, and adjusts the state of the transistor, including: If the comparison result of the first comparator is a first value and the comparison result of the second comparator is a second value, the RS trigger outputs a random digital pulse signal as a first output value, and the transistor is turned off; If the comparison result of the first comparator is the second value and the comparison result of the second comparator is the second value, the RS trigger outputs a random digital pulse signal as the second output value, and turns on the transistor.

[0101] Specifically, the RS trigger is a digital logic circuit, which can also be called an RS latch, and has two input terminals, namely: R (reset) and S (set). In the embodiment of the present disclosure, the input of the RS trigger is the result of the first comparator and the result of the second comparator. Assume that the comparison result of the first comparator is the S input and the comparison result of the second comparator is the R input; when applied, it can include a variety of situations, for example: If the S input is 1 and the R input is 0, the random digital pulse signal output by the RS flip-flop is 1.

[0102] If the S input and R input are both 0 at the same time, the RS flip-flop maintains its current state, that is, no change occurs.

[0103] If the S input is 0 and the R input is 1, the random digital pulse signal output by the RS flip-flop is 0.

[0104] That is, if the result of the first comparator is 1 and the result of the second comparator is 0, it can output 1, and if the result of the first comparator is 0 and the result of the second comparator is 1, it can output 0.

[0105] Of course, there may be other situations for the input and output settings here. For example, if the S input is 1 and the R input is 0, the random digital pulse signal output by the RS flip-flop is 0; if the S input and the R input are both 0, the flip-flop maintains its current state, that is, does not change; if the S input is 0 and the R input is 1, the random digital pulse signal output by the RS flip-flop is 1. There is no limitation on the setting of the RS flip-flop here.

[0106] In some embodiments, the method further comprises: The output result of the RS trigger is adjusted, and / or the output result is buffered.

[0107] Here, the adjustment may be inversion, that is, if the RS trigger is 0, it is adjusted to 1, and if the RS trigger is 1, it is adjusted to 0.

[0108] Here, the integrated circuit may further include: a buffer, and the buffer may use a NOT gate, the function of which is to reverse its input signal (that is, the output signal of the RS trigger), that is, when the RS trigger outputs a high level, the buffer will output a low level, and vice versa. In this way, the NOT gate not only helps to adjust the state of the signal, but also effectively reduces signal attenuation and noise interference, ensuring the stability and efficiency of the circuit.

[0109] In some embodiments, the random number generator further includes: a control unit, at least one of the first resistor, the second resistor, and the third resistor is a variable resistor; the capacitor is a variable capacitor; The method further comprises at least one of the following: The control unit periodically adjusts the resistance value of at least one of the first resistor, the second resistor, and the third resistor; and / or adjusts the capacitance value of the capacitor; The control unit adjusts the resistance value of at least one of the first resistor, the second resistor, and the third resistor according to application requirements; and / or adjusts the capacitance value of the capacitor.

[0110] Here, by adjusting the values ​​of resistors and capacitors periodically or according to application requirements, the control unit can improve the flexibility and adaptability of the system, so that it can maintain excellent performance under different operating conditions. This adjustment helps to optimize the circuit's response speed, filtering characteristics and stability, and can enhance the circuit's robustness to cope with environmental changes and load fluctuations. In addition, by reducing hardware requirements and simplifying the design, it can reduce costs, improve the system's energy efficiency, accuracy and maintainability, extend the equipment's service life, and support future upgrade needs.

[0111] In some embodiments, the data acquisition module includes: a trigger and a clock; the input end of the trigger is respectively connected to the output end of the random number generation module and the clock; the output end of the trigger is connected to the input end of the counter.

[0112] The data acquisition module generates a random number sequence according to the random digital pulse signal, including: The trigger receives the random pulse output by the random number generation module and the clock signal from the clock, performs a logic AND operation on the random pulse and the clock signal, and counts according to the result of the logic AND operation to obtain a random number sequence.

[0113] In some embodiments, the data acquisition module further includes: a counter and a serial port unit, and the method further includes at least one of the following: The counter controls the number of data bits of the random number sequence according to the data requirements of the target device; The serial port unit outputs the random number sequence to the target device.

[0114] It can be understood that the random number generation method provided in the above embodiment and the embodiment of the corresponding random number generator belong to the same concept, and the specific implementation process is detailed in the method embodiment, which will not be repeated here.

[0115] The random number generation method provided by the embodiment of the present disclosure is a true random number generator based on a memristor. The true random number generator simultaneously introduces the random response delay and random low-resistance state resistance of the memristor as entropy sources, making full use of the random resources of the memristor. In this way, the method comprehensively utilizes the two random resources of device response delay and low-resistance state resistance, improves circuit reliability, randomness and random number rate, and adds a rate control function to expand the application scenarios of the random number generator.

[0116] The embodiment of the present application provides a computer program product or a computer program, which includes a computer instruction, and the computer instruction is stored in a computer-readable storage medium. The processor of the computer device reads the computer instruction from the computer-readable storage medium, and the processor executes the computer instruction, so that the computer device performs an encryption method. The encryption method can use a random number sequence generated by a random number generator to generate a key, an initialization vector, a salt value, a random signature, etc.

[0117] An embodiment of the present application provides a computer-readable storage medium storing executable instructions, wherein executable instructions are stored. When the executable instructions are executed by a processor, the processor will execute the random number generation method provided by the embodiment of the present application.

[0118] In some embodiments, the computer-readable storage medium may be a memory such as FRAM, ROM, PROM, EPROM, EEPROM, flash memory, magnetic surface storage, optical disk, or CD-ROM; or it may be various devices including one or any combination of the above memories.

[0119] In some embodiments, executable instructions may be in the form of a program, software, software module, script or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and may be deployed in any form, including as a stand-alone program or as a module, component, subroutine or other unit suitable for use in a computing environment.

[0120] As an example, executable instructions may, but need not, correspond to a file in a file system, may be stored as part of a file storing other programs or data, such as in one or more scripts in a HyperText Markup Language (HTML) document, in a single file dedicated to the program in question, or in multiple coordinated files (e.g., files storing one or more modules, subroutines, or code portions).

[0121] By way of example, executable instructions may be deployed to be executed on one computing device, or on multiple computing devices located at one site, or on multiple computing devices distributed across multiple sites and interconnected by a communication network.

[0122] Figure 5 A schematic diagram of the structure of an electronic device provided in an embodiment of the present disclosure; Figure 5 As shown, the electronic device 50 includes: a processor 501, and a memory 502 communicatively connected to the processor 501; the memory 502 stores instructions that can be executed by the processor 501.

[0123] The processor may include a random number generator, which is used to generate a random number sequence. The random number generator may be used as follows: Figure 1 The structure shown.

[0124] In actual application, the electronic device 50 may further include: at least one network interface 503. The various components in the electronic device 50 are coupled together via a bus system 504. It is understood that the bus system 504 is used to achieve connection and communication between these components. In addition to the data bus, the bus system 504 also includes a power bus, a control bus, and a status signal bus. However, for the sake of clarity, Figure 5 In the figure, various buses are marked as bus system 504. There may be at least one processor 501 and at least one memory 502. The network interface 503 is used for wired or wireless communication between the electronic device 50 and other devices.

[0125] The memory 502 in the embodiment of the present disclosure is used to store various types of data to support the operation of the electronic device 50 .

[0126] The method disclosed in the above embodiment of the present disclosure can be applied to the processor 501, or implemented by the processor 501. The processor 501 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the hardware integrated logic circuit in the processor 501 or the instruction in the form of software. The above processor 501 may be a general processor, a digital signal processor (DSP, DiGital Signal Processor), or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc. The processor 501 can implement or execute the disclosed methods, steps and logic block diagrams in the embodiment of the present disclosure. The general processor may be a microprocessor or any conventional processor, etc. The steps of the method disclosed in the embodiment of the present disclosure can be directly embodied as a hardware decoding processor to execute, or a combination of hardware and software modules in the decoding processor to execute. The software module can be located in a storage medium, which is located in the memory 502. The processor 501 reads the information in the memory 502 and completes the steps of the above method in combination with its hardware.

[0127] In some embodiments, the electronic device 50 may be implemented by one or more application specific integrated circuits (ASICs), DSPs, programmable logic devices (PLDs), complex programmable logic devices (CPLDs), field programmable gate arrays (FPGAs), general-purpose processors, controllers, microcontrollers (MCUs), microprocessors, or other electronic components to execute the aforementioned method.

[0128] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps recorded in this disclosure can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved, and this document does not limit this.

[0129] In the above description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it can be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0130] Unless otherwise defined, all technical and scientific terms used in this disclosure have the same meaning as those commonly understood by those skilled in the art to which this disclosure belongs. The terms used in this disclosure are only for the purpose of describing the embodiments of this disclosure and are not intended to limit this disclosure.

[0131] It should be understood that in the various embodiments of the present disclosure, the size of the serial number of each implementation process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure.

[0132] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of the present disclosure, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0133] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A random number generator, characterized in that: The random number generator comprises: a random number generation module, a data acquisition module, and a power supply module; The power supply module is used to supply power to the random number generation module and the data acquisition module; The random number generation module is used to generate a random digital pulse signal based on the random response delay and random low-resistance state resistance of the memristor; The data acquisition module is used to generate a random number sequence according to the random digital pulse signal.

2. The random number generator according to claim 1, characterized in that The random number generation module comprises: a memristor, a capacitor, and an adjustment circuit; the first end of the adjustment circuit is connected to the first end of the memristor, and the second end of the adjustment circuit is connected to the second end of the memristor; the first end and the third end of the adjustment circuit are respectively connected to the first end and the second end of the capacitor, and the second end of the capacitor is grounded; the output end of the adjustment circuit is connected to the input end of the data acquisition module; The capacitor is used to charge or discharge the memristor to adjust the first reference voltage of the memristor; The adjustment circuit is used to output a random digital pulse signal according to the first reference voltage of the memristor.

3. The random number generator according to claim 2, characterized in that The adjustment circuit includes: an integrated circuit and a triode; The integrated circuit is used to compare the first reference voltage of the memristor, the high threshold voltage and the low threshold voltage of the resistance state change of the memristor, output a random digital pulse signal according to the comparison result, and adjust the state of the triode, the state being on or off; The state of the capacitor changes with the state of the transistor, and the state of the capacitor is charging or discharging; and the first reference voltage changes with the state of the capacitor.

4. The random number generator according to claim 3, characterized in that: The integrated circuit comprises: a first comparator, a second comparator, a set input and a reset input RS trigger; The first comparator is used to compare the first reference voltage with the high threshold voltage; The second comparator is used to compare the first reference voltage with the low threshold voltage; The RS trigger is used to output a random digital pulse signal and adjust the state of the transistor according to the comparison result of the first comparator and the comparison result of the second comparator.

5. The random number generator according to claim 4, characterized in that: The integrated circuit further includes: a first resistor, a second resistor, and a third resistor, which are used to provide the high threshold voltage for the first comparator and to provide the low threshold voltage for the second comparator.

6. The random number generator according to claim 4, characterized in that: The integrated circuit further includes: a buffer, used for adjusting the output result of the RS trigger and / or buffering the output result.

7. The random number generator according to claim 1, characterized in that: The data acquisition module comprises: a trigger and a clock; the input end of the trigger is respectively connected to the output end of the random number generation module and the clock; the output end of the trigger is connected to the input end of the counter.

8. The random number generator according to claim 7, characterized in that: The trigger is used to receive the random pulse output by the random number generation module and the clock signal from the clock, perform logic AND based on the random pulse and the clock signal, and count based on the logic AND result to obtain a random number sequence.

9. The random number generator according to claim 7, characterized in that: The data acquisition module further includes: a counter, which is used to control the number of data bits of the random number sequence according to the data requirements of the target device.

10. The random number generator according to claim 7, characterized in that: The data acquisition module also includes: a serial port unit, which is used to output the random number sequence to the target device.

11. A random number generation method, characterized in that: The method is applied to a random number generator, which includes: a random number generation module and a data acquisition module; the method includes: After the random number generator is powered on, the random number generation module generates a random digital pulse signal based on the random response delay and random low-resistance resistance of the memristor; The data acquisition module generates a random number sequence according to the random digital pulse signal.

12. The method according to claim 11, characterized in that The random number generation module includes: a memristor, a capacitor, and an adjustment circuit; the adjustment circuit includes: an integrated circuit and a triode; The random number generation module generates a random digital pulse signal based on the random response delay and random low-resistance resistance of the memristor, including: The integrated circuit compares the first reference voltage of the memristor, the high threshold voltage and the low threshold voltage of the resistance state change of the memristor, outputs a random digital pulse signal according to the comparison result, and adjusts the state of the triode, the state being on or off; The state of the capacitor changes with the state of the transistor, and the state of the capacitor is charging or discharging; and the first reference voltage changes with the state of the capacitor.

13. The method according to claim 12, characterized in that The integrated circuit comprises: a first comparator, a second comparator, and an RS trigger; The integrated circuit compares the first reference voltage of the memristor, the high threshold voltage and the low threshold voltage of the resistance state change of the memristor, outputs a random digital pulse signal according to the comparison result, and adjusts the state of the triode, including: The first comparator compares the first reference voltage and the high threshold voltage; The second comparator compares the first reference voltage and the low threshold voltage; The RS trigger outputs a random digital pulse signal and adjusts the state of the transistor according to the comparison result of the first comparator and the comparison result of the second comparator.

14. The method according to claim 13, characterized in that The RS trigger outputs a random digital pulse signal according to a comparison result of the first comparator and a comparison result of the second comparator, and adjusts the state of the transistor, including: If the comparison result of the first comparator is a first value and the comparison result of the second comparator is a second value, the RS trigger outputs a random digital pulse signal as a first output value, and the transistor is turned off; If the comparison result of the first comparator is the second value and the comparison result of the second comparator is the second value, the RS trigger outputs a random digital pulse signal as the second output value, and turns on the transistor.

15. The method according to claim 13, characterized in that The method further comprises: The output result of the RS trigger is adjusted, and / or the output result is buffered.

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