A random number generator and a random number generation method

Abstract

The present disclosure provides a random number generator and a random number generation method, which relate to the field of computer technology. The random number generator includes: a random number generation module, a data acquisition module, and a power supply module; the power supply module is used to supply power to the random number generation module and the data acquisition module; the random number generation module is used to generate a random digital pulse signal based on the random response delay and the random low-resistance state resistance value of the memristor; the data acquisition module is used to generate a random number sequence according to the random digital pulse signal. In this way, by simultaneously introducing the random response delay and the random low-resistance state resistance value of the memristor as entropy sources, the random resources of the memristor are fully utilized, the circuit structure is simplified, the circuit reliability, randomness, and random number rate are improved, and the application scenarios of the random number generator are expanded.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technologies, and in particular, to a random number generator and a random number generation method. Background Art

[0002] With the rapid development of a new generation of information and communication technologies represented by 5G (the 5th Generation Mobile Communication Technology), cloud, IoT (Internet of Things), etc., information security faces great challenges due to the invasiveness of traditional data encryption methods. In these encryption algorithms and cryptographic protocols, the quality of random numbers directly affects the performance of the cryptographic system. Therefore, encryption technologies require more unpredictable and secure random number sequences.

[0003] A random number generator (RNG) is an algorithm or device that can generate pseudo-random or truly random number sequences. In the prior art, a random number generator is provided, which designs a single-loop circuit based on a memristor and uses the random performance of the memristor to generate random analog signals, and generates a random number sequence based on the analog signals. However, the above solutions generally need to construct a random number generator through a complex circuit structure and only rely on the single random performance of the memristor, resulting in problems such as low random resource utilization, unstable random performance, and reduced reliability. Summary of the Invention

[0004] The present disclosure provides a random number generator and a random number generation method to at least solve the above technical problems existing in the prior art.

[0005] In a first aspect, an embodiment of the present disclosure provides a random number generator, where the random number generator includes: a random number generation module, a data acquisition module, and a power supply module;

[0006] The power supply module is configured to supply power to the random number generation module and the data acquisition module;

[0007] The random number generation module is configured to generate a random digital pulse signal based on the random response delay and the random low resistance state value of the memristor;

[0008] The data acquisition module is configured to generate a random number sequence according to the random digital pulse signal.

[0009] In the above solution, the random number generation module includes: a memristor, a capacitor, and an adjustment circuit; a first end of the adjustment circuit is connected to a first end of the memristor, and a second end of the adjustment circuit is connected to a second end of the memristor; a first end and a third end of the adjustment circuit are respectively connected to a first end and a second end of the capacitor, and the second end of the capacitor is grounded; an output end of the adjustment circuit is connected to an input end of the data acquisition module;

[0010] The capacitor is configured to charge or discharge the memristor to adjust a first reference voltage of the memristor;

[0011] The adjustment circuit is configured to output a random digital pulse signal according to the first reference voltage of the memristor.

[0012] In the above solution, the adjustment circuit includes: an integrated circuit and a triode;

[0013] The integrated circuit is configured to compare the first reference voltage of the memristor, a high threshold voltage and a low threshold voltage of the memristor state change, output a random digital pulse signal according to the comparison result, and adjust a state of the triode, where the state is on or off;

[0014] Wherein, a state of the capacitor changes with a state of the triode, and the state of the capacitor is charging or discharging; the first reference voltage changes with the state of the capacitor.

[0015] In the above solution, the integrated circuit includes: a first comparator, a second comparator, and an RS flip-flop;

[0016] The first comparator is configured to compare the first reference voltage and the high threshold voltage;

[0017] The second comparator is configured to compare the first reference voltage and the low threshold voltage;

[0018] The RS flip-flop is configured to output a random digital pulse signal according to a comparison result of the first comparator and a comparison result of the second comparator, and adjust a state of the triode.

[0019] In the above solution, the integrated circuit further includes: the first resistor, the second resistor, and the third resistor, configured to provide the high threshold voltage for the first comparator and provide the low threshold voltage for the second comparator.

[0020] In the above solution, the integrated circuit further includes: a buffer, configured to adjust an output result of the RS flip-flop and / or buffer the output result.

[0021] In the above solution, the data acquisition module includes: a trigger and a clock; the input ends of the trigger are respectively connected to the output end of the random number generation module and the clock; the output end of the trigger is connected to the input end of a counter.

[0022] In the above solution, the trigger is configured to receive the random pulses output by the random number generation module and the clock signals from the clock, perform a logical AND operation according to the random pulses and the clock signals, and perform counting according to the result of the logical AND operation to obtain a random number sequence.

[0023] In the above solution, the data acquisition module further includes: a counter, which is configured to control the number of digits of the random number sequence according to the data requirements of the target device.

[0024] In the above solution, the data acquisition module further includes: a serial port unit, which is configured to output the random number sequence to the target device.

[0025] In a second aspect, an embodiment of the present disclosure provides a random number generation method, which is applied to a random number generator. The random number generator includes: a random number generation module and a data acquisition module; the method includes:

[0026] After the random number generator is powered on, the random number generation module generates a random digital pulse signal based on the random response delay and the random low resistance state value of the memristor;

[0027] The data acquisition module generates a random number sequence according to the random digital pulse signal.

[0028] In the above solution, the random number generation module includes: a memristor, a capacitor, and an adjustment circuit; the adjustment circuit includes: an integrated circuit and a triode;

[0029] The random number generation module generates a random digital pulse signal based on the random response delay and the random low resistance state value of the memristor, including:

[0030] The integrated circuit compares the first reference voltage of the memristor, the high threshold voltage and the low threshold voltage of the change in the resistance state of the memristor, outputs a random digital pulse signal according to the comparison result, and adjusts the state of the triode, where the state is on or off;

[0031] Wherein, the state of the capacitor changes with the state of the triode, and the state of the capacitor is charging or discharging; the first reference voltage changes with the state of the capacitor.

[0032] In the above solution, the integrated circuit includes: a first comparator, a second comparator, and an RS flip-flop;

[0033] The integrated circuit compares a first reference voltage of the memristor, a high threshold voltage and a low threshold voltage of the resistance state change of the memristor, outputs a random digital pulse signal according to a comparison result, and adjusts a state of the triode, including:

[0034] The first comparator compares the first reference voltage and the high threshold voltage;

[0035] The second comparator compares the first reference voltage and the low threshold voltage;

[0036] The RS flip-flop outputs a random digital pulse signal according to the comparison result of the first comparator and the comparison result of the second comparator, and adjusts the state of the triode.

[0037] In the above solution, the RS flip-flop outputs a random digital pulse signal according to the comparison result of the first comparator and the comparison result of the second comparator, and adjusts the state of the triode, including:

[0038] If the comparison result of the first comparator is a first value and the comparison result of the second comparator is a second value, the RS flip-flop outputs a random digital pulse signal as a first output value, and turns off the triode;

[0039] If the comparison result of the first comparator is the second value and the comparison result of the second comparator is the second value, the RS flip-flop outputs a random digital pulse signal as a second output value, and turns on the triode.

[0040] In the above solution, the method further includes:

[0041] Adjust the output result of the RS flip-flop, and / or buffer the output result.

[0042] The embodiments of the present disclosure provide a random number generator and a random number generation method. The random number generator includes: a random number generation module, a data acquisition module, and a power supply module; the power supply module is used to supply power to the random number generation module and the data acquisition module; the random number generation module is used to generate a random digital pulse signal based on the random response delay and the random low resistance state value of the memristor; the data acquisition module is used to generate a random number sequence according to the random digital pulse signal. The design of the above random number generator and random number generation method achieves at least the following beneficial effects:

[0043] By simultaneously introducing the random response delay and the random low resistance state value of the memristor as entropy sources, making full use of the random resources of the memristor, the circuit structure is simplified, and the circuit reliability, randomness and random number rate are improved;

[0044] By designing the adjustment circuit in the random number generator, the rate control function is realized, and the application scenarios of the random number generator are expanded.

[0045] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it used to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 FIG. is a schematic structural diagram of a random number generator provided by an embodiment of the present disclosure;

[0047] Figure 2 FIG. is a schematic structural diagram of a random number generation module provided by an embodiment of the present disclosure;

[0048] Figure 3 FIG. is a schematic structural diagram of a data acquisition module provided by an embodiment of the present disclosure;

[0049] Figure 4 FIG. is a schematic flowchart of a random number generation method provided by an embodiment of the present disclosure;

[0050] Figure 5 FIG. is a schematic structural diagram of an electronic device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0051] In order to make the objectives, features, and advantages of the present disclosure more obvious and understandable, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. Apparently, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative efforts fall within the scope of the present disclosure.

[0052] The random number generator includes a pseudo-random number generator (PRNG, Pseudo-random number generator) and a true random number generator (TRNG, True Random Number Generator).

[0053] Pseudo-random number generators are the most common type of random number generators. They generate random numbers through deterministic algorithms. These random numbers appear to be random, but in fact, they are determined by an initial seed value and certain mathematical operations (such as the linear congruential method, the Mersenne Twister method, etc.). Since they are generated by algorithms, pseudo-random number generators are predictable. If the initial seed and the algorithm are known, the subsequent "random" numbers can be inferred.

[0054] True random number generators generate random numbers through physical processes such as radioactive decay, thermal noise, photon detection, etc. Since physical phenomena are unpredictable, the generated random numbers are completely random.

[0055] The key to a true random number generator lies in the entropy source. Traditional random number generators have many irreparable defects due to entropy source problems. The emergence of memristors has brought opportunities for the development of random number generators. During the process of the memristor's resistance change under the excitation of an external electric field, there are multiple inherent random characteristics, including random resistance, random telegraph noise (RTN), periodic random voltage, and random time delay, etc. This unique random characteristic of itself can be independently used as an entropy source to fabricate a new type of random number generator.

[0056] True random number generators in the prior art generally adopt a simple single-loop circuit based on memristors. Based on the random performance of the memristor during the resistance state change process, a random analog signal is generated, and then the analog signal is processed to obtain the corresponding random digital signal. Further, the digital signal is collected and processed to obtain a random number sequence. Although the above design scheme simplifies the circuit structure to a certain extent, it also brings some defects, such as a complex random number generator module, low utilization rate of random resources due to only using a single random performance of the device, unstable random performance, unstable circuit operation, and reduced reliability, etc.

[0057] Therefore, the embodiments of the present disclosure provide a random number generator, and the random number generator includes: a random number generation module, a data acquisition module, and a power supply module; the power supply module is used to supply power to the random number generation module and the data acquisition module; the random number generation module is used to generate a random digital pulse signal based on the random response time delay and random low-resistance state resistance of the memristor; the data acquisition module is used to generate a random number sequence according to the random digital pulse signal. In this way, by simultaneously introducing the random response time delay and random low-resistance state resistance of the memristor as the entropy source, the random resources of the memristor are fully utilized, the circuit structure is simplified, the circuit reliability, randomness, and random number rate are improved, and the application scenario of the random number generator is expanded.

[0058] Figure 1 The structural schematic diagram of a random number generator provided by the embodiments of the present disclosure is as Figure 1 shown, and the random number generator includes: a random number generation module, a data acquisition module, and a power supply module;

[0059] The power supply module is used to supply power to the random number generation module and the data acquisition module;

[0060] The random number generation module is used to generate random digital pulse signals based on the random response delay and the random low resistance state resistance value of the memristor;

[0061] The data acquisition module is used to generate a random number sequence according to the random digital pulse signal.

[0062] In some embodiments, the power supply module provides power for the entire random number generator to ensure that both the random number generation module and the data acquisition module can work properly, which is the energy supply part.

[0063] The random number generation module includes a memristor, which uses the characteristics of the memristor to generate random digital pulse signals. The memristor is a special electronic component, and its resistance value is affected not only by the current but also by the history of past currents (i.e., it has a memory effect). This characteristic enables the memristor to produce a certain random response when facing external stimuli. In the embodiments of the present disclosure, the random response delay and the random low resistance state resistance value are utilized.

[0064] Among them, the random response delay refers to the fact that the response time of the memristor to an electrical signal has a certain randomness; the random low resistance state resistance value refers to the fact that the resistance of the memristor can also exhibit a certain randomness in the low resistance state; the entropy source refers to the source of uncertainty in the system.

[0065] Here, the random number generation module simultaneously utilizes these two characteristics to generate an entropy source based on the random response delay and the random low resistance state resistance value, and generates random digital pulse signals; the data acquisition module converts the random digital pulse signals obtained from the random response of the memristor into a series of random number sequences, improving the circuit reliability, randomness, and random number rate, and expanding the application scenarios of the random number generator.

[0066] In some embodiments, the random number generation module includes: a memristor, a capacitor, and an adjustment circuit; the first end of the adjustment circuit is connected to the first end of the memristor, and the second end of the adjustment circuit is connected to the second end of the memristor; the first end and the third end of the adjustment circuit are respectively connected to the first end and the second end of the capacitor, and the second end of the capacitor is grounded; the output end of the adjustment circuit is connected to the input end of the data acquisition module;

[0067] The capacitor is used to charge or discharge the memristor to adjust the first reference voltage of the memristor;

[0068] The adjustment circuit is used to output random digital pulse signals according to the first reference voltage of the memristor.

[0069] Here, the memristor is one of the key components of the random number generation module. Its resistance value changes under the action of a certain external current, and this change is memory-based, that is, its resistance value is affected not only by the current current but also by the previous current history. By utilizing this characteristic, the memristor can provide a certain degree of randomness.

[0070] In order to utilize this characteristic, an adjustment circuit and a capacitor are provided. The capacitor can store electrical energy, release electrical energy, and participate in the voltage change process. It forms a part of the circuit together with the memristor. By charging and discharging the capacitor, the output random digital pulse signal can be affected.

[0071] Here, the adjustment circuit has three ports, where

[0072] The first end is connected to the first end of the memristor, and the second end is connected to the second end of the memristor;

[0073] The first end is connected to the first end of the capacitor, and the third end is connected to the second end of the capacitor. The second end of the capacitor is grounded.

[0074] The capacitor can change the voltage of the memristor through charging and discharging, thereby affecting the resistance value of the memristor and the first reference voltage. Then, the adjustment circuit outputs a digital pulse signal according to the first reference voltage.

[0075] In this way, a random digital pulse signal is generated through the synergistic effect of the memristor and the capacitor, which has the characteristics of low power consumption, high efficiency, and easy integration, and is suitable for fields such as random number generation, encryption, and secure communication. By precisely controlling the charging and discharging process of the capacitor, a highly adjustable and stable random signal output can be achieved.

[0076] In some embodiments, the adjustment circuit includes: an integrated circuit and a triode;

[0077] The integrated circuit is used to compare the first reference voltage of the memristor, the high threshold voltage and the low threshold voltage of the memristor resistance state change, output a random digital pulse signal according to the comparison result, and adjust the state of the triode, and the state is on or off;

[0078] Among them, the state of the capacitor changes with the state of the triode, and the state of the capacitor is charging or discharging; the first reference voltage changes with the state of the capacitor.

[0079] Here, the integrated circuit can adjust the on or off of the triode. The on or off of the triode will affect whether the capacitor is charging or discharging, and the charging or discharging of the capacitor will affect the first reference voltage of the memristor, thereby affecting the comparison result, and the comparison result will continue to affect the state of the triode, that is, the on or off switching occurs again.

[0080] That is to say, the integrated circuit realizes the conversion of capacitor charging and discharging by controlling the on and off states of the triode, thereby affecting the first reference voltage of the memristor. The first reference voltage in turn affects the comparison results of the integrated circuit, and these comparison results further adjust the working state of the triode, forming a feedback loop that causes the triode to periodically switch between on and off. This feedback mechanism enables the circuit to continuously output uninterrupted digital pulse signals, and due to the uncertainty in the memristor and the capacitor charging and discharging processes, the signals have a high degree of randomness. In this way, the integrated circuit not only maintains the stability of signal output but also enhances the randomness of the signals, meeting the requirements for high-quality random signals.

[0081] In some embodiments, the integrated circuit includes: a first comparator, a second comparator, a set input and a reset input (RS, Reset - Set) flip - flop;

[0082] The first comparator is configured to compare the first reference voltage and the high threshold voltage;

[0083] The second comparator is configured to compare the first reference voltage and the low threshold voltage;

[0084] The RS flip - flop is configured to output a random digital pulse signal according to the comparison results of the first comparator and the second comparator, and to adjust the state of the triode.

[0085] Here, the high threshold voltage can also be referred to as the first threshold voltage, and the low threshold voltage can also be referred to as the second threshold voltage. The "high" and "low" refer to the difference between the two threshold voltages, and the low threshold voltage is less than the high threshold voltage. The values of the high threshold voltage and the low threshold voltage are not limited.

[0086] Here, the RS flip - flop is a digital logic circuit, and can also be referred to as an RS latch. It has two input terminals, namely: R (reset) and S (set). In the embodiments of the present disclosure, the inputs of the RS flip - flop are the comparison results of the first comparator and the second comparator. Assuming that the comparison result of the first comparator is the S input and the comparison result of the second comparator is the R input; there can be various application cases. For example:

[0087] If the S input is 1 and the R input is 0, the random digital pulse signal output by the RS flip - flop is 1.

[0088] If the S input and the R input are both 0 at the same time, the RS flip - flop maintains its current state, that is, it does not change.

[0089] If the S input is 0 and the R input is 1, the random digital pulse signal output by the RS flip-flop is 0.

[0090] That is, if the comparison result of the first comparator is 1 and the comparison result of the second comparator is 0, it can output 1; if the comparison result of the first comparator is 0 and the comparison result of the second comparator is 1, it can output 0.

[0091] Of course, there can be other situations for the setting of the input and output here. For example, if the S input is 1 and the R input is 0, the random digital pulse signal output by the RS flip-flop is 0; if the S input and the R input are both 0 at the same time, the flip-flop maintains its current state, that is, it does not change; if the S input is 0 and the R input is 1, the random digital pulse signal output by the RS flip-flop is 1. The setting of the RS flip-flop is not limited here.

[0092] In this way, the circuit design combining the comparator and the RS flip-flop can efficiently generate random digital pulse signals and has multiple advantages. First, the dual comparison mechanism enhances the stability of the system and the tolerance to noise, ensuring the reliability of the signal output. Second, the flexible trigger control enables the circuit to generate accurate random signals according to requirements and is widely used in fields such as encryption and communication. In addition, this design simplifies the circuit structure, reduces the dependence on external components, and improves the integration and cost-effectiveness. Generally speaking, this design provides an efficient, reliable and low-power random number generation scheme, which is suitable for various digital applications.

[0093] In some embodiments, the integrated circuit further includes: the first resistor, the second resistor, and the third resistor, which are used to provide the high threshold voltage for the first comparator and the low threshold voltage for the second comparator.

[0094] Here, a connection relationship among the first resistor, the second resistor, and the third resistor, as well as the connection relationships with the first comparator, the second comparator, the memristor, the capacitor, etc. are provided.

[0095] The first end of the first resistor is connected to the power supply (VCC), and the second end is connected to the first end of the second resistor; the second end of the second resistor is connected to the first end of the third resistor, and the second end of the third resistor is grounded.

[0096] The second end of the first resistor is also connected to the first input terminal of the first comparator, and the second input terminal of the first comparator is connected to the first reference voltage terminal;

[0097] The second end of the second resistor, that is, the first end of the third resistor, is also connected to the second input terminal of the second comparator, and the first input terminal of the second comparator is connected to the first reference voltage terminal;

[0098] One end of the capacitor is connected to the second terminal of the third resistor and grounded, and the other end is connected to the first input terminal of the second comparator;

[0099] One end of the memristor (i.e., the first reference voltage terminal) is connected to the first comparator and the second comparator, and the other end is connected to the second terminal of the triode; the first terminal of the triode is connected to the output terminal of the RS flip-flop, and the third terminal of the triode is grounded.

[0100] Specifically, the functions of the first resistor, the second resistor, and the third resistor in the circuit are to set the high threshold voltage and the low threshold voltage by voltage division. And, since the third resistor is connected between the capacitor and the comparator, it can also help regulate the charging and discharging rates of the capacitor, thereby controlling the working cycle of the integrated circuit.

[0101] The different resistance values designed for the first resistor, the second resistor, and the third resistor can not only affect the specific values of the high threshold voltage and the low threshold voltage, but also affect the working cycle of the integrated circuit, that is, the charging and discharging times of the capacitor, when the output result of the comparator changes, etc., and ultimately affect when the output signal of the random number generation module changes.

[0102] In this way, the first resistor, the second resistor, and the third resistor in the integrated circuit provide the high threshold voltage and the low threshold voltage for the first comparator and the second comparator, ensuring that the two comparators can accurately judge the state of the input signal, making the comparator have higher accuracy and reliability when judging the input signal. It enhances the sensitivity and anti-interference ability of the circuit and avoids misjudgment caused by voltage fluctuations. In addition, through the cooperation of the third resistor, the power consumption and response speed of the circuit can be further optimized, improving the overall performance and stability of the system.

[0103] In some embodiments, the integrated circuit further includes: a buffer, which is used to adjust the output result of the RS flip-flop and / or buffer the output result.

[0104] Here, the buffer is used to adjust and / or buffer the output result of the RS flip-flop to ensure that the output result can be transmitted in a stable and reliable manner in the subsequent circuit.

[0105] The buffer can be implemented using a NOT gate. The function of the NOT gate is to invert its input signal (i.e., the output result of the RS flip-flop), that is, when the RS flip-flop outputs a high level, the buffer will output a low level, and vice versa. In this way, the NOT gate not only helps to adjust the state of the signal, but also effectively reduces signal attenuation and noise interference, ensuring the stability and efficiency of the circuit.

[0106] As Figure 2 shown, a schematic structural diagram of a random number generation module is provided; as Figure 2As shown, the random number generation module includes: a memristor (i.e., M in Figure 2 ), a capacitor (i.e., C in Figure 2 ), and an adjustment circuit;

[0107] The adjustment circuit includes: a triode (i.e., VT in Figure 2 ), and an integrated circuit;

[0108] For the integrated circuit, the present disclosure specifically provides a circuit structure, which includes: a first comparator (i.e., U1 in Figure 2 ), a second comparator (i.e., U2 in Figure 2 ), an RS flip-flop (i.e., the device with R and S in Figure 2 ), a first resistor (i.e., R1 in Figure 2 ), a second resistor (i.e., R2 in Figure 2 ), a third resistor (i.e., R3 in Figure 2 ), and a NOT gate (i.e., N in Figure 2 ).

[0109] In addition, Figure 2 in which Ui represents the first reference voltage terminal. VDD represents the power supply module. Uo represents the output terminal; R4 represents a voltage dividing resistor, one end is connected to VDD, and the other end is connected to the output terminal Uo.

[0110] The random number generation model will be described in combination with this structure.

[0111] The high threshold voltage during the resistance state transition of the memristor M is V H , and the low threshold voltage is V L .

[0112] When externally voltage excited with a voltage value higher than V H , the memristor M changes from the high resistance state to the low resistance state, and at this time the memristor M "opens";

[0113] When externally voltage excited with a voltage value lower than V L , the memristor M changes from the low resistance state to the high resistance state, and at this time the memristor M "closes".

[0114] After the resistance change of the memristor M from the high resistance state to the low resistance state is completed, it can be regarded as a low resistance state resistor with a stable resistance value.

[0115] Assume the voltage of the capacitor C is Vi (in combination with Figure 2 , Vi also represents the voltage of the first reference voltage terminal Ui) to analyze the relationship between the voltage of the capacitor C and the output terminal (i.e., Uo) of the integrated circuit. After the power supply (i.e., VDD) is powered on, the memristor M is in the high resistance state at this time, where the voltage across the memristor is V M1 , the high resistance state resistance value is R H , and the low resistance state resistance value is R L, when the voltage across the capacitor C is 0, the voltage V across the memristor M M1 =V DD - V R4 , at this time V M1 is greater than V H ; After a short random time delay, the memristor M changes from the high-resistance state to the low-resistance state, and VDD charges the capacitor C through R4 and the memristor M, and V i gradually increases from 0.

[0116] The basic working principle of the integrated circuit is as follows:

[0117] 1. When V i <V L <V H , V U1 =0, V U2 =1, U O =1. At this time, the triode is cut off, and VDD charges the capacitor C through the resistor R4 and the memristor M, and V i gradually increases; among them, V U1 is the output result of the comparator U1 (i.e., the first comparator), V U2 is the output result of the comparator U2 (i.e., the second comparator), and Uo is the output terminal;

[0118] 2. As Vi is gradually generated, the relationship between V i , V L , V H will also change. When it changes to V L <V i <V H , V U1 =0, V U2 =0, U O remains unchanged. At this time, the triode VT is cut off, and VDD continues to charge the capacitor C through the resistor R4 and the memristor M, and V i continues to gradually increase;

[0119] 3. The relationship between V i , V L , V H changes with the change of V i . When it changes to V L <V H <V i , V U1 =1, V U2 =0, U O =0. At this time, the triode VT conducts, and the memristor M conducts in reverse. At this time, the capacitor C discharges through the memristor M and the triode VT. As the capacitor discharges, V i gradually decreases;

[0120] 4. As Vi gradually decreases, the relationship between V i , V L , V H will also change. When it changes to V L < V i < V H , V U1 = 0, V U2 = 0, U O remains unchanged. At this time, the triode VT conducts, the memristor M conducts in reverse, and the capacitor C discharges through the memristor M and the triode, and V i continues to decrease;

[0121] 5. The relationship between V i , V L , V H changes with the change of V i . When it changes to V i < V L < V H , V U1 = 0, V U2 = 1, U O = 1. At this time, the triode is cut off, and VDD charges the capacitor C through R4 and the memristor M, and V i gradually increases.

[0122] It can be found from the above principle that the voltage of the capacitor C oscillates repeatedly between V L and V H . The output terminal Uo of the integrated circuit is at a high level during the charging of the capacitor C and at a low level during the discharging of the capacitor. When the capacitor C is charged, the resistance value of the memristor M is R4 + R L , and when the capacitor C is discharged, the resistance value of the memristor M is R L . The charge and discharge time is proportional to the resistance value of the memristor M.

[0123] Through the above design, a design is obtained in which the time-domain pulse width of the high level output by the output terminal Uo, the response delay of the memristor, and the low-resistance state resistance value R L are related. That is, the random performance of the circuit, namely, two random quantities, the random response delay and the random low-resistance state resistance value, are introduced, and the random performance of the circuit is improved. This means that the behavior of the circuit is no longer completely determined by deterministic factors, but rather a certain degree of uncertainty and variability are added, bringing better anti-interference ability and adaptability, especially in complex or changing working environments.

[0124] It should be noted that the integrated circuit can also adopt other circuit structures with the above functions, such as any 555 timer, etc., which are not limited here.

[0125] In some embodiments, the data acquisition module includes: a trigger and a clock; the input ends of the trigger are respectively connected to the output end of the random number generation module and the clock; the output end of the trigger is connected to the input end of a counter.

[0126] In some embodiments, the trigger is configured to receive the random pulses output by the random number generation module and the clock signals from the clock, perform a logical AND operation based on the random pulses and the clock signals, and perform counting according to the result of the logical AND operation to obtain a random number sequence.

[0127] Here, the random number generation module outputs a random digital pulse signal (Uo), and the trigger performs a logical AND operation on the clock signal (clk) and Uo. The trigger counts at the falling edge, counts "1" when the output is high, and counts "0" when the output is low, thereby obtaining a random number sequence.

[0128] In some embodiments, the data acquisition module further includes: a counter, which is configured to control the number of bits of the data in the random number sequence according to the data requirements of the target device.

[0129] Here, the counter is used to control the number of bits of the generated data to adapt to the storage upper limit of the FPGA.

[0130] In some embodiments, the data acquisition module further includes: a serial port unit, which is configured to output the random number sequence to the target device.

[0131] Here, the random number sequence is output to the target device, i.e., the signal receiving device, through the serial port unit.

[0132] Here, the data acquisition module may further include a state control machine, and the entire process of the data acquisition module is controlled by the state control machine.

[0133] Here, the data acquisition module can be designed through an FPGA (Field Programmable Gate Array). The FPGA has independent input / output (I / O) ports, an adjustable built-in clock signal, and integrates units such as a trigger, a clock, a counter, a serial port, and a state control machine, and can implement the shift register of binary data.

[0134] Figure 3 It is a schematic structural diagram of a data acquisition module provided by an embodiment of the present disclosure; as Figure 3 shown, the data acquisition module may include: a trigger, a counter, a serial port, a clock, and a state control machine;

[0135] Among them, the random number generation module outputs a random digital pulse signal (i.e., Uo). The flip-flop receives the clock signal clk and Uo for logical AND operation. The flip-flop counts on the falling edge, counts "1" when the output is high, and counts "0" when the output is low, thus obtaining a random number sequence. Then, it is output to the signal receiving device through the serial port unit.

[0136] In some embodiments, the random number generator further includes: a control unit;

[0137] At least one of the first resistor, the second resistor, and the third resistor is a variable resistor;

[0138] The control unit is configured to adjust the resistance value of at least one of the first resistor, the second resistor, and the third resistor.

[0139] Here, each resistor in the integrated circuit can be a variable resistor. In the design of the random number generator, a control unit can be provided. By using the control unit to adjust the resistance value of the variable resistor, the current flow mode or noise characteristics of the circuit can be changed, thereby affecting the output of random number generation. The change in the resistance value can make the generated random numbers more unpredictable, increasing the randomness and security of the system.

[0140] In addition, the adjustment of the resistance value by the control unit can make the random number generator have flexible performance. In different application scenarios, the resistance value can be adjusted as needed to optimize the generation characteristics of random numbers. For example, under different working conditions (such as temperature change, power supply fluctuation, etc.), adjusting the resistance value can maintain the stability and quality of random numbers. Different resistance settings can compensate for the influence of environmental changes on the random number generation process and ensure the stable quality of the generated random numbers.

[0141] In some embodiments, the random number generator further includes: a control unit;

[0142] The capacitor is a variable capacitor;

[0143] The control unit is configured to adjust the capacitance value of the capacitor.

[0144] Here, the change in the capacitance value directly affects the characteristics of current and voltage fluctuations in the circuit, thereby changing the random number generation process. By adjusting the capacitor, the time constant, charge and discharge characteristics, etc. of the circuit can be changed, thereby improving the unpredictability of the generated random numbers. By using a variable capacitor, changes can be generated in a wider range, making the generated random numbers more random and difficult to predict.

[0145] Here, in the design of a random number generator, a control unit can be provided. The control unit can be used to precisely adjust the capacitance value to optimize the performance of the random number generator. Different capacitance values will affect the noise characteristics, stability, and randomness of the circuit. The introduction of the control unit makes the adjustment more flexible, allowing the capacitance to be adjusted according to requirements in different working environments to obtain the best random number quality and adapt to different application scenarios.

[0146] By adjusting the capacitance value through the control unit, the influence of these environmental factors on the circuit performance can be compensated, ensuring the stability of the generated random number quality. In different working environments, the change in capacitance can adjust the response of the circuit, thus adapting to the change of external conditions and maintaining the stability of the system. The capacitance value can be conveniently adjusted through the control unit, so as to flexibly adjust the performance of the random number generator according to requirements. For example, in some specific occasions, higher randomness or stability may be required. The control unit can adjust the capacitance according to actual needs, avoiding the problem of unstable performance caused by capacitance mismatch. In addition, the design of variable capacitance makes the system more flexible in maintenance and upgrade.

[0147] In some embodiments, the control unit is configured to periodically adjust the resistance value of at least one of the first resistor, the second resistor, and the third resistor; and / or adjust the capacitance value of the capacitor.

[0148] The control unit is further configured to adjust the resistance value of at least one of the first resistor, the second resistor, and the third resistor according to application requirements; and / or adjust the capacitance value of the capacitor.

[0149] Here, by periodically or adjusting the values of the resistors and capacitors according to application requirements, the control unit can improve the flexibility and adaptability of the system, enabling it to maintain excellent performance under different working conditions. This adjustment helps to optimize the response speed, filtering characteristics, and stability of the circuit, and can enhance the robustness of the circuit to cope with environmental changes and load fluctuations. In addition, by reducing hardware requirements and simplifying the design, the cost can be reduced, the energy efficiency, accuracy, and maintainability of the system can be improved, the service life of the device can be extended, and future upgrade requirements can be supported. And by adjusting the resistance value of at least one of the first resistor, the second resistor, and the third resistor and the capacitance value of the capacitor, the working cycle of the integrated circuit can also be changed.

[0150] In some embodiments, the random number generator can be applied to electronic devices such as computers, Internet of Things devices, automotive electronics, wireless communication devices, and quantum computers; of course, it can also be applied to any other electronic devices that require high security, encryption processing, and unpredictability. There is no limitation here.

[0151] The true random number generator based on memristors provided by the embodiments of the present disclosure introduces both the random response delay of the memristor and the random low-resistance state resistance value as entropy sources, comprehensively utilizes two random resources of the device response delay and the low-resistance state resistance value, can make full use of the random resources of the memristor, simplifies the circuit structure, improves the circuit reliability, randomness and random number rate, and at the same time adds a rate control function, expanding the application scenarios of the random number generator.

[0152] Figure 4 is a schematic flowchart of a random number generation method provided by the embodiments of the present disclosure; as Figure 4 shown, the method is applied to a random number generator, and the random number generator includes: a random number generation module and a data acquisition module; the method includes:

[0153] Step 401, after the random number generator is powered on, the random number generation module generates a random digital pulse signal based on the random response delay of the memristor and the random low-resistance state resistance value;

[0154] Step 402, the data acquisition module generates a random number sequence according to the random digital pulse signal.

[0155] In some embodiments, the random number generator may adopt the above Figure 1 shown random number generator, and the specific structure is as described above, which will not be elaborated here.

[0156] In some embodiments, the random number generation module includes: a memristor, a capacitor, and an adjustment circuit; the adjustment circuit includes: an integrated circuit and a triode;

[0157] The random number generation module generates a random digital pulse signal based on the random response delay of the memristor and the random low-resistance state resistance value, including:

[0158] The integrated circuit compares the first reference voltage of the memristor, the high threshold voltage and the low threshold voltage of the memristor state change, outputs a random digital pulse signal according to the comparison result, and adjusts the state of the triode, where the state is on or off;

[0159] Wherein, the state of the capacitor changes with the state of the triode, and the state of the capacitor is charging or discharging; the first reference voltage changes with the state of the capacitor.

[0160] Here, the integrated circuit realizes the conversion of the charging and discharging of the capacitor by controlling the on and off states of the triode, thereby affecting the first reference voltage of the memristor. The first reference voltage in turn affects the comparison results of the integrated circuit, and these comparison results further adjust the working state of the triode, forming a feedback loop, resulting in the triode periodically switching between on and off. This feedback mechanism enables the circuit to continuously output uninterrupted digital pulse signals, and due to the uncertainty in the memristor and the capacitor charging and discharging processes, the signals have a high degree of randomness. In this way, the integrated circuit not only maintains the stability of signal output but also enhances the randomness of the signals, meeting the requirements for high-quality random signals.

[0161] In some embodiments, the integrated circuit includes: a first comparator, a second comparator, and an RS flip-flop;

[0162] The integrated circuit compares the first reference voltage of the memristor, the high threshold voltage and the low threshold voltage of the change in the memristor resistance state, outputs a random digital pulse signal according to the comparison results, and adjusts the state of the triode, including:

[0163] The first comparator compares the first reference voltage and the high threshold voltage;

[0164] The second comparator compares the first reference voltage and the low threshold voltage;

[0165] The RS flip-flop outputs a random digital pulse signal according to the comparison results of the first comparator and the second comparator, and adjusts the state of the triode.

[0166] In some embodiments, the RS flip-flop outputs a random digital pulse signal according to the comparison results of the first comparator and the second comparator, and adjusts the state of the triode, including:

[0167] If the comparison result of the first comparator is a first value and the comparison result of the second comparator is a second value, the RS flip-flop outputs a random digital pulse signal as a first output value and turns off the triode;

[0168] If the comparison result of the first comparator is a second value and the comparison result of the second comparator is a second value, the RS flip-flop outputs a random digital pulse signal as a second output value and turns on the triode.

[0169] Specifically, an RS flip-flop is a digital logic circuit, which can also be called an RS latch. It has two input terminals, namely: R (reset) and S (set). In the embodiments of the present disclosure, the inputs of the RS flip-flop are the results of the first comparator and the second comparator. Assume that the comparison result of the first comparator is the S input, and the comparison result of the second comparator is the R input. When applied, there can be various situations. For example:

[0170] If the S input is 1 and the R input is 0, the random digital pulse signal output by the RS flip-flop is 1.

[0171] If the S input and the R input are both 0 at the same time, the RS flip-flop maintains its current state, that is, it does not change.

[0172] If the S input is 0 and the R input is 1, the random digital pulse signal output by the RS flip-flop is 0.

[0173] That is, if the result of the first comparator is 1 and the result of the second comparator is 0, it can output 1. If the result of the first comparator is 0 and the result of the second comparator is 1, it can output 0.

[0174] Of course, there can be other situations for the setting of the input and output here. For example, if the S input is 1 and the R input is 0, the random digital pulse signal output by the RS flip-flop is 0; if the S input and the R input are both 0 at the same time, the flip-flop maintains its current state, that is, it does not change; if the S input is 0 and the R input is 1, the random digital pulse signal output by the RS flip-flop is 1. The setting of the RS flip-flop is not limited here.

[0175] In some embodiments, the method further includes:

[0176] Adjusting the output result of the RS flip-flop, and / or buffering the output result.

[0177] Here, the adjustment can be inversion, that is, if the RS flip-flop is 0, it is adjusted to 1, and if the RS flip-flop is 1, it is adjusted to 0.

[0178] Here, the integrated circuit may further include: a buffer. The buffer can use a NOT gate. The function of the NOT gate is to invert its input signal (that is, the output signal of the RS flip-flop). That is, when the RS flip-flop outputs a high level, the buffer will output a low level, and vice versa. In this way, the NOT gate not only helps to adjust the state of the signal, but also effectively reduces signal attenuation and noise interference, ensuring the stability and efficiency of the circuit.

[0179] In some embodiments, the random number generator further includes: a control unit, at least one of the first resistor, the second resistor, and the third resistor being a variable resistor; and the capacitor being a variable capacitor.

[0180] The method further includes at least one of the following:

[0181] The control unit periodically adjusts the resistance value of at least one of the first resistor, the second resistor, and the third resistor; and / or adjusts the capacitance value of the capacitor.

[0182] The control unit adjusts the resistance value of at least one of the first resistor, the second resistor, and the third resistor according to application requirements; and / or adjusts the capacitance value of the capacitor.

[0183] Here, by periodically or according to application requirements adjusting the values of the resistors and capacitors, the control unit can improve the flexibility and adaptability of the system, enabling it to maintain excellent performance under different operating conditions. Such adjustment helps to optimize the response speed, filtering characteristics, and stability of the circuit, and can enhance the robustness of the circuit to cope with environmental changes and load fluctuations. In addition, by reducing hardware requirements and simplifying the design, costs can be reduced, the energy efficiency, accuracy, and maintainability of the system can be improved, the service life of the device can be extended, and future upgrade requirements can be supported.

[0184] In some embodiments, the data acquisition module includes: a trigger and a clock; the input terminals of the trigger are respectively connected to the output terminal of the random number generation module and the clock; and the output terminal of the trigger is connected to the input terminal of a counter.

[0185] The data acquisition module generates a random number sequence according to the random digital pulse signal, including:

[0186] The trigger receives the random pulse output by the random number generation module and the clock signal from the clock, performs a logical AND operation according to the random pulse and the clock signal, and counts according to the result of the logical AND operation to obtain a random number sequence.

[0187] In some embodiments, the data acquisition module further includes: a counter and a serial port unit, and the method further includes at least one of the following:

[0188] The counter controls the number of bits of the data in the random number sequence according to the data requirements of the target device.

[0189] The serial port unit outputs the random number sequence to the target device.

[0190] It can be understood that the random number generation method provided in the above embodiments and the embodiments of the corresponding random number generator belong to the same concept. The specific implementation process can be found in the method embodiments and will not be elaborated here.

[0191] The random number generation method provided by the embodiments of the present disclosure is based on a memristor-based true random number generator. This true random number generator simultaneously introduces the random response delay of the memristor and the random low-resistance state resistance value as entropy sources, making full use of the random resources of the memristor. In this way, the method comprehensively utilizes two random resources, namely, the device response delay and the low-resistance state resistance value, improving the circuit reliability, randomness, and random number rate. At the same time, a rate control function is added, expanding the application scenarios of the random number generator.

[0192] The embodiments of the present application provide a computer program product or a computer program. The computer program product or the computer program includes computer instructions, and the computer instructions are stored in a computer-readable storage medium. The processor of the computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, causing the computer device to execute an encryption method. The encryption method can use a random number sequence generated by a random number generator to generate keys, initialization vectors, salt values, random signatures, etc.

[0193] The embodiments of the present application provide a computer-readable storage medium storing executable instructions, where the executable instructions are stored. When the executable instructions are executed by a processor, the processor will be caused to execute the random number generation method provided by the embodiments of the present application.

[0194] In some embodiments, the computer-readable storage medium can be a memory such as FRAM, ROM, PROM, EPROM, EEPROM, flash memory, magnetic surface memory, optical disc, or CD-ROM; or it can be various devices including one or any combination of the above memories.

[0195] In some embodiments, the executable instructions can be in the form of a program, software, software module, script, or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and can be deployed in any form, including being deployed as an independent program or being deployed as a module, component, subroutine, or other unit suitable for use in a computing environment.

[0196] As an example, the executable instructions may or may not correspond to a file in the file system, and can be stored as part of a file that stores other programs or data. For example, they can be stored in one or more scripts in a Hyper Text Markup Language (HTML) document, stored in a single file dedicated to the program being discussed, or stored in multiple cooperating files (such as files storing one or more modules, subroutines, or code portions).

[0197] As an example, the executable instructions can be deployed to execute on a single computing device, or on multiple computing devices located at one location, or on multiple computing devices distributed across multiple locations and interconnected by a communication network.

[0198] Figure 5 Schematic structural diagram of an electronic device provided by an embodiment of the present disclosure; as Figure 5 shown, the electronic device 50 includes: a processor 501, and a memory 502 communicatively connected to the processor 501; the memory 502 stores instructions executable by the processor 501.

[0199] The processor may include a random number generator for generating a random number sequence. The random number generator may adopt a structure as Figure 1 shown.

[0200] In practical applications, the electronic device 50 may further include: at least one network interface 503. Each component in the electronic device 50 is coupled together through a bus system 504. It can be understood that the bus system 504 is used to implement connection and communication between these components. In addition to the data bus, the bus system 504 also includes a power bus, a control bus, and a status signal bus. However, for the sake of clear illustration, in Figure 5 all kinds of buses are labeled as the bus system 504. Among them, the number of the processors 501 can be at least one, and the number of the memories 502 can be at least one. The network interface 503 is used for wired or wireless communication between the electronic device 50 and other devices.

[0201] The memory 502 in the embodiment of the present disclosure is used to store various types of data to support the operation of the electronic device 50.

[0202] The method disclosed in the above embodiments of the present disclosure can be applied to or implemented by the processor 501. The processor 501 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the integrated logic circuit in the hardware of the processor 501 or the instructions in the form of software. The above-mentioned processor 501 may be a general-purpose processor, a digital signal processor (DSP), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The processor 501 can implement or execute each method, step, and logic block diagram disclosed in the embodiments of the present disclosure. The general-purpose processor may be a microprocessor or any conventional processor, etc. Combining the steps of the method disclosed in the embodiments of the present disclosure, it can be directly embodied as being executed and completed by the hardware decoding processor, or executed and completed by the combination of the hardware and software modules in the decoding processor. The software module may be located in the storage medium, and this storage medium is located in the memory 502. The processor 501 reads the information in the memory 502 and combines its hardware to complete the steps of the foregoing method.

[0203] In some embodiments, the electronic device 50 may be implemented by one or more application-specific integrated circuits (ASICs), DSPs, programmable logic devices (PLDs), complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), general-purpose processors, controllers, microcontroller units (MCUs), microprocessors, or other electronic components for performing the foregoing method.

[0204] It should be understood that various forms of the processes shown above can be used, with steps reordered, added, or deleted. For example, the steps recited in the present disclosure can be executed in parallel, sequentially, or in a different order, as long as the desired results of the technical solutions disclosed in the present disclosure can be achieved, and no limitations are imposed herein.

[0205] In the above description, reference is made to "some embodiments", which describe a subset of all possible embodiments. However, it can be understood that "some embodiments" may be the same subset or different subsets of all possible embodiments and can be combined with each other without conflict.

[0206] Unless otherwise defined, all technical and scientific terms used in this disclosure have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terms used in this disclosure are for the purpose of describing embodiments of this disclosure only and are not intended to limit this disclosure.

[0207] It should be understood that in various embodiments of this disclosure, the magnitude of the serial numbers of each implementation process does not mean the sequence of execution, and the execution sequence of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of this disclosure.

[0208] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include at least one of such features. In the description of this disclosure, "a plurality" means two or more unless otherwise specifically defined.

[0209] As described above, the above are only specific embodiments of this disclosure, but the protection scope of this disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by this disclosure can easily think of changes or substitutions, which should be covered by the protection scope of this disclosure. Therefore, the protection scope of this disclosure should be subject to the protection scope of the claims.

Claims

1. A random number generator, characterized in that, The random number generator includes: a random number generation module, a data acquisition module, and a power supply module; The power supply module is used to supply power to the random number generation module and the data acquisition module; The random number generation module is used to generate a random digital pulse signal based on the random response delay and the random low resistance state value of the memristor; The data acquisition module is used to generate a random number sequence according to the random digital pulse signal; Among them, the random number generation module includes: a memristor, a capacitor, an adjustment circuit, an integrated circuit, and a triode; the capacitor is used to charge or discharge the memristor to adjust the first reference voltage of the memristor; the adjustment circuit is used to output a random digital pulse signal according to the first reference voltage of the memristor; The adjustment circuit includes: an integrated circuit and a triode; the integrated circuit is used to compare the first reference voltage of the memristor, the high threshold voltage and the low threshold voltage of the change of the memristor state, output a random digital pulse signal according to the comparison result, and adjust the state of the triode, the state being on or off; the state of the capacitor changes with the state of the triode, the state of the capacitor being charging or discharging; the first reference voltage changes with the state of the capacitor; The integrated circuit includes: a first comparator, a second comparator, and a set input and reset input RS flip-flop; The first comparator is used to compare the first reference voltage and the high threshold voltage; The second comparator is used to compare the first reference voltage and the low threshold voltage; The RS flip-flop is used to output a random digital pulse signal according to the comparison result of the first comparator and the comparison result of the second comparator, and adjust the state of the triode.

2. The random number generator according to claim 1, characterized in that, The first end of the adjustment circuit is connected to the first end of the memristor, and the second end of the adjustment circuit is connected to the second end of the memristor; the first end and the third end of the adjustment circuit are respectively connected to the first end and the second end of the capacitor, and the second end of the capacitor is grounded; the output end of the adjustment circuit is connected to the input end of the data acquisition module.

3. The random number generator according to claim 1, wherein The integrated circuit further includes: a first resistor, a second resistor, and a third resistor, which are used to provide the high threshold voltage for the first comparator and the low threshold voltage for the second comparator.

4. The random number generator according to claim 1, characterized in that, The integrated circuit further includes: a buffer, which is used to adjust the output result of the RS flip-flop and / or buffer the output result.

5. The random number generator according to claim 1, characterized in that, The data acquisition module includes: a flip-flop and a clock; the input end of the flip-flop is respectively connected to the output end of the random number generation module and the clock; the output end of the flip-flop is connected to the input end of the counter.

6. The random number generator according to claim 5, wherein, The flip-flop is used to receive the random pulse output by the random number generation module and the clock signal from the clock, perform a logical AND according to the random pulse and the clock signal, and count according to the logical AND result to obtain a random number sequence.

7. The random number generator according to claim 5, wherein The data acquisition module further includes: a counter, which is used to control the number of digits of the random number sequence according to the data requirements of the target device.

8. The random number generator according to claim 5, wherein, The data acquisition module further includes: a serial port unit for outputting the random number sequence to a target device.

9. A random number generation method, characterized in that, The method is applied to a random number generator, which includes: a random number generation module and a data acquisition module; the method includes: After the random number generator is powered on, the random number generation module generates a random digital pulse signal based on the random response delay and the random low resistance state value of the memristor. The data acquisition module generates a random number sequence according to the random digital pulse signal. The random number generation module includes: a memristor, a capacitor, and an adjustment circuit; the adjustment circuit includes: an integrated circuit and a triode. The random number generation module generates a random digital pulse signal based on the random response delay and the random low resistance state value of the memristor, including: The integrated circuit compares the first reference voltage of the memristor, the high threshold voltage and the low threshold voltage of the change in the memristor resistance state, outputs a random digital pulse signal according to the comparison result, and adjusts the state of the triode, where the state is conduction or cut-off; wherein, the state of the capacitor changes with the state of the triode, and the state of the capacitor is charging or discharging; the first reference voltage changes with the state of the capacitor. The integrated circuit includes: a first comparator, a second comparator, and an RS flip-flop. The integrated circuit compares the first reference voltage of the memristor, the high threshold voltage and the low threshold voltage of the change in the memristor resistance state, outputs a random digital pulse signal according to the comparison result, and adjusts the state of the triode, including: The first comparator compares the first reference voltage and the high threshold voltage. The second comparator compares the first reference voltage and the low threshold voltage. The RS flip-flop outputs a random digital pulse signal according to the comparison result of the first comparator and the comparison result of the second comparator, and adjusts the state of the triode.

10. The method according to claim 9, wherein The RS flip-flop outputs a random digital pulse signal according to the comparison result of the first comparator and the comparison result of the second comparator, and adjusts the state of the triode, including: If the comparison result of the first comparator is a first value and the comparison result of the second comparator is a second value, the RS flip-flop outputs a random digital pulse signal as a first output value and cuts off the triode. If the comparison result of the first comparator is a second value and the comparison result of the second comparator is a second value, the RS flip-flop outputs a random digital pulse signal as a second output value and turns on the triode.

11. The method according to claim 9, wherein The method further includes: Adjusting the output result of the RS flip-flop, and / or buffering the output result.

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