Fast CAD compilation with coarse macro reduction

Abstract

The invention relates to fast CAD compilation with coarse macro reduction. A system or method of the present disclosure may provide a library that includes a plurality of macros that may be pre-compiled prior to implementing a design. For example, the design may be mapped to one or more macros in a library, and the one or more macros may be laid out to a portion, one region, one or more regions of a region of the integrated circuit device and routed between the portion, one region, one or more regions of the region of the integrated circuit device to implement the design. Due to the macro that can be pre-compiled, the compilation time experienced by the designer can correspond to the layout and routing of one or more macro, which can be less than the compilation time of the fine-grained operation. A lookup table mask may be used to set pre-compiled logic units within a macro to set and / or adjust the functionality of the macro. Additionally or alternatively, layout and routing operations may be performed at finer granularity to reduce bottlenecks.

Description

Technical Field

[0001] The present invention relates generally to programmable logic devices. More specifically, the present disclosure relates to reducing compile time for programmable logic devices such as high-capacity field programmable gate arrays (FPGAs). Summary of the invention

[0002] This section is intended to introduce the reader to various aspects of the technology that may be related to various aspects of the present disclosure, which are described and / or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Therefore, it is understood that these statements should be understood from this perspective, and not as an admission of prior art.

[0003] Programmable logic devices are a class of integrated circuits that can be programmed to perform a variety of operations. For example, design software such as computer-aided design (CAD) software can be used to implement the design on a programmable logic device. The design software may include the option of using a macro to implement the design. However, the implementation may take a long time to compile, and the quality of the result (QoR) may be different. For example, macros may be placed and routed in many different locations of a programmable device, and placed and routed separately for each implementation, which may increase the compile time and also cause QoR variability. That is, the placement and routing operations may increase the compile time and QoR variability. Longer compile time and QoR variability may increase development costs, development time, and the uncertainty of time to reach the market. In fact, as the complexity and / or size of programmable logic devices increase, due to the increase in the number of fine-grained elements, the compile time and / or QoR of programmable logic devices may become more computationally intensive, resource intensive, and cost intensive. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Various aspects of the present disclosure may be better understood upon reading the following detailed description and referring to the accompanying drawings, in which:

[0005] Figure 1 is a block diagram of a system for programming an integrated circuit device according to an embodiment of the present disclosure;

[0006] Figure 2 According to the embodiment of the present disclosure Figure 1 A block diagram of an integrated circuit device;

[0007] Figure 3 According to the embodiment of the present disclosure Figure 1 A block diagram of a programmable fabric of an integrated circuit device;

[0008] Figure 4 The embodiment of the present disclosure is designed using macros. Figure 1 A block diagram of a programmable structure of an integrated circuit device;

[0009] Figure 5 A method for generating one or more macros for a library and configuring the library using one or more macros according to an embodiment of the present disclosure Figure 1 A flowchart of an example method of an integrated circuit device;

[0010] Figure 6 is a method for using one or more macro configurations according to an embodiment of the present disclosure Figure 1 A flowchart of an example method of an integrated circuit device;

[0011] Figure 7 According to the embodiments of the present disclosure, Figure 1 a schematic diagram for recursively performing placement and routing operations for one or more macros on an integrated circuit device;

[0012] Figure 8 is a method for adjusting one or more macros to Figure 1 A schematic diagram of implementing the design on a programmable structure of an integrated circuit device;

[0013] Fig. 9 is a method for reconfiguring one or more macros to Figure 1 A flowchart of an example method for implementing a design on an integrated circuit device; and

[0014] Fig.10 The embodiment according to the present invention includes Figure 1 A block diagram of a data processing system of an integrated circuit device. DETAILED DESCRIPTION

[0015] One or more specific embodiments are described below. In order to provide a concise description of these embodiments, not all features of an actual implementation are described in the specification. It should be understood that in the development of any such actual implementation, as with any engineering or design project, many implementation-specific decisions must be made to achieve the developer's specific goals, such as complying with system-related and business-related constraints, which may vary from implementation to implementation. In addition, it should be appreciated that such development work may be complex and time consuming, but it is still a routine task of design, fabrication, and manufacturing for a person of ordinary skill having the benefit of this disclosure.

[0016] When introducing elements of various embodiments of the present disclosure, the articles "a," "an," and "the" are intended to indicate that there are one or more elements. The terms "comprising," "including," and "having" are intended to be inclusive and indicate that there may be additional elements in addition to the listed elements. Additionally, it should be understood that references to "one embodiment" or "an embodiment" of the present disclosure should not be interpreted as excluding the existence of additional embodiments that also incorporate the recited features.

[0017] The present disclosure describes systems and techniques related to implementing designs on integrated circuit systems such as high-capacity field programmable gate arrays (FPGAs) using coarse-grained operations to reduce compile time and / or improve quality of results (QoR). In particular, the embodiments described herein are directed to placing and routing one or more pre-compiled macros on a programmable structure of an integrated circuit device. The macros may include groupings of logic units that may be mapped (e.g., technology mapped), placed (e.g., loaded) into regions of the programmable structure, and internally wired. To this end, the programmable structure may include regions consisting of one or more sectors, groups of sectors, portions of sectors, partitions, groups of partitions, portions of partitions, and the like. The pre-compiled macros may be placed (e.g., loaded) in regions of the programmable structure, and routing resources may be used to communicatively couple the macros to implement the design. In this way, the placement of the macros is limited to the region. Since the macros are pre-compiled before the placement and routing operations and the placement is limited to a specific region, the designer's compile time may be reduced and / or the QoR may be improved. That is, the implementation of coarse-grained operations rather than fine-grained operations may reduce the number of placement and routing decisions made during compilation. Additionally or alternatively, since the placement of macros is restricted to specific areas of the integrated circuit device, the variability of QoR may be reduced.

[0018] Considering the above situation, Figure 1 A block diagram of a system 10 is shown that can implement one or more functions. For example, a designer may desire to implement functions, such as the operations of the present disclosure, on an integrated circuit device 12 (e.g., a programmable logic device such as a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC)). In some cases, the designer may specify a high-level program to be implemented, such as Program or This may enable a designer to more efficiently and easily provide programming instructions to configure a set of programmable logic for the integrated circuit device 12 without requiring knowledge of a specific low-level hardware description language (e.g., Verilog or VHDL). Very similar to other high-level programming languages ​​(e.g., C++), a programmable logic designer familiar with such programming languages ​​may have a shorter learning curve than a designer who is required to learn an unfamiliar low-level hardware description language to implement new functionality in the integrated circuit device 12.

[0019] Designers can use design software 14 (e.g., Intel Corporation's The design software 14 may use a compiler 16 to convert the high-level program into a low-level description. In some embodiments, the compiler 16 and the design software 14 may be packaged into a single software application. The compiler 16 may provide machine-readable instructions representing the high-level program to the host 18 and the integrated circuit device 12. The host 18 may receive a host program 22 that may be implemented by the kernel program 20. In order to implement the host program 22, the host 18 may transmit instructions from the host program 22 to the integrated circuit device 12 via a communication link 24, and the communication link 24 may be, for example, direct memory access (DMA) communication or peripheral component interconnect express (PCIe) communication. In some embodiments, the kernel program 20 and the host 18 may implement the configuration of a logic block 26 on the integrated circuit device 12. The logic block 26 may include a circuit system and / or other logic units, and may be configured to implement arithmetic operations, such as addition and multiplication.

[0020] The designer can use the design software 14 to generate and / or specify a low-level program, such as the above-mentioned low-level hardware description language. For example, the design software 14 can be used to map the workload to one or more routing resources of the integrated circuit device 12 based on timing, line usage, logic utilization, and / or routability. Additionally or alternatively, the design software 14 can be used to route the first data to a portion of the integrated circuit device 12, and route the second data, power, and clock signal to a second portion of the integrated circuit device 12. In addition, in some embodiments, the system 10 can be implemented without the host program 22 and / or without a separate host program 22. In addition, in some embodiments, the techniques described herein can be implemented as a non-programmable circuit design in a circuit system. Therefore, the embodiments described herein are intended to be illustrative and not restrictive.

[0021] Turning now to a more detailed discussion of integrated circuit device 12, Figure 2 1 is a block diagram of an integrated circuit device 12 as an example of a programmable logic device (e.g., a field programmable gate array (FPGA)). In addition, it should be understood that the integrated circuit device 12 can be any other suitable type of programmable logic device (e.g., a structured ASIC, such as an eASIC from Intel Corporation ASIC). TMThe integrated circuit device 12 may have an input / output circuit system 42 for driving signals outside the device and for receiving signals from other devices via input / output pins 44. Interconnect resources 46, such as global and local vertical and horizontal conductive lines and buses, and / or configuration resources (e.g., hard-wired couplings, logic couplings not implemented by designer logic) may be used to route signals on the integrated circuit device 12. Additionally, the interconnect resources 46 may include fixed interconnects (conductive lines) and programmable interconnects (i.e., programmable connections between corresponding fixed interconnects). For example, the interconnect resources 46 may be used to route signals (e.g., clock or data signals) through the integrated circuit device 12. Additionally or alternatively, the interconnect resources 46 may be used to route power (e.g., voltage) through the integrated circuit device 12. Programmable logic 48 may include combinational and sequential logic circuit systems. For example, the programmable logic 48 may include lookup tables, registers, and multiplexers. In various embodiments, the programmable logic 48 may be configured to perform custom logic functions. The programmable interconnects associated with the interconnect resources may be considered part of the programmable logic 48.

[0022] A programmable logic device, such as an integrated circuit device 12, may include a programmable element 50 having a programmable logic 48. In some embodiments, at least some of the programmable elements 50 may be grouped into logic array blocks (LABs). As described above, a designer (e.g., a user, a customer) may (re)program (e.g., (re)configure) the programmable logic 48 to perform one or more desired functions. By way of example, some programmable logic devices may be programmed or reprogrammed by configuring the programmable element 50 using a mask programming arrangement that is performed during semiconductor manufacturing. Other programmable logic devices are configured after semiconductor manufacturing operations have been completed, such as by programming the programmable element 50 using electrical programming or laser programming. In general, the programmable element 50 may be based on any suitable programmable technology, such as fuses, antifuses, electrically programmable read-only memory technology, random access memory cells, mask programming elements, etc.

[0023] Many programmable logic devices are electrically programmed. Using an electrically programmed arrangement, the programmable element 50 can be formed by one or more memory cells. For example, during programming, configuration data is loaded into the memory cell using input / output pins 44 and input / output circuitry 42. In one embodiment, the memory cell can be implemented as a random access memory (RAM) cell. The use of the memory cell based on RAM technology described herein is intended to be only an example. In addition, since these RAM cells are loaded with configuration data during programming, they are sometimes referred to as configuration RAM cells (CRAM). These memory cells can each provide a corresponding static control output signal, which controls the state of the associated logic components in the programmable logic 48. In some embodiments, the output signal can be applied to the gate of the metal oxide semiconductor (MOS) transistor in the programmable logic 48.

[0024] Integrated circuit device 12 may include any programmable logic device, such as a field programmable gate array (FPGA) 70, such as Figure 3 As shown. For this example, FPGA 70 is referred to as an FPGA, but it should be understood that the device can be any suitable type of programmable logic device (e.g., an application-specific integrated circuit and / or an application-specific standard product). In one example, FPGA 70 is a sectorized FPGA of the type described in U.S. Patent Publication No. 2016 / 0049941, "Programmable Circuit Having Multiple Sectors", which is incorporated herein by reference in its entirety for all purposes. FPGA 70 can be formed on a single plane. Additionally or alternatively, FPGA 70 can be a three-dimensional FPGA having a base die and a structural die of the type described in U.S. Patent No. 10,833,679, "Multi-Purpose Interface for Configuration Data and Designer Fabric Data", which is incorporated herein by reference in its entirety for all purposes.

[0025] exist Figure 3 In the example of , FPGA 70 may include a transceiver 72, which may include and / or use input / output circuitry (e.g., Figure 270) and for driving signals out of the FPGA 70 and for receiving signals from other devices. Interconnect resources 46 may be used to route signals (e.g., clock or data signals) through the FPGA 70. The FPGA 70 is sectorized, meaning that programmable logic resources may be distributed through a plurality of discrete programmable logic sectors 74. The programmable logic sectors 74 may include a plurality of programmable elements 50 having operations defined by configuration memory 76 (e.g., CRAM). A power supply 78 may provide a voltage (e.g., supply voltage) source and a current source to a power distribution network (PDN) 80 that distributes power to the various components of the FPGA 70. Operating the circuitry of the FPGA 70 may result in power being drawn from the power distribution network 80.

[0026] Any suitable number of programmable logic sectors 74 may be present on FPGA 70. In fact, although 29 programmable logic sectors 74 are shown here, it should be appreciated that more or fewer programmable logic sectors may be present in actual implementations (e.g., in some cases, approximately 50, 100, 500, 1000, 5000, 10,000, 50,000, or 100,000 sectors or more). Programmable logic sectors 74 may include a sector controller (SC) 82 that controls the operation of programmable logic sectors 74. Sector controller 82 may communicate with device controller (DC) 84.

[0027] The sector controller 82 may accept commands and data from the device controller 84 and may read data from and write data to its configuration memory 76 based on control signals from the device controller 84. In addition to these operations, the sector controller 82 may be enhanced with many additional functions. For example, these functions may include local sequencing of reads and writes to implement error detection and correction on the configuration memory 76 and sequencing of test control signals to implement various test modes.

[0028] The sector controller 82 and the device controller 84 can be implemented as state machines and / or processors. For example, the operation of the sector controller 82 or the device controller 84 can be implemented as a separate routine in a memory containing a control program. The control program memory can be fixed in a read-only memory (ROM), or can be stored in a writable memory, such as a random access memory (RAM). The size of the ROM can be larger than the size used to store only one copy of each routine. This can allow the routine to have multiple variations, depending on the "mode" that the local controller may be placed in. When the control program memory is implemented as RAM, new routines can be written to the RAM to implement new operations and functions into the programmable logic sector 74. This can provide available scalability in an efficient and easy-to-understand manner. This can be useful because new commands can bring a lot of local activity within the sector, at the expense of only a small amount of communication between the device controller 84 and the sector controller 82.

[0029] Thus, the sector controller 82 may communicate with the device controller 84, which may coordinate the operation of the sector controller 82 and communicate commands initiated from outside the FPGA 70. To support such communications, the interconnection resource 46 may serve as a network between the device controller 84 and the sector controller 82. The interconnection resource 46 may support various signals between the device controller 84 and the sector controller 82. In one example, these signals may be sent as communication packets.

[0030] The use of configuration memory 76 based on RAM technology described herein is intended to be only one example. In addition, configuration memory 76 can be distributed (e.g., as RAM cells) throughout the various programmable logic sectors 74 of FPGA 70. Configuration memory 76 can provide corresponding static control output signals that control the state of the associated programmable element 50 or programmable component of interconnect resources 46. The output signal of configuration memory 76 can be applied to the gate of a metal oxide semiconductor (MOS) transistor that controls the state of the programmable element 50 or programmable component of interconnect resources 46.

[0031] The programmable element 50 of FPGA 40 may also include some signal metal (e.g., communication lines) to transmit signals. In an embodiment, the programmable logic sector 74 may be provided in the form of a vertical wiring channel (e.g., an interconnect formed along the y-axis of FPGA 70) and a horizontal wiring channel (e.g., an interconnect formed along the x-axis of FPGA 70), and each wiring channel may include at least one track to route at least one communication line. If desired, the communication line may be shorter than the entire length of the wiring channel. That is, the communication line may be shorter than the first die area or the second die area. A line of length L may span L wiring channels. Therefore, the length of the four lines in the horizontal wiring channel may be referred to as the "H4" line, and the length of the four lines in the vertical wiring channel may be referred to as the "V4" line.

[0032] As described above, some embodiments of the programmable logic structure can be configured using indirect configuration techniques. For example, an external host device can transmit configuration data packets to the configuration management hardware of FPGA 70. The data packets can be transmitted internally using data paths and specific firmware, which are usually customized for transmitting configuration data packets and can be based on a specific host device driver (e.g., for compatibility). Customization can also be associated with a specific device tape-out, which usually results in high cost of the specific tape-out and / or reduced scalability of FPGA 70.

[0033] Figure 4 It is a block diagram of a programmable structure of an integrated circuit device 12 that implements a design using a macro 100 (e.g., a precompiled macro). As described herein, a designer can use design software 14 to implement a high-level design to implement one or more functions on an integrated circuit device 12. Design software 14 may include a tool that converts a high-level design into a low-level description. For example, the tool (e.g., compiler 16, low-level virtual machine (LLVM)) can receive a high-level design in a high-level programming language and decompose the design into a low-level design, such as LLVM intermediate representation (IR), Verilog to wiring (VTR) netlist, compiler data flow graph, control flow graph, etc. The low-level design may include primitive operators, standard data types and / or widths, memory access modes, etc. The tool may map the low-level design to one or more macros 100 stored in a library. The macro 100 may be instantiated by the designer or inferred by the tool. For example, the macro 100 may be extracted from the low-level design as a subnet list. In another example, the tool may be used by a designer to create a design. The designer may select macros 100 from the library and determine the placement and routing between each of the macros 100 within the design software 14 to create a design. The tool may then use the selected macros 100 to implement the design.

[0034] A macro 100 (e.g., a meta-atom) may include a grouping of logic cells (e.g., that may be technology mapped, placed (e.g., relative to other elements in the macro), and internally wired. For example, a macro 100 may include functional blocks, such as LABs 102, RAM blocks, DSP blocks, M20k columns, etc. The macro 100 may also include wiring between each functional block to provide functionality, operations, and / or constant values. For communication between macros 100, each macro 100 may include input / output connections that may be communicatively coupled by overlapping input connections of one macro 100 with output connections of an adjacently placed macro 100 or by connecting two macros 100 to a wiring resource (e.g., an on-chip network, a trace, a data bus, etc.).

[0035] As shown, macro 100 can include three LABs 102 and macro intra-wiring resources 104. LAB 102 can include smaller programmable areas (e.g., logic cells, configurable logic blocks, or adaptive logic modules). By grouping multiple LABs 102 (e.g., clustering) into a macro 100, macro 100 can represent coarse-grained operations compared with single LAB 102. That is, LAB 102 can be a more fine-grained operation compared with corresponding macro 100. Therefore, macro can be aligned with coarse-grained grids. As used herein, coarse-grained represents that granularity is lower than the lowest granularity possible in the structure. For example, a coarse-grained area can correspond to macro 100, align with a grid, and can include multiple items in the following two or more items: LAB 102, RAM block, DSP block, M20k block, and other components of integrated circuit device 12. As shown, macro 100 can be a rectangular bounding box as a whole, wherein three LABs 102A, 102B, and 102C are coupled by macro intra-wiring resources 104 communication. However, macro 100 can be any suitable shape or size. For example, the shape of macro 100 can be square, circular, oval, hexagonal, rectangular, etc. In another example, macro 100 can include any suitable number of LABs 102, such as two or more LABs, five or more LABs, ten or more LABs, twenty or more LABs, one hundred or more LABs, etc. Macro 100 can be precompiled with LAB 102 before the designer implements the design and stored in the library. For example, macro 100 can be precompiled and stored in the library before the integrated circuit device 12 is compiled. In some embodiments, the designer can use a tool to download the library from the integrated circuit device 12 and / or the library can be integrated into the tool.

[0036] The macros 100 can be timed closed before compiling the integrated circuit device 12. For example, each macro 100 can include a maximum frequency (Fmax) and a timing that can be received from a register of the integrated circuit device. Therefore, when a tool performs timing analysis on a design (e.g., a complete design), the macros 100 can be viewed as a black box with one or more timing delays. For example, the timing analysis can be performed between each of the macros 100 and / or based on the bit-level logic corresponding to the macros 100. In this way, since each of the macros 100 is viewed as a black box, the timing analysis can be improved (e.g., the timing analysis can be accelerated).

[0037] The macros 100 may provide functionality and / or implement complex circuits or subsystems on the integrated circuit device 12. For example, the first macro 100A and the second macro 100B may correspond to a load operation, the third macro 100C may correspond to a complex operation, and the fourth macro 100D may correspond to a storage operation and be placed in the corresponding area 106. For example, the macro 100 may represent a 32-bit addition. In another example, the macro 100 may represent an inverse tangent operation.

[0038] To implement the design, the tool may perform placement and routing operations using one or more macros 100. The macros 100 may be placed (e.g., loaded) into one or more corresponding regions 106 of the integrated circuit device 12. For example, the programmable structure of the integrated circuit device 12 may include a coarse macro grid (e.g., an array) having a plurality of regions 106. The grid may include a repeating pattern of sectors 74, groups of sectors 74, and / or portions of sectors 74, or any other grouping. The sizing and / or positioning of the grid may affect the QoR variability. For example, a coarser grid having larger regions 106 may use less compile time than a finer grid having smaller regions 106 because the larger regions 106 may accommodate more macros 100 than the smaller regions 106. The larger region 106 may include more than two sectors, two or more partitions, etc., while the smaller region 106 may include a portion of a sector, one or more sectors, a portion of a partition, one or more partitions, etc. Additionally or alternatively, the coarser grid may include higher QoR variability due to the larger regions 106 than the smaller regions 106. By way of example, the grid may be configured with repeated LABs, DSP blocks, M20K columns, left reflections, right reflections, etc. The regions 106 may be configured individually, such as during a partial reconfiguration of the integrated circuit device 12, or collectively, such as during a reconfiguration of the integrated circuit device 12, via a bitstream having data indicative of a macro 100, a portion of a macro 100, and / or one or more macros 100.

[0039] As shown, the integrated circuit device 12 may include an array of regions 106. In the example shown, the regions 106 are uniform in shape and size. The regions 106 may be of any suitable shape (e.g., oval, rectangular, hexagonal) or size (e.g., different sizes). For example, the shape and / or size of the regions 106 may be determined based on resource allocation within the programmable structure. The regions 106 may be communicatively coupled via a boundary interface, a global network with switches, communication lines, traces / metal interconnect layers, etc.

[0040] The macros 100 may be placed into corresponding regions 106 of the integrated circuit device 12 based on the design. Additionally or alternatively, the macros 100 may be placed based on resource allocation within the corresponding regions 106. For example, if the amount of resources consumed by the macro 100 is greater than the amount of resources within one region 106, the macro 100 may be placed into two regions 106. In another example, if the amount of resources consumed by multiple macros 100 is less than the amount of resources within the region 106, multiple macros 100 may be placed into one region, thereby improving the layout and routing efficiency and / or operation of the integrated circuit device 12. For example, the first macro 100A and the second macro 100B may be placed in one region 106, the third macro 100C may be placed in six regions 106, and the fourth macro 100D may be placed in one region 106. That is, the macros 100 may be placed in corresponding regions 106, one or more corresponding regions 106, a portion of a region 106, and the like. In this manner, the placement of one or more macros 100 in region 106 may be restricted within region 106 , but may also be flexible.

[0041] After being placed in the corresponding area 106, the tool can couple the macro 100 communicatively via the macro-inter-wiring resource 108 to realize the design. The macro-inter-wiring resource 108 can include connecting wires, traces, programmable elements 50 (e.g., gates, triggers), etc. The macro-inter-wiring resource 108 can be the same or different from the macro-inter-wiring resource 104. The macro-inter-wiring can use a bit-level incremental wiring device, one or more pre-compiled bus wiring, and / or macro input / output (I / O) connections. The bit-level incremental wiring device can iteratively modify or refine the existing wiring between two or more macros 100 to improve the quality of data transmission, such as by reducing the total line length, optimizing timing, and / or minimizing congestion. The bit-level incremental wiring device can consider the bit-level connection between each of the macros 100, and iteratively improve the wiring to improve the operating efficiency of the integrated circuit device 12. Additionally or alternatively, the bit-level incremental wiring device can consider the macro-inter-wiring 104 to conceptualize the operating efficiency. Precompiled bus resources can include shared communication paths (e.g., physical channels, virtual channels) for providing data and / or signal transmission between macros 100. For example, bus resources can be traces connected from the output output of macro 100 to the input connections of different macros 100. Precompiled bus resources can be precompiled and stored in the library for use by designers. Additionally or alternatively, the input / output connections of two or more macros 100 can overlap or be adjacent to the overlapping boundary connections based on the layout of macro 100 on integrated circuit device 12. Since the wiring between macros 100 is connected by construction, the bit level incremental wiring device may not perform wiring functions. In this way, the efficiency of layout and wiring operations can be improved.

[0042] To improve implementation and increase flexibility in placement locations, the integrated circuit device 12 may include a network on chip (NOC) 110. The NOC 110 may be a hardened structure with a known location on the integrated circuit device 12. Placing the macro 100 adjacent to the NOC 110 may improve data consumption and / or production logic placement. For example, the macro 100 may use the NOC 110 to send data to and receive data from a memory, thereby improving operational efficiency. As shown, the memory access units (e.g., the first macro 100A, the second macro 100B, the fourth macro 100D) may be placed in an area 106 adjacent to or coupled to the NOC 110.

[0043] Additionally or alternatively, multiple designs may be placed and routed between regions 106 using macros 100. That is, multiple designs may be implemented on the integrated circuit device 12 based on the size of the regions 106 and / or their source utilization type (e.g., LAB, DSP). For example, the tool may place and route a first design using macros 100 in a first portion of the integrated circuit device 12, and place and route a second design using macros 100 in a second portion of the integrated circuit device 12. In an embodiment, the first portion and the second portion may overlap, which may improve implementation efficiency. In other embodiments, the first portion and the second portion may not overlap based on optimization parameters of the first design and / or the second design.

[0044] Figure 5 1 is a flowchart of an example method 140 for generating one or more macros 100 for a library and configuring an integrated circuit device 12 using the one or more macros 100. For example, a library may include one or more precompiled macros 100 having common functions, operations, and / or constant values ​​accessible to a designer. For example, the precompiled macros 100 may be downloaded from a cloud repository for use by a design software 14, bundled in the design software 14, bundled in an installation package and / or an update package, stored on an integrated circuit device 12, stored in a memory (e.g., flash memory or CD-ROM), stored in a memory communicatively coupled to the integrated circuit device, etc. Therefore, the design software 14 may use one or more macros 100 when implementing a design. A designer may use the design software 14 and / or a tool to create a design using the precompiled macros 100, and the tool may place and route the macros 100 onto the integrated circuit device 12 to implement the design. Since the macros 100 may be precompiled, the compilation time experienced by the designer may be reduced relative to compiling the entire design from scratch. Additionally, the integrated circuit device 12 may include an array of regions 106, which may reduce the number of layout options for the macro 100. In this manner, the variability in QoR may be reduced due to the reduced differences in different layouts in different embodiments.

[0045] At block 142, a plurality of macros 100 are generated for the library. The library may include macros 100 generated by, for, and / or using the design software 14. For example, the library may include a plurality of macros 100, each macro being used to implement operations, constant values, operators, functions, etc. on the integrated circuit device 12. The macros 100 may be generated by a manufacturer, a designer, other users (e.g., a designer), a third party, and / or any other suitable source. Additionally or alternatively, the macros 100 may be updated by the manufacturer and / or other users and sent to the design software 14 to update the library. For example, the manufacturer may redesign one or more macros 100 to improve the efficiency of the implementation or increase the flexibility of additional options, and send an indication of the redesigned macros 100 to the library for storage. In another example, the macros 100 may include one or more designer-specific functions. The designer may load one or more customized macros 100 into the library before implementing the design. In yet another example, the designer can load the design into the design software 14, and during the decomposition of the design, the tool can identify the portion of the design that is not mapped to the macro 100 and compile a customized macro based on the portion of the design. The tool can store the customized macro in a library for use in subsequent designs. In this way, the tool can infer the macro from the designer input. Additionally or alternatively, the tool can access an entry in a storage device that details the macro 100.

[0046] The library may also include one or more inter-macro routing resources 108. For example, the library may include pre-compiled bus routing generated using fixed and / or custom properties of macro input / output connections. The bus routing may be instantiated by the designer, tool, or may be generated by the manufacturer.

[0047] At block 144 , a design for the integrated circuit device 12 is received. For example, the design software 14 may receive the design to implement onto the integrated circuit device 12 .

[0048] At block 146, one or more macros 100 are matched to the design. The design may be bound to a data flow graph including one or more graph nodes that may be mapped to one or more macros 100 stored in a library. For example, each of the graph nodes may be mapped to a corresponding macro 100 corresponding to a memory access unit. Additionally or alternatively, one or more graph nodes may be mapped to a macro 100 corresponding to a complex operation and / or function that may be divided into one or more smaller operations, each of which may be mapped to a separate macro 100, or may be aggregated into a single macro 100 for common operations. Additionally or alternatively, the design may include portions that may not be mapped to one or more macros 100. This portion of the design may be implemented on an integrated circuit device 12 as a fine-grained portion. To this end, the tool may generate a bitstream indicating the portion of the design. The tool may compile the bitstream and the one or more macros 100 to generate a compiled design.

[0049] At block 148, the compiled design is sent to the integrated circuit device 12 for implementation. For example, the tool may send a bitstream indicating the design to the integrated circuit device 12 for implementation into one or more regions 108. The tool may perform placement and routing operations to implement the design on the integrated circuit device 12. For example, the tool may place the macro 100 into one region 106, a portion of a region 106, or one or more regions 106, and the tool may determine the routing between one or more macros 100. As described herein, the macro 100 may be pre-compiled. Therefore, the compilation time (including the placement and routing macro 100) that the user may experience may be reduced compared to the implementation of fine-grained operations compiled during user compilation time. Additionally or alternatively, the macro 100 may be loaded into the region 106 via a bitstream and used to partially reconfigure the integrated circuit device 12. This partial reconfiguration may be used to execute different targets in the same region 106 in a sequential manner before and after the partial reconfiguration.

[0050] Method 140 includes various steps represented by boxes. Although the flowchart shows these steps in a specific order, it should be understood that these steps can be performed in any suitable order, and specific steps can be performed simultaneously under appropriate circumstances. In addition, specific steps or parts of method 140 can be performed by separate systems or devices.

[0051] Figure 61 is a flow chart of an example method 170 for configuring an integrated circuit device 12 using one or more macros 100. In certain instances, portions of a design may not map to one or more macros 100 stored in a library. For example, if a design includes many bit-level operations, a portion of the design may not map to a macro 100 stored in a library. Portions of a design may be dynamically clustered into roughly macro-sized blocks and implemented on a programmable fabric. During compilation, blocks may be generated as custom macros 100 and stored for subsequent design use.

[0052] At block 172, a design is received. For example, a designer may create a design using the design software 14 and / or load the design into the design software 14.

[0053] At block 174, a determination is made whether the design uses one or more macros 100. As previously described, the tool may decompose the design into coarse-grained operations (e.g., primitives). The tool may determine whether the design can be implemented using only macros by attempting to map the operations to one or more macros 100 stored in the library.

[0054] If the design can be implemented using one or more macros 100, the compiled design is sent to the integrated circuit device 12 for implementation at block 176. For example, the tool may perform place and route operations to determine the location of each of the macros 100 on the integrated circuit device 12 and / or the routing between each of the macros 100. Additionally or alternatively, the tool may send a bitstream (e.g., a configuration bitstream) with pre-compiled macros 100 to a region 106, a portion of a region 106, or one or more regions 106 for placement.

[0055] If the design cannot be implemented using one of the macros 100, at block 178, a custom macro 100 may be generated. The tool may cluster portions of the design into one or more macro-sized blocks, and compile one or more macro-sized blocks during compilation to generate a custom macro 100. For example, the tool may perform placement and routing operations to determine the placement and / or routing of the custom macro 100 and one or more precompiled macros 100 to implement the design. The tool may send a bitstream indicating the custom macro 100 and / or the precompiled macro 100 to the integrated circuit device 12. That is, the tool may use the macro 100 to implement a portion of the design, and use the custom macro 100 to implement the remainder of the design. The custom macro 100 may be compiled during user compilation time. However, once the compilation is complete, if the custom macro 100 is saved to a library for future use, the compilation does not need to be performed again. Since at least one precompiled macro 100 may be used, the compilation time experienced by the designer may be reduced relative to compiling the entire design from scratch. Additionally or alternatively, a combination of macros 100 and fine-grained operations corresponding to portions of the design may be used to compile the design. Although fine-grained operations may be used without using macros 100, compile time may be reduced because one or more pre-compiled macros 100 may be implemented without compilation during user compile time.

[0056] At block 180, the design is compiled using the custom macro 100. The tool may compile the design using one or more pre-compiled macros 100 and one or more macro-sized blocks corresponding to the custom macro 100. That is, the tool may implement the design as a mix of coarse-grained and fine-grained operations, thereby reducing the compilation time experienced by the designer.

[0057] Returning to the custom macro 100, the size of the custom macro 100 can be determined based on user input, design, or a combination thereof. For example, the designer can determine the number of functions to be clustered into the custom macro 100, the number of LABs 102, the size of the portion of the design, etc. Additionally or alternatively, the designer can enter one or more cut lines in the portion of the design, and the tool can cluster and compile the custom macro 100 based on the cut lines. In another example, the tool can provide a suggested custom macro 100 size and / or portion of the design to cluster into the custom macro 100. Additionally or alternatively, the tool can dynamically generate a custom macro 100 based on a portion of the design that is not mapped to a pre-compiled macro 100. For example, the tool can determine the shape and / or size of the custom macro 100 based on the number of LABS 102, the size and / or shape of the unoccupied area 106 within the integrated circuit device 12, the function, etc. Additionally or alternatively, the tool can iteratively determine the shape and / or size of the custom macro 100 to improve the placement and routing operations. The size of the custom macro 100 can affect compile time and QoR. For example, a larger custom macro 100 with more LABs 102 can reduce compile time but also reduce QoR compared to a smaller custom macro 100 with fewer LABs 102.

[0058] Method 170 includes various steps represented by boxes. Although the flowchart shows these steps in a specific order, it should be understood that these steps can be performed in any suitable order, and specific steps can be performed simultaneously under appropriate circumstances. In addition, specific steps or parts of method 170 can be performed by separate systems or devices.

[0059] Figure 71 is a schematic diagram of recursively performing placement and routing operations for one or more macros 100 on an integrated circuit device 12. The placement and routing operations can be run with a recursive smaller granularity to solve bottleneck problems, such as critical paths or routing congestion between macros. For example, the tool can first place and route one or more macros 100 in one or more regions 106. Then, the tool can decompose the macro 100 into gradually finer granularity and run additional placement and routing operations. For example, the tool can perform a second placement and routing operation between the LABs 102 of each macro 100 to improve the operation of the integrated circuit device 12. In another example, the tool can perform a third placement and routing operation between the programmable elements 50 of the LABs 102. These finer level repairs can solve bottleneck problems by adjusting the layout of finer granularity elements in the macro 100, providing additional routing between finer granularity elements, adjusting the routing in the macro 100, adjusting the routing between the finer granularity elements of the macro 100, etc. That is, the tool may perform additional placement and routing operations based on the placement of components defined by macro 100 and / or the placement of components on integrated circuit device 12. In certain embodiments, the additional placement and routing operations may be performed in response to input from a designer. For example, the designer may indicate bit level and / or plane compilation for the additional placement and routing operations.

[0060] Considering the foregoing, Figure 7 The first routing resource 202A and the first routing resource 202B (eg, Figure 4 The first placement and routing operation 200 is indicated by the macro-inter-macro routing resource 108 and the second routing resource 206A and the second routing resource 206B (eg, with respect to Figure 410. The tool may include a first layout and routing operation 204 (intra-macro routing resources 104 described in the drawings). During the first layout and routing operation 200, the tool may communicatively couple the first macro 100A with the second macro 100B via the first routing resource 202A, and communicatively couple the third macro 100C with the fourth macro 100D via the first routing resource 202B. The granularity of the second layout and routing operation 204 may be finer than the first layout and routing operation 200. For example, during the second layout and routing operation 204, the LAB 102 of the first macro 100A may be coupled to the LAB 102 of the second macro 100B via the second routing resource 206A, and the LAB 102 of the third macro 100C may be coupled to an additional LAB 102 of the second macro 100B. The second routing resource 206A and the second routing resource 206B may provide additional paths for communication between macros 100, thereby reducing bottlenecks. The second wiring resource 206A and the second wiring resource 206B can be coupled to the I / O connection of LAB 102, and its granularity can be finer than the first wiring resource 202A and the first wiring resource 202B. For example, compared with the first wiring resource 202A and the first wiring resource 202B, the second wiring resource 206A and the second wiring resource 206B can be finer granularity. In this way, the tool can improve the layout and wiring between each of the macros 100 of different bit levels. In an embodiment, the first wiring resource 202A and the first wiring resource 202B can be the same as the second wiring resource 206A and the second wiring resource 206B. In other embodiments, the first wiring resource 202A and the first wiring resource 202B can be different from the second wiring resource 206A and the second wiring resource 206B. Additionally or alternatively, some of the first wiring resource 202A and the first wiring resource 202B can be the same as the second wiring resource 206A and the second wiring resource 206B, and some can be different.

[0061] Figure 8It is a schematic diagram for adjusting one or more macros 100 to implement a design on a programmable structure of an integrated circuit device 12. As described herein, using macros 100 can reduce compilation time because the fine-grained logic within the macros 100 is compiled before the integrated circuit device is compiled. In this way, device compilation can be used to make decisions on coarse-grained logic (e.g., region 106, coarse-grained macros 100, etc.). However, using different functions (e.g., addition, subtraction, multiplication, and division) in a design can involve using many different macros, which can increase the size of the library. In an embodiment, a library may include a set of basic macros 100 corresponding to a specific function. The macros 100 can be adjusted (e.g., mutated, reprogrammed, reconfigured) to provide additional functions. That is, by operating the macros 100 during compilation, the number of macros 100 stored in the library can be reduced. During compilation, the macros 100 can be dynamically set using a lookup table (LUT) mask to assign constant values, apply inversion, apply switching inputs, etc.

[0062] The LUT mask may include a LUT configuration, such as a set of bits that can be adjusted to adjust the functionality of the corresponding macro 100. For example, a macro 100 that provides a greater than or equal to operation may be adjusted to an equal to operation by adjusting the LUT configuration of the macro 100. That is, the macro 100 may be compiled to switch between operations by changing only a few bits in the logic. Additionally or alternatively, a macro 100 that provides a division operation may be adjusted to a multiplication operation by adjusting the LUT configuration of the macro 100. With coarse-grained operations, LUT mask adjustments may be performed very quickly with little or no impact on the designer's compile time.

[0063] As shown, a first implementation of macro 100A includes a first LUT mask 220 having a LUT configuration of "110100", and a second implementation of macro 100B includes a second LUT mask 222 having a LUT configuration of "010010". By way of example, the first LUT mask 220 can set the first macro 100A to a constant value, and the second LUT mask 222 can set the second macro 100B to a first operation (e.g., multiplication). The first LUT mask 220 and / or the second LUT mask 222 can be adjusted by dynamically setting the values ​​in the LUT, as shown by arrow 224. After setting the second LUT mask 222 of the second macro 100B, the LUT configuration can be adjusted to "010110", which can correspond to a second operation (e.g., division) that may be different from the first operation. Additionally or alternatively, the first LUT mask 220 can be adjusted to set the first macro 100A to a constant value that may be different from the original constant value. In this way, the LUT mask 220 and the LUT mask 222 may be dynamically adjusted to change the functionality of the first macro 100A and / or the second macro 100B. Thus, a library may include a set of basic macros 100 that may be adjusted, which may reduce the size of the library.

[0064] Fig. 9 1 is a flow chart of an example method 250 for adjusting one or more macros 100 to implement a design on an integrated circuit device 12. For example, placement and routing operations may be recursively performed at a finer granularity to reduce bottlenecks. Additionally or alternatively, the functionality (e.g., operation) of the macro 100 may be adjusted by adjusting a LUT mask. In this manner, one or more macros 100 may be used to implement a design.

[0065] At block 252, a design for an integrated circuit device 12 using one or more macros 100 is received, similar to the design described with respect to FIG. Figure 5 Described block 144. The tool may decompose the design into one or more coarse-grained operations and map these operations to macros 100 stored in the library. The tool may perform placement and routing operations using one or more macros 100 based on the design.

[0066] At block 254, the macro 100 in one or more macros 100 may be adjusted based on the design. For example, the design may change based on designer input, and the change may be achieved by adjusting one or more bits within the macro 100. In another example, a portion of the design may include an operation parameter that may correspond to an inverse operation of the macro 100. Thus, the tool may set a LUT mask to adjust the functionality of the macro 100 based on the design. The tool may dynamically set the LUT mask during compilation of the design.

[0067] At block 256, the routing between one or more macros 100 may be adjusted. The tool may perform additional placement and routing operations at different granularities to reduce bottlenecks. For example, the tool may perform additional placement and routing operations to communicatively couple one or more LABs 102 between macros 100. In another example, the tool may perform additional placement and routing operations to communicatively couple programmable elements 50 and / or logic blocks 26 within a LAB 102. Additional placement and routing operations may be performed during compilation of the design.

[0068] At block 258, the compiled design may be sent to the integrated circuit device 12 for implementation, similar to the implementation described with respect to Figure 6 Description of box 176 and about Figure 5 Box 148 of the description.

[0069] Method 250 includes various steps represented by boxes. Although the flowchart shows these steps in a particular order, it should be understood that these steps can be performed in any suitable order, and certain steps can be performed simultaneously where appropriate. For example, the tool can first receive the design (box 252), adjust the wiring between one or more macros (box 256), and then adjust the macros in one or more macros (box 254). In another example, the tool can first receive the design (box 252), adjust the macros in one or more macros (box 254), and then adjust the wiring between one or more macros (box 256). In addition, certain steps or portions of method 250 can be performed by separate systems or devices.

[0070] In view of the foregoing, the integrated circuit device 12 may be a data processing system (e.g., Fig.10 Components included in the data processing system 300 shown in FIG. 300 may include the integrated circuit device 12 (e.g., a programmable logic device), a host processor 304 (e.g., a processor), a memory and / or storage circuit system 306, and a network interface 308. The data processing system 300 may include more or fewer components (e.g., an electronic display, a designer interface structure, an ASIC). In addition, Fig.10Any circuit components depicted in the diagram may include an integrated circuit (e.g., integrated circuit device 12). Host processor 304 may include any of the aforementioned processors, which may manage data processing requests for data processing system 300 (e.g., perform encryption, decryption, machine learning, video processing, speech recognition, image recognition, data compression, database search ranking, bioinformatics, network security pattern recognition, spatial navigation, cryptocurrency operations, etc.). Memory and / or storage circuit system 306 may include random access memory (RAM), read-only memory (ROM), one or more hard disk drives, flash memory, etc. Memory and / or storage circuit system 306 may store data to be processed by data processing system 300. In some cases, memory and / or storage circuit system 306 may also store a configuration program (bitstream) for programming integrated circuit device 12. Network interface 308 may allow data processing system 300 to communicate with other electronic devices. Data processing system 300 may include several different packages, or may be contained within a single package on a single package substrate. For example, components of data processing system 300 may be located on several different packages at one location (e.g., a data center) or at multiple locations. For example, components of data processing system 300 may be located in separate geographic locations or regions, such as cities, states, or countries.

[0071] In one example, data processing system 300 may be part of a data center that processes a variety of different requests. For example, data processing system 300 may receive data processing requests via network interface 308 to perform encryption, decryption, machine learning, video processing, speech recognition, image recognition, data compression, database search ranking, bioinformatics, network security pattern recognition, spatial navigation, digital signal processing, or some other specialized task.

[0072] The above discussion is provided by way of example. In fact, the embodiments of the present disclosure may be susceptible to various modifications and alternative forms. In fact, many other suitable forms of high-capacity integrated circuits can be manufactured according to the above-mentioned technology. For example, other high-capacity integrated circuit devices may include one or more regions 106 that may be configured with one or more macros 100. The macros 100 that can be precompiled are to reduce the compilation time experienced by the designer. In this way, less time can be used to reconfigure and / or configure the high-capacity integrated circuit. In addition, the high-capacity integrated circuit device may include an on-chip network for data transmission, thereby improving the implementation efficiency of the design.

[0073] Although the embodiments set forth in the present disclosure may be susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the accompanying drawings and have been described in detail herein. However, it should be understood that the present disclosure is not intended to be limited to the particular forms disclosed. The present disclosure is intended to cover all modifications, equivalents, and alternatives that fall within the spirit and scope of the present disclosure defined by the appended claims.

[0074] The techniques presented and claimed herein are cited and applied to material objects and specific examples of a practical nature that significantly improve the art, and therefore, they are not abstract, intangible, or purely theoretical. In addition, if any claim attached at the end of this specification contains one or more elements designated as "a unit for [performing] [a function] ..." or "a step for [performing] [a function] ...", it is intended that these elements be interpreted in accordance with 35 U.S.C. 112(f). However, for any claim containing elements designated in any other manner, it is intended that these elements not be interpreted in accordance with 35 U.S.C. 112(f).

[0075] Example Embodiments

[0076] Example embodiments 1. A tangible, non-transitory, computer-readable medium having instructions stored thereon, wherein the instructions, when executed, cause a processor to perform the following operations: receive a design to be implemented on a programmable structure of an integrated circuit device; determine that the design can be implemented using one or more macros from a library comprising a plurality of macros, wherein each of the plurality of macros comprises a pre-compiled logic unit; and compile the design by placing and routing the one or more macros aligned to a coarse-grained grid on the programmable structure.

[0077] Example embodiment 2. A tangible, non-transitory, computer-readable medium according to example embodiment 1, wherein the instructions, when executed, cause a processor to: determine that a portion of a design cannot be implemented using one or more macros; and generate a custom macro based on the portion of the design.

[0078] Example embodiment 3. The tangible, non-transitory, computer-readable medium of example embodiment 2, wherein the instructions, when executed, cause the processor to generate a custom macro by determining a size or shape of the custom macro based on user input.

[0079] Example embodiment 4. A tangible, non-transitory, computer-readable medium according to example embodiment 1, wherein the instructions, when executed, cause a processor to determine routing between one or more macros using a bit-level incremental router, pre-compiled bus routing stored in a library, connections of one or more macros, or any combination thereof.

[0080] Example embodiment 5. The tangible, non-transitory, computer-readable medium of example embodiment 1, wherein the instructions, when executed, cause a processor to set a function of a corresponding macro by setting a lookup table mask of a corresponding macro of one or more macros based on a design.

[0081] Example embodiment 6. The tangible, non-transitory, computer-readable medium of example embodiment 1, wherein the instructions, when executed, cause a processor to compile a design by routing between components of a first macro of the one or more macros and components of a second macro of the one or more macros.

[0082] Example embodiment 7. A tangible, non-transitory, computer-readable medium according to example embodiment 1, wherein the instructions, when executed, cause the processor to compile the design in the following manner: placing a first macro of one or more macros into a proximate network-on-chip (NOC); and placing a second macro of the one or more macros into a proximate NOC, wherein the first macro and the second macro are communicatively coupled via the NOC.

[0083] Example embodiment 8. A tangible, non-transitory, computer-readable medium according to example embodiment 1, wherein the instructions, when executed, cause the processor to perform the following operations: sending a bitstream to at least partially reconfigure the integrated circuit device using one or more macros, wherein the bitstream includes data for configuring one or more regions of the coarse-grained grid.

[0084] Example embodiment 9. A tangible, non-transitory, computer-readable medium according to example embodiment 8, wherein the instructions, when executed, cause the processor to perform the following operations: layout a macro of one or more macros in a first area of ​​one or more areas; layout the macros in a first group of areas of one or more areas; or cluster a first group of one or more macros in a second area of ​​one or more areas.

[0085] Example embodiment 10. A method may include: receiving, by a processing circuit system, a design to be implemented on a programmable structure of an integrated circuit device; determining, by the processing circuit system, that the design can be implemented using one or more macros from a library including a plurality of macros, wherein each of the plurality of macros includes a pre-compiled logic unit; and compiling, by the processing circuit system, the design by placing and routing the one or more macros aligned to a coarse-grained grid on the programmable structure.

[0086] Example Embodiment 11. The method of Example Embodiment 10 may include: communicatively coupling, by the processing circuitry, a first macro and a second macro of the one or more macros by overlapping an input connection of a first macro of the one or more macros with an output connection of a second macro of the one or more macros.

[0087] Example embodiment 12. The method according to example embodiment 10 may include: determining, by the processing circuit system, that a portion of the design cannot be implemented using one or more macros; generating, by the processing circuit system, a custom macro based on the portion of the design; and compiling, by the processing circuit system, the custom macro during design compilation.

[0088] Example Embodiment 13. The method of Example Embodiment 12, wherein generating, by the processing circuitry, the custom macro may include determining a shape and size of the custom macro based on a portion of the design.

[0089] Example Embodiment 14. The method according to Example Embodiment 10 may include: setting, by the processing circuitry, a lookup table mask of a corresponding macro of the one or more macros to assign a constant value, operation, or input.

[0090] Example embodiment 15. The method of example embodiment 10, wherein compiling the design by the processing circuitry may include determining routing between components of a first macro of the one or more macros and components of a second macro of the one or more macros.

[0091] Example embodiment 16. An integrated circuit device may include: a memory including a plurality of macros; and a programmable logic circuit system including a coarse-grained grid, the coarse-grained grid being configurable by one or more of the plurality of macros to implement a design, wherein corresponding macros of the plurality of macros include pre-compiled logic units.

[0092] Example Embodiment 17. The integrated circuit device of Example Embodiment 16, comprising a network on chip (NOC) configurable to communicatively couple a first macro of the one or more macros and a second macro of the one or more macros.

[0093] Example Embodiment 18. The integrated circuit device of Example Embodiment 16, wherein each of the plurality of macros comprises a lookup table mask corresponding to a function of each macro.

[0094] Example Embodiment 19. The integrated circuit device according to Example Embodiment 16 may include a plurality of pre-compiled bus wirings stored in a memory and configured to communicatively couple one or more macros.

[0095] Example embodiment 20. The integrated circuit device according to example embodiment 16 may include: each macro of the plurality of macros includes an input / output connection, wherein an input connection of a first macro of the one or more macros overlaps an output connection of a second macro of the one or more macros to communicatively couple the first macro and the second macro.

Claims

1. A tangible, non-transitory, computer-readable medium having instructions stored thereon, wherein: When the instructions are executed, the processor performs the following operations: receiving a design to be implemented into a programmable structure of an integrated circuit device; determining that the design can be implemented using one or more macros from a library comprising a plurality of macros, wherein each of the plurality of macros comprises a precompiled logic unit; and The design is compiled by placing and routing one or more macros aligned to the coarse-grained grid on the programmable fabric.

2. The tangible, non-transitory, computer-readable medium of claim 1, wherein: When the instructions are executed, the processor performs the following operations: determining that a portion of the design cannot be implemented using the one or more macros; and A custom macro is generated based on the portion of the design.

3. The tangible, non-transitory, computer-readable medium of claim 2, wherein: When the instructions are executed, the processor generates the custom macro by performing the following operations: The size or shape of the custom macro is determined based on user input.

4. The tangible, non-transitory, computer-readable medium of claim 1, wherein: When the instructions are executed, the processor performs the following operations: Routing between the one or more macros is determined using a bit-level incremental router, pre-compiled bus routing stored in the library, connections of the one or more macros, or any combination thereof.

5. The tangible, non-transitory, computer-readable medium of claim 1, wherein: When the instructions are executed, the processor performs the following operations: The function of a corresponding macro of the one or more macros is set by setting a lookup table mask of the corresponding macro based on the design.

6. The tangible, non-transitory, computer-readable medium of claim 1, wherein: The instructions, when executed, cause the processor to compile the design by performing the following operations: Routing is performed between components of a first macro of the one or more macros and components of a second macro of the one or more macros.

7. The tangible, non-transitory, computer-readable medium of any one of claims 1-5, wherein: When executed, the instructions cause the processor to compile the design by performing the following operations: placing a first macro of the one or more macros into a neighboring network-on-chip (NOC); and A second macro of the one or more macros is placed adjacent to the NOC, wherein the first macro and the second macro are communicatively coupled via the NOC.

8. The tangible, non-transitory, computer-readable medium of any one of claims 1-5, wherein: When the instructions are executed, the processor performs the following operations: A bitstream is sent to at least partially reconfigure the integrated circuit device using the one or more macros, wherein the bitstream includes data for configuring one or more regions of the coarse-grained grid.

9. The tangible, non-transitory, computer-readable medium of claim 8, wherein: When the instructions are executed, the processor performs the following operations: placing a macro of the one or more macros in a first area of ​​the one or more areas; placing the macro in a first set of regions within the one or more regions; or A first group of the one or more macros is clustered in a second area of ​​the one or more areas.

10. A method comprising: receiving, via the processing circuitry, a design to be implemented into a programmable structure of an integrated circuit device; determining, via the processing circuitry, that the design is implementable using one or more macros from a library comprising a plurality of macros, wherein each of the plurality of macros comprises a precompiled logic unit; and The design is compiled via the processing circuitry by placing and routing one or more macros aligned to a coarse-grained grid on the programmable fabric.

11. The method according to claim 10, comprising: The first macro and the second macro are communicatively coupled via the processing circuitry by overlapping input connections of a first macro of the one or more macros with output connections of a second macro of the one or more macros.

12. The method according to claim 10, comprising: determining, via the processing circuitry, that a portion of the design cannot be implemented using the one or more macros; generating, via the processing circuitry, a custom macro based on the portion of the design; as well as The custom macro is compiled via the processing circuitry during compilation of the design.

13. The method according to claim 12, wherein: Generating the custom macro via the processing circuit system includes: A shape and size of the custom macro is determined based on the portion of the design.

14. The method according to any one of claims 10 to 13, comprising: A lookup table mask for a corresponding macro of the one or more macros is set via the processing circuitry to assign a constant value, operation, or input.

15. The method according to any one of claims 10 to 13, wherein: Compiling the design via the processing circuitry includes: Routing between components of a first macro of the one or more macros and components of a second macro of the one or more macros is determined.

16. An integrated circuit device comprising: A memory including a plurality of macros; as well as A programmable logic circuit system includes a coarse-grained grid configurable by one or more of the plurality of macros to implement a design, wherein respective ones of the plurality of macros include pre-compiled logic cells. 17 . The integrated circuit device of claim 16 , comprising a network on chip (NOC) configurable to communicatively couple a first macro of the one or more macros and a second macro of the one or more macros.

18. The integrated circuit device of claim 16, wherein: Each of the plurality of macros includes a lookup table mask corresponding to a function of each macro.

19. The integrated circuit device of any one of claims 16-18, comprising a plurality of pre-compiled bus routings stored in the memory and configured to communicatively couple the one or more macros.

20. The integrated circuit device according to any one of claims 16 to 18, comprising: Each macro of the plurality of macros includes input / output connections, wherein input connections of a first macro of the one or more macros overlap output connections of a second macro of the one or more macros to communicatively couple the first macro and the second macro.

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