Instruction generation method and device, electronic equipment and readable storage medium

Abstract

Embodiments of the invention provide an instruction generation method and apparatus, an electronic device and a readable storage medium. The method comprises the steps of obtaining an instruction generation demand; the instruction generation demand comprises an instruction feature demand and an instruction number; based on feature tags corresponding to a plurality of to-be-matched instructions in a preset instruction set, determining the to-be-matched instructions matched with the instruction feature demand in the preset instruction set to obtain a target instruction set; and randomly generating target instructions matched with the instruction number based on the target instruction set. Therefore, the parameters of the instruction generator do not need to be manually adjusted one by one, so that on the premise of ensuring the randomness of the target instruction, human errors are avoided through a mode of matching the feature requirements with the feature tags, the instruction accuracy is improved, the instruction generation complexity is reduced, and the instruction generation efficiency is improved to a certain extent.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to an instruction generation method, device, electronic device and readable storage medium. Background Art

[0002] With the rapid development of information technology, the performance and reliability of the processor as the core component of the computer system are directly related to the operating efficiency and data security of the entire system. In the design and verification process of the processor, the accuracy and efficiency of the instruction set are one of the key factors. In order to ensure that the processor can execute various instructions accurately, it is particularly important to select instructions with specific characteristics for a large number of tests in the verification process.

[0003] In the related art, the instruction generator is the main tool for generating test instruction streams. However, during the instruction generation process, verification personnel often need to manually adjust the parameters of the instruction generator one by one according to the instruction generation requirements, so as to generate instruction streams that meet the instruction generation requirements one by one. This not only increases the complexity and labor cost of instruction generation, but also easily introduces human errors, resulting in low efficiency of instruction generation and failure to ensure instruction accuracy. Summary of the invention

[0004] In order to overcome the problems existing in the related art, the present invention provides an instruction generation method, device, electronic device and readable storage medium.

[0005] In a first aspect, the present invention provides an instruction generation method, the method comprising: Obtaining instruction generation requirements; the instruction generation requirements include instruction feature requirements and instruction quantity; Based on feature tags corresponding to a plurality of to-be-matched instructions in a preset instruction set, determining in the preset instruction set the to-be-matched instructions that match the instruction feature requirement, and obtaining a target instruction set; Based on the target instruction set, a target instruction matching the instruction quantity is randomly generated.

[0006] Optionally, when the number of the instruction feature requirements is at least two, the instruction generation requirement further includes a conditional probability corresponding to each of the instruction feature requirements; and the randomly generating a target instruction matching the number of instructions based on the target instruction set includes: Based on the conditional probabilities corresponding to the instruction feature requirements, randomly selecting an instruction set from at least two instruction sets corresponding to at least two instruction feature requirements as the target instruction set; the number of the instruction feature requirements is equal to the number of the instruction sets; randomly generating a target instruction from the target instruction set; Re-select an instruction set randomly from at least two instruction sets corresponding to at least two instruction feature requirements based on the conditional probability corresponding to each of the instruction feature requirements, and start executing from the target instruction set step until a target instruction matching the number of instructions is generated.

[0007] Optionally, the method further comprises: Obtaining a preset instruction set; the preset instruction set includes a plurality of instructions to be matched; Based on the instruction features of each of the instructions to be matched, a feature label corresponding to each of the instructions to be matched is determined.

[0008] Optionally, the step of determining, based on feature tags corresponding to a plurality of to-be-matched instructions in a preset instruction set, instructions to be matched that match the instruction feature requirement in the preset instruction set to obtain a target instruction set includes: For any of the to-be-matched instructions in the preset instruction set, matching the feature tag corresponding to the to-be-matched instruction with the instruction feature requirement; When the feature tag corresponding to the instruction to be matched successfully matches the instruction feature requirement, a target instruction set is formed based on the instruction to be matched.

[0009] Optionally, the instruction feature requirement includes a first requirement, a second requirement and a third requirement, the first requirement is used to indicate the generation of an instruction having one or more first features, the second requirement is used to indicate the generation of an instruction having one or more first features but not having one or more second features, and the third requirement is used to indicate the generation of an instruction not having one or more second features.

[0010] In a second aspect, the present invention provides an instruction generation device, the device comprising: A first acquisition module is used to acquire instruction generation requirements; the instruction generation requirements include instruction feature requirements and instruction quantity; A first determination module is used to determine, in the preset instruction set, instructions to be matched that match the instruction feature requirement based on feature tags corresponding to multiple instructions to be matched in the preset instruction set, to obtain a target instruction set; The first generating module is used to randomly generate target instructions matching the instruction quantity based on the target instruction set.

[0011] Optionally, when the number of the instruction feature requirements is at least two, the instruction generation requirement further includes a conditional probability corresponding to each of the instruction feature requirements; and the first generation module includes: A first selection module is used to randomly select an instruction set from at least two instruction sets corresponding to at least two instruction feature requirements as a target instruction set based on the conditional probability corresponding to each of the instruction feature requirements; the number of the instruction feature requirements is equal to the number of the instruction sets; A first generating submodule, used for randomly generating a target instruction from the target instruction set; The first execution module is used to randomly select an instruction set from at least two instruction sets corresponding to at least two instruction feature requirements based on the conditional probability corresponding to each of the instruction feature requirements, and start execution from the target instruction set step until a target instruction matching the number of instructions is generated.

[0012] Optionally, the device further comprises: A second acquisition module is used to acquire a preset instruction set; the preset instruction set includes a plurality of instructions to be matched; The second determination module is used to determine the feature label corresponding to each of the instructions to be matched based on the instruction feature of each of the instructions to be matched.

[0013] Optionally, the first determining module includes: A first matching module, configured to match, for any of the to-be-matched instructions in the preset instruction set, a feature tag corresponding to the to-be-matched instruction with the instruction feature requirement; The first adding module is used to form a target instruction set based on the instruction to be matched when the feature tag corresponding to the instruction to be matched successfully matches the instruction feature requirement.

[0014] Optionally, the instruction feature requirement includes a first requirement, a second requirement and a third requirement, the first requirement is used to indicate the generation of an instruction having one or more first features, the second requirement is used to indicate the generation of an instruction having one or more first features but not having one or more second features, and the third requirement is used to indicate the generation of an instruction not having one or more second features.

[0015] In a third aspect, the present invention provides an electronic device comprising: a processor, a memory, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the instruction generation method described in any one of the first aspects is implemented.

[0016] In a fourth aspect, the present invention provides a readable storage medium, which, when instructions in the storage medium are executed by a processor of an electronic device, enables the electronic device to execute the steps in the instruction generation method in any one of the embodiments of the first aspect above.

[0017] In an embodiment of the present invention, by obtaining instruction generation requirements; the instruction generation requirements include instruction feature requirements and the number of instructions; based on the feature tags corresponding to multiple instructions to be matched in the preset instruction set, the instructions to be matched that match the instruction feature requirements are determined in the preset instruction set to obtain a target instruction set; based on the target instruction set, target instructions that match the number of instructions are randomly generated. In this way, based on the instruction feature requirements, a target instruction set can be matched from the preset instruction set, and a target instruction can be randomly generated based on the target instruction set. The instruction feature requirements can be automatically matched with the instructions to be matched based on the instruction generation requirements, without manually adjusting the parameters of the instruction generator one by one according to the instruction generation requirements to generate instructions. Therefore, under the premise of ensuring the randomness of the target instruction, human errors are avoided by matching the feature requirements with the feature tags, the instruction accuracy is improved, and the complexity of instruction generation is reduced, thereby improving the efficiency of instruction generation to a certain extent. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0019] Figure 1 is a flowchart of a method for generating instructions provided by an embodiment of the present invention; Figure 2 is a schematic diagram of a preset instruction set provided by an embodiment of the present invention; Figure 3 is a schematic diagram of an instruction generation result provided by an embodiment of the present invention; Figure 4 is a structural diagram of an instruction generation device provided by an embodiment of the present invention; Figure 5 It is a structural diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0020] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0021] Figure 1 is a flowchart of a method for generating instructions according to an embodiment of the present invention. Figure 1As shown, the method may include: Step 101, obtaining instruction generation requirements; the instruction generation requirements include instruction feature requirements and instruction quantity.

[0022] In an embodiment of the present invention, the instruction generation requirements of the instruction stream required for the processor verification process are defined in advance according to the verification test requirements of the processor verification. As a programmable component, the processor needs to perform a wide variety of tasks, and the instruction set becomes complex and changeable. In order to ensure that the processor can run stably in various application scenarios, the verification team must conduct extensive tests on different types of instructions. These instructions may involve multiple aspects such as data processing, memory access, control flow transfer, etc., and each instruction has its unique execution characteristics and potential problem points. Therefore, the verification test requirements of processor verification often require the generation of instructions with specific characteristics, for example: the feature type may include the instruction operation type (such as arithmetic operation, logical operation, bit operation, etc.), the data type processed by the instruction (such as integer, floating point, etc.), and the control type of the instruction (such as conditional execution, loop control, interrupt processing, etc.). Instructions with different specific characteristics can correspond to the number of instructions generated required for the instruction feature requirements. The instruction generation requirements can be obtained based on the demand information input by the user to the instruction generator through the interactive interface. Therefore, the instruction generation requirements can include instruction feature requirements and instruction quantity. The instruction feature requirements can be used to describe specific requirements such as instruction operation requirements, instruction processing data requirements, and instruction control requirements. The number of instructions can be used to define the number of random instructions that need to be generated. Specifically, the instruction feature requirements may include a first requirement, a second requirement, and a third requirement, wherein the first requirement is used to indicate the generation of instructions having one or more first features, the second requirement is used to indicate the generation of instructions having one or more first features and not having one or more second features, and the third requirement is used to indicate the generation of instructions not having one or more second features. The first feature and the second feature may be any instruction feature, and the present invention does not limit the specific content of the first feature and the second feature. Exemplarily, the first requirement may be used to indicate the generation of instructions having arithmetic operation features, or, the generation of instructions having both integer operation features and addition operation features. The second requirement may be used to indicate the generation of instructions having integer operation features and arithmetic operation features, but not having addition operation indications.

[0023] Step 102: Based on feature tags corresponding to a plurality of to-be-matched instructions in a preset instruction set, determine the to-be-matched instructions that match the instruction feature requirement in the preset instruction set to obtain a target instruction set.

[0024] In an embodiment of the present invention, a preset instruction set may be determined based on instructions in a preset instruction set architecture that matches a processor verification process, and the preset instruction set includes a plurality of instructions to be matched, each of which is marked with a feature tag. Based on the feature tags corresponding to the instructions to be matched, the instructions to be matched that match the instruction feature requirements are determined in the preset instruction set to obtain a target instruction set. Different instruction feature requirements may correspond to different target instruction sets, that is, for each instruction feature requirement, a target instruction set that meets the instruction feature requirement is determined in the preset instruction set, and the target instruction set includes the instructions to be matched that match the instruction feature requirements in the preset instruction set. The instructions to be matched that match the instruction feature requirements refer to instructions to be matched whose feature tags are the same as the instruction features described in the instruction feature requirements as having or not having.

[0025] Exemplarily, when the instruction feature requirement is the first requirement, the first requirement is used to indicate the generation of an instruction with one or more first features, then it is necessary to determine the to-be-matched instruction whose feature tag is exactly the same as one or more first features in the first requirement as the to-be-matched instruction that matches the instruction feature requirement; when the instruction feature requirement is the second requirement, the second requirement is used to indicate the generation of an instruction with one or more first features and without one or more second features, then it is necessary to determine the to-be-matched instruction whose feature tag is exactly the same as one or more first features in the second requirement and does not contain one or more second features at all as the to-be-matched instruction that matches the instruction feature requirement; when the instruction feature requirement is the third requirement, the third requirement is used to indicate the generation of an instruction without one or more second features, then it is necessary to determine the to-be-matched instruction whose feature tag does not contain one or more second features at all as the to-be-matched instruction that matches the instruction feature requirement.

[0026] Step 103: Based on the target instruction set, randomly generate target instructions that match the instruction quantity.

[0027] In the embodiment of the present invention, based on the target instruction set, a target instruction is randomly selected and generated from the target instruction set. When the number of instructions is greater than or equal to two, a random selection operation is performed from the target instruction set the same number of instructions as the number of instructions, and a target instruction matching the number of instructions is generated.

[0028] In summary, in an embodiment of the present invention, by obtaining instruction generation requirements; the instruction generation requirements include instruction feature requirements and the number of instructions; based on the feature tags corresponding to multiple instructions to be matched in the preset instruction set, the instructions to be matched that match the instruction feature requirements are determined in the preset instruction set to obtain a target instruction set; based on the target instruction set, target instructions that match the number of instructions are randomly generated. In this way, based on the instruction feature requirements, a target instruction set can be matched from the preset instruction set, and a target instruction can be randomly generated based on the target instruction set. The instruction feature requirements can be automatically matched with the instructions to be matched based on the instruction generation requirements, without manually adjusting the parameters of the instruction generator one by one according to the instruction generation requirements to generate instructions. Therefore, under the premise of ensuring the randomness of the target instruction, human errors are avoided by matching the feature requirements with the feature tags, the instruction accuracy is improved, and the complexity of instruction generation is reduced, thereby improving the efficiency of instruction generation to a certain extent.

[0029] Furthermore, in the related art, instruction generation is often based on manually written preset templates or rules, which makes it difficult to flexibly respond to the complex requirements that continue to emerge in CPU design. Through the method of matching feature requirements and feature tags provided in the embodiments of the present invention, it is possible to target complex instruction feature requirements, such as an instruction feature requirement for generating an instruction with one or more first features and not having one or more second features. By matching feature requirements with feature tags, a target instruction that matches the complex instruction feature requirement can be randomly generated, thereby improving the flexibility and comprehensiveness of instruction generation.

[0030] Optionally, when the number of the instruction feature requirements is at least two, the instruction generation requirement also includes a conditional probability corresponding to each of the instruction feature requirements.

[0031] In an embodiment of the present invention, when the number of instruction feature requirements is at least two, the instruction generation requirement may further include the conditional probability corresponding to each instruction feature requirement, wherein the conditional probability is used to characterize the random generation probability for different instruction feature requirements when randomly generating instructions. Exemplarily, the conditional probability corresponding to instruction feature requirement 1 is 40%, and the conditional probability corresponding to instruction feature requirement 2 is 60%, then the probability of the randomly generated target instruction meeting instruction feature requirement 1 is 40%, and the probability of meeting instruction feature requirement 2 is 60%.

[0032] Accordingly, step 103 may include the following steps: Step 201: Based on the conditional probability corresponding to each of the instruction feature requirements, randomly select an instruction set from at least two instruction sets corresponding to at least two instruction feature requirements as a target instruction set; the number of the instruction feature requirements is equal to the number of the instruction sets.

[0033] In an embodiment of the present invention, when the number of instruction feature requirements is at least two, that is, when one instruction generation requirement contains at least two instruction feature requirements, it is characterized that the instruction generation requirement needs to randomly generate instructions based on at least two instruction feature requirements, then each instruction feature requirement will be matched with the feature tags corresponding to multiple instructions to be matched in the preset instruction set, and at least two instruction sets will be obtained. One instruction feature requirement will correspond to one instruction set. Based on the conditional probability corresponding to each instruction feature requirement, an instruction set is randomly selected from at least two instruction sets corresponding to at least two instruction feature requirements as the target instruction set. In other words, the conditional probability corresponding to each instruction feature requirement is used as the probability of randomly selecting an instruction set from at least two instruction sets. The instruction generator will randomly select an instruction set from at least two instruction sets according to the conditional probability corresponding to each instruction set, and the probability of each instruction set being selected depends on its corresponding conditional probability value. Exemplarily, assuming that the conditional probability corresponding to instruction feature requirement 1 is 40%, and the conditional probability corresponding to instruction feature requirement 2 is 60%, then the conditional probability that a randomly selected instruction set is an instruction set corresponding to instruction feature requirement 1 is 40%, and the conditional probability that a randomly selected instruction set is an instruction set corresponding to instruction feature requirement 2 is 60%.

[0034] Step 202: randomly generate a target instruction from the target instruction set.

[0035] In the embodiment of the present invention, a random selection is performed among the to-be-matched instructions included in the target instruction set, and a target instruction is generated based on the randomly selected to-be-matched instruction.

[0036] Exemplarily, after randomly selecting an instruction to be matched from the instructions to be matched contained in the target instruction set, the process of the instruction generator generating the target instruction based on the selected instruction to be matched can be: obtaining the opcode (Opcode) corresponding to the selected instruction to be matched. Select and fill the register or immediate field. If the selected instruction to be matched involves register operation, a valid register number is randomly selected for filling. If the selected instruction to be matched requires an immediate number, a random immediate value that meets the instruction format requirements is generated. According to the instruction type of the selected instruction to be matched and the target instruction set architecture, determine other field information for generating the target instruction, for example, if it involves conditional execution or affects the status flag of the processor, it may be necessary to randomly set the corresponding condition code or flag bit field, etc. The above fields are assembled into a complete binary instruction, i.e., the target instruction, according to the requirements of the instruction format. The generated target instruction is stored in the instruction cache, or sent to the execution unit (such as the processor core) through the bus for processor verification.

[0037] Step 203: reselect an instruction set randomly from at least two instruction sets corresponding to at least two instruction feature requirements based on the conditional probability corresponding to each of the instruction feature requirements, and start executing from the target instruction set step until a target instruction matching the number of instructions is generated.

[0038] In the embodiment of the present invention, after a target instruction is randomly generated from the target instruction set, steps 201 to 202 are repeatedly performed until a target instruction matching the number of instructions is generated. That is, each time a target instruction is generated, it is necessary to randomly select an instruction set from at least two instruction sets corresponding to at least two instruction feature requirements based on the conditional probability corresponding to each instruction feature requirement as the target instruction set, and then randomly select and generate the target instruction from the target instruction set.

[0039] In an embodiment of the present invention, when the number of instruction feature requirements is at least two, an instruction set can be randomly selected from at least two instruction sets as a target instruction set based on the conditional probability corresponding to each instruction feature requirement, and then a target instruction can be randomly selected from the target instruction set. In this way, more instruction combinations and boundary conditions can be covered by at least two instruction feature requirements, thereby more comprehensively verifying the function of the CPU, and by randomly selecting an instruction set as a target instruction set and randomly selecting a target instruction from the target instruction set, the randomness of the instruction generation process is ensured, thereby increasing the unpredictability of processor verification, and making the test process closer to actual usage.

[0040] Optionally, the embodiment of the present invention may further include the following steps: Step 301: Obtain a preset instruction set; the preset instruction set includes a plurality of instructions to be matched.

[0041] In an embodiment of the present invention, a preset instruction set is obtained, and the preset instruction set is determined based on instructions of a preset instruction set architecture that matches the processor verification process. The preset instruction set includes multiple instructions to be matched. Exemplarily, the instructions to be matched included in the preset instruction set may be ADD, SUB, ORI, and ALL, etc.

[0042] Step 302: Determine a feature label corresponding to each of the instructions to be matched based on the instruction feature of each of the instructions to be matched.

[0043] In the embodiment of the present invention, since different instructions to be matched can be used to implement different functions, the different functions that can be implemented by the instructions can be marked with feature tags, and the feature tags can characterize the instruction characteristics of the instructions to be matched, wherein the feature tags may include control state (csr), floating point (float), integer (int), calculation (cal), addition (plus), logic (logic) and shift (shift), etc. Exemplarily, if the instruction can query or change the hardware status by reading or writing the control status register, the instruction can be marked with the feature tag csr; if the instruction is used to perform floating-point arithmetic operations (such as addition, subtraction, multiplication, division, etc.) and logical operations, the instruction can be marked with the feature tag float; if the instruction is used to perform integer arithmetic operations and logical operations, the instruction can be marked with the feature tag int; if the instruction involves numerical or logical operations, the instruction can be marked with the feature tag cal; if the instruction is used to calculate the sum of two numbers, the instruction can be marked with the feature tag plus; if the instruction involves logical operations such as AND, OR, NOT, XOR, etc., the instruction can be marked with the feature tag logic; if the instruction involves shifting the binary bits of data to the left or right by a specified number of bits, the instruction can be marked with the feature tag shift. It can be understood that an instruction can have multiple instruction features, and accordingly, an instruction to be matched can also correspond to multiple feature tags.

[0044] According to the functions that the instructions can achieve, the instruction features of the instructions are determined, and the instruction features are marked with feature tags. For example, assuming that the instruction to be matched is an ADD instruction, and the ADD instruction can achieve the integer addition operation function, it can be determined that the instruction has addition operation features, operation features, and integer type features, and accordingly, the feature tags int, cal, and plus can be used to mark the ADD instruction; if the instruction to be matched is an AND instruction, and the AND instruction can achieve the integer logic operation function, it can be determined that the instruction has integer type features and logic features, and accordingly, the feature tags int and logic can be used to mark the AND instruction.

[0045] In an embodiment of the present invention, by determining the feature label corresponding to each instruction to be matched based on the instruction feature of each instruction to be matched, different target instruction sets can be obtained by matching according to different instruction feature requirements in the process of determining the target instruction set, and finally the target instruction is randomly generated from the selected target instruction set, thereby improving the simplicity of the instruction feature requirement matching process and the efficiency of determining the target instruction set.

[0046] Optionally, step 102 may include the following steps: Step 401: For any of the to-be-matched instructions in the preset instruction set, match the feature tag corresponding to the to-be-matched instruction with the instruction feature requirement.

[0047] Step 402: When the feature tag corresponding to the instruction to be matched successfully matches the instruction feature requirement, a target instruction set is formed based on the instruction to be matched.

[0048] In an embodiment of the present invention, for any instruction to be matched in a preset instruction set, one or more feature tags corresponding to the instruction to be matched are obtained. The feature tag corresponding to the instruction to be matched is matched with the instruction feature requirement. In the case where the feature tag corresponding to the instruction to be matched successfully matches the instruction feature requirement, a target instruction set is formed based on the instruction to be matched. Exemplarily, the instruction generator can pre-construct an empty target instruction set, and in the case where the feature tag corresponding to the instruction to be matched successfully matches the instruction feature requirement, the instruction to be matched is added to the target instruction set. Among them, the situation where the feature tag corresponding to the instruction to be matched successfully matches the instruction feature requirement may include: when the content of the instruction feature requirement includes the need to have a certain feature, the feature tag corresponding to the instruction to be matched needs to be exactly the same as the feature that needs to be possessed in the instruction feature requirement, and it is deemed that the feature tag corresponding to the instruction to be matched successfully matches the instruction feature requirement; when the content of the instruction feature requirement includes the need not to have a certain feature, the feature tag corresponding to the instruction to be matched needs to not include any feature that needs not to be possessed in the instruction feature requirement, and it is deemed that the feature tag corresponding to the instruction to be matched successfully matches the instruction feature requirement; when the content of the instruction feature requirement includes the need to have a certain feature and the need not to have another feature, the feature tag corresponding to the instruction to be matched also needs to be exactly the same as the feature that needs to be possessed in the instruction feature requirement, and needs to not include any feature that needs not to be possessed in the instruction feature requirement, and it is deemed that the feature tag corresponding to the instruction to be matched successfully matches the instruction feature requirement.

[0049] In the embodiment of the present invention, by matching the feature tags of the instructions to be matched with the instruction feature requirements, the instructions to be matched that meet the instruction feature requirements can be matched more accurately and quickly, thereby obtaining a target instruction set.

[0050] For example, assume that the following six features are needed to generate an instruction stream, namely control state (csr), floating point (float), integer (int), calculation (cal), addition (plus), logic (logic), and shift (shift). Select 20 instructions from a certain instruction set architecture to form a preset instruction set, and add feature tags to each instruction to be matched in the preset instruction set, such as Figure 2 shown.

[0051] Assume that the instruction stream to be generated contains a total of 3 fragment instruction streams. The instruction feature requirements of the first fragment instruction stream are: the probability of generating instructions with the csr feature is 80%, the probability of generating instructions with the plus feature is 20%, and the number of instructions is 5; the instruction feature requirements of the second fragment instruction stream are: generating instructions with both the int and cal features but not the plus feature, and the number of instructions is 5; the instruction feature requirements of the third fragment instruction stream are: generating instructions with both the float and logic features with a probability of 40%, the probability of generating instructions with the shift feature is 60%, and the number of instructions is 10.

[0052] According to the instruction feature requirements set above, a target instruction set corresponding to each instruction feature requirement is determined.

[0053] Specifically, the instruction feature requirements of the first fragment instruction stream may correspond to two target instruction sets, SET_csr and SET_plus, and all elements of the set SET_csr are all instructions to be matched with the feature tag csr: SET_csr = {CSRRW, CSRRS, CSRRC} All elements of the set SET_plus are all instructions to be matched with the feature tag plus: SET_plus = {ADD,FADD_S,ADDI,ADDIW} The instruction feature requirement of the second fragment instruction stream may correspond to a target instruction set SET_int_cal, where all elements of the set are all instructions to be matched that have both feature tags int and cal but do not have a feature tag plus: SET_int_cal = {SUB, DIV, MUL, FSQRT_S} The instruction feature requirements of the third fragment instruction stream can correspond to two target instruction sets, SET_float_logic and SET_shift. All elements of the set SET_float_logic are all instructions to be matched with the feature tag csr: SET_float_logic = {ANDI, ORI, XORI} All elements of the set SET_shift are all instructions to be matched with the characteristic label shift: SET_shift = {SLL, SLT, SLTI, SLLI, SRLI} Finally, the instruction stream is generated in sequence. First, the first fragment instruction stream is generated. When generating each instruction, the target set is first randomly selected. The probability of selecting the set SET_csr is 80%, and the probability of selecting the set SET_plus is 20%. After randomly selecting a target instruction set, randomly select an instruction from the target instruction set. The probability of selecting each instruction is the same. Repeat the above steps 5 times to obtain 5 target instructions. The process of generating the second fragment instruction stream is: directly randomly select 1 instruction from the target instruction set SET_int_cal, repeat the above steps 5 times until 5 target instructions are selected. The process of generating the third fragment instruction stream is: select SET_float_logic with a probability of 40% and select SET_shift with a probability of 60%. After randomly selecting a target instruction set, randomly select 1 instruction from the target instruction set. Repeat the above steps 10 times until 10 target instructions are selected. Exemplarily, the first fragment instruction stream, the second fragment instruction stream, and the third fragment instruction stream finally generated can be as follows. Figure 3 shown.

[0054] Figure 4 is a schematic diagram of the structure of an instruction generation device provided by an embodiment of the present invention, such as Figure 3 As shown, the device may specifically include: The first acquisition module 501 is used to acquire instruction generation requirements; the instruction generation requirements include instruction feature requirements and instruction quantity; A first determination module 502 is used to determine, in the preset instruction set, instructions to be matched that match the instruction feature requirement based on feature tags corresponding to multiple instructions to be matched in the preset instruction set, to obtain a target instruction set; The first generating module 503 is used to randomly generate target instructions matching the instruction quantity based on the target instruction set.

[0055] The embodiment of the present invention provides an instruction generation device, which obtains instruction generation requirements; the instruction generation requirements include instruction feature requirements and the number of instructions; based on the feature tags corresponding to multiple instructions to be matched in the preset instruction set, the instructions to be matched that match the instruction feature requirements are determined in the preset instruction set to obtain a target instruction set; based on the target instruction set, target instructions that match the number of instructions are randomly generated. In this way, based on the instruction feature requirements, a target instruction set can be matched from the preset instruction set, and a target instruction can be randomly generated based on the target instruction set. The instruction feature requirements can be automatically matched with the instructions to be matched based on the instruction generation requirements, without manually adjusting the parameters of the instruction generator one by one according to the instruction generation requirements to generate instructions, thereby avoiding errors under the premise of ensuring the randomness of the target instructions by matching the feature requirements with the feature tags, improving the accuracy of the instructions, and reducing the complexity of instruction generation, thereby improving the efficiency of instruction generation to a certain extent.

[0056] Optionally, when the number of the instruction feature requirements is at least two, the instruction generation requirement further includes conditional probabilities corresponding to each of the instruction feature requirements; the first generation module 503 includes: A first selection module is used to randomly select an instruction set from at least two instruction sets corresponding to at least two instruction feature requirements as a target instruction set based on the conditional probability corresponding to each of the instruction feature requirements; the number of the instruction feature requirements is equal to the number of the instruction sets; A first generating submodule, used for randomly generating a target instruction from the target instruction set; The first execution module is used to randomly select an instruction set from at least two instruction sets corresponding to at least two instruction feature requirements based on the conditional probability corresponding to each of the instruction feature requirements, and start execution from the target instruction set step until a target instruction matching the number of instructions is generated.

[0057] Optionally, the device further comprises: A second acquisition module is used to acquire a preset instruction set; the preset instruction set includes a plurality of instructions to be matched; The second determination module is used to determine the feature label corresponding to each of the instructions to be matched based on the instruction feature of each of the instructions to be matched.

[0058] Optionally, the first determining module 502 includes: A first matching module, configured to match, for any of the to-be-matched instructions in the preset instruction set, a feature tag corresponding to the to-be-matched instruction with the instruction feature requirement; The first adding module is used to form a target instruction set based on the instruction to be matched when the feature tag corresponding to the instruction to be matched successfully matches the instruction feature requirement.

[0059] Optionally, the instruction feature requirement includes a first requirement, a second requirement and a third requirement, the first requirement is used to indicate the generation of an instruction having one or more first features, the second requirement is used to indicate the generation of an instruction having one or more first features but not having one or more second features, and the third requirement is used to indicate the generation of an instruction not having one or more second features.

[0060] The present invention also provides an electronic device, see Figure 5 , including: a processor 601, a memory 602, and a computer program 6021 stored in the memory and executable on the processor, wherein the processor implements the instruction generation method of the aforementioned embodiment when executing the program.

[0061] The present invention also provides a readable storage medium, when the instructions in the storage medium are executed by a processor of an electronic device, the electronic device can execute the instruction generation method of the aforementioned embodiment.

[0062] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0063] The algorithm and display provided herein are not inherently related to any particular computer, virtual system or other device. Various general purpose systems can also be used together with the teachings based on this. According to the above description, it is obvious that the structure required for constructing such systems. In addition, the present invention is not directed to any specific programming language either. It should be understood that various programming languages ​​can be utilized to realize the content of the present invention described herein, and the description of the above specific languages ​​is for disclosing the best mode of the present invention.

[0064] In the description provided herein, a large number of specific details are described. However, it is understood that embodiments of the present invention can be practiced without these specific details. In some instances, well-known methods, structures and techniques are not shown in detail so as not to obscure the understanding of this description.

[0065] Similarly, it should be understood that in order to streamline the present invention and aid in understanding one or more of the various inventive aspects, in the above description of exemplary embodiments of the present invention, the various features of the present invention are sometimes grouped together into a single embodiment, figure, or description thereof. However, this disclosed method should not be interpreted as reflecting the following intention: that the claimed invention requires more features than the features explicitly recited in each claim. More specifically, as reflected in the claims below, inventive aspects lie in less than all the features of the individual embodiments disclosed above. Therefore, the claims that follow the specific embodiment are hereby expressly incorporated into the specific embodiment, with each claim itself serving as a separate embodiment of the present invention.

[0066] Those skilled in the art will appreciate that the modules in the devices in the embodiments may be adaptively changed and arranged in one or more devices different from the embodiments. The modules or units or components in the embodiments may be combined into one module or unit or component, and further may be divided into a plurality of submodules or subunits or subcomponents. All features disclosed in this specification (including the accompanying claims, abstracts and drawings) and all processes or units of any method or device so disclosed may be combined in any combination, except that at least some of such features and / or processes or units are mutually exclusive. Unless otherwise expressly stated, each feature disclosed in this specification (including the accompanying claims, abstracts and drawings) may be replaced by an alternative feature that provides the same, equivalent or similar purpose.

[0067] The various component embodiments of the present invention may be implemented in hardware, or in software modules running on one or more processors, or in a combination thereof. It should be understood by those skilled in the art that a microprocessor or a digital signal processor (DSP) may be used in practice to implement some or all of the functions of some or all of the components in the sorting device according to the present invention. The present invention may also be implemented as a device or apparatus program for executing part or all of the methods described herein. Such a program for implementing the present invention may be stored on a computer-readable medium, or may be in the form of one or more signals. Such a signal may be downloaded from an Internet website, or provided on a carrier signal, or provided in any other form.

[0068] It should be noted that the above embodiments illustrate the present invention rather than limit it, and that those skilled in the art may devise alternative embodiments without departing from the scope of the appended claims. In the claims, any reference symbol between brackets shall not be construed as a limitation on the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "one" or "an" preceding an element does not exclude the presence of a plurality of such elements. The present invention may be implemented by means of hardware comprising a number of different elements and by means of a suitably programmed computer. In a unit claim enumerating a number of devices, several of these devices may be embodied by the same hardware item. The use of the words first, second, and third, etc., does not indicate any order. These words may be interpreted as names.

[0069] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0070] It should be noted that all actions of acquiring signals, information or data in this application are carried out in compliance with the relevant data protection laws and policies of the country where they are located and with the authorization given by the owner of the corresponding device.

[0071] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

[0072] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A method for generating an instruction, characterized in that: The method comprises: Obtaining instruction generation requirements; the instruction generation requirements include instruction feature requirements and instruction quantity; Based on feature tags corresponding to a plurality of to-be-matched instructions in a preset instruction set, determining in the preset instruction set the to-be-matched instructions that match the instruction feature requirement, and obtaining a target instruction set; Based on the target instruction set, a target instruction matching the instruction quantity is randomly generated.

2. The method according to claim 1, characterized in that: In the case where the number of the instruction feature requirements is at least two, the instruction generation requirement further includes a conditional probability corresponding to each of the instruction feature requirements; and the randomly generating a target instruction matching the number of instructions based on the target instruction set includes: Based on the conditional probabilities corresponding to the instruction feature requirements, randomly selecting an instruction set from at least two instruction sets corresponding to at least two instruction feature requirements as the target instruction set; the number of the instruction feature requirements is equal to the number of the instruction sets; randomly generating a target instruction from the target instruction set; Re-select an instruction set randomly from at least two instruction sets corresponding to at least two instruction feature requirements based on the conditional probability corresponding to each of the instruction feature requirements, and start executing from the target instruction set step until a target instruction matching the number of instructions is generated.

3. The method according to claim 1, characterized in that: The method further comprises: Obtaining a preset instruction set; the preset instruction set includes a plurality of instructions to be matched; Based on the instruction features of each of the instructions to be matched, a feature label corresponding to each of the instructions to be matched is determined.

4. The method according to claim 3, characterized in that The step of determining, based on feature tags corresponding to a plurality of to-be-matched instructions in a preset instruction set, instructions to be matched that match the instruction feature requirement in the preset instruction set to obtain a target instruction set includes: For any of the to-be-matched instructions in the preset instruction set, matching the feature tag corresponding to the to-be-matched instruction with the instruction feature requirement; When the feature tag corresponding to the instruction to be matched successfully matches the instruction feature requirement, a target instruction set is formed based on the instruction to be matched.

5. The method according to claim 1, characterized in that The instruction feature requirements include a first requirement, a second requirement, and a third requirement. The first requirement is used to indicate the generation of an instruction with one or more first features, the second requirement is used to indicate the generation of an instruction with one or more first features but not one or more second features, and the third requirement is used to indicate the generation of an instruction without one or more second features.

6. An instruction generating device, characterized in that: The device comprises: A first acquisition module is used to acquire instruction generation requirements; the instruction generation requirements include instruction feature requirements and instruction quantity; A first determination module is used to determine, in the preset instruction set, instructions to be matched that match the instruction feature requirement based on feature tags corresponding to multiple instructions to be matched in the preset instruction set, to obtain a target instruction set; The first generating module is used to randomly generate target instructions matching the instruction quantity based on the target instruction set.

7. The device according to claim 6, characterized in that In the case where the number of the instruction feature requirements is at least two, the instruction generation requirement further includes conditional probabilities corresponding to each of the instruction feature requirements; the first generation module includes: A first selection module is used to randomly select an instruction set from at least two instruction sets corresponding to at least two instruction feature requirements as a target instruction set based on the conditional probability corresponding to each of the instruction feature requirements; the number of the instruction feature requirements is equal to the number of the instruction sets; A first generating submodule, used for randomly generating a target instruction from the target instruction set; The first execution module is used to randomly select an instruction set from at least two instruction sets corresponding to at least two instruction feature requirements based on the conditional probability corresponding to each of the instruction feature requirements, and start execution from the target instruction set step until a target instruction matching the number of instructions is generated.

8. The device according to claim 6, characterized in that The device also includes: A second acquisition module is used to acquire a preset instruction set; the preset instruction set includes a plurality of instructions to be matched; The second determination module is used to determine the feature label corresponding to each of the instructions to be matched based on the instruction feature of each of the instructions to be matched.

9. An electronic device, characterized in that: include: A processor, a memory, and a computer program stored in the memory and executable on the processor, wherein the processor implements the instruction generation method according to any one of claims 1 to 5 when executing the program.

10. A readable storage medium, characterized in that: When the instructions in the storage medium are executed by a processor of an electronic device, the electronic device is enabled to execute the instruction generation method described in any one of claims 1-5.

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