Instruction Generation Method, Device, Electronic Device, and Readable Storage Medium

Abstract

An embodiment of the present invention provides an instruction generation method, apparatus, electronic device, and readable storage medium. By obtaining an instruction generation requirement, where the instruction generation requirement includes an instruction feature requirement and the number of instructions; based on the feature tags corresponding to multiple to-be-matched instructions in a preset instruction set, determining the to-be-matched instructions that match the instruction feature requirement in the preset instruction set to obtain a target instruction set; and randomly generating target instructions that match the number of instructions based on the target instruction set. In this way, it is not necessary to manually adjust the parameters of the instruction generator one by one, thereby avoiding human errors through the matching of feature requirements and feature tags while ensuring the randomness of the target instructions, improving the instruction accuracy, reducing the complexity of instruction generation, and to a certain extent improving the efficiency of instruction generation.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular, to an instruction generation method, apparatus, electronic device, and readable storage medium. Background Art

[0002] With the rapid development of information technology, as the core component of a computer system, the performance and reliability of a processor are directly related to the operating efficiency and data security of the entire system. In the design and verification process of a processor, the accuracy and efficiency of an instruction set are one of the key factors. To ensure that the processor can execute various instructions accurately, it is particularly important to select instructions with specific characteristics for a large number of tests in the verification process.

[0003] In related technologies, an instruction generator is the main tool for generating a test instruction stream. However, during the instruction generation process, verification personnel often need to manually adjust the parameters of the instruction generator one by one according to the instruction generation requirements to generate an instruction stream that meets the instruction generation requirements one by one. This not only increases the complexity and labor cost of instruction generation, but also easily introduces human errors, resulting in low instruction generation efficiency and inability to ensure instruction accuracy. Summary of the Invention

[0004] To overcome the problems existing in related technologies, the present invention provides an instruction generation method, apparatus, electronic device, and readable storage medium.

[0005] In a first aspect, the present invention provides an instruction generation method, the method including:

[0006] Obtaining an instruction generation requirement; the instruction generation requirement includes an instruction feature requirement and an instruction quantity;

[0007] Based on the feature tags corresponding to multiple to-be-matched instructions in a preset instruction set, determining, in the preset instruction set, a to-be-matched instruction that matches the instruction feature requirement to obtain a target instruction set;

[0008] Based on the target instruction set, randomly generating a target instruction that matches the instruction quantity.

[0009] Optionally, when the number of the instruction feature requirements is at least two, the instruction generation requirement further includes a conditional probability corresponding to each of the instruction feature requirements; the randomly generating a target instruction that matches the instruction quantity based on the target instruction set includes:

[0010] Based on the conditional probability corresponding to each of the instruction feature requirements, randomly selecting an instruction set from at least two instruction sets corresponding to at least two instruction feature requirements as the target instruction set; the number of the instruction feature requirements is equal to the number of the instruction sets;

[0011] Randomly generate a target instruction from the set of target instructions;

[0012] Re - start the execution from the step of randomly selecting one instruction set from at least two instruction sets corresponding to at least two instruction feature requirements based on the conditional probability corresponding to each instruction feature requirement, until target instructions matching the number of instructions are generated.

[0013] Optionally, the method further includes:

[0014] Obtain a preset instruction set; the preset instruction set includes a plurality of instructions to be matched;

[0015] Based on the instruction features of each instruction to be matched, determine the feature labels corresponding to each instruction to be matched.

[0016] Optionally, determining the instructions to be matched that match the instruction feature requirements in the preset instruction set based on the feature labels corresponding to a plurality of instructions to be matched in the preset instruction set to obtain a target instruction set includes:

[0017] For any instruction to be matched in the preset instruction set, match the feature label corresponding to the instruction to be matched with the instruction feature requirements;

[0018] When the feature label corresponding to the instruction to be matched successfully matches the instruction feature requirements, form a target instruction set based on the instruction to be matched.

[0019] Optionally, the instruction feature requirements include a first requirement, a second requirement, and a third requirement. The first requirement is used to indicate generating instructions with one or more first features, the second requirement is used to indicate generating instructions with one or more first features and without one or more second features, and the third requirement is used to indicate generating instructions without one or more second features.

[0020] In a second aspect, the present invention provides an instruction generation device, and the device includes:

[0021] A first acquisition module, configured to acquire an instruction generation requirement; the instruction generation requirement includes an instruction feature requirement and the number of instructions;

[0022] A first determination module, configured to determine the instructions to be matched that match the instruction feature requirements in the preset instruction set based on the feature labels corresponding to a plurality of instructions to be matched in the preset instruction set, to obtain a target instruction set;

[0023] A first generation module, configured to randomly generate target instructions matching the number of instructions based on the target instruction set.

[0024] Optionally, when the number of the instruction feature requirements is at least two, the instruction generation requirement further includes a conditional probability corresponding to each instruction feature requirement; the first generation module includes:

[0025] A first selection module, configured to randomly select an instruction set from at least two instruction sets corresponding to at least two instruction feature requirements based on the conditional probability corresponding to each instruction feature requirement, as the target instruction set; the number of the instruction feature requirements is equal to the number of the instruction sets;

[0026] A first generation sub-module, configured to randomly generate a target instruction from the target instruction set;

[0027] A first execution module, configured to restart the execution from the step of randomly selecting an instruction set from at least two instruction sets corresponding to at least two instruction feature requirements based on the conditional probability corresponding to each instruction feature requirement, as the target instruction set, until a target instruction matching the number of the instructions is generated.

[0028] Optionally, the apparatus further includes:

[0029] A second acquisition module, configured to acquire a preset instruction set; the preset instruction set includes a plurality of instructions to be matched;

[0030] A second determination module, configured to determine a feature label corresponding to each instruction to be matched based on the instruction features of each instruction to be matched.

[0031] Optionally, the first determination module includes:

[0032] A first matching module, configured to match the feature label corresponding to an instruction to be matched in the preset instruction set with the instruction feature requirement;

[0033] A first addition module, configured to form a target instruction set based on the instruction to be matched when the feature label corresponding to the instruction to be matched matches the instruction feature requirement.

[0034] Optionally, the instruction feature requirement includes a first requirement, a second requirement, and a third requirement. The first requirement is used to indicate generating an instruction having one or more first features, the second requirement is used to indicate generating an instruction having one or more first features and not having one or more second features, and the third requirement is used to indicate generating an instruction not having one or more second features.

[0035] In a third aspect, the present invention provides an electronic device, including: a processor, a memory, and a computer program stored on the memory and executable on the processor, where when the processor executes the program, the instruction generation method according to any one of the above first aspects is implemented.

[0036] In a fourth aspect, the present invention provides a readable storage medium, when the instructions in the storage medium are executed by a processor of an electronic device, enabling the electronic device to execute the steps in the instruction generation method according to any one of the above first aspects.

[0037] In the embodiments of the present invention, by obtaining an instruction generation requirement; the instruction generation requirement includes an instruction feature requirement and an instruction quantity; based on the feature tags corresponding to multiple to-be-matched instructions in a preset instruction set, determining, in the preset instruction set, the to-be-matched instructions that match the instruction feature requirement to obtain a target instruction set; and randomly generating, based on the target instruction set, target instructions that match the instruction quantity. In this way, based on the instruction feature requirement, a target instruction set can be matched from the preset instruction set, and target instructions can be randomly generated based on the target instruction set, which can directly automatically match the instruction feature requirement with the to-be-matched instructions according to the instruction generation requirement, without manually adjusting the parameters of the instruction generator one by one according to the instruction generation requirement to generate instructions. Therefore, on the premise of ensuring the randomness of the target instructions, human errors are avoided by the method of matching the feature requirement with the feature tag, the instruction accuracy is improved, the complexity of instruction generation is reduced, and the instruction generation efficiency is improved to a certain extent. Description of the Drawings

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0039] Figure 1 is a flowchart of the steps of an instruction generation method provided by an embodiment of the present invention;

[0040] Figure 2 is a schematic diagram of a preset instruction set provided by an embodiment of the present invention;

[0041] Figure 3 is a schematic diagram of an instruction generation result provided by an embodiment of the present invention;

[0042] Figure 4 is a structural diagram of an instruction generation device provided by an embodiment of the present invention;

[0043] Figure 5It is a structural diagram of an electronic device provided by an embodiment of the present invention. Detailed implementation manners

[0044] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0045] Figure 1 It is a step flowchart of an instruction generation method provided by an embodiment of the present invention. As Figure 1 shown, the method may include:

[0046] Step 101, obtain an instruction generation requirement; the instruction generation requirement includes an instruction feature requirement and the number of instructions.

[0047] In the embodiments of the present invention, according to the verification test requirements verified by the processor in advance, the instruction generation requirements of the instruction stream required for the processor verification process are defined. As a programmable component, the processor needs to execute a wide variety of tasks, and the instruction set thus becomes complex and changeable. To ensure the stable operation of the processor in various application scenarios, the verification team must conduct extensive tests on different types of instructions. These instructions may involve multiple aspects such as data processing, memory access, and control flow transfer, and each instruction has its unique execution characteristics and potential problem points. Therefore, the verification test requirements for processor verification often need to generate instructions with specific characteristics. For example, the characteristic types may include instruction operation types (such as arithmetic operations, logical operations, bit operations, etc.), data types processed by the instructions (such as integer type, floating-point type, etc.), and control types of the instructions (such as conditional execution, loop control, interrupt handling, etc.). Instructions with different specific characteristics can correspond to the number of instructions generated according to the instruction characteristic requirements. The instruction generation requirements can be obtained based on the requirement information input by the user to the instruction generator through the interaction interface. Therefore, the instruction generation requirements can include instruction characteristic requirements and the number of instructions. The instruction characteristic requirements can be used to describe specific requirements such as instruction operation requirements, data requirements processed by the instructions, and control requirements of the instructions. The number of instructions can be used to define the number of random instructions to be generated. Specifically, the instruction characteristic requirements can include a first requirement, a second requirement, and a third requirement. The first requirement is used to indicate the generation of instructions with one or more first characteristics, the second requirement is used to indicate the generation of instructions with one or more first characteristics and without one or more second characteristics, and the third requirement is used to indicate the generation of instructions without one or more second characteristics. The first characteristic and the second characteristic can be any instruction characteristic, and the present invention does not limit the specific content of the first characteristic and the second characteristic. Exemplarily, the first requirement can be used to indicate the generation of instructions with arithmetic operation characteristics, or the generation of instructions with both integer operation characteristics and addition operation characteristics. The second requirement can be used to indicate the generation of instructions with integer operation characteristics and arithmetic operation characteristics but without addition operation indications.

[0048] Step 102: Based on the characteristic tags corresponding to multiple to-be-matched instructions in the preset instruction set, determine the to-be-matched instructions that match the instruction characteristic requirements in the preset instruction set to obtain a target instruction set.

[0049] In an embodiment of the present invention, the preset instruction set may be determined based on instructions in a preset instruction set architecture that matches the processor verification process. The preset instruction set includes multiple instructions to be matched, and each instruction to be matched is marked with a feature label. Based on the feature label corresponding to the instruction to be matched, an instruction to be matched that matches the instruction feature requirement is determined in the preset instruction set, and a target instruction set is obtained. Different instruction feature requirements may correspond to different target instruction sets. That is, for each instruction feature requirement, a target instruction set that meets the instruction feature requirement is determined in the preset instruction set, and the target instruction set includes the instructions to be matched in the preset instruction set that match the instruction feature requirement. An instruction to be matched that matches the instruction feature requirement means that the feature label of the instruction to be matched is the same as the instruction feature that is described as having or not having in the instruction feature requirement.

[0050] Exemplarily, when the instruction feature requirement is the first requirement, and the first requirement is used to indicate generating an instruction with one or more first features, it is necessary to determine an instruction to be matched whose feature label is exactly the same as one or more first features in the first requirement as the instruction to be matched that matches the instruction feature requirement; when the instruction feature requirement is the second requirement, and the second requirement is used to indicate generating an instruction with one or more first features and not having one or more second features, it is necessary to determine an instruction to be matched whose feature label is exactly the same as one or more first features in the second requirement and completely does not include one or more second features as the instruction to be matched that matches the instruction feature requirement; when the instruction feature requirement is the third requirement, and the third requirement is used to indicate generating an instruction that does not have one or more second features, it is necessary to determine an instruction to be matched whose feature label completely does not include one or more second features as the instruction to be matched that matches the instruction feature requirement.

[0051] Step 103: Randomly generate target instructions that match the number of instructions based on the target instruction set.

[0052] In an embodiment of the present invention, based on the target instruction set, a target instruction is randomly selected and generated from the target instruction set. When the number of instructions is greater than or equal to two, a random selection operation is performed the same number of times as the number of instructions from the target instruction set, and target instructions that match the number of instructions are generated.

[0053] In summary, in the embodiments of the present invention, requirements are generated by obtaining instructions; the instruction generation requirements include instruction feature requirements and the number of instructions; based on the feature tags corresponding to multiple to-be-matched instructions in a preset instruction set, to-be-matched instructions that match the instruction feature requirements are determined in the preset instruction set to obtain a target instruction set; based on the target instruction set, target instructions that match the number of instructions are randomly generated. In this way, based on the instruction feature requirements, a target instruction set can be matched from the preset instruction set, and target instructions can be randomly generated based on the target instruction set, which can directly match the instruction feature requirements with the to-be-matched instructions according to the instruction generation requirements, without manually adjusting the parameters of the instruction generator one by one according to the instruction generation requirements to generate instructions. Therefore, on the premise of ensuring the randomness of the target instructions, human errors are avoided by the method of matching feature requirements with feature tags, the accuracy of the instructions is improved, the complexity of instruction generation is reduced, and the efficiency of instruction generation is improved to a certain extent.

[0054] Furthermore, in the related art, instruction generation often relies on manually writing preset templates or rules, which are difficult to flexibly handle the constantly emerging complex requirements in CPU design. By the method of matching feature requirements with feature tags provided in the embodiments of the present invention, for complex instruction feature requirements, such as the instruction feature requirement is to generate an instruction with one or more first features and without one or more second features, a target instruction that matches the complex instruction feature requirement can be randomly generated by the method of matching feature requirements with feature tags, which improves the flexibility and comprehensive applicability of instruction generation.

[0055] Optionally, when the number of the instruction feature requirements is at least two, the instruction generation requirements further include the conditional probabilities corresponding to the respective instruction feature requirements.

[0056] In the embodiments of the present invention, when the number of the instruction feature requirements is at least two, the instruction generation requirements may further include the conditional probabilities corresponding to the respective instruction feature requirements, where the conditional probability is used to represent the random generation probability for different instruction feature requirements when randomly generating instructions. Exemplarily, the conditional probability corresponding to instruction feature requirement 1 is 40%, and the conditional probability corresponding to instruction feature requirement 2 is 60%. Then the probability that the randomly generated target instruction meets instruction feature requirement 1 is 40%, and the probability that it meets instruction feature requirement 2 is 60%.

[0057] Correspondingly, step 103 may include the following steps:

[0058] Step 201, randomly select one instruction set from at least two instruction sets corresponding to at least two instruction feature requirements as the target instruction set based on the conditional probabilities corresponding to the respective instruction feature requirements; the number of the instruction feature requirements is equal to the number of the instruction sets.

[0059] In an embodiment of the present invention, when the number of instruction feature requirements is at least two, that is, when at least two instruction feature requirements are included in one instruction generation requirement, it indicates that the current instruction generation requirement is to randomly generate an instruction based on at least two instruction feature requirements. Then, for each instruction feature requirement, it will be matched with the feature tags corresponding to multiple to-be-matched instructions in the preset instruction set, and at least two instruction sets will be obtained. One instruction feature requirement corresponds to one instruction set. Based on the conditional probabilities corresponding to each instruction feature requirement, a random selection is made from at least two instruction sets corresponding to at least two instruction feature requirements to obtain a target instruction set. That is to say, the conditional probabilities corresponding to each instruction feature requirement are used as the probabilities for randomly selecting an instruction set from at least two instruction sets. The instruction generator will randomly select an instruction set from at least two instruction sets according to the conditional probabilities corresponding to each instruction set, and the probability of each instruction set being selected depends on its corresponding conditional probability value. Exemplarily, assume that the conditional probability corresponding to instruction feature requirement 1 is 40% and the conditional probability corresponding to instruction feature requirement 2 is 60%. Then the conditional probability that a randomly selected instruction set is the instruction set corresponding to instruction feature requirement 1 is 40%, and the conditional probability that a randomly selected instruction set is the instruction set corresponding to instruction feature requirement 2 is 60%.

[0060] Step 202: Randomly generate a target instruction from the target instruction set.

[0061] In an embodiment of the present invention, a random selection is made from the to-be-matched instructions included in the target instruction set, and a target instruction is generated based on the randomly selected to-be-matched instruction.

[0062] Exemplarily, after randomly selecting a to-be-matched instruction from the to-be-matched instructions included in the target instruction set, the process of the instruction generator generating a target instruction based on the selected to-be-matched instruction can be as follows: Obtain the operation code (Opcode) corresponding to the selected to-be-matched instruction. Select and fill the register or immediate number field. If the selected to-be-matched instruction involves register operations, randomly select a valid register number for filling. If the selected to-be-matched instruction requires an immediate number, generate a random immediate value that meets the instruction format requirements. According to the instruction type of the selected to-be-matched instruction and the target instruction set architecture, determine other field information for generating the target instruction. For example, if it involves conditional execution or affects the status flags of the processor, it may be necessary to randomly set the corresponding condition code or flag bit fields, etc. Assemble the above fields into a complete binary instruction according to the requirements of the instruction format, that is, the target instruction. Store the generated target instruction in the instruction cache or send it to the execution unit (such as the processor core) through the bus for processor verification.

[0063] Step 203: Start executing from the step of randomly selecting, based on the conditional probabilities corresponding to each of the instruction feature requirements, one instruction set from at least two instruction sets corresponding to at least two instruction feature requirements as the target instruction set until a target instruction matching the number of instructions is generated.

[0064] In an embodiment of the present invention, after randomly generating a target instruction from the target instruction set, steps 201 to 202 are repeatedly executed until a target instruction matching the number of instructions is generated. That is to say, in the process of generating each target instruction, it is necessary to randomly select, based on the conditional probabilities corresponding to each instruction feature requirement, one instruction set from at least two instruction sets corresponding to at least two instruction feature requirements as the target instruction set, and then randomly select and generate a target instruction from the target instruction set.

[0065] In an embodiment of the present invention, when the number of instruction feature requirements is at least two, one instruction set can be randomly selected from at least two instruction sets as the target instruction set based on the conditional probabilities corresponding to each instruction feature requirement, and then a target instruction is randomly selected from the target instruction set. In this way, through at least two instruction feature requirements, more instruction combinations and boundary conditions can be covered, so as to more comprehensively verify the functions of the CPU. And by randomly selecting an instruction set as the target instruction set and randomly selecting a target instruction from the target instruction set, the randomness of the instruction generation process is ensured, thereby increasing the unpredictability of the processor verification and making the test process closer to the actual usage situation.

[0066] Optionally, an embodiment of the present invention may further include the following steps:

[0067] Step 301: Obtain a preset instruction set; the preset instruction set includes a plurality of instructions to be matched.

[0068] In an embodiment of the present invention, a preset instruction set is obtained. The preset instruction set is determined based on instructions of a preset instruction set architecture matching the processor verification process. The preset instruction set includes a plurality of instructions to be matched. Exemplarily, the instructions to be matched included in the preset instruction set may be ADD, SUB, ORI, and ALL, etc.

[0069] Step 302: Determine the feature tags corresponding to each of the instructions to be matched based on the instruction features of each of the instructions to be matched.

[0070] In the embodiments of the present invention, since different instructions to be matched can be used to implement different functions, different functions that the instructions can implement can be marked with feature tags. The feature tags can represent the instruction features of the instructions to be matched. Among them, the feature tags can include control status (csr), floating point (float), integer (int), calculation (cal), addition (plus), logic (logic), and shift (shift), etc. Exemplarily, if an instruction can query or change the hardware status by reading or writing a control status register, the instruction can be marked with the feature tag csr; if an instruction is used to perform arithmetic operations (such as addition, subtraction, multiplication, division, etc.) and logical operations on floating-point numbers, the instruction can be marked with the feature tag float; if an instruction is used to perform arithmetic operations and logical operations on integers, the instruction can be marked with the feature tag int; if an instruction involves numerical or logical operations, the instruction can be marked with the feature tag cal; if an instruction is used to calculate the sum of two numbers, the instruction can be marked with the feature tag plus; if an instruction involves logical operations such as AND, OR, NOT, XOR, etc., the instruction can be marked with the feature tag logic; if an instruction involves shifting the binary bits of data to the left or right by a specified number of bits, the instruction can be marked with the feature tag shift. It can be understood that an instruction can have multiple instruction features. Correspondingly, an instruction to be matched can also correspond to multiple feature tags.

[0071] According to the functions that the instructions can implement, determine the instruction features of the instructions, and mark the instruction features with feature tags. Exemplarily, assume that the instruction to be matched is an ADD instruction, and the ADD instruction can implement the function of integer addition operation. Then it can be determined that the instruction has addition operation feature, operation feature, and integer type feature. Correspondingly, the ADD instruction can be marked with the feature tags int, cal, and plus; the instruction to be matched is an AND instruction, and the AND instruction can implement the function of integer logical operation. Then it can be determined that the instruction has integer type feature and logical feature. Correspondingly, the AND instruction can be marked with the feature tags int and logic.

[0072] In the embodiments of the present invention, by determining the feature tags corresponding to each instruction to be matched based on the instruction features of each instruction to be matched, different target instruction sets can be matched according to different instruction feature requirements in the process of determining the target instruction set, and finally a target instruction is randomly generated from the selected target instruction set, which improves the simplicity of the instruction feature requirement matching process and improves the determination efficiency of the target instruction set.

[0073] Optionally, step 102 may include the following steps:

[0074] Step 401: For any of the to-be-matched instructions in the preset instruction set, match the feature label corresponding to the to-be-matched instruction with the instruction feature requirement.

[0075] Step 402: When the feature label corresponding to the to-be-matched instruction matches the instruction feature requirement, form a target instruction set based on the to-be-matched instruction.

[0076] In an embodiment of the present invention, for any to-be-matched instruction in the preset instruction set, one or more feature labels corresponding to the to-be-matched instruction are obtained. The feature label corresponding to the to-be-matched instruction is matched with the instruction feature requirement. When the feature label corresponding to the to-be-matched instruction matches the instruction feature requirement, a target instruction set is formed based on the to-be-matched instruction. Exemplarily, an instruction generator may pre-construct an empty target instruction set, and when the feature label corresponding to the to-be-matched instruction matches the instruction feature requirement, add the to-be-matched instruction to the target instruction set. Among them, the situation where the feature label corresponding to the to-be-matched instruction matches the instruction feature requirement may include: when the content of the instruction feature requirement includes that a certain feature needs to be possessed, the feature label corresponding to the to-be-matched instruction needs to be exactly the same as the feature that needs to be possessed in the instruction feature requirement, then it is considered that the feature label corresponding to the to-be-matched instruction matches the instruction feature requirement; when the content of the instruction feature requirement includes that a certain feature needs not to be possessed, the feature label corresponding to the to-be-matched instruction needs not to include any feature that needs not to be possessed in the instruction feature requirement, then it is considered that the feature label corresponding to the to-be-matched instruction matches the instruction feature requirement; when the content of the instruction feature requirement includes that a certain feature needs to be possessed and another feature needs not to be possessed, then the feature label corresponding to the to-be-matched instruction also needs to be exactly the same as the feature that needs to be possessed in the instruction feature requirement, and needs not to include any feature that needs not to be possessed in the instruction feature requirement, then it is considered that the feature label corresponding to the to-be-matched instruction matches the instruction feature requirement.

[0077] In an embodiment of the present invention, by matching the feature label of the to-be-matched instruction with the instruction feature requirement, the to-be-matched instruction that meets the instruction feature requirement can be matched more accurately and quickly, and then the target instruction set can be obtained.

[0078] Exemplarily, assume that six features are required to generate an instruction stream, namely control state (csr), floating point (float), integer (int), calculation (cal), addition (plus), logic (logic), and shift (shift). Twenty instructions are selected from a certain instruction set architecture to form a preset instruction set, and feature labels are assigned to each to-be-matched instruction in the preset instruction set, as Figure 2 shown.

[0079] Suppose the instruction stream to be generated consists of 3 fragment instruction streams. The instruction feature requirements of the first fragment instruction stream are as follows: the probability of generating an instruction with the feature csr is 80%, the probability of having the feature plus is 20%, and the number of instructions is 5. The instruction feature requirements of the second fragment instruction stream are: generate instructions that have both the int and cal features but do not have the plus feature, and the number of instructions is 5. The instruction feature requirements of the third fragment instruction stream are: generate instructions that have both the float and logic features with a probability of 40%, and the probability of having the feature shift is 60%, and the number of instructions is 10.

[0080] According to the above-set instruction feature requirements, determine the target instruction sets corresponding to each instruction feature requirement.

[0081] Specifically, the instruction feature requirements of the first fragment instruction stream can correspond to two target instruction sets, SET_csr and SET_plus. All elements of the set SET_csr are all the to-be-matched instructions with the feature label csr:

[0082] SET_csr = {CSRRW, CSRRS, CSRRC}

[0083] All elements of the set SET_plus are all the to-be-matched instructions with the feature label plus:

[0084] SET_plus = {ADD,FADD_S,ADDI,ADDIW}

[0085] The instruction feature requirements of the second fragment instruction stream can correspond to one target instruction set SET_int_cal. All elements of this set are all the to-be-matched instructions that have both the feature labels int and cal but do not have the feature label plus:

[0086] SET_int_cal = {SUB, DIV, MUL, FSQRT_S}

[0087] The instruction feature requirements of the third fragment instruction stream can correspond to two target instruction sets, SET_float_logic and SET_shift. All elements of the set SET_float_logic are all the to-be-matched instructions with the feature label csr:

[0088] SET_float_logic = {ANDI, ORI, XORI}

[0089] All elements of the set SET_shift are all the to-be-matched instructions with the feature label shift:

[0090] SET_shift = {SLL, SLT, SLTI, SLLI, SRLI}

[0091] Finally, generate the instruction stream in sequence. First, generate the first segment of the instruction stream. When generating each instruction, first randomly select the target set. The probability of selecting the set SET_csr is 80%, and the probability of selecting the set SET_plus is 20%. After randomly selecting a target instruction set, then randomly select an instruction from the target instruction set, and the probability of selecting each instruction is the same. Repeat the above steps 5 times to obtain 5 target instructions. The process of generating the second segment of the instruction stream is as follows: directly randomly select 1 instruction from the target instruction set SET_int_cal, and repeat the above steps 5 times until 5 target instructions are selected. The process of generating the third segment of the instruction stream is as follows: select SET_float_logic with a probability of 40% and SET_shift with a probability of 60%. After randomly selecting a target instruction set, then randomly select 1 instruction from the target instruction set, and repeat the above steps 10 times until 10 target instructions are selected. Exemplarily, the finally generated first segment of the instruction stream, the second segment of the instruction stream, and the third segment of the instruction stream can be as Figure 3 shown.

[0092] Figure 4 is a schematic structural diagram of an instruction generation device provided by an embodiment of the present invention. As Figure 3 shown, the device may specifically include:

[0093] The first acquisition module 501 is configured to acquire the instruction generation requirement; the instruction generation requirement includes the instruction feature requirement and the instruction quantity;

[0094] The first determination module 502 is configured to determine, based on the feature tags corresponding to multiple to-be-matched instructions in the preset instruction set, the to-be-matched instruction that matches the instruction feature requirement in the preset instruction set, and obtain the target instruction set;

[0095] The first generation module 503 is configured to randomly generate target instructions that match the instruction quantity based on the target instruction set.

[0096] An embodiment of the present invention provides an instruction generation device, which obtains an instruction generation requirement; the instruction generation requirement includes an instruction feature requirement and the number of instructions; based on the feature tags corresponding to multiple to-be-matched instructions in a preset instruction set, determines the to-be-matched instructions that match the instruction feature requirement in the preset instruction set to obtain a target instruction set; and randomly generates target instructions that match the number of instructions based on the target instruction set. In this way, based on the instruction feature requirement, a target instruction set can be matched from the preset instruction set, and target instructions can be randomly generated based on the target instruction set, which can directly match the instruction feature requirement with the to-be-matched instructions according to the instruction generation requirement, without manually adjusting the parameters of the instruction generator one by one according to the instruction generation requirement to generate instructions. Therefore, on the premise of ensuring the randomness of the target instructions, manual errors are avoided by the method of matching the feature requirement with the feature tag, the accuracy of the instructions is improved, the complexity of instruction generation is reduced, and the efficiency of instruction generation is improved to a certain extent.

[0097] Optionally, when the number of the instruction feature requirements is at least two, the instruction generation requirement further includes the conditional probability corresponding to each instruction feature requirement; the first generation module 503 includes:

[0098] A first selection module, configured to randomly select an instruction set from at least two instruction sets corresponding to at least two instruction feature requirements as the target instruction set based on the conditional probability corresponding to each instruction feature requirement; the number of the instruction feature requirements is equal to the number of the instruction sets;

[0099] A first generation sub-module, configured to randomly generate target instructions from the target instruction set;

[0100] A first execution module, configured to restart the step of randomly selecting an instruction set from at least two instruction sets corresponding to at least two instruction feature requirements as the target instruction set based on the conditional probability corresponding to each instruction feature requirement until target instructions that match the number of instructions are generated.

[0101] Optionally, the device further includes:

[0102] A second acquisition module, configured to acquire a preset instruction set; the preset instruction set includes multiple to-be-matched instructions;

[0103] A second determination module, configured to determine the feature tags corresponding to each to-be-matched instruction based on the instruction features of each to-be-matched instruction.

[0104] Optionally, the first determination module 502 includes:

[0105] A first matching module, configured to match, for any to-be-matched instruction in the preset instruction set, a feature tag corresponding to the to-be-matched instruction with the instruction feature requirement;

[0106] A first adding module, configured to, when the feature tag corresponding to the to-be-matched instruction matches the instruction feature requirement, form a target instruction set based on the to-be-matched instruction.

[0107] Optionally, the instruction feature requirement includes a first requirement, a second requirement, and a third requirement. The first requirement is used to indicate generating an instruction having one or more first features. The second requirement is used to indicate generating an instruction having one or more first features and not having one or more second features. The third requirement is used to indicate generating an instruction not having one or more second features.

[0108] The present invention further provides an electronic device. Refer to Figure 5 , including: a processor 601, a memory 602, and a computer program 6021 stored on the memory and executable on the processor. When the processor executes the program, the instruction generation method of the foregoing embodiment is implemented.

[0109] The present invention further provides a readable storage medium. When instructions in the storage medium are executed by a processor of an electronic device, the electronic device is enabled to execute the instruction generation method of the foregoing embodiment.

[0110] For the apparatus embodiment, since it is basically similar to the method embodiment, the description is relatively simple. For related parts, refer to the partial description of the method embodiment.

[0111] The algorithms and displays provided herein are not inherently related to any particular computer, virtual system, or other device. Various general-purpose systems can also be used in conjunction with the teachings herein. The structure required to construct such a system will be apparent from the above description. In addition, the present invention is not directed to any particular programming language. It should be understood that the content of the present invention described herein can be implemented using various programming languages, and the description of the specific language above is for disclosing the best mode of the present invention.

[0112] In the specification provided herein, a large number of specific details are set forth. However, it can be understood that the embodiments of the present invention can be practiced without these specific details. In some instances, well-known methods, structures, and technologies have not been shown in detail so as not to obscure the understanding of this specification.

[0113] Similarly, it should be understood that, for the purpose of streamlining the present invention and assisting in understanding one or more of the various inventive aspects, in the foregoing description of the exemplary embodiments of the present invention, the various features of the present invention are sometimes grouped together into a single embodiment, figure, or description thereof. However, the disclosed method should not be construed as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as reflected in the following claims, the inventive aspects lie in less than all the features of the single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into the detailed description, with each claim standing on its own as a separate embodiment of the present invention.

[0114] Those skilled in the art will appreciate that the modules in the devices in the embodiments can be adaptively changed and disposed in one or more devices different from the embodiments. The modules or units or components in the embodiments can be combined into one module or unit or component, and in addition, they can be divided into multiple sub-modules or sub-units or sub-components. Except that at least some of such features and / or processes or units are mutually exclusive, any combination can be used to combine all the features disclosed in this specification (including the accompanying claims, abstract, and drawings) and all the processes or units of any method or device so disclosed. Unless otherwise expressly stated, each feature disclosed in this specification (including the accompanying claims, abstract, and drawings) can be replaced by an alternative feature that provides the same, equivalent, or similar purpose.

[0115] The various component embodiments of the present invention can be implemented in hardware, or in software modules running on one or more processors, or in a combination thereof. Those skilled in the art should understand that a microprocessor or a digital signal processor (DSP) can be used in practice to implement some or all of the functions of some or all of the components in the sorting device according to the present invention. The present invention can also be implemented as a device or apparatus program for performing part or all of the methods described herein. Such a program for implementing the present invention can be stored on a computer-readable medium, or can be in the form of one or more signals. Such signals can be downloaded from an Internet website, or provided on a carrier signal, or in any other form.

[0116] It should be noted that the above embodiments are illustrative of the present invention rather than restrictive thereof, and those skilled in the art can design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in the claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The present invention can be implemented by means of hardware including several different elements and by means of a suitably programmed computer. In a unit claim listing several devices, several of these devices may be embodied by the same item of hardware. The use of the words first, second, and third, etc. does not denote any order. These words may be interpreted as names.

[0117] Those skilled in the art can clearly understand that for the convenience and brevity of description, the specific working processes of the systems, devices, and units described above can refer to the corresponding processes in the foregoing method embodiments and will not be repeated here.

[0118] It should be pointed out that all actions of obtaining signals, information, or data in this application are carried out on the premise of complying with the corresponding data protection regulations and policies of the country where it is located and with the authorization given by the owner of the corresponding device.

[0119] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, and improvements made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

[0120] The above is only the specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed by the present invention and should be covered by the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A method for generating an instruction, characterized in that: The method comprises: Obtaining instruction generation requirements; the instruction generation requirements include at least two instruction feature requirements, conditional probabilities corresponding to the at least two instruction feature requirements, and the number of instructions, wherein the conditional probability is used to characterize the random generation probability for the instruction feature requirements when randomly generating instructions; For any of the instruction feature requirements, based on feature tags corresponding to a plurality of instructions to be matched in a preset instruction set, determine the instructions to be matched that match the instruction feature requirement in the preset instruction set, obtain an instruction set corresponding to the instruction feature requirement, and determine a target instruction set based on the conditional probabilities corresponding to each of the instruction feature requirements and the instruction sets corresponding to each of the instruction feature requirements; Based on the target instruction set, a target instruction matching the instruction quantity is randomly generated.

2. The method according to claim 1, characterized in that The determining of the target instruction set based on the conditional probabilities corresponding to the instruction feature requirements and the instruction sets corresponding to the instruction feature requirements includes: Based on the conditional probabilities corresponding to the instruction feature requirements, randomly selecting an instruction set from at least two instruction sets corresponding to at least two instruction feature requirements as the target instruction set; the number of the instruction feature requirements is equal to the number of the instruction sets; The randomly generating target instructions matching the number of instructions based on the target instruction set includes: randomly generating a target instruction from the target instruction set; Re-select an instruction set randomly from at least two instruction sets corresponding to at least two instruction feature requirements based on the conditional probability corresponding to each of the instruction feature requirements, and start executing from the target instruction set step until a target instruction matching the number of instructions is generated.

3. The method according to claim 1, characterized in that The method further comprises: Obtaining a preset instruction set; the preset instruction set includes a plurality of instructions to be matched; Based on the instruction features of each of the instructions to be matched, a feature label corresponding to each of the instructions to be matched is determined.

4. The method according to claim 3, characterized in that The step of determining, based on feature tags corresponding to a plurality of to-be-matched instructions in a preset instruction set, instructions to be matched that match the instruction feature requirement in the preset instruction set to obtain a target instruction set includes: For any of the to-be-matched instructions in the preset instruction set, matching the feature tag corresponding to the to-be-matched instruction with the instruction feature requirement; When the feature tag corresponding to the instruction to be matched successfully matches the instruction feature requirement, a target instruction set is formed based on the instruction to be matched.

5. The method according to claim 1, characterized in that: The instruction feature requirements include a first requirement, a second requirement, and a third requirement. The first requirement is used to indicate the generation of an instruction with one or more first features, the second requirement is used to indicate the generation of an instruction with one or more first features but not one or more second features, and the third requirement is used to indicate the generation of an instruction without one or more second features.

6. An instruction generating device, characterized in that: The device comprises: A first acquisition module is used to acquire instruction generation requirements; the instruction generation requirements include at least two instruction feature requirements, conditional probabilities corresponding to the at least two instruction feature requirements, and the number of instructions, the conditional probability being used to characterize the random generation probability for the instruction feature requirements when randomly generating instructions; A first determination module is used to determine, for any of the instruction feature requirements, an instruction to be matched that matches the instruction feature requirement in the preset instruction set based on feature tags corresponding to a plurality of instructions to be matched in the preset instruction set, obtain an instruction set corresponding to the instruction feature requirement, and determine a target instruction set based on conditional probabilities corresponding to each of the instruction feature requirements and the instruction set corresponding to each of the instruction feature requirements; The first generating module is used to randomly generate target instructions matching the instruction quantity based on the target instruction set.

7. The device according to claim 6, characterized in that In the case where the number of the instruction feature requirements is at least two, the instruction generation requirement further includes conditional probabilities corresponding to each of the instruction feature requirements; the first determination module includes: A first selection module is used to randomly select an instruction set from at least two instruction sets corresponding to at least two instruction feature requirements as a target instruction set based on the conditional probability corresponding to each of the instruction feature requirements; the number of the instruction feature requirements is equal to the number of the instruction sets; The first generating module comprises: A first generating submodule, used for randomly generating a target instruction from the target instruction set; The first execution module is used to randomly select an instruction set from at least two instruction sets corresponding to at least two instruction feature requirements based on the conditional probability corresponding to each of the instruction feature requirements, and start execution from the target instruction set step until a target instruction matching the number of instructions is generated.

8. The device according to claim 6, characterized in that The device also includes: A second acquisition module is used to acquire a preset instruction set; the preset instruction set includes a plurality of instructions to be matched; The second determination module is used to determine the feature label corresponding to each of the instructions to be matched based on the instruction feature of each of the instructions to be matched.

9. An electronic device, characterized in that: include: A processor, a memory, and a computer program stored in the memory and executable on the processor, wherein the processor implements the instruction generation method according to any one of claims 1 to 5 when executing the program.

10. A readable storage medium, characterized in that: When the instructions in the storage medium are executed by a processor of an electronic device, the electronic device is enabled to execute the instruction generation method described in any one of claims 1 to 5.

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