On-orbit SSD (Solid State Disk) data ground recovery method and device

Abstract

The invention discloses an on-orbit SSD (Solid State Disk) data ground recovery method, which comprises the following steps that: a HOST end communicates with a JTAG (Joint Test Action Group) interface of an SSD main control CPU (Central Processing Unit) through a GPIO (General Purpose Input / Output) pin and a simulated JTAG time sequence, controls the HOST end to enter a debugging mode and then controls an NIS (Network Interface Server) peripheral to read data from an NAND Flash, transmits the data to the HOST end through the JTAG interface, marks the physical address of the data and then downloads the data to the ground; the ground device forms a manufacturer-defined write instruction according with a front-end interface protocol of the in-orbit SSD according to the data and the physical address, issues the write instruction to the ground SSD, and writes the data into the ground SSD according to the physical address; and performing power-down restarting on the ground SSD to recover data from the on-orbit SSD. In an extreme space environment, under the condition that firmware codes cannot be operated by SSD equipment due to RAM device faults, it can still be guaranteed that the stored data of the SSD can be recovered on the ground.

Description

Technical Field

[0001] The present invention belongs to the field of aerospace, and in particular relates to a method and device for recovering on-orbit SSD (solid state hard disk) data on the ground. Background Art

[0002] With the surge in space data, solid-state drive (SSD) arrays are being widely used for satellite storage. Compared with traditional storage media, SSDs provide higher read and write speeds and better random access performance, allowing satellites to quickly process and transmit large amounts of data. In addition, the shock resistance and radiation resistance of SSDs enable them to perform well in the harsh space environment, ensuring data security and integrity. Storage solutions based on SSD arrays not only improve the efficiency of data storage, but also enhance the reliability and flexibility of satellite systems. By adopting SSD arrays, satellites can better meet the high requirements of modern scientific research and commercial applications for data processing, thereby promoting the development of space exploration and earth observation technology.

[0003] In the complex space environment, SSDs face various risks of damage, especially when the SSD main control RAM (random access memory) device suffers irreversible damage, the SSD firmware will not be able to run. In this case, the SSD can no longer exchange data with its corresponding HOST (host) through the front-end interface (serial ATA or NVME interface), so the previously stored data cannot be read out and the subsequent data cannot be written.

[0004] In the prior art, the solution to the damage of the SSD master RAM device is usually to replace the device. Since the master RAM device is a volatile memory device, it only serves as a storage medium when the SSD firmware code is running and a storage medium for data cache in the SSD. Therefore, when the master RAM device is damaged, the valid data stored in the NAND Flash array will not be destroyed, and the problem can be solved by replacing the damaged RAM device. Alternatively, when the RAM device is integrated in the master control, the SSD firmware can be re-run by replacing the master control, and the valid data in the SSD can be recovered by combining the common abnormal power-off recovery mechanism in the SSD firmware design.

[0005] However, the above-mentioned method of replacing components is not applicable to the aerospace field. Generally, the aerospace field's solution to the damage of SSD master control RAM components is to perform SSD array redundancy backup, and back up data by introducing a redundant number of SSDs. In this way, when the main SSD is damaged, it can be replaced by the backup SSD, thereby ensuring the reliability of data storage to a certain extent. However, in extreme scenarios, if both the main and backup SSD master control RAM components are damaged, the reliability of the data in the SSD cannot be guaranteed. Summary of the invention

[0006] In order to solve the above problems existing in the prior art, the present invention provides an on-orbit SSD data ground recovery method and device.

[0007] The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0008] A method for recovering data of an on-orbit SSD on the ground, wherein a HOST end corresponding to the on-orbit SSD is provided with a GPIO pin, and the GPIO pin is connected to a JTAG interface of a main control CPU of the on-orbit SSD;

[0009] The method comprises:

[0010] The HOST end communicates with the JTAG interface through the GPIO pin and the JTAG timing simulated based on the GPIO pin, and controls the master CPU to enter the debugging mode through the JTAG interface according to the SSD master CPU debugging architecture protocol, controls the master CPU to manipulate the NIS peripheral to read data from the NAND Flash of the on-orbit SSD, and transmits the data to the HOST end through the JTAG interface, marks the physical address of the read data in the NAND Flash, and transmits the data and the physical address to the ground;

[0011] The ground device forms a manufacturer-defined write instruction that complies with the front-end interface protocol of the on-orbit SSD according to the received data and physical address, and sends the manufacturer-defined write instruction to the ground SSD, so as to write the data into the ground SSD according to the physical address through the manufacturer-defined write instruction;

[0012] The ground SSD is powered off and restarted to recover the data from the on-orbit SSD in the ground SSD.

[0013] Optionally, the HOST end is provided with an FPGA chip, the GPIO pin is the GPIO pin of the FPGA chip, each operation performed by the HOST end is realized by executing a computer program by the FPGA chip, and the operation of simulating the JTAG timing is accelerated by a logic circuit realized by the FPGA chip;

[0014] Alternatively, the HOST end is provided with a CPU chip, the GPIO pins are the GPIO pins of the CPU chip, and various operations performed by the HOST end are implemented by executing a computer program through the CPU chip.

[0015] Optionally, the ground equipment includes: a first device and a second device;

[0016] The ground device forms a manufacturer-defined write instruction that complies with the front-end interface protocol of the on-orbit SSD according to the received data and the physical address, and sends the manufacturer-defined write instruction to the ground SSD, so as to write the data into the ground SSD according to the physical address through the manufacturer-defined write instruction, including:

[0017] The first device parses the received data and physical address, and after parsing, sends the data and physical address to the second device via Ethernet;

[0018] The second device converts the received data and physical address into a manufacturer-defined write instruction that complies with the front-end interface protocol of the on-orbit SSD, and sends the manufacturer-defined write instruction to the ground SSD to write the data into the ground SSD according to the physical address through the manufacturer-defined write instruction.

[0019] Optionally, the second device sends the manufacturer-customized write instruction to the ground SSD, including: sending the manufacturer-customized write instruction to the ground SSD through a serial ATA interface or a PCIe interface.

[0020] Optionally, the method is enabled when the HOST detects a failure of the on-track SSD.

[0021] The present invention also provides an on-orbit SSD data ground recovery device, wherein a HOST end corresponding to the on-orbit SSD is provided with a GPIO pin, and the GPIO pin is connected to a JTAG interface of a main control CPU of the on-orbit SSD;

[0022] The device comprises:

[0023] An on-orbit module is configured at the HOST end, and is used to communicate with the JTAG interface through the GPIO pin and the JTAG timing simulated based on the GPIO pin, and according to the SSD master CPU debugging architecture protocol, control the master CPU to enter the debugging mode through the JTAG interface, control the master CPU to manipulate the NIS peripheral to read data from the NAND Flash of the on-orbit SSD, and transmit the data to the HOST end through the JTAG interface, mark the physical address of the read data in the NAND Flash, and transmit the data and the physical address to the ground;

[0024] The ground module is configured on the ground and is used to form a manufacturer-defined write instruction that complies with the front-end interface protocol of the on-orbit SSD based on the received data and physical address, and send the manufacturer-defined write instruction to the ground SSD, so as to write the data into the ground SSD according to the physical address through the manufacturer-defined write instruction, so that the data from the on-orbit SSD can be restored after the ground SSD is powered off and restarted.

[0025] Optionally, the HOST end is provided with an FPGA chip, the GPIO pin is the GPIO pin of the FPGA chip, the on-track module is implemented by executing a computer program through the FPGA chip, and the operation of simulating the JTAG timing is accelerated by a logic circuit implemented by the FPGA chip;

[0026] Alternatively, the HOST end is provided with a CPU chip, the GPIO pin is the GPIO pin of the CPU chip, and the on-track module is implemented by executing a computer program through the CPU chip.

[0027] Optionally, the ground module includes: a data parsing unit and a protocol conversion unit;

[0028] The data parsing unit is used to parse the received data and physical address, and send the data and physical address to the protocol conversion unit after parsing;

[0029] The protocol conversion unit is used to convert data and physical addresses into manufacturer-defined write instructions that comply with the front-end interface protocol of the on-orbit SSD, and send the manufacturer-defined write instructions to the ground SSD so that the data can be written into the ground SSD according to the physical address through the manufacturer-defined write instructions.

[0030] Optionally, the protocol conversion unit sends the manufacturer-defined write instruction to the ground SSD, including: sending the manufacturer-defined write instruction to the ground SSD through a serial ATA interface or a PCIe interface.

[0031] Optionally, the data parsing unit is applied to a first device, the protocol conversion unit is applied to a second device, and the first device and the second device communicate via Ethernet.

[0032] The on-orbit SSD data ground recovery method provided by the present invention can ensure that the SSD stored data can be recovered on the ground when the SSD device cannot run the firmware code due to RAM device failure in extreme space environment, and can greatly recover the losses caused by data loss. Especially for SSD devices storing operating systems, their data recovery can help restore the system operating status on the ground, help problem analysis and avoid the loss of work / research results.

[0033] The present invention will be further described in detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 It is a flowchart of a method for recovering on-orbit SSD data on the ground provided by an embodiment of the present invention;

[0035] Figure 2It is an on-orbit design architecture in the on-orbit SSD data ground recovery method provided by an embodiment of the present invention;

[0036] Figure 3 It is a ground design architecture in the on-orbit SSD data ground recovery method provided by an embodiment of the present invention;

[0037] Figure 4 It is a structural schematic diagram of an on-orbit SSD data ground recovery device provided by an embodiment of the present invention;

[0038] Figure 5 yes Figure 4 Schematic diagram of the structure of the ground module in the device shown. DETAILED DESCRIPTION

[0039] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0040] With the gradual promotion of high-performance computer platforms deployed in satellite applications, SSDs no longer store single payload data, so not all data will be transmitted to the ground in the country. When the SSD master control RAM device fails, especially in extreme space environments, when the SSD device no longer has the ability to run the normal firmware code due to RAM device failure, a technology that can restore SSD data on the ground can greatly restore the operating status and data of the on-orbit high-energy computer platform and recover the losses caused by data loss in extremely harsh conditions.

[0041] In order to achieve the above-mentioned purpose, an embodiment of the present invention provides a method for ground recovery of on-orbit SSD data. At the beginning of satellite design, the method connects the GPIO pin of the HOST end corresponding to the on-orbit SSD with the JTAG interface of the main control CPU of the on-orbit SSD in hardware. Usually, the HOST end and the on-orbit SSD communicate through the front-end interface (serial ATA or NVME interface). In the embodiment of the present invention, the GPIO pin of the HOST end is additionally connected to the JTAG interface of the main control CPU of the on-orbit SSD for use in data recovery.

[0042] See also Figure 1 As shown, the on-orbit SSD data ground recovery method provided by the embodiment of the present invention includes the following steps:

[0043] S10. The HOST end communicates with the JTAG interface of the master CPU through the GPIO pin and the JTAG timing simulated based on the GPIO pin. According to the SSD master CPU debugging architecture protocol, the master CPU is controlled to enter the debugging mode through the JTAG interface, and the master CPU controls the NIS peripheral to read data from the NAND Flash of the on-orbit SSD, and transmits it to the HOST end through the JTAG interface, marking the physical address of the read data in the NAND Flash, and transmitting the data and physical address to the ground.

[0044] Specifically, since the GPIO pins on the HOST side are connected to the JTAG interface of the main control CPU, a hardware connection path for the HOST side to communicate with the main control CPU is formed. On this basis, by performing program coding on the HOST side to simulate the JTAG timing and control the signal level changes on the GPIO pins, the HOST side and the main control CPU can communicate through the JTAG protocol. In this way, the HOST side can send control instructions to the main control CPU according to the SSD main control CPU debugging architecture protocol, control the main control CPU to enter the debug mode, and control the main control CPU to control the NIS peripherals that are also located on the main control chip of the on-orbit SSD. Specifically, the main control chip of the on-orbit SSD contains the main control CPU and various peripherals. These peripherals communicate with the CPU through a bus. These peripherals include NAND Flash Interfaces (NIS) peripherals, also known as NIS controllers. Therefore, when the main control CPU is controlled by the HOST end, it no longer fetches and executes instructions from the RAM storing the SSD firmware program according to the original process, but obeys the control of the HOST end to control the NIS peripherals also located on the main control chip of the on-orbit SSD. Then, the HOST end can read out the data in the NAND Flash array of the on-orbit SSD through the NIS peripherals in sequence, and store them in the valid RAM resources of the on-orbit SSD except for the firmware program, and then transmit the data from the valid RAM resources to the HOST end through the JTAG interface. It should be noted that even if the RAM resources occupied by the SSD firmware may have failed, there are still other RAM resources that have not failed in the main control chip of the on-orbit SSD, so the data read from the NAND Flash array can be stored in this part of the valid RAM resources. Then, the HOST end marks the read data with a physical address, where the physical address includes the location of the NAND Flash in the NAND Flash array and the location of the data in the NAND Flash. Finally, the HOST end transmits the data and physical address to the ground in the territory.

[0045] S20. The ground device generates a manufacturer-defined write instruction that complies with the front-end interface protocol of the on-orbit SSD based on the received data and physical address, and sends the manufacturer-defined write instruction to the ground SSD to write the data into the ground SSD according to the physical address through the manufacturer-defined write instruction.

[0046] Specifically, the ground equipment obtains the data and the marked physical address, parses it and converts it into a write instruction that complies with the front-end interface protocol of the SSD, and sends it to the ground SSD. Among them, the ground SSD is the same model as the on-orbit SSD. The write instruction is a manufacturer-specific custom instruction provided by the manufacturer, which is mainly used to implement write operations that support direct addressing of the NAND Flash array and the physical address of the NAND Flash, thereby improving the efficiency of data replication. There are many ways for the ground equipment to send the manufacturer's customized write instructions to the ground SSD. For example, the manufacturer's customized write instructions can be sent to the ground SSD through the serial ATA interface or the PCIe (Peripheral Component Interconnect Express) interface.

[0047] S30 , power off and restart the ground SSD to restore the data from the on-orbit SSD in the ground SSD.

[0048] It is understandable that since the ground SSD and the on-orbit SSD are of the same model, the data in the NAND FLASH array of the ground SSD is empty. Therefore, after writing all the data stored in the NAND FLASH array of the on-orbit SSD, the ground SSD is powered off and restarted, and the data recovery can be completed using the common abnormal power-off recovery mechanism in the firmware.

[0049] The on-orbit SSD data ground recovery method provided by the embodiment of the present invention can ensure that the SSD stored data can be recovered on the ground when the SSD device cannot run the firmware code due to RAM device failure in extreme space environment, and can greatly recover the losses caused by data loss. In particular, for SSD devices storing operating systems, data recovery can help restore the system operating status on the ground, help problem analysis, and avoid the loss of work / research results.

[0050] In one embodiment, the HOST end is provided with an FPGA chip, the GPIO pins of the HOST end are the GPIO pins of the FPGA chip, and various operations performed by the HOST end are implemented by executing computer programs through the FPGA chip, and the operations simulating JTAG timing are accelerated by the logic circuit implemented by the FPGA chip.

[0051] Specifically, Figure 2As shown, the GPIO pins of the FPGA are connected to the JTAG pins of the on-track SSD master CPU, and a computer program that complies with the JTAG standard and the on-track SSD master CPU debugging architecture protocol is developed on the FPGA to enable the FPGA to control the on-track SSD master CPU to enter the debugging mode through the JTAG interface, thereby having the function of controlling the on-track SSD master CPU. On this basis, the driver related to the SSD NIS peripheral is transplanted on the FPGA, and the underlying operations of reading and writing the NIS peripheral registers or reading and writing the master CPU address space are replaced by the FPGA controlling the master CPU through the JTAG interface to achieve the function of the FPGA controlling the NIS peripheral to access the NAND Flash of the on-track SSD by controlling the master CPU, and transmitting the data to the HOST end through the JTAG interface, forming a Figure 1 The NAND data acquisition module is shown in FIG. Then, the physical address of the NAND Flash is marked at the application layer to record the physical address of the read data stored in the NAND Flash, so as to facilitate data replication on the ground. Finally, the data is transmitted to the ground to form a Figure 2 The data tag download module shown in .

[0052] It is worth mentioning that among the various operations performed by the HOST end, the operation of simulating JTAG timing belongs to the underlying logic, which can be implemented by configuring the logic circuit of the FPGA. Therefore, the operation of simulating JTAG timing can be accelerated by the logic circuit implemented in the FPGA chip.

[0053] In one embodiment, the HOST end is provided with a CPU chip, and the GPIO pins of the HOST end are the GPIO pins of the CPU chip, and the various operations performed by the HOST end are implemented by the CPU chip executing a computer program. Among them, the operation of simulating the JTAG timing is also implemented by the CPU chip executing a computer program. Different from the previous embodiment, the operation of simulating the JTAG timing here is simulated by software logic. Due to the limitation of the CPU frequency of the CPU chip, the JTAG interface frequency simulated by software logic is not as high as in the previous embodiment. Therefore, in the previous embodiment, the acceleration of the logic circuit in the FPGA chip can effectively increase the JTAG interface frequency and improve the data transmission performance.

[0054] In one embodiment, the ground device includes: a first device and a second device; accordingly, the ground device forms a manufacturer-defined write instruction that complies with the front-end interface protocol of the on-orbit SSD according to the received data and the physical address, and sends the manufacturer-defined write instruction to the ground SSD to write the data into the ground SSD according to the physical address, including:

[0055] (1) The first device parses the received data and physical address, and after parsing, sends the data and physical address to the second device via Ethernet;

[0056] (2) The second device converts the received data and physical address into a manufacturer-defined write instruction that complies with the front-end interface protocol of the on-orbit SSD, and sends the manufacturer-defined write instruction to the ground SSD to write the data into the ground SSD according to the physical address.

[0057] In this embodiment, if Figure 3 As shown, the hardware body on the ground includes three parts: a first device, a second device, and a ground SDD. The first device communicates with the second device via Ethernet, and the second device performs manufacturer-defined write instruction operations on the SSD through a common SSD front-end interface to complete the replication of the on-orbit data. The first device mainly implements the analysis of the on-orbit data after it is transmitted down, and sends the data and the physical address in the NAND Flash array where it is located to the second device via Ethernet. The second device mainly converts the first sent data and physical address into a manufacturer-defined write instruction that complies with the SSD front-end interface protocol, and sends it to the ground SSD.

[0058] In practical applications, both the first device and the second device may be computers, but the present invention is not limited thereto.

[0059] The method provided by the embodiment of the present invention is preferably enabled when the HOST detects a fault in the on-orbit SSD. Specifically, under normal working conditions, the HOST will send instructions to the on-orbit SDD to access reading, writing and other functions. During this process, if the on-orbit SDD does not respond for many times, it means that there is a fault in the on-orbit SDD. At this time, the HOST can enable the method provided by the embodiment of the present invention, so as to cooperate with the ground equipment to recover the data in the on-orbit SDD on the ground.

[0060] Based on the same inventive concept, an embodiment of the present invention further provides an on-orbit SSD data ground recovery device, wherein the HOST end corresponding to the on-orbit SSD is provided with a GPIO pin, and the GPIO pin is connected to the JTAG interface of the main control CPU of the on-orbit SSD; Figure 4 As shown, the on-orbit SSD data ground recovery device provided by the embodiment of the present invention includes: an on-orbit module 1 and a ground module 2.

[0061] The on-orbit module 1 is configured at the HOST end, and is used to communicate with the JTAG interface through the GPIO pin and the JTAG timing simulated based on the GPIO pin, and according to the SSD master CPU debugging architecture protocol, control the master CPU to enter the debugging mode through the JTAG interface, control the master CPU to manipulate the NIS peripheral to read data from the NAND Flash of the on-orbit SSD, and transmit it to the HOST end through the JTAG interface, mark the physical address of the read data in the NAND Flash, and transmit the data and the physical address to the ground;

[0062] The ground module 2 is configured on the ground and is used to form a manufacturer-defined write instruction that complies with the front-end interface protocol of the on-orbit SSD based on the received data and physical address, and send the manufacturer-defined write instruction to the ground SSD, so as to write the data into the ground SSD according to the physical address through the manufacturer-defined write instruction, so that the data from the on-orbit SSD can be restored after the ground SSD is powered off and restarted.

[0063] Optionally, the HOST end is provided with an FPGA chip, the GPIO pins are the GPIO pins of the FPGA chip, the on-track module is implemented by executing a computer program through the FPGA chip, and the operation of simulating the JTAG timing is accelerated by a logic circuit implemented by the FPGA chip. Alternatively, the HOST end is provided with a CPU chip, the GPIO pins are the GPIO pins of the CPU chip, and the on-track module is implemented by executing a computer program through the CPU chip.

[0064] Optionally, as in Figure 5 As shown in , the ground module 2 includes: a data parsing unit 201 and a protocol conversion unit 202;

[0065] The data parsing unit 201 is used to parse the received data and physical address, and send the data and physical address to the protocol conversion unit 202 after parsing;

[0066] The protocol conversion unit 202 is used to convert data and physical addresses into manufacturer-defined write instructions that comply with the front-end interface protocol of the on-orbit SSD, and send the manufacturer-defined write instructions to the ground SSD to write the data into the ground SSD according to the physical address through the manufacturer-defined write instructions.

[0067] Optionally, the protocol conversion unit sends the manufacturer-defined write instruction to the ground SSD, including: sending the manufacturer-defined write instruction to the ground SSD through a serial ATA interface or a PCIe interface.

[0068] In the embodiment of the present invention, the data parsing unit 201 and the protocol conversion unit 202 are both functional modules formed by writing computer programs, and they can be applied to the same electronic device (such as a computer) at the same time, or they can be applied to different electronic devices respectively.

[0069] Optionally, the data parsing unit is applied to the first device, the protocol conversion unit is applied to the second device, and the first device and the second device communicate via Ethernet. Thus, after the data parsing unit 201 in the first device completes the parsing of the data and the physical address, the first device can send the data and the physical address to the protocol conversion unit 202 in the second device via Ethernet.

[0070] The on-orbit SSD data ground recovery device provided by the embodiment of the present invention can ensure that the SSD stored data can be recovered on the ground when the SSD device cannot run the firmware code due to RAM device failure in extreme space environment, and can greatly recover the losses caused by data loss. In particular, for SSD devices storing operating systems, data recovery can help restore the system operating status on the ground, help problem analysis, and avoid the loss of work / research results.

[0071] It should be noted that, for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0072] It should be noted that the terms "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Instead, they are merely examples of devices and methods consistent with some aspects of the present invention.

[0073] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification.

[0074] Although the present invention is described herein in conjunction with various embodiments, in the process of implementing the claimed invention, those skilled in the art can understand and implement other changes to the disclosed embodiments by viewing the drawings and the disclosed content. In the description of the present invention, the term "comprising" does not exclude other components or steps, "one" or "an" does not exclude multiple situations, and "multiple" means two or more, unless otherwise clearly and specifically limited. In addition, certain measures are recorded in different embodiments, but this does not mean that these measures cannot be combined to produce good results.

[0075] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, devices (equipment), or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware, which are collectively referred to as "modules" or "systems" herein. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes. The computer program is stored / distributed in a suitable medium, provided together with other hardware or as part of the hardware, or may take other distribution forms, such as through the Internet or other wired or wireless telecommunications systems.

[0076] The present invention is described with reference to the flowcharts and / or block diagrams of the methods, apparatuses (devices) and computer program products of the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0077] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0078] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0079] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A method for recovering on-orbit SSD data on the ground, characterized in that: A GPIO pin is provided at the HOST end corresponding to the on-track SSD, and the GPIO pin is connected to the JTAG interface of the main control CPU of the on-track SSD; The method comprises: The HOST end communicates with the JTAG interface through the GPIO pin and the JTAG timing simulated based on the GPIO pin, and controls the master CPU to enter the debugging mode through the JTAG interface according to the SSD master CPU debugging architecture protocol, controls the master CPU to manipulate the NIS peripheral to read data from the NAND Flash of the on-orbit SSD, and transmits the data to the HOST end through the JTAG interface, marks the physical address of the read data in the NAND Flash, and transmits the data and the physical address to the ground; The ground device forms a manufacturer-defined write instruction that complies with the front-end interface protocol of the on-orbit SSD according to the received data and physical address, and sends the manufacturer-defined write instruction to the ground SSD, so as to write the data into the ground SSD according to the physical address through the manufacturer-defined write instruction; The ground SSD is powered off and restarted to recover the data from the on-orbit SSD in the ground SSD.

2. The on-orbit SSD data ground recovery method according to claim 1, characterized in that: The HOST end is provided with an FPGA chip, the GPIO pin is the GPIO pin of the FPGA chip, various operations performed by the HOST end are realized by executing a computer program through the FPGA chip, and the operation of simulating the JTAG timing is accelerated by a logic circuit realized by the FPGA chip; Alternatively, the HOST end is provided with a CPU chip, the GPIO pins are the GPIO pins of the CPU chip, and various operations performed by the HOST end are implemented by executing a computer program through the CPU chip.

3. The on-orbit SSD data ground recovery method according to claim 1, characterized in that: The ground equipment includes: a first device and a second device; The ground device forms a manufacturer-defined write instruction that complies with the front-end interface protocol of the on-orbit SSD according to the received data and the physical address, and sends the manufacturer-defined write instruction to the ground SSD, so as to write the data into the ground SSD according to the physical address through the manufacturer-defined write instruction, including: The first device parses the received data and physical address, and after parsing, sends the data and physical address to the second device via Ethernet; The second device converts the received data and physical address into a manufacturer-defined write instruction that complies with the front-end interface protocol of the on-orbit SSD, and sends the manufacturer-defined write instruction to the ground SSD to write the data into the ground SSD according to the physical address through the manufacturer-defined write instruction.

4. The on-orbit SSD data ground recovery method according to claim 3, characterized in that: The second device sends the manufacturer-defined write instruction to the ground SSD, including: sending the manufacturer-defined write instruction to the ground SSD through a serial ATA interface or a PCIe interface.

5. The on-orbit SSD data ground recovery method according to claim 1, characterized in that: The method is enabled when the HOST detects a failure of the on-track SSD.

6. An on-orbit SSD data ground recovery device, characterized in that: A GPIO pin is provided at the HOST end corresponding to the on-track SSD, and the GPIO pin is connected to the JTAG interface of the main control CPU of the on-track SSD; The device comprises: An on-orbit module is configured at the HOST end, and is used to communicate with the JTAG interface through the GPIO pin and the JTAG timing simulated based on the GPIO pin, and according to the SSD master CPU debugging architecture protocol, control the master CPU to enter the debugging mode through the JTAG interface, control the master CPU to manipulate the NIS peripheral to read data from the NAND Flash of the on-orbit SSD, and transmit the data to the HOST end through the JTAG interface, mark the physical address of the read data in the NAND Flash, and transmit the data and the physical address to the ground; The ground module is configured on the ground and is used to form a manufacturer-defined write instruction that complies with the front-end interface protocol of the on-orbit SSD based on the received data and physical address, and send the manufacturer-defined write instruction to the ground SSD, so as to write the data into the ground SSD according to the physical address through the manufacturer-defined write instruction, so that the data from the on-orbit SSD can be restored after the ground SSD is powered off and restarted.

7. The on-orbit SSD data ground recovery device according to claim 6, characterized in that: The HOST end is provided with an FPGA chip, the GPIO pin is the GPIO pin of the FPGA chip, the on-track module is implemented by executing a computer program through the FPGA chip, and the operation of simulating the JTAG timing is accelerated by a logic circuit implemented by the FPGA chip; Alternatively, the HOST end is provided with a CPU chip, the GPIO pin is the GPIO pin of the CPU chip, and the on-track module is implemented by executing a computer program through the CPU chip.

8. The on-orbit SSD data ground recovery device according to claim 6, characterized in that: The ground module includes: a data parsing unit and a protocol conversion unit; The data parsing unit is used to parse the received data and physical address, and send the data and physical address to the protocol conversion unit after parsing; The protocol conversion unit is used to convert data and physical addresses into manufacturer-defined write instructions that comply with the front-end interface protocol of the on-orbit SSD, and send the manufacturer-defined write instructions to the ground SSD so that the data can be written into the ground SSD according to the physical address through the manufacturer-defined write instructions.

9. The on-orbit SSD data ground recovery device according to claim 8, characterized in that: The protocol conversion unit sends the manufacturer-defined write instruction to the ground SSD, including: sending the manufacturer-defined write instruction to the ground SSD through a serial ATA interface or a PCIe interface.

10. The on-orbit SSD data ground recovery device according to claim 8, characterized in that: The data parsing unit is applied to a first device, the protocol conversion unit is applied to a second device, and the first device and the second device communicate via Ethernet.

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