Server motherboard, server, bandwidth acquisition method, product, device and medium

Abstract

The present application discloses a server motherboard, a server, a bandwidth acquisition method, a product, a device and a medium, relating to the technical field of server interface control. The server motherboard includes a bandwidth allocation identification component provided for a bus device slot. The bandwidth allocation identification component can identify the bandwidth allocation situation of the corresponding bus device slot and is available for query by a processor. Thus, automatic identification and allocation of bandwidth resources are realized based on the bandwidth allocation identification component, without occupying any resources of GPIO, solving the technical problem of designing a GPIO identification circuit to make a bandwidth allocation table with low allocation efficiency, and achieving the technical effects of not occupying GPIO resources, saving the use of GPIO, and improving the allocation efficiency.

Description

Technical Field

[0001] The present application relates to the technical field of server interface control, and particularly to a server motherboard, a server, a bandwidth acquisition method, a product, a device, and a medium. Background Art

[0002] In the field of servers, with the rapid development of hardware technology, the data transfer speed and bandwidth requirements between the CPU (Central Processing Unit) and PCIe (Peripheral Component Interconnect Express) devices are constantly increasing.

[0003] The PICe interfaces on the server motherboard generally use PCIe x8 slots and PCIe x16 slots, which are convenient for plugging in different types of expansion cards in the later stage. Even if the gold fingers on the expansion card are x2 or x4, they can still be plugged into the PCIe x8 slot or the PCIe x16 slot. In the related art, in the method of automatically identifying and allocating bandwidth by PCIe, the dynamic configuration of bandwidth can be based on a GPIO (General Purpose Input Output) chip, but it requires occupying GPIO resources and adding a bandwidth allocation table in the detection and allocation program, resulting in low bandwidth allocation efficiency. Summary of the Invention

[0004] The present application provides a server motherboard, a server, a bandwidth acquisition method, a product, a device, and a medium, so as to at least solve the problem of low allocation efficiency in the related art that a GPIO recognition circuit needs to be designed to make a bandwidth allocation table.

[0005] The present application provides a server motherboard, including: a bus device slot configured on the server motherboard;

[0006] The server motherboard further includes a bandwidth allocation identification component provided for the bus device slot, and the bandwidth allocation identification component is connected to the processor; the bandwidth allocation identification component is configured to identify the bandwidth allocation situation of the bus device slot and provide it for the processor to query.

[0007] The present application further provides a server, including: any one of the above server motherboards.

[0008] The present application further provides a bandwidth acquisition method, implemented based on any one of the above server motherboards; the method includes:

[0009] Polling and addressing the bandwidth allocation identification component configured for the bus device slot;

[0010] Based on the response of the bandwidth allocation identification component, obtain the bandwidth allocation situation of the corresponding bus device slot.

[0011] This application also provides an electronic device, including: a memory for storing a computer program; a processor for implementing the steps of any of the above bandwidth acquisition methods when executing the computer program.

[0012] This application also provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above bandwidth acquisition methods are implemented.

[0013] This application also provides a computer program product, including a computer program. When the computer program is executed by a processor, the steps of any of the above bandwidth acquisition methods are implemented.

[0014] Through this application, since a bandwidth allocation identification component is set for the bus device slot, this bandwidth allocation identification component can identify the bandwidth allocation situation of the corresponding bus device slot and can be queried by the processor. Thus, automatic identification and allocation of bandwidth resources are realized based on the bandwidth allocation identification component, without occupying any GPIO resources, solving the technical problem of the need to design a GPIO identification circuit for making a bandwidth allocation table with low allocation efficiency, achieving the technical effects of not occupying GPIO resources, saving the use of GPIO, and improving the allocation efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] To more clearly illustrate the embodiments of this application, the following will briefly introduce the drawings required in the embodiments. Obviously, the drawings in the following description are only some embodiments of this application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0016] Figure 1 A schematic structural diagram of a server motherboard provided by an embodiment of this application;

[0017] Figure 2 A schematic structural diagram of a programmable device provided by an embodiment of this application;

[0018] Figure 3 A schematic addressing process diagram of a programmable device provided by an embodiment of this application;

[0019] Figure 4 A schematic structural diagram of a server provided by an embodiment of this application;

[0020] Figure 5 A schematic process diagram of a bandwidth acquisition method provided by an embodiment of this application;

[0021] Figure 6 Schematic flowchart of another bandwidth acquisition method provided by an embodiment of the present application;

[0022] Figure 7 Schematic structural diagram of a bandwidth acquisition device provided by an embodiment of the present application. Detailed implementation manners

[0023] Next, the technical solutions in the embodiments of the present application will be clearly and completely described with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0024] It should be noted that in the description of the present application, the terms "including", "comprising" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements but also includes other elements not explicitly listed, or further includes elements inherent to such process, method, article or device. The terms "first", "second", etc. in the present application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0025] To enable those skilled in the art of the present technology to better understand the solution of the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific implementation manners.

[0026] Combined with the specific application environment architecture or specific hardware architecture on which the execution of the bandwidth acquisition method depends, the specific application environment architecture or specific hardware architecture will be described herein.

[0027] The bandwidth acquisition method provided by the embodiment of the present application is essentially an automatic addressing acquisition method for the bandwidth of the server CPU bus device slot (such as a PCIe slot) based on a bandwidth allocation identification component (such as a programmable device, specifically an FPGA (Field Programmable Gate Array)). Among them, by setting a bandwidth allocation identification component (such as a programmable device, specifically an FPGA chip) for each bus device slot (including standard PCIe slots on the server motherboard and also including standard PCIe slots on the adapter card connected to the server motherboard), the bandwidth allocation identification component can identify the bandwidth allocation situation of the corresponding bus device slot and is available for the processor to query. Thus, the processor can realize the automatic identification and allocation of bandwidth resources based on the bandwidth allocation identification component, without occupying any resources of the GPIO, saving the use of the GPIO and improving the bandwidth allocation efficiency.

[0028] The following first explains the technical contents related to FPGA and PCIe.

[0029] FPGA is a chip that can re-edit its internal structure to achieve the purpose of use. FPGA emerged as a semi-custom circuit in the field of application-specific integrated circuits. It not only solves the shortcomings of custom circuits, but also overcomes the shortcomings of the limited number of gate circuits of the original programmable devices. FPGA has higher integration, stronger logic functions and greater flexibility.

[0030] FPGA is widely used in many fields, such as communications, electronics, video signal processing, aerospace, etc., and has launched many powerful products with the advantages of low cost, low power consumption and high performance.

[0031] In recent years, with the rise of 5G, autonomous driving, AI and big data technologies, FPGA has ushered in new development opportunities.

[0032] FPGA has advantages in processing efficiency and flexibility in the field of AI. In the future, it will usher in new growth with the development of A1 technology. It includes many categories, such as robots, speech recognition, image recognition, natural language processing and expert systems. The market potential of FPGA cannot be underestimated.

[0033] At the same time, how to improve the programmability of FPGA has always been the focus of industry research. Programmability here refers to both the flexibility of hardware and the ease of use at the software level. Therefore, the architecture of FPGA is also constantly being renovated and upgraded.

[0034] The technical solution provided by the embodiments of the present application is based on the application design of FPGA, so that the FPGA chip can identify the bandwidth allocation status of the bus device slot (such as the PCIe slot), thereby facilitating the processor to automatically address and obtain and allocate bandwidth, thereby reducing the occupancy of GPIO and improving the efficiency of bandwidth allocation.

[0035] PCIe has made fundamental changes in bus structure, which are mainly reflected in two aspects: first, it changes from parallel bus to serial bus; second, it adopts point-to-point interconnection. The bus connecting the devices under the bridge in the original parallel bus structure is changed into a link. A link can contain one or more channels. Each channel consists of two pairs of differential signal lines to form a dual-simplex serial transmission channel. There are no dedicated data, address, control and clock lines. Various transactions on the bus are organized into information packets for transmission. Another feature of PCIe that breaks through the traditional bus is the point-to-point interconnection method. Each device is connected by an independent link and has exclusive bandwidth. This is an effective solution to improve the transmission rate.

[0036] The PCIe bus structure treats a link as a bus, thus maintaining compatibility with the traditional PCI bus in terms of address space, configuration mechanism and software. One PCIe device occupies one bus (link), so there are many bridges and buses in a PCIe-based computer. Traditional PCI devices can also run on the PCIe platform. Through the PCIe to PCI (or PCI-X) bridge, the PCI (or PCI-X) bus can be brought out, and traditional PCI devices can be integrated into the PCI Express structure by hanging on such a bus. In related technologies, the CPU and motherboard can increase support for PCIe4.0; or, PCIe 5.0 can be provided and fully backward compatible with 4.0 and 3.0 devices; or, up to 16 CPU PCIe 5.0 channels and up to 4 CPU PCIe 4 channels can be provided; or, up to 20 CPU PCIe 4.0 channels can be provided.

[0037] PCIe (Peripheral Component Interconnect Express) is a high-speed serial computer expansion card standard, mainly used to connect the CPU and various expansion cards, such as graphics cards, sound cards, and network adapters. The bandwidth of PCIe is closely related to its version and the number of lanes.

[0038] Here are the details of the different versions of PCIe and their bandwidth:

[0039] PCIe 1.0: The online bit transfer rate is 2.5Gb / s, using 8 / 10 encoding, so the bandwidth of PCIe 1.0x1 is 250MB / s.

[0040] PCIe 2.0: The online bit transfer rate is doubled to 5Gb / s, using 8 / 10 encoding, so the bandwidth of PCIe 2.0x 1 is 500MB / s.

[0041] PCIe 3.0: The online bit transfer rate is 8Gb / s, using 128 / 130 encoding, so the bandwidth of PCIe 3.0x 1 is 1GB / s.

[0042] PCIe 4.0: The online bit transfer rate is increased to 16GT / s.

[0043] PCIe 5.0: The online bit transfer rate can reach up to 32GT / s.

[0044] In addition, the bandwidth of PCIe is also related to the number of its lanes (Lanes). For example, the theoretical maximum bandwidth of a PCIe x1 slot is 1GB / s, which is suitable for devices with low requirements for data transmission; the theoretical maximum bandwidth of a PCIe x4 slot is 4GB / s, which is suitable for devices with medium bandwidth requirements; the theoretical maximum bandwidth of a PCIe x8 slot is 8GB / s, which is suitable for devices with higher requirements for data transmission speed; the PCIe x16 slot has the highest theoretical maximum bandwidth of 16GB / s and is widely used to connect high-performance graphics cards.

[0045] The PICe interfaces on server motherboards generally use PCIe x8 slots and PCIe x16 slots, which are convenient for plugging in different types of expansion cards in the later stage. Even if the gold fingers on the expansion card are x2 or x4, they can still be plugged into the PCIe x8 slot or the PCIe x16 slot. However, in related technologies, the bandwidth directly provided by the CPU to the PCIe x8 slot and the PCIe x16 slot is the maximum bandwidth. When an expansion card with a small number of inserted lanes is inserted, it cannot be effectively recognized, and the CPU still allocates the maximum bandwidth, resulting in waste of PCIe resources and loss of CPU functions. For example, two PCIE X8 devices are inserted into two PCIE X16 slots, but it is impossible to support two X8 devices in one X16 slot; automatic recognition and bandwidth allocation of PCIe cannot be achieved.

[0046] In response to this, a method for automatically recognizing and allocating the bandwidth of PCIe has been proposed in related technologies. The specific methods that can be adopted include two: one is to use a PCA9555 GPIO expansion chip to replace GPIO for dynamic configuration of the bandwidth; the other is to use a physical detection method of controlling current or voltage by detecting the resistance on the circuit board to determine the required bandwidth. However, both of the above methods require adding a bandwidth allocation table in the detection and allocation program. After the expansion chip detection or physical resistance detection obtains the changed data, it is necessary to match the numerical value with the corresponding number of lanes in the pre-set bandwidth allocation table, and then the CPU analyzes the corresponding bandwidth for allocation. In the early stage, it is necessary to statistically simulate and build a table for different expansion cards. The type numbers of the corresponding expansion cards are fixed. After inserting the data of an expansion card not in the table, there will be recognition errors, and it is necessary to match the table during use, resulting in low efficiency of overall recognition and allocation of bandwidth. In addition, the bandwidth can also be allocated by the level of the pin on the PCIe device side, but there are also situations where the allocation is not refined and accurate.

[0047] Meanwhile, due to the large number of server models and many customer customization requirements, the diversity of the connection forms of the server CPU PCIe ports is extremely complex. The connections between the CPU PCIe ports on different motherboards and devices and riser cards are not the same, and the PCIe port distribution inside the clips of the riser cards themselves is also diverse. For each model and each customized shipment configuration BIOS (Basic Input Output System), separate development and adaptation need to be carried out according to the motherboard PCIe port topology and the PCIe port topologies of several riser cards matched with the motherboard, resulting in extremely cumbersome development of the server firmware for a specific configuration and affecting the customization development and mass production efficiency of server products.

[0048] To address at least one of the above technical problems, embodiments of the present application provide a scheme for automatically addressing and obtaining the bandwidth of the server CPU PCIe slot based on FPGA chip application design. Among them, the FPGA chip sets the pin levels for the PCIe slot bandwidth to be used as a bandwidth allocation identification component capable of identifying the slot bandwidth allocation situation. This bandwidth allocation identification component can identify the bandwidth allocation situation of the bus device slot, and this bandwidth allocation identification component is connected to the processor and can supply the processor to obtain the bandwidth allocation situation based on automatic addressing and then perform bandwidth allocation. It does not require the participation of GPIO, does not occupy the resources of GPIO, and does not require table lookup and comparison, improving the bandwidth allocation efficiency.

[0049] In some embodiments, the bus device slot can be a standard PCIe slot configured in the server, specifically, it can be a standard PCIe slot on the server motherboard or a standard PCIe slot on the riser card connected to the server motherboard, so as to adapt to various different PCIe port topologies, simplify the server firmware development process, facilitate server product customization, and improve the mass production efficiency.

[0050] Exemplarily, Figure 1 is a schematic structural diagram of a server motherboard provided by an embodiment of the present application. Refer to Figure 1 , the server motherboard 10 may include: a bus device slot 11 configured on the server motherboard 10; the server motherboard 10 further includes a bandwidth allocation identification component 12 provided for the bus device slot 11, and the bandwidth allocation identification component 12 is connected to the processor 100; the bandwidth allocation identification component 12 is configured to identify the bandwidth allocation situation of the bus device slot 11 and supply it for the processor 100 to query.

[0051] Among them, the bus device slot 11 configured on the server motherboard 10 is used to connect a bus device and a processor 100. Exemplarily, the bus device slot can be a standard PCIe slot of the server. The standard PCIe slot of the server can be a standard PCIe slot on the server motherboard or a standard PCIe slot on an adapter card. The bus device can include expansion cards such as a graphics card, a network card, and a sound card, which is not limited herein.

[0052] Among them, the bandwidth allocation identification component 12 configured for the bus device slot 11 can identify the bandwidth allocation situation of the bus device slot 11 and provide it for the processor 100 to address and query, so that the processor 100 can automatically obtain the bandwidth allocation situation of the corresponding bus device slot 11 by polling and addressing the bandwidth allocation identification component 12, and then perform bandwidth allocation. Exemplarily, the bandwidth allocation identification component 12 can be implemented based on hardware design, which will be detailed later.

[0053] Exemplarily, in terms of spatial layout, the bandwidth allocation identification component 12 can be placed beside the bus device slot 11; or the bandwidth allocation identification component 12 can be placed at other free space positions on the server motherboard 10 or the adapter card, which is not limited herein.

[0054] In the embodiments of the present application, the bandwidth allocation identification component 12 is set for the bus device slot 11 and can be set in one-to-one correspondence with the bus device slot 11. Exemplarily, the number of bus device slots 11 is equal to the number of bandwidth allocation identification components 12, and each bandwidth allocation identification component 12 is configured to represent the bandwidth allocation situation of a corresponding bus device slot 11.

[0055] It should be noted that Figure 1 only exemplarily shows that the number of bus device slots 11 is 3, the number of corresponding bandwidth allocation identification components 12 is 3, and the bandwidth allocation identification components 12 are in one-to-one correspondence with the bus device slots 11, but it does not constitute a limitation on the server motherboard 10 provided in the embodiments of the present application. In other embodiments, the number of bus device slots 11 configured on the server motherboard 10 can also be 1, 2, 4 or other numbers, and the number of bandwidth allocation identification components 12 correspondingly is 1, 2, 4 or other numbers, which is not limited herein.

[0056] In the server motherboard 10 provided in the embodiments of the present application, by setting the bandwidth allocation identification component 12 for the bus device slot 11, the bandwidth allocation identification component 12 can identify the bandwidth allocation situation of the corresponding bus device slot 11 and can be queried by the processor 100. Thus, automatic identification and allocation of bandwidth resources are realized based on the bandwidth allocation identification component 12, without occupying any GPIO resources, saving the use of GPIO, and without table look-up matching, improving the bandwidth allocation efficiency.

[0057] In some embodiments, the bandwidth allocation identification component 12 includes a programmable device; the programmable device identifies the bandwidth allocation of the corresponding bus device slot 11 based on high and low level settings.

[0058] Among them, the internal structure of the programmable device can be re - edited to flexibly adapt to different bus device slots 11 and identify the bandwidth allocation of the corresponding bus device slot 11. Specifically, for bus device slots 11 with different bandwidth allocation situations, based on the editing of the internal structure of the programmable device, such as high and low level settings, flexible identification of different bandwidth allocation situations is realized. When the high and low level settings are different, the identified bandwidth allocation situations are different.

[0059] In the server motherboard provided by the embodiments of the present application, by setting the bandwidth allocation identification component 12 for the bus device slot 11, the bandwidth allocation identification component 12 can identify the bandwidth allocation of the corresponding bus device slot 11 and be queried by the processor 100. Thus, automatic identification and allocation of bandwidth resources are realized based on the bandwidth allocation identification component 12. Among them, no resources of GPIO are occupied, the use of GPIO is saved, and no table - look - up matching is required, improving the bandwidth allocation efficiency. At the same time, by setting the broadband allocation identification component 12 as a programmable device, based on the high and low levels of different pins of the programmable device, the bandwidth allocation of the bus device slot 11 is identified. The implementation method is simple and flexibly variable, facilitating adaptation to a variety of different bus port topologies, improving the accuracy and efficiency of bandwidth allocation, simplifying the server firmware development process, facilitating the customized development of server products, and improving the mass production efficiency.

[0060] Exemplarily, the programmable device may include an FPGA chip. In the embodiments of the present application, by placing an FPGA chip beside each standard PCIe slot of the server (which can be a standard PCIe slot on the motherboard or a standard PCIe slot on the Riser card), and setting the high and low levels of the FPGA chip pins based on the bandwidth allocation of the standard PCIe slot, the bandwidth allocation of the standard PCIe slot is identified based on the FPGA chip, facilitating the processor to poll and address the FPGA chips configured for all standard PCIe slots to automatically obtain the bandwidth allocation of each standard PCIe slot and perform bandwidth allocation, realizing efficient and accurate automatic bandwidth allocation.

[0061] In some embodiments, continue to refer to Figure 1 , the bandwidth allocation identification component 12, such as a programmable device, is connected to the processor 100 based on the system management bus (SMBUS IIC bus).

[0062] Among them, the system management bus is a two-wire, synchronous, serial bus that can be used to connect various monitoring chips on the server motherboard 10, such as the programmable device used as the bandwidth allocation identification component 12 in the embodiments of the present application, specifically an FPGA chip.

[0063] Exemplarily, an FPGA chip is placed beside each standard PCIe slot of the server (which can be a standard PCIe slot on the server motherboard or a standard PCIe slot on the adapter card). The FPGA chip is connected to the processor 100 through the system management bus, so that the processor 100 can monitor the bandwidth allocation situation of the PCIe slot, realize automatic addressing acquisition of the bandwidth allocation situation, and further realize bandwidth allocation.

[0064] In some embodiments, the programmable device at least includes a signal interface configured to connect to the system management bus, so that the programmable device can communicate with the processor based on the signal interface.

[0065] Among them, the number of signal interfaces included in the programmable device is set based on the harness of the system management bus. When the system management bus is a two-wire bus, the number of signal interfaces of the programmable device corresponds to two, so as to connect to the system management bus and realize communication.

[0066] Specifically, the system management bus may include a clock signal line and a data signal line. Correspondingly, the signal interface of the programmable device may include a clock signal interface and a data signal interface.

[0067] In some embodiments, Figure 2 is a schematic structural diagram of a programmable device provided by the embodiments of the present application. Taking the programmable device as the FPGA chip U1 as an example, the structure of the programmable device is shown. Refer to Figure 2 , in the FPGA chip U1 used as the programmable device, the signal interface includes a clock signal interface SCK and a data signal interface SDA; the clock signal interface SCK is configured to connect to the clock signal line SMBUS_SCK of the system management bus to synchronize the clock signal, facilitating synchronous data transmission; the data signal interface SDA is configured to connect to the data signal line SMBUS_SDA of the system management bus to transmit data signals; the data signal is the actual data related to the bandwidth allocation situation of the associated bus device slot 11, which will be detailed later.

[0068] Among them, the signal interface of the FPGA chip U1 can be connected to the GPIO interface of the processor through the IIC bus of the clock signal line SMBUS_SCK and the IIC bus of the data signal line SMBUS_SDA.

[0069] Thus, by setting the signal interface of the programmable device to include a clock signal interface and a data signal interface, connecting the clock signal line of the system management bus based on the clock signal interface, and connecting the data signal line of the system management bus based on the data signal interface, clock signal synchronization and data signal transmission are achieved, thereby enabling communication between the programmable device and the processor based on the system management bus, facilitating the processor to query the programmable device to obtain the bandwidth allocation of the bus device slot 11 associated with the data signal, thus achieving automatic query and acquisition of the bandwidth, and further achieving bandwidth allocation. In other implementation manners, when the processor and the programmable device communicate based on other types of buses, the programmable device can also be correspondingly provided with a communication interface to achieve connection with the processor based on the bus, which is not limited herein.

[0070] In some embodiments, with continued reference to Figure 2 , taking the FPGA chip U1 as an example of the programmable device, the programmable device may further include a signal acquisition interface, and the signal acquisition interface is configured to set an identification signal output port corresponding to the bus device slot 11 based on high and low levels, that is, a sub-port.

[0071] Exemplarily, Figure 2 SubGH, SubEF, SubCD, and SubAB are shown as the signal acquisition interfaces in , which respectively correspond to pins 12, 11, 10, and 9 of the FPGA chip U1. By pulling up or pulling down pins 12, 11, 10, and 9, or connecting them to power or ground, the high and low levels of the corresponding signal acquisition interfaces can be set. Specifically, pulling up the pin or connecting it to power makes the level of the corresponding signal acquisition interface high; pulling down the pin or connecting it to ground makes the level of the corresponding signal acquisition interface low, thereby achieving the setting of the high and low levels of different signal acquisition interfaces. Among them, when the signal output ports of the bus device slot 11 are different, the high and low level settings of the signal acquisition interfaces are different, thereby achieving the identification of the signal output ports of the bus device slot 11.

[0072] In the server motherboard provided by the embodiments of the present application, based on the setting of the high and low levels of the signal acquisition interface of the programmable device, the identification of different signal output ports of the bus device slot 11 can be achieved, and the firmware setting method is simple, with good flexibility and strong versatility.

[0073] In some embodiments, the number of signal acquisition interfaces is at least one; different signal acquisition interfaces are configured to identify different signal output ports.

[0074] Specifically, the number of signal acquisition interfaces in the programmable device can be set based on the number of signal output ports of the bus device slot 11. For example, the number of signal acquisition interfaces in the programmable device is equal to the number of signal output ports of the bus device slot 11, and they are set in a one-to-one matching manner. Based on this, when the signal acquisition interface in the programmable device is set to a high level, the corresponding signal output port of the bus device slot 11 is used; when the signal acquisition interface in the programmable device is set to a low level, the corresponding signal output port of the bus device slot 11 is not used, thereby flexibly identifying different signal output ports of the bus device slot 11 based on the high and low level settings of the signal acquisition interface in the programmable device.

[0075] Understandably, Figure 2 The number of signal acquisition interfaces is shown as 4, namely SubGH, SubEF, SubCD and SubAB, but it does not constitute a limitation on the server motherboard provided in the embodiment of the present application. In other embodiments, the number of signal acquisition interfaces can also be 1, 2, 3, 5 or other numbers, which can be set based on the number of signal output ports of the bus device slot, which is not limited here.

[0076] In some embodiments, continue to refer to Figure 2 Taking the FPGA chip U1 used as a programmable device as an example, the programmable device also includes a first type of identification pin and a second type of identification pin; the first type of identification pin is configured to identify the processor associated with the corresponding bus device slot 11; the second type of identification pin is configured to identify the processor port associated with the corresponding bus device slot 11.

[0077] For example, Figure 2 The first type of identification pins are shown as CPU0, CPU1, CPU2 and CPU3, which correspond to pin 1, pin 2, pin 3 and pin 4 of the FPGA chip U1 respectively; the second type of identification pins are shown as PE0, PE1, PE2 and PE3, which correspond to pin 5, pin 6, pin 7 and pin 8 of the FPGA chip U1 respectively.

[0078] The first type of identification pin can identify the processor associated with the bus device slot 11, and CPU0, CPU1, CPU2 and CPU3 correspond to different processors. The second type of identification pin can identify the processor port associated with the bus device slot 11, and PE0, PE1, PE2 and PE3 correspond to different processor ports. Figure 2As shown, by connecting the first type identification pin or the second type identification pin to the power supply VCC, the corresponding pin can be set to a high level; by connecting the first type identification pin or the second type identification pin to the ground GND, the corresponding pin can be set to a low level. When the associated processors are different, the high and low level settings of the corresponding first type identification pins are different; when the processor ports are different, the high and low level settings of the corresponding second type identification pins are different. Therefore, by setting the high and low levels of the first type identification pins and the second type identification pins, the associated processors and processor ports can be flexibly identified, and the firmware setting method is simple, flexible, and versatile.

[0079] In some embodiments, the number of first-class identification pins is at least one; different first-class identification pins are configured to identify different processors; and / or, the number of second-class identification pins is at least one; different second-class identification pins are configured to identify different processor ports.

[0080] Specifically, the number of first-class identification pins in a programmable device can be set based on the number of associated processors. For example, the number of first-class identification pins in a programmable device can be equal to the number of associated processors, and the first-class identification pins and the associated processors are set in a one-to-one matching manner. Based on this, the first-class identification pin can be set to a high level to identify the corresponding associated processor.

[0081] Similarly, the number of second-class identification pins in a programmable device can be set based on the number of processor ports. For example, the number of second-class identification pins in a programmable device can be equal to the number of processor ports, and the second-class identification pins and processor ports are set in a one-to-one correspondence. Based on this, the second-class identification pin can be set to a high level to identify the corresponding processor port.

[0082] Understandably, Figure 2 It is only exemplarily shown that the number of the first-class identification pins and the number of the second-class identification pins are both 4, but it does not constitute a limitation on the server motherboard provided in the embodiment of the present application. In other embodiments, the number of the first-class identification pins can also be 1, 2, 3, 5 or other numbers, which can be set based on the number of associated processors; the number of the second-class identification pins can also be 1, 2, 3, 5 or other numbers, which can be set based on the number of processor ports; the number of the first-class identification pins and the number of the second-class identification pins can be equal or different, which is not limited here.

[0083] In some embodiments, the bus device slot 11 at least includes the bus device slot 11 on the server mainboard 10 ; and the bandwidth allocation identification component 12 is at least disposed on the server mainboard 10 .

[0084] Specifically, the bandwidth allocation identification component 12 and the corresponding bus device slot 11 are both located on the same server motherboard 10, facilitating corresponding matching settings.

[0085] In some embodiments, the bus device slot 11 further includes a bus device slot 11 on an adapter card connected to the server motherboard 10; the bandwidth allocation identification component 12 is also provided on the adapter card.

[0086] Among them, the adapter card (Riser card), as a server expansion card, is mainly used to provide additional expansion slots within the server chassis with limited space, so as to install more hardware devices, such as network adapters, hard disk controllers, etc. The adapter card can be installed in the bus device slot of the server motherboard, such as a standard PCIe slot, to transfer the expansion slots on the server motherboard to a position more suitable for the server chassis, thereby making full use of the internal space of the server, enhancing the expandability and flexibility of the server.

[0087] In the embodiments of the present application, by setting the bandwidth allocation identification component 12 for the bus device slot 11, the bandwidth allocation identification component 12 can identify the bandwidth allocation situation of the corresponding bus device slot 11 and can be queried by the processor 100. Thus, automatic identification and allocation of bandwidth resources are realized based on the bandwidth allocation identification component 12. Among them, no resources of GPIO are occupied, saving the use of GPIO, and there is no need to look up a table for matching, improving the bandwidth allocation efficiency; at the same time, by setting the broadband allocation identification component 12 as a programmable device, based on setting the high and low levels of different pins of the programmable device, the bandwidth allocation situation of the bus device slot 11 is identified. The implementation method is simple and flexibly variable, facilitating adaptation to a variety of different bus port topologies, improving the bandwidth allocation accuracy and efficiency, simplifying the server firmware development process, facilitating the customized development of server products, and improving the mass production efficiency; at the same time, for the bus device slot on the adapter card connected to the server motherboard, the configured bandwidth allocation identification component 12 is also provided on the corresponding adapter card to ensure that the bandwidth allocation identification component 12 and the corresponding bus device slot 11 are both located on the same adapter card, facilitating corresponding matching settings.

[0088] In some embodiments, the bandwidth allocation identification component 12 is implemented based on an FPGA chip. When designing the bus device slot of the server motherboard, the FPGA chip is set in the hardware circuit of the server motherboard or its connected adapter card. Specifically, according to the sub-ports of the PCIe port of the processor to which the slot belongs, the signal acquisition interface and the levels of the first type of identification pins and the second type of identification pins in the FPGA chip are set to identify the bandwidth allocation situation of the bus device slot.

[0089] The FPGA chip can transmit an addressing byte to the processor through the system management bus.

[0090] Exemplarily, the meanings of the addressed bytes are shown in Table 1 and Table 2 below.

[0091] Table 1 Address Table of Addressed Bytes of FPGA Chip

[0092]

[0093] In Table 1, the address offset represents the offset, which is a relative address value used to represent the position offset relative to a certain base address. The data / address byte corresponding to this address offset is byte0.

[0094] Table 2 Meaning Table of Addressed Bytes

[0095]

[0096] In Table 2, the meanings represented by different bits in the addressed byte are described. In the addressed byte byte0, bits 0 to 1 are used to identify the sub-ports, including sub-ports AB, CD, EF, and GH; bits 2 to 3 are used to identify the processor ports, including 4 ports, namely PE0, PE1, PE2, and PE3; bits 4 to 5 are used to identify the associated processors, including 4 processors, namely CPU0, CPU1, CPU2, and CPU3.

[0097] Among them, the FPGA chip defines the actual meaning represented by the high and low level signals input by each pin based on the signal acquisition interface, the first type of representation pins, and the second type of identification pins, as shown in Table 3 below.

[0098] Table 3 Table of the Actual Meanings Represented by the High and Low Level Signals Input by Each Pin Defined by the FPGA Chip

[0099]

[0100] Table 3 shows the communication protocol between the FPGA chip with the PCIe slot configuration defined internally and the root node (RootPort) of the BIOS. Among them, when the PCIe slot is powered on, the information represented by the bytes transmitted to the root node of the BIOS is defined, and this information includes: which sub-port of which port (i.e., PE port) of which processor is connected to this PCIe slot.

[0101] Through the above Table 3 and the following Table 4 for addressing, query whether the addressed FPGA chip will return the confirmation character ack, and based on the slot address (i.e., sub-port address) of the returned confirmation character ack, the bandwidth form allocated by the processor for each root node of the PCIe slot can be obtained according to Table 5 below, that is, the bandwidth allocation situation is obtained through automatic addressing.

[0102] Table 4 Definition Table of Addressing Bytes for FPGA Chips

[0103]

[0104] The coding meanings of the addressing bytes are shown in Table 4. Among them, the addressing byte byte0 can be an 8-bit binary code. In the table, bit represents a bit, with a total of 0 to 7 bits; for example, bit 7 to 6 represent bits 6 to 7 in the 8-bit binary code, and the same applies to others, which will not be elaborated here. Among them, bits 6 to 7 can be reserved, bits 4 to 5 are determined by the input level of the first type of identification pin and are used to identify which processor it belongs to, that is, one of CPU0 to CPU3; bits 2 to 3 are determined by the input level of the second type of identification pin and are used to identify which processor port it belongs to, that is, one of PE0 to PE3; bits 0 to 1 are determined by the input level of the signal acquisition interface and represent which sub-port of this PE port it belongs to, that is, one of AB, CD, EF, GH.

[0105] Table 5 Corresponding Table of Processor Allocating Bandwidth Forms for Each PCIe Root Node

[0106]

[0107] In some embodiments, the FPGA chip can read the values of the pins of the first type of identification pins CPU0 to CPU3, the second type of identification pins PE0 to PE3, and the signal acquisition interface (i.e., sub-ports) SubAB, SubCD, SubEF, and SubGH, and write them into internal registers; the FPGA chip receives a query from the system management bus of the processor (BIOS configured by the processor), determines whether the queried address is the same as the address of this FPGA chip. If it is the same, it responds to the addressing byte byte0 to the root node of the BIOS through the system management bus. If it is not the same, it returns to the previous step to continue comparing the addresses.

[0108] Reference Figure 3 , which shows an addressing process of a programmable device. The process specifically may include the following steps:

[0109] S30. Start.

[0110] S31. Read the values of the feature pins and write them into internal registers.

[0111] Among them, the feature pins may include the first type of identification pins CPU0 to CPU3, the second type of identification pins PE0 to PE3, and the signal acquisition interface (i.e., sub-ports) SubAB, SubCD, SubEF, and SubGH pins. Based on the values of the feature pins, the bandwidth allocation situation of the device bus slot is identified.

[0112] In this step, the FPGA chip writes the generated addressing byte byte0 into the internal register based on the values of its own characteristic pins.

[0113] S32. Receive a query from the system management bus of the processor.

[0114] In this step, the FPGA chip receives a query from the system management bus of the processor (the processor performs a query action based on the BIOS computer program configured by the processor).

[0115] S33. Based on the query address being the same as the address of this FPGA, respond to the processor with the addressing byte through the system management bus.

[0116] This step may include: the FPGA chip determines whether the query address is the same as the address of this FPGA chip. If it is the same, then through the system management bus, respond to the root node of the BIOS with the addressing byte byte0. If it is not the same, return to the previous step to continue comparing the addresses.

[0117] In the embodiments of the present application, based on the FPGA chip settings, it is possible to uniformly encode which processor is used in the current PCIe slot, which PE port of the processor is used, and which sub-port under the PE port is used into an 8-bit addressing byte address, and this addressing byte address is also the address of the FPGA chip in the system management bus.

[0118] Based on this, when the server is powered on, the processor polls and addresses all FPGA chips in the PCIe slots based on the computer program configured by the BIOS, traverses whether the sub-port addresses of all PCIe root nodes of all processors are in use, determines the bandwidth allocation situation of each PCIe port, and uses the bandwidth of each PCIe root node of each processor obtained to perform the allocation, so as to achieve automatic acquisition and allocation of bandwidth.

[0119] In some embodiments, the BIOS computer program may be stored in a ROM (Read-Only Memory), and when the server is powered on, the processor extracts the BIOS computer program stored in the ROM and executes it to achieve automatic addressing based on the FPGA chip to obtain the usage situation of the PCIe slots, so as to achieve automatic acquisition and allocation of the PCIe slot bandwidth allocation situation.

[0120] The embodiments of the present application also provide a server, including any one of the above server motherboards, and having corresponding beneficial effects.

[0121] Exemplarily, Figure 4 is a schematic structural diagram of a server provided by an embodiment of the present application. Refer to Figure 4, the server 20 may further include a processor 100 and an input / output system chip 200. The input / output system chip may be a BIOS (BIOS is a computer program stored in the ROM). Both the bandwidth allocation identification component 12 and the input / output system chip 200 are connected to the processor 100; the processor 100 runs the computer program built in the input / output system chip 200 to obtain the bandwidth allocation situation of the bus device slot 11 associated with the bandwidth allocation identification component 12 and allocate bandwidth.

[0122] Exemplarily, the processor 100 may be connected to other devices, including the bandwidth allocation identification component 12 and the input / output system chip 200, through a PCH (Platform Controller Hub) chip; or be connected through other chips or structural components, which is not limited herein.

[0123] Figure 4 In, the bus device slot 11 may be a PCIe slot, and the bandwidth allocation identification component 12 may be an FPGA chip. One FPGA chip is correspondingly set for each PCIe slot. A PCIe device is plugged into the gold fingers of the PCIe slot. The signal port of the FPGA chip is connected to the PCH chip through the system management bus to be connected to the processor 100. The FPGA chip is installed on the board where the PCIe slot is located.

[0124] In the server provided by the embodiment of the present application, the input / output system chip 200 may have a built-in computer program and be run by the processor 100 when the server is powered on; the processor 100 runs the computer program to perform polling addressing on the bandwidth allocation identification component 12, obtain the bandwidth allocation situation of the corresponding bus device slot 11 identified by the bandwidth allocation identification component 12, and then perform bandwidth allocation, realizing automatic identification and allocation of bandwidth resources, without occupying any resources of the GPIO, saving the use of the GPIO, and improving the bandwidth allocation efficiency.

[0125] In some embodiments, the server may further include an adapter card, and the adapter card is connected to the server motherboard; the bus device slots are arranged on the server motherboard and the adapter card, and the bandwidth allocation identification components are correspondingly arranged on the server motherboard and the adapter card.

[0126] Specifically, the bus device slots at least include the bus device slots on the server motherboard; the bandwidth allocation identification components are at least arranged on the server motherboard.

[0127] Specifically, the bandwidth allocation identification component and the corresponding bus device slot are both located on the same server motherboard, which is convenient for corresponding matching settings.

[0128] In addition, the bus device slot further includes a bus device slot on an adapter card connected to the server motherboard; the bandwidth allocation identification component is also provided on the adapter card.

[0129] Among them, for the bus device slot on the adapter card connected to the server motherboard, the configured bandwidth allocation identification component is also provided on the corresponding adapter card, so as to implement that the bandwidth allocation identification component and the corresponding bus device slot are both on the same adapter card, which is convenient for corresponding matching settings.

[0130] In some embodiments, the bandwidth allocation identification component is implemented based on an FPGA chip. When designing the bus device slot of the server motherboard, the FPGA chip is set in the hardware circuit of the server motherboard or its connected adapter card. Specifically, according to the sub-ports of the PCIe ports of the processors to which the slots belong, the signal acquisition interfaces and the levels of the first type of identification pins and the second type of identification pins in the FPGA chip are set, so as to flexibly identify the bandwidth allocation situation of the bus device slots.

[0131] The embodiments of the present application further provide a bandwidth acquisition method. The bandwidth acquisition method can be implemented based on any of the above server motherboards and has corresponding beneficial effects.

[0132] Exemplarily, Figure 5 is a schematic flowchart of a bandwidth acquisition method provided by an embodiment of the present application. Referring to Figure 5 , the bandwidth acquisition method may include:

[0133] S51. Poll and address the bandwidth allocation identification component configured for the bus device slot.

[0134] Among them, there may be at least one bandwidth allocation identification component configured for the bus device slot in the server. By polling and addressing the bandwidth allocation identification component, the bandwidth allocation situations of all bus device slots in the server can be obtained.

[0135] S52. Based on the response of the bandwidth allocation identification component, obtain the bandwidth allocation situation of the corresponding bus device slot.

[0136] Among them, in response to the query of the processor, the bandwidth allocation identification component sends the bandwidth allocation situation of the corresponding bus device slot to the processor, so that the processor can obtain the bandwidth allocation situation of the corresponding bus device slot.

[0137] In the bandwidth acquisition method provided by the embodiments of the present application, the processor can automatically obtain the bandwidth allocation situation of the corresponding bus device slot by polling and addressing the bandwidth allocation identification component configured for the bus device slot, realizing automatic bandwidth acquisition and allocation. Among them, it does not need to occupy any resources of the GPIO, saves the use of the GPIO, and improves the bandwidth allocation efficiency.

[0138] In some embodiments, "obtaining the bandwidth allocation situation of the corresponding bus device slot" in this step may specifically include:

[0139] Obtaining the addressing information fed back by the bandwidth allocation identification component;

[0140] Based on the addressing information, parsing out the associated identification information, where the identification information includes the target processor, the target processor port, and the target signal output port of the bus device slot;

[0141] Based on the identification information, determining the bandwidth allocation situation of the corresponding bus device slot.

[0142] Among them, the addressing information may include the addressing byte byte0. For the relevant description of the addressing byte byte0, reference can be made to the foregoing text and will not be elaborated here. Parsing this addressing information can obtain the identification information, that is, which processor the current bus device slot uses, which port of the processor it uses, and which sub-port under the port it uses, and then combining Table 5 in the foregoing text to determine the bandwidth allocation situation.

[0143] In the embodiments of the present application, the processor can determine the bandwidth allocation situation of the bus device slot based on the acquisition and parsing of the addressing information, with high efficiency and high accuracy.

[0144] In some embodiments, the bandwidth allocation identification component is connected to the processor based on the system management bus.

[0145] Based on this, polling addressing of the bandwidth allocation identification component configured for the bus device slot may specifically include:

[0146] Scanning the bus data transmitted on the system management bus;

[0147] Receiving the addressing byte responded by the bandwidth allocation identification component until the scanning is completed; among them, the addressing byte is associated with the bandwidth allocation situation of the bus device slot.

[0148] In the embodiments of the present application, the bandwidth allocation identification component is scanned based on the system management bus, and the corresponding addressing byte is received when the bandwidth allocation identification component responds, so as to complete the polling addressing of the bandwidth allocation identification component, obtain the bandwidth allocation situations of all corresponding bus device slots, and achieve efficient acquisition of slot bandwidth, which is convenient for accurate bandwidth allocation.

[0149] In some embodiments, Figure 6 is a schematic flowchart of another bandwidth acquisition method provided by the embodiments of the present application. Refer to Figure 6 , this bandwidth acquisition method may include the following steps:

[0150] S60. Start.

[0151] Specifically, the process starts to be executed when the server is turned on.

[0152] S61. Scan system management bus data.

[0153] Specifically, the processor or the BIOS connected thereto scans bus data of the system management bus.

[0154] Exemplarily, the BIOS performs polling addressing on all PCIe slot FPGA chips. Within the addressing address range, the subport occupies 2 bits, the PE port occupies 2 bits, the processor bit number occupies 2 bits, and the total number of bits is 6 bits, and the corresponding number is 2 to the power of 6, that is, 0 to 63.

[0155] S62. The FPGA connected based on the system management bus responds and receives the addressing byte.

[0156] Specifically, the BIOS determines whether the system management bus device, that is, the FPGA connected to the system management bus responds; if the FPGA responds, the BIOS receives the addressing byte byte0 of the FPGA chip, that is, the BIOS reads the FPGA chip and obtains the addressing byte byte0; if the FPGA does not respond, it returns to the previous step to continue scanning the system management bus data.

[0157] S63. According to the addressing bytes, the processor, port and sub-port are parsed and bandwidth is allocated until the scan is completed.

[0158] Specifically, the BIOS parses the addressing byte byte 0. Based on the read addressing byte byte 0, the BIOS parses the processor to which the current bus device slot / slot belongs, the port of the processor, the sub-port number under the port, and allocates bandwidth.

[0159] Furthermore, the BIOS determines whether the scanning of the system management bus is completed; if the scanning is completed, the process ends, that is, S64 is executed; otherwise, the process returns to continue scanning the system management bus data.

[0160] Among them, BIOS records the address data returned by all slot FPGA chips, translates the address data to port bandwidth with reference to Table 5 above, and allocates bandwidth.

[0161] S64, end.

[0162] After the BIOS uses the acquired bandwidth of each processor and each slot root node for allocation, the bandwidth allocation is completed and the boot process continues.

[0163] In the bandwidth acquisition method provided by the embodiments of the present application, when the server is powered on, the BIOS can perform polling addressing on all FPGA chips in the PCIe slots. During the startup process, the BIOS traverses whether the sub-port addresses of all PCIe root nodes of all processors are in use to determine the bandwidth allocation of each PCIe port. The BIOS uses the bandwidth of each PCIe root node of each processor obtained to perform the allocation and continues the startup process.

[0164] The embodiments of the present application can realize the automatic allocation of the server CPU PCIe bandwidth resources, without the need to design a GPIO recognition circuit to make a bandwidth allocation table and without occupying GPIO resources; it has strong versatility and is applicable to any server computer system. Based on the BIOS for bandwidth allocation, a general server PCIe bandwidth adaptive allocation mechanism is proposed, forming a unified specification for server system design, which can arbitrarily apply PCIe port resources and is convenient for self-configuration; there is no need to use complex and cumbersome GPIO level recognition to design a bandwidth allocation table, and there is no need to manually transmit the motherboard bandwidth design changes, that is, there is no need to develop a customized BIOS version for PCIe bandwidth allocation for each designed motherboard; without the participation of any GPIO resources of the motherboard PCH, the use of GPIO is saved, and it can be realized that the bandwidth of each PCIe slot can be detected by the BIOS through system management bus addressing during the server startup, automatically recognized and dynamically allocated the PCIe bandwidth required by the slot, realizing the standardization of bandwidth allocation design. For the server motherboard and riser card adopting this technical solution, they can be arbitrarily assembled and configured without re-adapting the BIOS to the slot bandwidth.

[0165] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by means of software plus a necessary general hardware platform. Of course, it can also be implemented by hardware, but in many cases, the former is a better implementation method.

[0166] The embodiments of the present application also provide a bandwidth acquisition device. Refer to Figure 7 , the bandwidth acquisition device may include: a polling addressing module 71 configured to perform polling addressing on the bandwidth allocation identification component configured for the bus device slot; a bandwidth identification module 72 configured to obtain the bandwidth allocation of the corresponding bus device slot based on the response of the bandwidth allocation identification component.

[0167] In some embodiments, in the bandwidth acquisition device, the bandwidth identification module 72 is configured to obtain the bandwidth allocation situation of the corresponding bus device slot, which may specifically include that the bandwidth identification module 72 is configured to: obtain the addressing information fed back by the bandwidth allocation identification component; based on the addressing information, parse out the associated identification information, where the identification information includes the target processor, the target processor port, and the target signal output port of the bus device slot; based on the identification information, determine the bandwidth allocation situation of the corresponding bus device slot.

[0168] In some embodiments, the bandwidth allocation identification component is connected to the processor based on the system management bus.

[0169] Based on this, the polling addressing module 71 is specifically configured to: scan the bus data transmitted on the system management bus; receive the addressing bytes responded by the bandwidth allocation identification component until the scanning is completed; where the addressing bytes are associated with the bandwidth allocation situation of the bus device slot.

[0170] In the embodiments of the present application, the descriptions of the features in the corresponding embodiments of the bandwidth acquisition device can refer to the relevant descriptions in the corresponding embodiments of the bandwidth acquisition method, which will not be elaborated here one by one.

[0171] The embodiments of the present application further provide an electronic device, including a memory and a processor. A computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any one of the above embodiments of the bandwidth acquisition method.

[0172] The embodiments of the present application further provide a computer-readable storage medium, in which a computer program is stored. Wherein, the computer program is configured to execute the steps in any one of the above embodiments of the bandwidth acquisition method when running.

[0173] In an exemplary embodiment, the above computer-readable storage medium may include, but is not limited to: USB flash drive, read-only memory (abbreviated as ROM), random access memory (abbreviated as RAM), mobile hard disk, magnetic disk, or optical disc and other various media that can store computer programs.

[0174] The embodiments of the present application further provide a computer program product. The above computer program product includes a computer program, and when the computer program is executed by a processor, it implements the steps in any one of the above embodiments of the bandwidth acquisition method.

[0175] The embodiments of the present application further provide another computer program product, including a non-volatile computer-readable storage medium. The non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, it implements the steps in any one of the above embodiments of the bandwidth acquisition method.

[0176] Those skilled in the art may further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods for each specific application to implement the described functions, but such implementation should not be considered to exceed the scope of this application.

[0177] The server motherboard, server, bandwidth acquisition method, product, device, and medium provided in this application have been introduced in detail above. Specific examples have been used herein to elaborate on the principles and implementation manners of this application. The description of the above embodiments is only used to help understand the method and its core idea of this application. It should be noted that for those of ordinary skill in the art in this technical field, without departing from the principle of this application, several improvements and modifications can be made to this application, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A server motherboard, characterized in that, Comprising: Bus device slots configured on the server motherboard; The server motherboard further includes a bandwidth allocation identification component set for the bus device slots, and the bandwidth allocation identification component is connected to the processor; the bandwidth allocation identification component is configured to identify the bandwidth allocation situation of the bus device slots and is provided for the processor to query; The processor is further connected to an input / output system chip, and the processor is configured to run a computer program of the input / output system chip to perform polling addressing on the bandwidth allocation identification component and obtain addressing information fed back by the bandwidth allocation identification component based on the response of the bandwidth allocation identification component; Based on the addressing information, associated identification information is parsed, and the identification information includes a target processor, a target processor port, and a target signal output port of the bus device slot; and based on the identification information, the bandwidth allocation situation corresponding to the bus device slot is determined; The bandwidth allocation identification component includes a programmable device; The programmable device includes a first type of identification pin, a second type of identification pin, and a signal acquisition interface; The first type of identification pin is configured to identify the processor associated with the corresponding bus device slot; The second type of identification pin is configured to identify the processor port associated with the corresponding bus device slot; The signal acquisition interface is configured to identify the signal output port corresponding to the bus device slot; The addressing information includes an addressing byte, and different bits of the addressing byte represent the target processor, the target processor port, and the target signal output port associated with the bus device slot.

2. The server motherboard according to claim 1, wherein The programmable device sets and identifies the bandwidth allocation situation corresponding to the bus device slot based on high and low levels.

3. The server motherboard according to claim 2, characterized in that, The programmable device is connected to the processor based on the system management bus.

4. The server motherboard according to claim 3, wherein, The programmable device at least includes a signal interface, and the signal interface is configured to connect to the system management bus.

5. The server motherboard according to claim 4, characterized in that, The signal acquisition interface is configured to set and identify the signal output port corresponding to the bus device slot based on high and low levels.

6. The server motherboard according to claim 5, wherein The number of the signal acquisition interfaces is at least one; Different signal acquisition interfaces are configured to identify different signal output ports.

7. The server motherboard according to claim 1, characterized in that The number of the first type of identification pins is at least one; Different first type of identification pins are configured to identify different processors; And / or, The number of the second type of identification pins is at least one; Different second type of identification pins are configured to identify different processor ports.

8. The server motherboard according to claim 4, characterized in that, The signal interface includes a clock signal interface and a data signal interface; The clock signal interface is configured to connect to the clock signal line of the system management bus to synchronize the clock signal; The data signal interface is configured to connect to the data signal line of the system management bus to transmit a data signal; the data signal is associated with the bandwidth allocation situation of the bus device slot.

9. The server motherboard according to claim 1, characterized in that The bus device slot at least includes the bus device slot on the server motherboard; the bandwidth allocation identification component is at least set on the server motherboard.

10. The server motherboard according to claim 1, characterized in that, The bus device slot further includes the bus device slot on an adapter card connected to the server motherboard; the bandwidth allocation identification component is also set on the adapter card.

11. A server, characterized in that, Including the server motherboard according to any one of claims 1-10.

12. The server according to claim 11, wherein, It further includes an adapter card, and the adapter card is connected to the server motherboard; The bus device slots are arranged on the server motherboard and the adapter card, and the bandwidth allocation identification components are correspondingly arranged on the server motherboard and the adapter card.

13. The server according to claim 11, wherein It further includes the processor and the input / output system chip, and the bandwidth allocation identification component is also connected to the processor; The processor runs the computer program built in the input / output system chip to obtain the bandwidth allocation situation of the bus device slot associated with the bandwidth allocation identification component and allocate bandwidth.

14. A bandwidth acquisition method, characterized in that, Implemented based on the server motherboard according to any one of claims 1-10; the method includes: Polling and addressing the bandwidth allocation identification components configured for the bus device slots; Based on the response of the bandwidth allocation identification component, obtaining the bandwidth allocation situation corresponding to the bus device slot; Wherein, the obtaining the bandwidth allocation situation corresponding to the bus device slot includes: Obtaining the addressing information fed back by the bandwidth allocation identification component; Based on the addressing information, parsing out the associated identification information, and the identification information includes the target processor, the target processor port, and the target signal output port of the bus device slot; Based on the identification information, determining the bandwidth allocation situation corresponding to the bus device slot; Wherein, the bandwidth allocation identification component includes a programmable device; the programmable device includes a first type of identification pin, a second type of identification pin, and a signal acquisition interface; the first type of identification pin is configured to identify the processor associated with the corresponding bus device slot; the second type of identification pin is configured to identify the processor port associated with the corresponding bus device slot; the signal acquisition interface is configured to identify the signal output port corresponding to the bus device slot; the addressing information includes an addressing byte, and different bits of the addressing byte represent the target processor, the target processor port, and the target signal output port associated with the bus device slot.

15. The bandwidth acquisition method according to claim 14, characterized in that The bandwidth allocation identification component is connected to the processor based on the system management bus; The polling and addressing the bandwidth allocation identification components configured for the bus device slots includes: Scanning the bus data transmitted on the system management bus; Receiving the addressing byte responded by the bandwidth allocation identification component until the scanning is completed; wherein, the addressing byte is associated with the bandwidth allocation situation of the bus device slot.

16. A computer program product comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the steps of the bandwidth acquisition method according to any one of claims 14 to 15.

17. An electronic device, characterized in that, Including: A memory for storing a computer program; A processor for implementing the steps of the bandwidth acquisition method according to any one of claims 14 to 15 when executing the computer program.

18. A computer-readable storage medium, characterized in that, A computer program is stored in the computer-readable storage medium, and when the computer program is executed by the processor, it implements the steps of the bandwidth acquisition method according to any one of claims 14 to 15.

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