Data transmission method, data receiving method, equipment and system

Abstract

The invention relates to the technical field of data transmission, in particular to a data transmission method, a data receiving method, equipment and a system. The data transmission method is applied to a host device and comprises the steps that clock frequencies are determined, and the clock frequencies comprise a first frequency, a second frequency lower than the first frequency or / and a third frequency higher than the first frequency; the composite signal is transmitted through the change trend of the clock frequency and the transmission period, the composite signal comprises a clock signal and a characteristic signal, and the clock signal and the characteristic signal are transmitted synchronously. According to the invention, the characteristic signal is fused on the clock signal, the use number of data transmission interfaces is reduced in a composite mode, and the transmission efficiency is improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the technical field of data transmission, and specifically to a data transmission method, a data receiving method, a device and a system. Background Art

[0002] IIS (Inter-IC Sound) is a data transmission bus between chips. In general scenarios, it is usually used to transmit audio data streams between host chips and slave chips. The IIS host provides clock signals for communication in the transmission protocol: SCK serial clock signal, one clock cycle corresponds to the sampling time of one bit of audio data; LRCK frame clock signal, used to indicate the left and right channel attributes of audio data; SDATA serial data signal, indicating the bit value corresponding to the current SCK clock. The slave receives or sends audio bit data on the SDATA signal line using the SCK clock edge provided by the host.

[0003] To achieve the above data transmission process, the traditional IIS bus needs to use three GPIO (General Purpose Input / Output) ports, and additional serial ports and other communication methods are required to control and switch between chips. This places certain requirements on the number of GPIO ports on the chip. Summary of the invention

[0004] The object of the present invention is to provide a data transmission method, a data receiving method, a device and a system to reduce interface requirements and improve transmission efficiency.

[0005] In a first aspect, the present invention provides a data transmission method, applied to a host device, comprising: determining a clock frequency, the clock frequency comprising a first frequency, a second frequency lower than the first frequency and / or a third frequency higher than the first frequency; transmitting a composite signal through a changing trend of the clock frequency and a transmission period, the composite signal comprising a clock signal and a characteristic signal, the clock signal and the characteristic signal being transmitted synchronously.

[0006] In a second aspect, the present invention provides a data transmission device, comprising a memory and a processor, wherein the memory is connected to the processor, and the processor is used to execute one or more computer programs stored in the memory, and when the processor executes the one or more computer programs, the data transmission device implements the data transmission method as described above.

[0007] In a third aspect, the present invention provides a data receiving method, applied to a slave device, comprising: receiving a clock signal, when the clock frequency of the clock signal changes, determining that the clock signal is a composite signal, and analyzing the composite signal according to its frequency change trend and transmission period, the composite signal including the clock signal and a characteristic signal, and the clock signal and the characteristic signal are transmitted synchronously.

[0008] In a fourth aspect, the present invention provides a data receiving device, comprising a memory and a processor, wherein the memory is connected to the processor, and the processor is used to execute one or more computer programs stored in the memory, and when the processor executes the one or more computer programs, the data receiving device implements the data receiving method as described above.

[0009] In a fifth aspect, the present invention provides a data transmission system, the system comprising the above-mentioned data transmission device and the above-mentioned data receiving device, the data transmission device is used to execute the above-mentioned data transmission method, and the data receiving device is used to execute the above-mentioned data receiving method.

[0010] In the data transmission method provided by the present invention, a composite signal is transmitted through the changing trend of the clock frequency and the transmission period, and a characteristic signal is integrated into the clock signal, thereby reducing the number of interfaces required; the clock signal and the characteristic signal are transmitted synchronously, thereby improving the transmission efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments of the present application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0012] Figure 1 A schematic diagram of the structure of the master-slave device communication provided by an embodiment of the present invention; Figure 2A , 2B Schematic diagram of different code elements represented by different frequency change trends provided in an embodiment of the present invention; Figure 3 A specific flow chart of the data transmission method provided by an embodiment of the present invention; Figure 4A A schematic diagram of the symbol representation of binary symbols under the same trend provided by an embodiment of the present invention; Figure 4B A schematic diagram of code element representation of an M-ary code element under various change trends provided by an embodiment of the present invention; Figure 5A specific flow chart of the data receiving method provided by the prior art and the embodiment of the present invention. DETAILED DESCRIPTION

[0013] In order to make the purpose, technical solutions and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present application.

[0014] It should be noted that, if there is no conflict, the various features in the embodiments of the present application can be combined with each other, all within the scope of protection of the present application. In addition, although the functional module division is performed in the device schematic diagram and the logical order is shown in the flow chart, in some cases, the steps shown or described can be performed in a sequence different from the module division in the device or the flow chart. Furthermore, the words "first", "second", "third", etc. used in this application do not limit the data and execution order, but only distinguish the same items or similar items with basically the same functions and effects.

[0015] Reference Figure 1 As shown, the host device 101 communicates with the slave device 102 for audio transmission. In the figure, SCK is the clock signal for data transmission, LRCK is the left / right channel data word latch clock for audio transmission, SDATA is the transmitted audio data, and SCK and LRCK work together to ensure that the audio data can be transmitted in the correct timing. Generally, SCK and LRCK are clock signals with the same frequency or a multiple relationship.

[0016] The present application embodiment provides a data transmission method, which is applied to a host device 101. Figure 3 The data transmission method includes: determining a clock frequency, wherein the clock frequency includes a first frequency, a second frequency lower than the first frequency, and / or a third frequency higher than the first frequency; transmitting a composite signal through a changing trend of the clock frequency and a transmission period, wherein the composite signal includes a clock signal and a characteristic signal, and the clock signal and the characteristic signal are transmitted synchronously.

[0017] The clock frequency can be the SCK frequency, which is usually sent by a clock generator as a reference beat for communication operations. The host device 101 is usually responsible for sending commands and data, while the slave device 102 is responsible for receiving commands and performing corresponding operations, or returning data to the host device 101. The data transmission between the master and the slave needs to follow a common clock signal, and the clock synchronization mechanism is implemented through the communication protocol to ensure that the master and the slave maintain the consistency of the clock frequency during the communication process. On the other hand, the clock frequency can also be the LRCK frequency. The main function of the LRCK signal is to switch the data of the left and right channels, and identify the left and right channels according to the high and low levels of the LRCK. In this way, the receiving end can correctly identify and separate the data of the left and right channels according to the LRCK signal.

[0018] The above transmission cycle is a fixed and appropriate time length, and the specific value can be customized, but it should adapt to the slave device's ability to resolve frequency changes. The transmission cycle can be implemented using a timer. The durations of different clock frequencies in the transmission cycle may be the same or different. The same timer can be used for the same duration requirements, and different timers can be used for different duration requirements.

[0019] The above-mentioned composite signal refers to a signal that is a fusion of a clock signal and a characteristic signal. The clock signal is a synchronization tone followed by both the master and slave machines. The characteristic signal is a hidden signal transmitted synchronously at the GPIO port of the clock signal. The clock frequency is adjusted for transmission using specific rules and is parsed on the slave side using corresponding rules.

[0020] The above-mentioned clock frequency change trends include two types. Taking the first frequency as a reference, when the clock frequency changes from the first frequency to the second frequency, its slope is negative, which can be regarded as the code element "0". When the clock frequency changes from the first frequency to the third frequency, its slope is positive, which can be regarded as the code element "1". Of course, the code element can also be "1" when the slope is negative and "0" when the slope is positive. The main purpose of the present invention is to assign different code element representations according to different frequency change trends, and changes or improvements to certain conditions should also be included in the protection scope of the present invention.

[0021] As an example, see Figure 2A , 2B , which shows different symbol representations in different frequency change trends, Figure 2A It shows that under the first frequency as the reference, the time period P1 is the second frequency with a frequency lower than the first frequency, and the time period P2 is the third frequency with a frequency higher than the first frequency. According to the modulation rule exemplified above, at the beginning of the transmission period P, the first frequency is down-converted to the second frequency, and its slope is negative. The symbol of the characteristic signal in the entire transmission period P is "0"; Figure 2BIt shows that the time period P1' is the third frequency which is higher than the first frequency, and the time period P2' is the second frequency which is lower than the first frequency. At the beginning of the transmission cycle, the first frequency is upconverted to the third frequency with a positive slope. The code element of the characteristic signal in the entire transmission cycle P' is "1".

[0022] After a transmission cycle, when another transmission cycle begins, the above process of acquiring the data to be transmitted and modulating the clock frequency according to the characteristic signal is repeated. If the characteristic signal is continuously transmitted in adjacent transmission cycles, the first frequency is still used as a reference, and the clock frequency is adjusted accordingly according to the characteristic signal at the beginning of the transmission cycle. For example, if the transmitted code element is "1", the clock frequency at the beginning of the transmission cycle is the third frequency, and the clock frequency in the second half of the transmission cycle is the second frequency.

[0023] In addition to binary, code elements can also be in M-base (M>2). For M-base code elements, the frequency change trend needs to follow more complex change rules. There may be multiple change trends in a transmission cycle, or there may be more combinations of different frequencies, etc. However, the core remains unchanged, and the type and meaning of code elements are defined by the frequency change trend.

[0024] In some specific embodiments, the above-mentioned data transmission method includes a first data transmission mode and a second data transmission mode; in the first data transmission mode, the clock frequency is the first frequency, and the host device transmits the clock signal at the first frequency; in the second data transmission mode, the clock frequency is a combination frequency of the first frequency, the second frequency and the third frequency in different time periods, and the host device transmits the above-mentioned composite signal at the combination frequency.

[0025] Before sending the clock signal and data, the host device obtains the data to be transmitted and analyzes whether the data to be transmitted contains the characteristic signal. If not, it enters the first data transmission mode, uses the first frequency as the clock signal, and communicates with the slave device. If so, it enters the second data transmission mode, uses the first frequency as a reference, and controls the clock frequency with the code elements of the characteristic signal, and different code elements modulate different frequency change trends.

[0026] Reference Figure 3, which shows the specific process of the above-mentioned data transmission method. Before transmitting data, the host device obtains the data to be transmitted, and selectively enters the first transmission mode or the second transmission mode according to whether the data to be transmitted contains a characteristic signal. In the first transmission mode, the synchronous clock frequency of the host device and the slave device is the first frequency, that is, the clock GPIO port of the host device transmits a clock signal of the first frequency, and transmits data or command communication at other GPIO ports according to the first frequency; in the second transmission mode, the synchronous clock frequencies of the host device and the slave device are the first frequency, the second frequency and the third frequency in different time periods, respectively, and the time nodes at which the first frequency, the second frequency and the third frequency appear are modulated according to the characteristic signal, and finally a clock signal with a characteristic signal is formed, that is, a composite signal, and other GPIO ports also perform data transmission or command communication according to the clock signal after the modulation.

[0027] In order to keep the transmission rate between the master and slave machines unchanged, taking the first frequency as a reference benchmark, the second frequency, the third frequency and their respective proportions in the transmission period need to be adapted to the proportion of the first frequency in the transmission period. For example, the second frequency and the third frequency are two clock frequencies of equal time and equal difference, and the sum of the values ​​of the second frequency and the third frequency is equal to twice the first frequency. Specifically, the first frequency can be 44kHz, the second frequency can be 24kHz, and its proportion in the transmission period is 50%, and the third frequency can be 64kHz, and its proportion in the transmission period is also 50%.

[0028] As another example, the ratio of the difference between the first frequency and the second frequency to the difference between the third frequency and the first frequency is equal to the inverse ratio of the duration of the second frequency and the duration of the third frequency in the transmission period. Specifically, the first frequency can be 44kHz, the second frequency can be 40kHz, the difference between the first frequency and the second frequency can be 4kHz, the third frequency can be 60kHz, the difference between the third frequency and the first frequency can be 16kHz, the duration of the second frequency in the transmission period can be 16 / (4+16) = 80%, and the duration of the third frequency in the transmission period can be 40 / (4+16) = 20%.

[0029] In this way, it can be ensured that no matter in the first transmission mode or the second transmission mode, within the transmission period, the average transmission rates of the second frequency and the third frequency are equal to the transmission rate of the first frequency.

[0030] The above embodiment is for the case where the transmission rate is constant. When the transmission rate is variable, the relationship between the first frequency, the second frequency and the third frequency may not be restricted, but they must have an obvious characteristic of a frequency variation trend.

[0031] There are at least two ways to represent code elements. The binary code elements are "0" and "1", and the M-ary code elements contain more. Therefore, there are at least two changing trends of the clock frequency in the transmission cycle, the first changing trend and the second changing trend. Under the premise of ensuring that the transmission rate remains unchanged, the slope of the first changing trend and the slope of the second changing trend are inversely related to each other; under the premise of variable transmission rate, the slope of the first changing trend and the slope of the second changing trend can be in the same direction or inversely related, and there needs to be a clear distinction when they are in the same direction.

[0032] As an example, see Figure 4A As shown, it shows the code representation of binary code elements under the same direction relationship of slopes. With the first frequency as the reference benchmark, the fourth frequency is higher than the first frequency, and the fifth frequency is higher than the fourth frequency. At the beginning of the transmission period P, the first frequency is upgraded to the fourth frequency, which is the first frequency change trend, and the slope is positive. In the latter part of the transmission period P, it is further upgraded to the fifth frequency, which is the second frequency change trend, and the slope is also positive. Taking the first frequency as the reference, the two slopes are both positive, but the slope of the first frequency change trend is lower than the slope of the second frequency change trend. Different code representations can be given according to different degrees of change trends. For example, the code element is "0" when the first frequency change trend is, and the code element is "1" when the second frequency change trend is.

[0033] As another example, refer to Figure 4B As shown, it shows the code representation of M-ary code elements under various change trends. With the first frequency as the reference benchmark, the sixth frequency is lower than the first frequency, the seventh frequency and the eighth frequency are both higher than the first frequency and the eighth frequency is higher than the seventh frequency. At the beginning of the transmission period P, the first frequency is down-converted to the sixth frequency, which is the third frequency change trend with a negative slope. In the middle and front part of the transmission period P, the frequency is increased to the seventh frequency and the frequency is higher than the first frequency, which is the fourth frequency change trend with a positive slope. In the middle and rear part of the transmission period P, the frequency is further increased to the eighth frequency, which is the fifth frequency change trend with a positive slope. At the end of the transmission period P, it is restored to the first frequency, which is the sixth frequency change trend with a zero slope. Taking the first frequency as a reference, the slope of the third frequency change trend is negative, and the slopes of the fourth frequency change trend and the fifth frequency change trend are both positive, but the slope of the fourth frequency change trend is lower than the slope of the fifth frequency change trend. Different code elements can be assigned to different degrees of change trends. For example, the code element is "00" for the third frequency change trend, the code element is "01" for the fourth frequency change trend, the code element is "10" for the fifth frequency change trend, and the code element is "11" for the sixth frequency change trend.

[0034] Correspondingly, as another aspect of an embodiment of the present application, an embodiment of the present application provides a data receiving method, which is applied to a slave device, including: receiving a clock signal, and when the clock frequency of the clock signal changes, determining that the clock signal is a composite signal, and parsing the composite signal according to its frequency change trend and transmission period, the composite signal includes a clock signal and a characteristic signal, and the clock signal and the characteristic signal are transmitted synchronously.

[0035] The above-mentioned frequency variation trend and transmission period may be preset in the slave device, and the code element corresponding to the frequency variation trend should also be preset, so that the characteristic signal can be correctly analyzed.

[0036] The slave device obtains the clock signal through the clock GPIO port, and analyzes whether the clock frequency has changed to a certain extent. When there is no change or the clock only has a slight jitter, it enters the first transmission mode and receives data according to the clock signal. When a certain degree of change occurs, it enters the second transmission mode and obtains the corresponding code element through the frequency change trend according to the preset code element rule, and then analyzes the characteristic signal actually carried in the clock signal.

[0037] Similar to the above-mentioned data transmission method, the data receiving method includes a first data receiving mode and a second data receiving mode; in the first data receiving mode, the clock frequency is the first frequency, and the slave device receives the transmission data at the first frequency; in the second data transmission mode, the clock frequency is the combination frequency of the first frequency, the second frequency or / and the third frequency in different time periods, and the slave device receives the composite signal at the combination frequency.

[0038] The above transmission data refers to the host device through other GPIO ports (non-clock GPIO ports, such as Figure 1 In the first transmission mode, the slave device receives the data transmitted by the host device according to the first frequency. Similarly, in the second transmission mode, the slave device receives the data transmitted by the host device in different time periods corresponding to the first frequency, the second frequency, and the third frequency.

[0039] Reference Figure 5, which shows the specific process of the above-mentioned data receiving method, the slave device receives the transmission data, and selectively enters the first receiving mode or the second receiving mode according to whether the transmission data contains a characteristic signal. In the first receiving mode, the synchronization clock frequency of the host device and the slave device is the first frequency, that is, the clock GPIO port of the host device transmits a clock signal of the first frequency, and receives data or command communication at other GPIO ports according to the first frequency; in the second receiving mode, the clock signal is received, and the clock signal with the characteristic signal, that is, the composite signal, is parsed according to the preset frequency change trend rule and transmission period, the characteristic signal therein is extracted, and the transmission data or command communication is received according to the clock signal.

[0040] Considering that the transmission of characteristic signals is a one-way transmission mode, the host device uses error control coding when transmitting characteristic data in the second transmission mode. By adopting error control coding, the slave device has a certain ability to detect and recover error symbols when demodulating composite signals, which effectively improves the stability of transmission and the reliability of data. The typical error control coding is a Hamming code with a code length of 12, 8 information bits, and 4 supervision codes. This means that a single characteristic data transmission will transmit 12 symbols and actually carry 1 byte of valid information.

[0041] As another aspect of the embodiment of the present application, the embodiment of the present application provides a data transmission device and a data receiving device. The data transmission device and the data receiving device can be software modules, and the software modules include several instructions, which are stored in a memory, and the processor can access the memory and call the instructions for execution to complete the data transmission method described in each of the above embodiments.

[0042] In some embodiments, the data transmission device and the data receiving device can be constructed by hardware devices, for example, the data transmission device and the data receiving device can be constructed by one or more chips, and the chips can work in coordination with each other to complete the data transmission method and the data receiving method described in the above embodiments. For another example, the data transmission device and the data receiving device can also be constructed by a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a single-chip microcomputer, an ARM (Acorn RISC Machine), a programmable logic device, a discrete gate or transistor logic, a discrete hardware component, or any combination of these components.

[0043] It should be noted that the above-mentioned data transmission device and data receiving device can execute the data transmission method and data receiving method provided in the implementation mode of the present application, and have the corresponding functional modules and beneficial effects of the execution method. For technical details not fully described in the data transmission device implementation mode, please refer to the data transmission method and data receiving method provided in the implementation mode of the present application.

[0044] An embodiment of the present application also provides a data transmission system, which includes the above-mentioned data transmission device and the above-mentioned data receiving device, the data transmission device is used to execute the above-mentioned data transmission method, and the data receiving device is used to execute the above-mentioned data receiving method.

[0045] Finally, it should be noted that the present application can be implemented in many different forms and is not limited to the embodiments described in this specification. These embodiments are not intended to be additional limitations on the content of the present application. The purpose of providing these implementation methods is to make the understanding of the disclosure of the present application more thorough and comprehensive. And under the thinking of the present application, the above-mentioned technical features continue to be combined with each other, and there are many other changes in different aspects of the present application as described above, which are all deemed to be within the scope of the present application specification. Further, for those of ordinary skill in the art, improvements or changes can be made according to the above description, and all these improvements and changes should fall within the scope of protection of the claims attached to the present application.

Claims

1. A data transmission method, applied to a host device, characterized in that: include: Determine a clock frequency, wherein the clock frequency includes a first frequency, a second frequency lower than the first frequency, and / or a third frequency higher than the first frequency; A composite signal is transmitted through the changing trend of the clock frequency and the transmission period, wherein the composite signal includes a clock signal and a characteristic signal, and the clock signal and the characteristic signal are transmitted synchronously.

2. The data transmission method according to claim 1, characterized in that: The data transmission method includes a first data transmission mode and a second data transmission mode; In the first data transmission mode, the clock frequency is the first frequency, and the host device transmits the clock signal at the first frequency; In the second data transmission mode, the clock frequency is a combination frequency of the first frequency, the second frequency or / and the third frequency in different time periods, and the host device transmits the composite signal at the combination frequency.

3. The data transmission method according to claim 1 or 2, characterized in that: The variation trend of the clock frequency is specifically as follows: Taking the first frequency as the reference frequency, when the clock frequency changes to the second frequency or the third frequency, the code element of the characteristic signal is determined according to the frequency change trend in combination with the transmission period.

4. The data transmission method according to claim 1 or 2, characterized in that: The sum of the values ​​of the second frequency and the third frequency is equal to twice the first frequency.

5. The data transmission method according to claim 1 or 2, characterized in that: In one transmission cycle, average transmission rates of the second frequency and the third frequency are equal to the transmission rate of the first frequency.

6. The data transmission method according to claim 1 or 2, characterized in that: In one transmission cycle, at least a first change trend and / or a second change trend are included, and the slope of the first change trend and the slope of the second change trend are opposite to or in the same direction.

7. A data transmission device, characterized in that: It includes a memory and a processor, the memory is connected to the processor, the processor is used to execute one or more computer programs stored in the memory, and when the processor executes the one or more computer programs, the data transmission device implements the data transmission method according to any one of claims 1 to 6.

8. A data receiving method, applied to a slave device, characterized in that: include: A clock signal is received, and when the clock signal has a clock frequency change, the clock signal is determined to be a composite signal, and the composite signal is analyzed according to its frequency change trend and transmission period, wherein the composite signal includes a clock signal and a characteristic signal, and the clock signal and the characteristic signal are transmitted synchronously.

9. The data receiving method according to claim 8, characterized in that: The clock frequency includes a first frequency, a second frequency lower than the first frequency, and / or a third frequency higher than the first frequency; At the beginning of the transmission period, the frequency variation trend is determined with the first frequency as a reference frequency, and the characteristic signal is analyzed according to the frequency variation trend and the transmission period.

10. The data receiving method according to claim 9, characterized in that: The data receiving method includes a first data receiving mode and a second data receiving mode; In the first data receiving mode, the clock frequency is the first frequency, and the host device receives transmission data at the first frequency; In the second data transmission mode, the clock frequency is a combination frequency of the first frequency, the second frequency and / or the third frequency in different time periods, and the slave device receives the composite signal at the combination frequency.

11. A data receiving device, characterized in that: It includes a memory and a processor, the memory is connected to the processor, the processor is used to execute one or more computer programs stored in the memory, and when the processor executes the one or more computer programs, the data receiving device implements the data receiving method as described in any one of claims 8 to 10.

12. A data transmission system, comprising a data transmission device as claimed in claim 7 and a data receiving device as claimed in claim 11, wherein the data transmission device is used to execute the data transmission method as claimed in any one of claims 1-6, and the data receiving device is used to execute the data receiving method as claimed in any one of claims 8-10.

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