Electronic device, operating method thereof, memory system, and storage medium

Abstract

The embodiment of the invention provides electronic equipment, an operation method of the electronic equipment, a memory system and a storage medium. The electronic equipment comprises a host system and a memory system coupled with the host system, the memory system includes a memory controller; the host system comprises a host storage part; the operation method comprises the following steps: the memory system sends an index value; the index value is stored in the memory controller; the host system receives the index value and obtains serial port information corresponding to the index value according to the index value; serial port information is stored in a host storage part; wherein the storage capacity occupied by the index value is smaller than the storage capacity occupied by the serial port information.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to an electronic device and an operating method thereof, a memory system, and a storage medium. Background Art

[0002] With the development of computer application technology, electronic devices in related technologies generally have log functions, and their log files store a large amount of serial port information to record the operation of the equipment. Maintenance personnel can understand the operation status and abnormal problems of the equipment based on the serial port information.

[0003] However, as people's requirements for electronic devices continue to increase, there are still many problems with the logging function of electronic devices that need to be solved. Summary of the invention

[0004] In view of this, the embodiments of the present disclosure propose an electronic device and an operation method thereof, a memory system, and a storage medium. Among them, the embodiments of the present disclosure provide an electronic device including a host system and a memory system coupled to the host system; the memory system includes a memory controller; the host system includes a host storage unit. The embodiments of the present disclosure provide an operation method of an electronic device, including: the memory system sends an index value; the index value is stored in the memory controller; the host system receives the index value and obtains serial port information corresponding to the index value according to the index value; the serial port information is stored in the host storage unit; wherein the storage capacity occupied by the index value is less than the storage capacity occupied by the serial port information.

[0005] In some embodiments, obtaining the serial port information corresponding to the index value according to the index value includes: obtaining the serial port information corresponding to the index value according to the index value in combination with a mapping table; the mapping table includes all serial port information and index values ​​corresponding to all the serial port information; the mapping table is stored in the host storage unit.

[0006] In some embodiments, the memory system also includes a memory device coupled to the memory controller; the operating method also includes: before the memory system sends the index value, the host system obtains all serial port information in the memory device, sets index values ​​corresponding to all the serial port information; and establishes the mapping table according to all the serial port information and the index values ​​corresponding to all the serial port information.

[0007] In some embodiments, the index value corresponds to the serial port information one by one.

[0008] In some embodiments, the memory system sending the index value includes: sending the index value when an abnormal situation occurs in the memory system.

[0009] An embodiment of the present disclosure also provides an electronic device, which includes: a host system and a memory system coupled to the host system; the memory system includes a memory controller; the host system includes a host storage unit; the memory system is configured to: send an index value; the index value is stored in the memory controller; the host system is configured to: receive the index value, and obtain corresponding serial port information according to the index value; the serial port information is stored in the host control unit; wherein the storage capacity occupied by the index value is less than the storage capacity occupied by the serial port information.

[0010] In some embodiments, the host system is configured to: obtain serial port information corresponding to the index value according to the index value in combination with a mapping table; the mapping table includes all serial port information and index values ​​corresponding to all the serial port information; the mapping table is stored in the host storage unit.

[0011] In some embodiments, the memory system also includes: a memory device coupled to the memory controller; the host system is also configured to: before the memory system sends the index value, obtain all serial port information in the memory device, set index values ​​corresponding to all the serial port information; and establish the mapping table according to all the serial port information and the index values ​​corresponding to all the serial port information.

[0012] In some embodiments, the index value corresponds to the serial port information one by one.

[0013] In some embodiments, the memory system is further configured to send the index value when an abnormal condition occurs in the memory system.

[0014] An embodiment of the present disclosure also provides a memory system coupled to a host system, comprising: a memory controller; the memory controller is configured to: send an index value; the index value is stored in the memory controller; the index value corresponds to serial port information stored in the host system; wherein the storage capacity occupied by the index value is smaller than the storage capacity occupied by the serial port information.

[0015] An embodiment of the present disclosure also provides a memory system coupled to a host system, comprising: a memory controller and a memory device coupled to the memory controller; the memory controller is configured to: send an index value; the index value is stored in the memory controller; the memory device is configured to: receive the index value, determine serial port information corresponding to the index value according to the index value; and send the serial port information to the memory controller; the serial port information is stored in the memory device; the memory controller is also configured to: receive the serial port information; and send the serial port information to the host system.

[0016] In some embodiments, the memory device is configured to: obtain serial port information corresponding to the index value according to the index value in combination with a mapping table; the mapping table includes all serial port information and index values ​​corresponding to all the serial port information; the mapping table is stored in the memory device.

[0017] The embodiments of the present disclosure further provide a storage medium having executable instructions stored thereon. When the executable instructions are executed by an electronic device, the steps of the method for operating the electronic device described in the above embodiments of the present disclosure can be implemented.

[0018] An embodiment of the present disclosure provides an electronic device and an operating method thereof, a memory system, and a storage medium, wherein the electronic device includes a host system and a memory system coupled to the host system; the memory system includes a memory controller; the host system includes a host storage unit; the operating method includes: the memory system sends an index value; the index value is stored in the memory controller; the host system receives the index value, and obtains serial port information corresponding to the index value according to the index value; the serial port information is stored in the host storage unit; wherein the storage capacity occupied by the index value is less than the storage capacity occupied by the serial port information. In the disclosed embodiment, since the storage capacity occupied by the index value is smaller than the storage capacity occupied by the serial port information corresponding to the index value, by storing the serial port information in the host storage unit and storing the index value corresponding to the serial port information in the memory controller, when the memory controller feeds back the serial port information to the host system, the memory controller only needs to send the index value corresponding to the serial port information to the host system, and the host system obtains the corresponding serial port information from the host storage unit according to the index value; in this way, on the one hand, since the storage capacity occupied by the index value sent by the memory controller to the host system is small, the amount of data sent by the memory controller to the host system is reduced, the data transmission time is saved, and it is beneficial to improve the data transmission efficiency; on the other hand, compared with storing the serial port information in the memory controller, storing the index value in the memory controller saves the storage space of the memory controller and improves the memory resource utilization of the memory controller. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 A schematic diagram of an exemplary system having a memory system according to an embodiment of the present disclosure;

[0020] Figure 2a A schematic diagram of an exemplary memory card having a memory system according to an embodiment of the present disclosure;

[0021] Figure 2b A schematic diagram of an exemplary solid-state drive having a memory system according to an embodiment of the present disclosure;

[0022] Figure 3a A schematic diagram of the distribution of storage cells of a three-dimensional NAND memory according to an embodiment of the present disclosure;

[0023] Figure 3b A schematic diagram of an exemplary memory including a peripheral circuit according to an embodiment of the present disclosure;

[0024] Figure 4 A cross-sectional schematic diagram of a memory cell array including a NAND memory string according to an embodiment of the present disclosure;

[0025] Figure 5 A schematic diagram of an exemplary memory device including a memory cell array and a peripheral circuit according to an embodiment of the present disclosure;

[0026] Figure 6 A schematic diagram of the structure of an electronic device provided in an embodiment of the present disclosure;

[0027] Figure 7 A schematic diagram of information interaction between a memory controller and a host system provided by an embodiment of the present disclosure;

[0028] Figure 8 A schematic diagram of the structure of another electronic device provided by an embodiment of the present disclosure;

[0029] Fig. 9 A schematic diagram of a process for implementing an operation method of an electronic device provided by an embodiment of the present disclosure;

[0030] Fig.10 Another schematic diagram of information interaction between a memory controller and a host system provided by an embodiment of the present disclosure;

[0031] Fig.11 A schematic diagram of the composition structure of a memory system provided in an embodiment of the present disclosure.

[0032] In the above drawings (which are not necessarily drawn to scale), similar reference numerals may describe similar components in different views. Similar reference numerals with different letter suffixes may represent different examples of similar components. The accompanying drawings generally illustrate various embodiments discussed herein by way of example and not limitation. DETAILED DESCRIPTION

[0033] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0034] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0035] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0036] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present disclosure necessarily has the first element, component, region, layer or part.

[0037] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0038] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0039] In order to enable a more detailed understanding of the features and technical contents of the embodiments of the present disclosure, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present disclosure.

[0040] The memory device in the embodiments of the present disclosure includes but is not limited to a three-dimensional NAND memory. For ease of understanding, a three-dimensional NAND memory is taken as an example for description.

[0041] Figure 1 A block diagram of an exemplary system 100 having a memory device according to some aspects of the present disclosure is shown. The system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory therein. Figure 1As shown in , system 100 may include a host 108 and a memory system 102, the memory system 102 having one or more memory devices 104 and a memory controller 106. The host 108 may be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of an electronic device. The host 108 may be configured to send data to the memory device 104 or receive data from the memory device 104.

[0042] According to some embodiments, the memory controller 106 is coupled to the memory device 104 and the host 108 and is configured to control the memory device 104. The memory controller 106 can manage data stored in the memory device 104 and communicate with the host 108. In some embodiments, the memory controller 106 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 106 is designed to operate in a high duty cycle environment solid state drive (SSD) or embedded multimedia card (eMMC), which is used as a data storage for mobile devices such as smart phones, tablet computers, laptop computers, etc. and enterprise storage arrays.

[0043] The memory controller 106 may be configured to control the operation of the memory device 104, such as read, erase, and program operations. The memory controller 106 may also be configured to manage various functions regarding data stored or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction codes (ECC) regarding data read from or written to the memory device 104. The memory controller 106 may also perform any other suitable functions, such as formatting the memory device 104. The memory controller 106 may communicate with an external device (e.g., a host 108) according to a specific communication protocol. For example, the memory controller 106 can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, peripheral component interconnect (PCI) protocol, PCI Express (PCI-E) protocol, advanced technology attachment (ATA) protocol, serial ATA protocol, parallel ATA protocol, small computer mini interface (SCSI) protocol, enhanced small disk interface (ESDI) protocol, integrated drive electronics (IDE) protocol, Firewire protocol, etc.

[0044] The memory controller 106 and the one or more memory devices 104 may be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 102 may be implemented and packaged into different types of terminal electronic products. Figure 2a In one example shown in , the memory controller 106 and the single memory device 104 can be integrated into a memory card 202. The memory card 202 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 may also include a processor that connects the memory card 202 to a host (e.g., Figure 1 The memory card connector 204 is coupled to the host 108 in the embodiment. Figure 2b In another example shown in , the memory controller 106 and the plurality of memory devices 104 may be integrated into an SSD 206. The SSD 206 may also include a processor that interfaces the SSD 206 with a host (e.g., Figure 1 In some implementations, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0045] Figure 3a A schematic diagram of the structure of a storage cell array of a three-dimensional NAND memory is given as an example. Figure 3a As shown, the memory cell array of the three-dimensional NAND memory is composed of several parallel and staggered rows of memory cell rows parallel to the gate isolation structure, every two rows of memory cell rows are separated by the gate isolation structure and the upper selection gate isolation structure, and each memory cell row includes a plurality of memory cells. The gate isolation structure may include a first gate isolation structure and a second gate isolation structure, the first gate isolation structure divides the memory cell array into a plurality of memory blocks (Blocks), the plurality of second gate isolation structures may divide the memory blocks into a plurality of finger storage areas (Fingers), and the upper selection gate isolation structure disposed in the middle of each finger storage area may divide the finger storage area into two parts, thereby dividing the finger storage area into two memory slices. Figure 3a The memory block shown in FIG. 1 includes 6 memory cells. In practical applications, the number of memory cells in a memory block is not limited thereto. In some embodiments, each memory block can be coupled to multiple word lines (WL), and multiple memory cells coupled to each independently controlled word line constitute a page.

[0046] It should be noted that Figure 3a The number of memory cell rows between the gate isolation structure and the upper selection gate isolation structure given in the disclosure is only an exemplary demonstration and is not used to limit the number of memory cell rows contained in a finger storage area of ​​the three-dimensional NAND memory in the present disclosure. In actual applications, the number of memory cell rows contained in a finger storage area can be adjusted according to actual conditions, such as 2, 4, 8, 16, etc.

[0047] Figure 3b 1 is a schematic circuit diagram of an exemplary memory device 300 including peripheral circuits according to some aspects of the present disclosure. The memory device 300 may be Figure 1 300 may include a memory cell array 301 and a peripheral circuit 302 coupled to the memory cell array 301. The memory cell array 301 is taken as an example of a three-dimensional NAND memory cell array, wherein the memory cell 306 is a NAND memory cell, and the memory cell 306 is provided in the form of an array of memory strings 308, each memory string 308 extending vertically above a substrate (not shown). Figure 3b As shown in , each memory string 308 may include a lower selection transistor 310 (also known as a source selection transistor BSG, which includes a source selection gate) at its source terminal and an upper selection transistor 312 (also known as a drain selection transistor TSG, which includes a drain selection gate) at its drain terminal. The source selection transistor BSG310 and the drain selection transistor TSG312 can be configured to activate the selected memory string 308 during read and program operations. In some embodiments, the sources of the memory strings 308 in the same memory block 304 are coupled through the same source line (SL) 314 (e.g., a common SL). In other words, according to some embodiments, all memory strings 308 in the same memory block 304 have an array common source (ACS). According to some embodiments, the TSG312 of each memory string 308 is coupled to a corresponding bit line (BL) 316, and user data can be read or written from the bit line 316 via an output bus (not shown). In some embodiments, each storage string 308 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of a transistor having TSG312) or a deselection voltage (e.g., 0 V) ​​to a corresponding TSG312 via one or more TSG lines 313 and / or by applying a selection voltage (e.g., higher than the threshold voltage of a transistor having BSG310) or a deselection voltage (e.g., 0 V) ​​to a corresponding BSG310 via one or more BSG lines 315.

[0048] like Figure 3bAs shown in , the memory string 308 can be organized into a plurality of memory blocks 304, each of which can have a common source line 314 (e.g., coupled to ground). In some embodiments, each memory block 304 is a basic data unit for an erase operation, that is, all memory cells 306 on the same memory block 304 are erased at the same time. In order to erase the memory cells 306 in a selected memory block 304, the source lines 314 coupled to the selected memory block 304 and the unselected memory blocks 304 in the same plane as the selected memory block 304 can be biased with an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)). It should be understood that in some examples, the erase operation can be performed at a half-memory block level, at a quarter-memory block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. The memory cells 306 of adjacent memory strings 308 can be coupled by word lines 318, which select which row of memory cells 306 is affected by the read and program operations. In some embodiments, in combination with the previous Figure 3a , multiple memory cells are isolated by an upper selection gate isolation structure and a gate isolation structure, and multiple memory cells between the upper selection gate isolation structure and the gate isolation structure are arranged into multiple memory cell rows, and each memory cell row is parallel to the gate isolation structure and the upper selection gate isolation structure.

[0049] refer to Figure 3a , Figure 3b Each memory cell 306 in the plurality of memory cells is coupled to a corresponding word line 318, and each memory string 308 is coupled to a corresponding bit line 316 via a corresponding selection transistor (such as the top selection transistor (TSG) 312).

[0050] Figure 4 FIG. 3 is a cross-sectional schematic diagram of an exemplary memory cell array 301 including a memory string 308 using NAND as an example according to some aspects of the present disclosure. Figure 4 As shown, the NAND memory cell array 301 may include a stacked structure 410, which includes a plurality of gate layers 411 and a plurality of insulating layers 412 that are alternately stacked in sequence, and a channel structure that vertically penetrates the gate layers 411 and the insulating layers 412, wherein the channel structure is coupled with each gate layer to form a memory cell, and the channel structure is coupled with a plurality of gate layers in the stacked structure 410 to form a memory string 308. The gate layers 411 and the insulating layers 412 may be alternately stacked, and two adjacent gate layers 411 are separated by a layer of insulating layer 412.

[0051] The constituent material of the gate layer 411 may include a conductive material. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 411 includes a metal layer, for example, a tungsten layer. In some embodiments, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 may include a control gate surrounding a memory cell. The gate layer 411 at the top of the stacked structure 410 may extend laterally as an upper selection gate line, the gate layer 411 at the bottom of the stacked structure 410 may extend laterally as a lower selection gate line, and the gate layer 411 extending laterally between the upper selection gate line and the lower selection gate line may serve as a word line layer.

[0052] In some embodiments, the stacked structure 410 may be disposed on a substrate 401. The substrate 401 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material.

[0053] In some embodiments, the memory string 308 includes a channel structure extending vertically through the stacked structure 410. In some embodiments, the channel structure includes a channel hole filled with (one or more) semiconductor materials (e.g., as a semiconductor channel) and (one or more) dielectric materials (e.g., as a memory film). In some embodiments, the semiconductor channel includes silicon, for example, polysilicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trapping / storage layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a column shape). According to some embodiments, the semiconductor channel, the tunneling layer, the storage layer, and the barrier layer are arranged radially from the center of the column toward the outer surface of the column in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0054] Return to reference Figure 3b, the peripheral circuit 302 may be coupled to the memory cell array 301 through the bit line 316, the word line 318, the source line 314, the BSG line 315, and the TSG line 313. The peripheral circuit 302 may include any suitable analog, digital, and mixed signal circuits for facilitating the operation of the memory cell array 301 by applying a voltage signal and / or a current signal to each target memory cell 306 and sensing a voltage signal and / or a current signal from each target memory cell 306 via the bit line 316, the word line 318, the source line 314, the BSG line 315, and the TSG line 313. The peripheral circuit 302 may include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 5 Some exemplary peripheral circuits are shown, and the peripheral circuit 302 includes a page buffer / sense amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, a control logic 512, a register 514, an interface 516, and a data bus 518. It should be understood that in some examples, it may also include Figure 5 Additional peripheral circuits not shown.

[0055] The page buffer / sense amplifier 504 can be configured to read data from the memory cell array 301 and program (write) data to the memory cell array 301 according to the control signal from the control logic 512. In one example, the page buffer / sense amplifier 504 can store the program data (write user data) to be programmed into the memory cell array 301. In another example, the page buffer / sense amplifier 504 can perform a program verification operation to ensure that the data has been correctly programmed into the memory cell 306 coupled to the selected word line 318. In yet another example, the page buffer / sense amplifier 504 can also sense a low-power signal from the bit line 316 representing the data bit stored in the memory cell 306, and amplify the small voltage swing to a recognizable logic level in a read operation. The column decoder / bit line driver 506 can be configured to be controlled by the control logic 512, and select one or more memory strings 308 by applying a bit line voltage generated from the voltage generator 510.

[0056] The row decoder / word line driver 508 may be configured to be controlled by the control logic 512 and select / deselect the memory block 304 of the memory cell array 301 and select / deselect the word line 318 of the memory block 304. The row decoder / word line driver 508 may also be configured to drive the word line 318 using the word line voltage generated from the voltage generator 510. In some embodiments, the row decoder / word line driver 508 may also select / deselect and drive the BSG line 315 and the TSG line 313. As described in detail below, the row decoder / word line driver 508 is configured to perform a programming operation on the memory cell 306 coupled to the (one or more) selected word lines 318. The voltage generator 510 may be configured to be controlled by the control logic 512 and generate a word line voltage (e.g., a read voltage, a program voltage, a pass voltage, a channel boosting voltage, a verification voltage, etc.), a bit line voltage, and a source line voltage to be supplied to the memory cell array 301.

[0057] The control logic 512 may be coupled to each of the other parts in the peripheral circuits described above, and is configured to control the operation of each of the other parts in the peripheral circuits. The register 514 may be coupled to the control logic 512, and includes a status register, a command register, and an address register for storing status information, a command operation code (OP code), and a command address for controlling the operation of each peripheral circuit. The interface 516 may be coupled to the control logic 512, and act as a control buffer to buffer control commands received from a host (not shown) and relay them to the control logic 512, and to buffer status information received from the control logic 512 and relay them to the host. The interface 516 may also be coupled to the column decoder / bit line driver 506 via the data bus 518, and act as a data I / O interface and a data buffer to buffer data and relay them to the memory cell array 301 or relay or buffer data from the memory cell array 301.

[0058] In the related art, with the rapid development of computer application technology, electronic devices generally have a log function, in which a large amount of serial port information is stored in the log file of the electronic device to record the operation of the device. During the development and debugging process, a large amount of serial port information will be added to the firmware located in the memory controller to record the operation status of the device, abnormal problems (bugs), etc. Developers or maintenance personnel use the log function to find the serial port information in the log file to locate and solve the abnormal problems of the device.

[0059] Exemplary, reference Figure 6 , Figure 7 , Figure 6 A schematic diagram of the structure of an electronic device provided in an embodiment of the present disclosure; Figure 7A schematic diagram of information interaction between a memory controller and a host system provided in an embodiment of the present disclosure; Figure 6 , the electronic device 600 includes a host system 601 and a memory system 602 coupled to the host system 601, the memory system 602 includes a memory controller 603, and the memory controller includes a first firmware 604. In the process of development and debugging, the developer or maintenance personnel uses the host system 601 to save the development or debugging information (i.e., serial port information) in the form of a file in the first firmware 604 of the memory controller 603. Here, the storage capacity of the first firmware can be selected and set according to the storage capacity of the serial port information. In other words, when the storage capacity of the serial port information is larger, the storage capacity of the first firmware used to store the serial port information is larger. When the serial port information needs to be called, the host system 601 sends an instruction to the memory controller 603 to instruct to obtain the corresponding serial port information. Reference Figure 7 After receiving the instruction, the memory controller 603 loads the serial port information stored in the first firmware 604 and sends the serial port information corresponding to the instruction to the host system 601.

[0060] However, with the continuous updating of electronic devices, the number of serial port information to be called gradually increases, and the memory space (storage capacity of the first firmware) used to store serial port information in the memory controller also increases accordingly. At the same time, the memory controller spends more time to output serial port information; and the serial port information stored in the first firmware is difficult to be removed, which brings an additional burden to the use of electronic devices. Exemplarily, when the storage capacity of the serial port information to be called by the host system is 36 bytes (Bytes), the memory controller loads the 36Bytes serial port information corresponding to the instruction in the first firmware, and then sends the 36Bytes serial port information to the host system. Based on this, as the number of serial port information to be called gradually increases, the number of serial port information sent by the memory controller to the host system also gradually increases. In addition, it should be noted that in the process of the memory system (here is the memory controller) sending serial port information to the host system, the serial port information needs to be formatted into a string first, and then the string is sent to the host system; in this way, as the number of serial port information called gradually increases, the complexity of the memory system transmitting serial port information to the host system increases.

[0061] Based on one or more of the above problems, the present disclosure provides an electronic device and an operating method thereof, a memory system, and a storage medium; Figure 8 , Figure 8A schematic diagram of the composition structure of another electronic device provided in an embodiment of the present disclosure; wherein the electronic device 800 includes a host system 801 and a memory system 802 coupled to the host system 801; the host system 801 includes a host storage unit 803 and a host control unit 804. The host control unit 804 is used to send instructions, and the host storage unit 803 is used to store instruction information, etc. The host control unit 804 and the host storage unit 803 can be coupled in any suitable manner; the memory system 802 includes a memory controller 805 and a memory device 806; the memory controller 805 is used to control the memory device 806 to perform operations such as reading, writing, and erasing, and the memory controller 805 and the memory device 806 can be coupled in any suitable manner. The memory controller 805 includes a second firmware 807, which can be used to load / store information corresponding to different applications, such as storing the index value described below. It should be noted that the first firmware 604 described in the above embodiment and the second firmware 807 described in the embodiment of the present disclosure are both located in the corresponding memory controller. In some embodiments, the first firmware 604 and the second firmware 807 may be the same or different. It should be understood that the storage capacity of the second firmware can be selected and set according to actual needs, such as the storage capacity occupied by the index value. Exemplarily, when the storage capacity of the index value is small, the storage capacity of the second firmware for storing the index value is set to be small, so that the storage capacity of the memory controller can be saved.

[0062] refer to Fig. 9 , Fig. 9 The present invention provides a schematic diagram of an operation method of an electronic device according to an embodiment of the present invention; wherein the operation method of the electronic device comprises the following steps:

[0063] Step S901: the memory system sends an index value; the index value is stored in a memory controller of the memory system;

[0064] Step S902: the host system receives the index value, and obtains the serial port information corresponding to the index value according to the index value; the serial port information is stored in the host storage unit; wherein the storage capacity occupied by the index value is smaller than the storage capacity occupied by the serial port information.

[0065] It should be noted that before executing the above step S901, the operation method further includes: the host system obtains all serial port information in the memory device, sets index values ​​corresponding to all serial port information; and establishes a mapping table according to all serial port information and index values ​​corresponding to all serial port information.

[0066] Exemplary, reference Figure 8 , Fig. 9 and Fig.10 , Fig.10Another schematic diagram of information interaction between a memory controller and a host system provided in an embodiment of the present disclosure. Among them, after the memory device 806 completes the programming / writing operation of the data, the log files corresponding to all the applications in the memory device 806 are scanned to obtain the serial port information stored in all the log files; a corresponding index value is set for each serial port information in all the serial port information, and all the index values ​​are stored in the memory controller 805 of the memory system; specifically, all the index values ​​are stored in the second firmware 807 of the memory controller 805. Here, the index value and the serial port information can be one-to-one or one-to-many; in order to facilitate accurate search of serial port information, in the embodiment of the present disclosure, the index value and the serial port information correspond one-to-one. In some specific embodiments, the index value is determined by the file where the serial port information is located and the position in the file, so that it can be ensured that the index value corresponds one-to-one with the serial port information. In some embodiments, reference Fig.10 The number of index values ​​may include multiple, such as index value 1, index value 2, index value 3…, and the number of corresponding serial port information may also include multiple, such as serial port information 1, serial port information 2, serial port information 3…, where index value 1 corresponds to serial port information 1, index value 2 corresponds to serial port information 2, index value 3 corresponds to serial port information 3….

[0067] It should be noted that the storage capacity occupied by the index value is less than the storage capacity occupied by the serial port information corresponding to the index value; in some specific embodiments, the storage capacity occupied by the index value is 1 / 6 of the storage capacity occupied by the corresponding serial port information; that is, the storage capacity occupied by the serial port information is 6 times the storage capacity occupied by the index value corresponding to the serial port information; exemplarily, the storage capacity occupied by the serial port information is 36Bytes, and the storage capacity occupied by the index value corresponding to the serial port information is 6Bytes. Based on this, since the storage capacity occupied by the index value is less than the storage capacity occupied by the serial port information, the index value is stored in the memory controller, and the memory controller can save a lot of storage space compared to storing the serial port information corresponding to the index value in the memory controller.

[0068] Next, a mapping table is constructed based on all the serial port information and all the index values ​​to achieve the mapping between the serial port information and the index values. In other words, the mapping table includes all the serial port information and the index values ​​corresponding to all the serial port information. Next, the mapping table and all the corresponding serial port information are stored in the host storage unit 803.

[0069] It should be noted that, in the embodiment of the present disclosure, after the mapping table is constructed for all serial port information and all index values, all serial port information may be removed to reduce the additional storage space occupied by the serial port information.

[0070] Next, step S901 is executed to send an index value to the host system 801 when an abnormal situation occurs in the memory system 802 .

[0071] It should be noted that abnormal situations may include situations where a vulnerability (bug) occurs in the memory system and maintenance personnel call serial port information; they may also include situations where developers or maintenance personnel subjectively want to obtain or view serial port information when the memory system is operating normally. In the above situations, developers or maintenance personnel can use the host system (such as the host control unit) to send instructions to the memory system to instruct it to obtain the corresponding serial port information.

[0072] In step S901, after receiving the instruction, the memory system sends the index value corresponding to the serial port information to the host control unit of the host system according to the instruction. It should be understood that the storage capacity of the index value is smaller than the storage capacity of the serial port information corresponding to the index value. The memory controller sends the index value to the host system, which can reduce the amount of data sent by the memory controller compared to the memory controller sending the corresponding serial port information to the host system. At the same time, it reduces the time spent by the memory controller and improves the data transmission efficiency or transmission performance.

[0073] Next, step S902 is executed, where the host system is used to receive the index value, and after receiving the corresponding index value, obtain the serial port information corresponding to the index value according to the index value.

[0074] In some specific embodiments, the host control unit 804 of the host system is used to receive the index value, search the mapping table stored in the host storage unit 803 according to the index value, and obtain the serial port information corresponding to the index value in combination with the mapping table. Fig.10 , the memory controller 805 loads the corresponding index value in the second firmware 807, the storage capacity of the index value is, for example, 6 Bytes, and sends the index value to the host system 801. After receiving the index value, the host system 801 traverses all serial port information in conjunction with the mapping table 808, parses the corresponding index value, and determines the serial port information corresponding to the corresponding index value.

[0075] In the disclosed embodiment, during the process of the host system acquiring serial port information, the memory system only needs to send an index value to the host system, and there is no need to convert the serial port information into a formatted string for transmission. In this way, on the one hand, the amount of transmitted data is reduced and the data transmission efficiency is improved; on the other hand, the complexity of data transmission is reduced and the data transmission performance is improved.

[0076] Based on this, in the embodiment of the present disclosure, since the storage capacity occupied by the index value is smaller than the storage capacity occupied by the serial port information corresponding to the index value, by storing the serial port information in the host storage unit and storing the index value corresponding to the serial port information in the memory controller, when the memory controller needs to feedback the serial port information to the host system, the memory controller only needs to send the index value corresponding to the serial port information to the host system, and the host system obtains the corresponding serial port information from the host storage unit according to the index value; in this way, on the one hand, since the storage capacity occupied by the index value sent by the memory controller to the host system is small, the amount of data sent by the memory controller to the host system is reduced, the data transmission time is saved, and it is beneficial to improve the data transmission efficiency and transmission performance; on the other hand, compared with storing the serial port information in the memory controller, storing the index value in the memory controller saves the storage space of the memory controller and improves the memory resource utilization of the memory controller.

[0077] Based on the operating method of the above-mentioned electronic device, an electronic device is provided in an embodiment of the present disclosure, wherein the electronic device includes: a host system and a memory system coupled to the host system; the memory system includes a memory controller; the host system includes a host storage unit; the memory system is configured to: send an index value; the index value is stored in the memory controller; the host system is configured to: receive the index value, and obtain corresponding serial port information according to the index value; the serial port information is stored in the host control unit; wherein the storage capacity occupied by the index value is less than the storage capacity occupied by the serial port information.

[0078] In some embodiments, the host system is configured to: obtain serial port information corresponding to the index value according to the index value in combination with a mapping table; the mapping table includes all serial port information and index values ​​corresponding to all the serial port information; the mapping table is stored in the host storage unit.

[0079] In some embodiments, the memory system also includes: a memory device coupled to the memory controller; the host system is also configured to: before the memory system sends the index value, obtain all serial port information in the memory device, set index values ​​corresponding to all the serial port information; and establish the mapping table according to all the serial port information and the index values ​​corresponding to all the serial port information.

[0080] In some embodiments, the index value corresponds to the serial port information one by one.

[0081] In some embodiments, the memory system is further configured to send the index value when an abnormal condition occurs in the memory system.

[0082] Based on the above-mentioned electronic device and its operating method, a memory system is provided in an embodiment of the present disclosure, wherein the memory system is coupled to a host system, and the memory system includes: a memory controller; the memory controller is configured to: send an index value; the index value is stored in the memory controller; the index value corresponds to serial port information stored in the host system; wherein the storage capacity occupied by the index value is less than the storage capacity occupied by the serial port information.

[0083] Based on the above-mentioned electronic device and its operation method, another memory system is provided in an embodiment of the present disclosure, wherein the memory system is coupled to a host system, and includes: a memory controller and a memory device coupled to the memory controller; the memory controller is configured to: send an index value; the index value is stored in the memory controller; the memory device is configured to: receive the index value, determine serial port information corresponding to the index value according to the index value; and send the serial port information to the memory controller; the serial port information is stored in the memory device; the memory controller is also configured to: receive the serial port information; and send the serial port information to the host system.

[0084] refer to Fig.11 , Fig.11 A schematic diagram of the composition structure of a memory system provided in an embodiment of the present disclosure, wherein the memory system 1101 includes a memory controller 1102 and a memory device 1103; the memory controller 1102 is used to control the memory device 1103 to perform operations such as reading, writing, and erasing, and the memory controller 1102 and the memory device 1103 can be coupled in any suitable manner. The memory controller 1102 includes a second firmware 1104, and the second firmware 1104 can be used to load information corresponding to different applications, such as the index value described below. It should be noted that the second firmware 1104 described in the embodiment of the present disclosure is the same as the second firmware 807 described in the aforementioned embodiment. As in the aforementioned embodiment, the serial port information corresponds to the index value one by one, and a mapping table is constructed according to all the serial port information and the index values ​​corresponding to all the serial port information. The memory device 1103 includes a third firmware 1105, and the third firmware 1105 can be used to store all the serial port information and the mapping table. In other words, in the embodiment of the present disclosure, all serial port information and its mapping table are stored in the memory device 1103, such as the third firmware 1105 of the memory device 1103; the index value corresponding to the serial port information is stored in the memory controller 1102, such as the second firmware 1104 of the memory controller 1102.

[0085] Among them, when the memory system 1101 receives the host system ( Fig.11After receiving the instruction to obtain the serial port information sent by the memory controller 1102 (not shown), the memory device 1103 sends the index value to the memory device 1103 through the memory controller 1102. In some embodiments, the memory device 1103 traverses all the serial port information according to the received index value and the mapping table, determines the serial port information corresponding to the index value, and then sends the serial port information to the memory controller. After obtaining the corresponding serial port information, the memory controller formats the serial port information into a character string and sends it to the host system.

[0086] In the disclosed embodiment, since the storage capacity occupied by the index value is smaller than the storage capacity occupied by the serial port information corresponding to the index value, storing the index value in the memory controller can save the storage space of the memory controller and improve the storage space utilization rate of the memory controller compared to storing the serial port information corresponding to the index value in the memory controller.

[0087] A storage medium is also provided in an embodiment of the present disclosure. The storage medium stores executable instructions. When the executable instructions are executed by an electronic device, the steps of the electronic device operating method described in the above embodiment of the present disclosure can be implemented.

[0088] In some specific embodiments, the storage medium can be a magnetic random access memory (FRAM), a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, a magnetic surface storage, an optical disk, or a compact disc read-only memory (CD-ROM); it can also be various devices including one or any combination of the above-mentioned memory devices.

[0089] In some embodiments, executable instructions may be in the form of a program, software, software module, script or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and may be deployed in any form, including as a stand-alone program or as a module, component, subroutine or other unit suitable for use in a computing environment.

[0090] As an example, executable instructions may, but need not, correspond to a file in a file system, may be stored as part of a file that stores other programs or data, such as in one or more scripts in a HyperText Markup Language (HTML) document, in a single file dedicated to the program in question, or in multiple coordinated files (e.g., files storing one or more modules, subroutines, or code portions).

[0091] It should be noted that: "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. In addition, the technical solutions recorded in the embodiments of the present disclosure can be combined arbitrarily without conflict. The above is only a preferred embodiment of the present disclosure and is not intended to limit the scope of protection of the present disclosure.

Claims

1. A method for operating an electronic device, characterized in that: The electronic device includes a host system and a memory system coupled to the host system; The memory system includes a memory controller; The host system includes a host storage unit; The operation method comprises: The memory system sends an index value; the index value is stored in the memory controller; The host system receives the index value, and acquires serial port information corresponding to the index value according to the index value; the serial port information is stored in the host storage unit; The storage capacity occupied by the index value is smaller than the storage capacity occupied by the serial port information.

2. The operating method according to claim 1, characterized in that: The acquiring, according to the index value, serial port information corresponding to the index value comprises: According to the index value, in combination with the mapping table, obtaining the serial port information corresponding to the index value; The mapping table includes all serial port information and index values ​​corresponding to all the serial port information; the mapping table is stored in the host storage unit.

3. The operating method according to claim 2, characterized in that: The memory system also includes a memory device coupled to the memory controller; The operation method also includes: Before the memory system sends the index value, the host system obtains all serial port information in the memory device, sets index values ​​corresponding to all the serial port information; and establishes the mapping table according to all the serial port information and the index values ​​corresponding to all the serial port information.

4. The operating method according to claim 3, characterized in that: The index value corresponds to the serial port information one by one.

5. The operating method according to claim 1, characterized in that: The memory system sends an index value, including: When an abnormal situation occurs in the memory system, the index value is sent.

6. An electronic device, characterized in that: The electronic device comprises: a host system and a memory system coupled to the host system; the memory system comprises a memory controller; the host system comprises a host storage unit; The memory system is configured to: send an index value; the index value is stored in the memory controller; The host system is configured to: receive the index value, and obtain corresponding serial port information according to the index value; the serial port information is stored in the host control unit; The storage capacity occupied by the index value is smaller than the storage capacity occupied by the serial port information.

7. The electronic device according to claim 6, characterized in that: The host system is configured as: According to the index value, in combination with the mapping table, obtaining the serial port information corresponding to the index value; The mapping table includes all serial port information and index values ​​corresponding to all the serial port information; the mapping table is stored in the host storage unit.

8. The electronic device according to claim 7, characterized in that: The memory system further includes: a memory device coupled to the memory controller; The host system is also configured to: Before the memory system sends the index value, all serial port information in the memory device is obtained, and index values ​​are set corresponding to all the serial port information; and the mapping table is established according to all the serial port information and the index values ​​corresponding to all the serial port information.

9. The electronic device according to claim 8, characterized in that: The index value corresponds to the serial port information one by one.

10. The electronic device according to claim 6, characterized in that: The memory system is also configured to: When an abnormal situation occurs in the memory system, the index value is sent.

11. A memory system, characterized in that: coupled to a host system, comprising: a memory controller; The memory controller is configured to: send an index value; the index value is stored in the memory controller; the index value corresponds to the serial port information stored in the host system; The storage capacity occupied by the index value is smaller than the storage capacity occupied by the serial port information.

12. A memory system, characterized in that: coupled to a host system, comprising: a memory controller and a memory device coupled to the memory controller; The memory controller is configured to: send an index value; the index value is stored in the memory controller; The memory device is configured to: receive the index value, determine the serial port information corresponding to the index value according to the index value; and send the serial port information to the memory controller; the serial port information is stored in the memory device; The memory controller is further configured to: receive the serial port information; and send the serial port information to the host system.

13. The memory system according to claim 12, wherein: The memory device is configured to: acquire serial port information corresponding to the index value according to the index value in combination with a mapping table; The mapping table includes all serial port information and index values ​​corresponding to all serial port information; the mapping table is stored in the memory device.

14. A storage medium, characterized in that: The storage medium stores executable instructions, and when the executable instructions are executed by the electronic device, the steps of the electronic device operating method described in any one of claims 1 to 5 can be implemented.

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