Routing network, clock frequency management method of routing node and related equipment

Abstract

The embodiment of the invention provides a routing network, a clock frequency management method of a routing node and related equipment, and the routing network comprises at least one routing node; each routing node comprises at least one input port and a buffer which is correspondingly connected with the input port and is used for caching input information; each routing node is used for determining the input information caching amount of the buffer correspondingly connected with each input port; determining a path load condition based on the input information caching amount; a clock frequency management request matched with the path load condition is sent to an upstream routing node based on the path load condition, so that the current clock frequency of the upstream routing node conforms to a preset clock frequency, and the preset clock frequency is smaller than or equal to the current clock frequency; and each input port sends a clock frequency management request to the output port of the corresponding upstream routing node. According to the technical scheme provided by the embodiment of the invention, the power consumption of the routing network can be accurately reduced.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of computer technology, and in particular to a clock frequency management method for a routing network and a routing node and related equipment. Background Art

[0002] As a communication architecture of SoC (System on Chip), routing network (such as Network on Chip, NoC) connects various processors, memory, I / O and other units inside SoC by imitating the design concept of computer network to form a reconfigurable, efficient and flexible communication network. As the design integration of chip system increases, the complexity of routing network in chip system also increases accordingly, and the proportion of power consumption of routing network in the total power consumption of chip system also increases accordingly.

[0003] Therefore, in this context, how to provide a technical solution to accurately reduce the power consumption of the routing network has become a technical problem that technical personnel in this field urgently need to solve. Summary of the invention

[0004] In view of this, an embodiment of the present invention provides a routing network, a clock frequency management method of a routing node, and related devices to accurately reduce the power consumption of the routing network.

[0005] To achieve the above objectives, the embodiments of the present invention provide the following technical solutions.

[0006] In a first aspect, an embodiment of the present invention provides a routing network, comprising: at least one routing node; each of the routing nodes comprises: at least one input port and a buffer connected to each input port, each buffer being used to buffer input information received by the corresponding connected input port;

[0007] Each routing node is used to:

[0008] Determine the input information buffer capacity of the buffer corresponding to each input port of the routing node; determine the path load between the input port and the output port of the upstream routing node that interacts with the input port based on the input information buffer capacity; and send a clock frequency management request matching the path load condition to the upstream routing node based on the path load condition, so that the current clock frequency of the upstream routing node meets the preset clock frequency, wherein the preset clock frequency is less than or equal to the current clock frequency; and send the clock frequency management request from each input port to the output port of the corresponding upstream routing node.

[0009] In a second aspect, an embodiment of the present invention provides a clock frequency management method for a routing node, which is applied to each routing node in the routing network described in the first aspect, and the method includes:

[0010] Determining the input information buffer capacity of the input port of the routing node;

[0011] Determine the path load between the input port and the output port of the upstream routing node with which the input port interacts with information based on the input information buffer amount;

[0012] Based on the path load condition, a clock frequency management request matching the path load condition is sent to the upstream routing node, so that the current clock frequency of the upstream routing node meets the preset clock frequency, wherein the preset clock frequency is less than or equal to the current clock frequency;

[0013] The clock frequency management request is sent to an output port of a corresponding upstream routing node.

[0014] In a third aspect, an embodiment of the present invention provides a clock frequency management method for a routing node, which is applied to each routing node in the routing network described in the first aspect, and the method includes:

[0015] Acquiring clock frequency management requests received by each output port of the routing node;

[0016] Determining an executable target clock frequency management request based on the preset clock frequencies in each clock frequency management request;

[0017] Executing the target clock frequency management request so that the current clock frequency of the routing node meets the preset clock frequency in the target clock frequency management request; the preset clock frequency is less than or equal to the current clock frequency;

[0018] The clock frequency management request is a request sent by an input port of each downstream routing node for information interaction with each output port of the routing node.

[0019] In a fourth aspect, an embodiment of the present invention provides an electronic device, including a memory and a processor, wherein the memory stores a program, and the processor calls the program stored in the memory to execute the clock frequency management method of the routing node as described in the first aspect.

[0020] In a fifth aspect, an embodiment of the present invention provides a storage medium, wherein the storage medium stores a program, and when the program is executed, the clock frequency management method of the routing node as described in the first aspect is implemented.

[0021] In a sixth aspect, an embodiment of the present invention provides a computer program product, including a computer program, wherein when the computer program is executed by a processor, the clock frequency management method of the routing node as described in the first aspect is implemented.

[0022] A routing network provided by an embodiment of the present invention comprises: at least one routing node; each of the routing nodes comprises: at least one input port and a buffer corresponding to each input port, each buffer being used to buffer input information received by the correspondingly connected input port; each routing node is used to: determine the input information buffer capacity of the buffer corresponding to each input port of the routing node; determine the path load condition between the input port and the output port of the upstream routing node with which the input port interacts with information based on the input information buffer capacity; and send a clock frequency management request matching the path load condition to the upstream routing node based on the path load condition, so that the current clock frequency of the upstream routing node meets the preset clock frequency, wherein the preset clock frequency is less than or equal to the current clock frequency; and send the clock frequency management request by each input port to the output port of the corresponding upstream routing node.

[0023] It can be seen that the technical solution provided by the embodiment of the present invention can determine the input information cache amount of the buffer connected to each input port of the routing node when the routing node acts as a downstream routing node in the routing network, so as to determine the path load between the output ports of the upstream routing node connected to the input port. Since the path load is proportional to the clock frequency and the power consumption of the routing network, that is, the greater the path load, the greater the power consumption of the routing network, and the higher the clock frequency; therefore, after determining the input information cache amount of the input port, the embodiment of the present invention can generate a matching clock frequency management request based on the path load determined by the input information cache amount, so that the path load corresponding to the input port for information interaction is directly proportional to the clock frequency and the power consumption of the routing network. The current clock frequency of the upstream routing node meets the preset clock frequency; since the preset clock frequency is less than or equal to the current clock frequency, based on the technical solution provided by the embodiment of the present invention, since the preset clock frequency is less than the current clock frequency, the generated clock frequency management request can achieve the effect of reducing the current clock frequency of the upstream routing node when the path load situation is that the path is blocked, thereby reducing the transmission of high-frequency information of the upstream routing node and reducing the power consumption of the routing node; at the same time, when the path load situation is that the path is not blocked, a clock frequency management request of the preset clock frequency equal to the current clock frequency can be sent to the upstream routing node, so that the current clock frequency of the upstream routing node can be maintained. It can be seen that this solution can comprehensively consider the path load situation of the downstream routing node to send a clock frequency management request that meets the path load situation (i.e., matches the path load situation) to the upstream routing node, so as to achieve refined control of the power consumption of each routing node, thereby accurately reducing the power consumption of the routing network. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0025] Figure 1 is a schematic diagram of a structure of a routing network provided by an embodiment of the present invention;

[0026] Figure 2 is a schematic diagram of the structure of a routing network with a mesh topology structure provided by an embodiment of the present invention;

[0027] Figure 3 It is a schematic diagram of a working process of a routing network provided by an embodiment of the present invention;

[0028] Figure 4 It is a flow chart of a clock frequency management method for a routing node provided by an embodiment of the present invention;

[0029] Figure 5 is a result schematic diagram of different path load levels provided by an embodiment of the present invention;

[0030] Figure 6 is another flow chart of the clock frequency management method of the routing node provided by the embodiment of the present invention;

[0031] Figure 7 It is a schematic diagram of a process of executing a clock frequency management request provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0032] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0033] With the development of integrated circuits and the improvement of technology, the integration of chip systems is also increasing, and large-scale SoC (System on Chip) design has become the mainstream. Routing networks (such as NoC (Network on Chip)) are used to realize the on-chip interconnection of various devices in SoC, building the skeleton of the entire SoC and playing a pivotal role in the entire SoC.

[0034] Since NoC is distributed throughout the SoC, it accounts for a large proportion of the power consumption of the entire SoC. Therefore, the power consumption of NoC has become the most challenging aspect affecting the entire SoC.

[0035] In SoC design, NoC is usually designed as a synchronous single-frequency mode, which is divided into fixed frequency mode and variable frequency mode. Fixed frequency mode NoC is mostly used in embedded SoC design. In this design, the entire NoC uses a unified working clock, and the clock frequency will no longer change after the SoC is running normally. Variable frequency mode NoC has been widely used in the design of various types of SoCs. Designers predetermine the typical application scenarios of SoCs, and determine and record the operating frequency of NoC in each application scenario based on the bandwidth and latency requirements of the application scenarios for NoC. When the SoC is running, the preset operating frequency is selected for the NoC based on the current working scenario, and the NoC operating frequency is updated only when the working scenario changes.

[0036] Although the above-mentioned variable frequency mode NoC can optimize the proportion of NoC power consumption in SoC power consumption to a certain extent, since the entire NoC runs at a uniform operating frequency and cannot adaptively adjust the operating frequency, it is very necessary to accurately reduce the power consumption of NoC.

[0037] In order to solve the above problems, an embodiment of the present invention provides a routing network, which is used to provide a structural basis for accurately reducing the power consumption of the routing network.

[0038] Please refer to Figure 1 , Figure 1 It is a schematic diagram of the structure of a routing network provided by an embodiment of the present invention.

[0039] like Figure 1 As shown, the routing network includes at least one routing node 1; each routing node 1 includes: at least one input port 11 and a buffer 12 corresponding to each input port 11, each buffer 12 is used to buffer input information received by the corresponding input port 11;

[0040] Each routing node 1 is used to:

[0041] Determine the input information cache capacity of the buffer 12 corresponding to each input port 11 of the routing node 1; determine the path load between the input port 12 and the output port of the upstream routing node that interacts with the input port 12 based on the input information cache capacity; and send a clock frequency management request matching the path load condition to the upstream routing node based on the path load condition, so that the current clock frequency of the upstream routing node meets the preset clock frequency, and the preset clock frequency is less than or equal to the current clock frequency; and, each input port 12 sends a clock frequency management request to the output port of the corresponding upstream routing node.

[0042] In the routing network provided by the embodiment of the present invention, a buffer 12 is correspondingly provided at each input port 11 of each routing node 1 for buffering input information received by the correspondingly connected input port 11 .

[0043] Therefore, each input port 11 can determine the path load status between the input port 11 and the output port of the upstream routing node connected thereto by checking the buffer status (input information buffer amount) in the buffer 12 .

[0044] Then, a clock frequency management request is generated and sent based on the path load condition, so that the current clock frequency of the upstream routing node meets the preset clock frequency.

[0045] The preset clock frequency is determined based on the path load condition, and the preset clock frequency is less than or equal to the current clock frequency. Therefore, when the current clock frequency meets the preset clock frequency, the clock frequency of the upstream routing node has the function of alleviating the path load condition, thereby providing a structural basis for reducing the power consumption of the upstream routing node and thereby accurately reducing the power consumption of the routing network.

[0046] It can be seen that the technical solution provided by the embodiment of the present invention can determine the input information cache amount of the cache connected to each input port of the routing node when the routing node acts as a downstream routing node in the routing network, so as to determine the path load between the output ports of the upstream routing node connected to the input port. Since the path load is proportional to the clock frequency and the power consumption of the routing network, that is, the greater the path load, the greater the power consumption of the routing network, and the higher the clock frequency; therefore, after determining the input information cache amount of the input port, the embodiment of the present invention can generate a matching clock frequency management request based on the path load determined by the input information cache amount, so that the upstream routing node The current clock frequency meets the preset clock frequency; since the preset clock frequency is less than or equal to the current clock frequency, based on the technical solution provided by the embodiment of the present invention, since the preset clock frequency is less than the current clock frequency, the generated clock frequency management request can achieve the effect of reducing the current clock frequency of the upstream routing node when the path load situation is that the path is blocked, thereby reducing the transmission of high-frequency information of the upstream routing node and reducing the power consumption of the routing node; at the same time, when the path load situation is that the path is not blocked, a clock frequency management request of the preset clock frequency equal to the current clock frequency can be sent to the upstream routing node, so that the current clock frequency of the upstream routing node can be maintained. It can be seen that this solution can comprehensively consider the path load situation of the downstream routing node to send a clock frequency management request that meets the path load situation (i.e., matches the path load situation) to the upstream routing node, so as to achieve refined control of the power consumption of each routing node, thereby accurately reducing the power consumption of the routing network.

[0047] In one embodiment, the input port 12 may include different types of physical channels, and each type of physical channel is connected to a corresponding buffer 12; the input information includes corresponding types of input information transmitted by each type of physical channel; the buffer 12 connected to each type of physical channel is used to cache the corresponding types of input information transmitted by the physical channel.

[0048] The input port 11 of each routing node 1 can be composed of multiple physical channels of different types. In order to facilitate the caching of input information transmitted by different types of physical channels, a corresponding number of n buffers 12 can be set based on the number n of physical channels in an input port 11, and each buffer 12 caches input information received by a type of physical channel.

[0049] In one embodiment, each type of input information includes: input information of a command type transmitted through a physical channel of a command type, input information of a response type transmitted through a physical channel of a response type, and input information of a data type transmitted through a physical channel of a data type, wherein the input information of the command type includes input information of a data read or write command type and input information of a consistency command type.

[0050] Exemplarily, the physical channel for transmitting input information of a data read or write command type may be a request command channel (Req Channel); the physical channel for transmitting a response type may be a response channel (Rsp Channel), and the input information of the response type may be a read or write response; the physical channel for transmitting a data type may be a data channel (Data Channel); and the physical channel for transmitting input information of a consistency command type may be a consistency command channel (Probe Channel).

[0051] Please continue to refer to Figure 1 , each routing node 1 may also include: at least one output port 13;

[0052] Each routing node 1 is also used for:

[0053] Obtaining clock frequency management requests received by each output port 13 of the routing node 1; and determining executable target clock frequency management requests based on the preset clock frequencies in each clock frequency management request; and executing the target clock frequency management request so that the current clock frequency of the routing node meets the preset clock frequency in the target clock frequency management request;

[0054] The clock frequency management request is a request sent by the input port of each downstream routing node for information interaction with each output port 13 of the routing node 1 .

[0055] It can be seen that in the embodiment of the present invention, when each routing node 1 generates a clock frequency management request, it is generated by each input port 11, and whether each routing node 1 maintains or switches the current clock frequency is determined and executed after comprehensive consideration of the clock frequency management request received by each output port 13 and sent by the input port of the downstream routing node corresponding to each output port 13. Therefore, during the operation of the chip system, the situation that each routing node in the routing network acts as both an upstream routing node and a downstream routing node can be fully considered, and the current clock frequency of each routing node 1 can be accurately and reliably adjusted to provide a basis for accurately reducing the clock frequency of the routing node, thereby achieving accurate reduction of the power consumption of the routing network.

[0056] As the design integration of the chip system increases, the number of routing nodes 1 in the routing network in the chip system also increases, and the topological structure types of the routing network formed by each routing node 1 are also enriched. Therefore, in the routing network described in the embodiment of the present invention, the topological structure formed by each routing node at least includes: a mesh topological structure, a ring topological structure, and a crossbar structure.

[0057] In the ring topology, each routing node is connected to two other routing nodes to form a closed loop, and data is transmitted along the ring. It has the characteristics of high transmission efficiency, easy implementation and maintenance, etc.

[0058] In a mesh topology, all routing nodes are interconnected, and each routing node is connected to at least two other routing nodes, forming an integrated network between all routing nodes. It has high reliability and flexibility.

[0059] The crossbar structure is also called a crossbar switch matrix or a crossbar switch matrix. It consists of multiple input ports, multiple output ports, and a switch matrix. It has the characteristics of internal non-blocking, high scalability, and high switching capacity.

[0060] Of course, the topology of the routing network can also be a bus topology (Bus Topology): all devices are connected to a shared communication line, and data is transmitted along this line; star topology (Star Topology): all nodes are directly connected to a central node, and the central node is responsible for forwarding data.

[0061] The above topology is only an example, and any routing network with any topology can adopt the configuration of the buffer in the routing network and the determination of the buffer status evaluation structure provided by the embodiment of the present invention, thereby realizing precise control of the power consumption of each routing node based on the clock frequency management request sent by each input port.

[0062] To facilitate understanding of the topological structure of a routing network, the embodiment of the present invention is described by taking a routing network with a mesh topological structure as an example.

[0063] Please refer to Figure 2 , Figure 2 It is a schematic diagram of the structure of a routing network of a mesh topology structure provided by an embodiment of the present invention.

[0064] like Figure 2 As shown, the routing network includes:

[0065] 9 routing nodes (RU, router): routing node 1 0 、Routing Node 11 、Routing Node 1 2 、Routing Node 1 3 、Routing Node 1 4 、Routing Node 1 5 、Routing Node 1 6 、Routing Node 1 7 、Routing Node 1 8 .

[0066] Functional modules mounted on 12 mounting nodes: M0~M4, MS0~MS2, S0~S3.

[0067] Among them, M represents the function module (Function) as the sender (master); S represents the function as the receiver (salve); MS means that the function can be used as both a master and a slave.

[0068] Each mount node can mount one Function. Function can be a processor core (Core), memory (memory) or an input / output (Input / Output) device.

[0069] Figure 2 In the structure shown, 9 RUs form a 3*3 mesh topology.

[0070] by Figure 2 For example, each routing node in the structure shown has 4 input ports and 4 output ports. Figure 2 Each routing node in the structure shown is a 4*4 crossbar structure consisting of 4 input ports and 4 output ports. The main function of each routing node is to buffer the input information received by the input port and to implement routing via the output port. The crossbar structure can be used to route the input information received by each input port to any output port.

[0071] Each input port can be composed of multiple physical channels of different types. As mentioned above, each input port has four physical channels: Req Channel, Probe Channel, Rsp Channel and Data Channel.

[0072] Among them, Req Channel is mainly used to transmit data read / write commands, Rsp Channel is used to transmit read / write response information, Data Channel is used to transmit data, and Probe Channel is used to transmit consistency commands.

[0073] Commands, responses, data, etc. on the physical channel are transmitted in packet format.

[0074] The following is a discussion of common methods for reducing the power consumption of a routing network to illustrate that the routing network provided by the embodiment of the present invention can achieve accurate reduction of the power consumption of the routing network. For ease of explanation, the output port of each routing node is recorded as an Src port, and the input port is recorded as a Tgt port.

[0075] Since the channels for information exchange between each routing node are based on a handshake mechanism of tokens, when transmitting a packet, the Tgt port of the downstream routing node will release a token to the Src port of the upstream routing node. After the Src port of the upstream routing node receives the token from the downstream routing node, it will consider that the downstream routing node has enough buffer space to receive the packet.

[0076] by Figure 2 Taking the routing network structure shown in the figure as an example, the entire routing path for M1 to access S2 is set as: M1->routing node 1 1 -> Routing Node 1 4 -> Routing Node 1 3 -> Routing Node 1 8 ->S2.

[0077] Take a common scenario where the input information is an access request as an example. In this scenario, S2 fails to process the access request in time or the internal buffer space is full or other reasons prevent it from continuing to send the request to routing node 1. 8 Release token, resulting in routing node 1 8 If token is missing, then routing node 1 8 Unable to continue sending packets to S2, causing routing node 1 8 The data stream between S2 and S1 is terminated. 8 The token is sufficient, and the upstream path "M1->routing node 1 1 -> Routing Node 1 4 -> Routing Node 1 3 -> Routing Node 1 8 "At this time, the transmission and movement of high-frequency input information will continue until routing node 1 8 The buffer is full, causing routing node 1 8 Unable to route to its upstream node: routing node 1 3 Release the token, which makes routing node 1 3 and routing node 1 8 Terminate the flow of packets.

[0078] By analogy, this path congestion will continue to be transmitted to the upstream routing node and M1, and the packet flow will stop only when it is transmitted to the source end M1. Therefore, when a path congestion occurs at a certain routing node, the path load is serious, and the high-frequency data flow movement of its upstream routing node is meaningless and cannot bring performance improvement, but instead leads to a large amount of power consumption waste.

[0079] Based on this, in the embodiment of the present invention, by providing an implementation basis for reducing the current clock frequency of the upstream routing node, it is avoided that when the downstream routing node is congested and the path load is serious (CongestionRegion), the flow of meaningless high data flow of the upstream routing node causes the increase of the power consumption of the routing network. That is, the routing network provided by the embodiment of the present invention can alleviate the path congestion between routing nodes and reduce the path load; and then reduce the high-frequency data movement of the upstream routing node, so as to achieve the purpose of reducing the power consumption of the routing network.

[0080] To further demonstrate the working effect of the routing network provided by the embodiment of the present invention, please refer to Figure 3 , Figure 3 It is a schematic diagram of a working process of a routing network provided by an embodiment of the present invention.

[0081] Figure 3 The figure shows the interconnection structure of two 4*4 routing nodes: RUX and RUY.

[0082] like Figure 3 As shown, each port of each routing node (for information exchange with other routing nodes) has an input port Tgt and an output port Src.

[0083] The input port Tgt1 of RUX is connected to the output port Src3 of RUY, and the output port Src1 of RUX is connected to the input port Tgt3 of RUY.

[0084] In each routing node, each input port Tgti (i = 0, 1, 2, 3) has a buffer ( Figure 3 The input information received by the corresponding connected input port (such as command, response or data) is cached. The input information input from each input port 11 is routed to each output port Srci (i=0, 1, 2, 3) through the cache. For example, if the input port Tgt0 of RUY receives an input information, the input information is first stored in the cache of Tgt0 of RUY, then output from RUY-Src3 to RUX-Tgt1 through routing, and then stored in the cache of Tgt1 of RUX.

[0085] For ease of explanation, the buffer of Tgt0 of RUY is recorded as RUY-Tgt0-TQ, and the buffer of Tgt1 of RUX is recorded as RUX-Tgt1-TQ. It should be noted that since each input port 11 supports multiple types of physical channels, there are multiple buffers belonging to each input port 11.

[0086] Each RU works internally on the master clock RU_CLK, and the write operation clock of each buffer (the working clock when buffering input information) uses the clock accompanying the input information. For example, RUX works on RUX_CLK, RUY works on RUY_CLK, and the write operation clock of RUX-Tgt1-TQ uses RUY_CLK, which will be transmitted to RUX along with the input information.

[0087] Since the entire NoC is designed synchronously, that is, the same phase frequency division clock design technology is used, the main clock phase of each RU in the entire routing network is the same, and the frequency can only be a power of 2 of the highest operating frequency of the routing network (such as RUX_CLK and RUY_CLK are in the same phase relationship). This ensures that each RU can run independently at different clock frequencies and ensures the security of the transmission of input information between different RUs.

[0088] like Figure 3 As shown, by detecting the change in the number of cache entries in RUX-Tgt1-TQ, the cache state of the path can be evaluated, and a clock frequency management request can be issued to SRC3 of RUY according to the cache state evaluation result (such as Figure 3 The dashed arrow output from the input port Tgt1 of the RUX indicates the sending of the clock frequency management request). The clock frequency management request will be sent from the RUX-Tgt1 port and belongs to the Tgt port signal group (Group).

[0089] It should be noted that the clock frequency management request is generated and sent in units of the input ports of the routing node. The clock frequency management requests sent by each input port are independent of each other, but the execution of the clock frequency management request is in units of RU. Whether the RU maintains or switches the current clock frequency depends on the path load of the input ports of all downstream routing nodes that interact with the output port.

[0090] Therefore, in a routing node, on the one hand, clock frequency management requests that match the path load conditions are generated through each input port, so that the current clock frequency of the upstream routing node connected to it meets the preset clock frequency; on the other hand, the clock frequency management requests sent by the input ports of each downstream node are received through the output port, and the path load conditions of the input ports connected to each output port are comprehensively considered, and the corresponding clock frequency management requests are executed to achieve refined control of the power consumption of each routing node, thereby accurately reducing the power consumption of the routing network.

[0091] Based on the structure of the routing network provided above, the embodiment of the present invention further provides a clock frequency management method for routing nodes, which is used to accurately reduce the power consumption of the routing network.

[0092] Please refer to Figure 4 , Figure 4 The present invention provides a flow chart of a method for managing the clock frequency of a routing node according to an embodiment of the present invention. The method is applied to each routing node in a routing network.

[0093] like Figure 4 As shown, the method comprises the following steps:

[0094] Step S101, determining the input information buffer capacity of the input port of the routing node.

[0095] The input information buffer capacity can be obtained from the buffers correspondingly connected to each input port.

[0096] Step S102: determining the path load between the input port and the output port of the upstream routing node with which the input port interacts based on the input information buffer amount.

[0097] The input information buffer capacity can reflect the specific path load situation, so an accurate and appropriate preset clock frequency can be determined based on the input information buffer capacity, thereby generating a reliable clock frequency management request.

[0098] Step S103: sending a clock frequency management request matching the path load condition to an upstream routing node based on the path load condition.

[0099] The clock frequency management request sent makes the current clock frequency of the upstream routing node conform to the preset clock frequency.

[0100] The matching with the path load condition means that the clock frequency management request sent to the upstream routing node can realize the adjustment for the specific path load condition. For example, when the currently determined path load condition is path congestion, the generated clock frequency management request matching it can alleviate the path load condition of the path congestion. When the currently determined path load condition is path non-congestion, the generated clock frequency management request matching it can maintain the path load condition of the path non-congestion. Thus, in combination with the actual path load condition, a matching clock frequency management request is generated to produce a positive effect on the path load condition.

[0101] Therefore, the clock frequency management request sent based on the path load condition and matching it can enable the upstream routing node to maintain the current clock frequency or switch the current clock frequency.

[0102] The preset clock frequency is less than or equal to the current clock frequency.

[0103] Step S104: sending the clock frequency management request to the output port of the upstream routing node.

[0104] It can be seen that the technical solution provided by the embodiment of the present invention can determine the input information cache amount of the buffer connected to each input port of the routing node when the routing node acts as a downstream routing node in the routing network, so as to determine the path load between the output ports of the upstream routing node connected to the input port. Since the path load is proportional to the clock frequency and the power consumption of the routing network, that is, the greater the path load, the greater the power consumption of the routing network, and the higher the clock frequency; therefore, after determining the input information cache amount of the input port, the embodiment of the present invention can generate a matching clock frequency management request based on the path load determined by the input information cache amount, so that the path load corresponding to the input port for information interaction is directly proportional to the clock frequency and the power consumption of the routing network. The current clock frequency of the upstream routing node meets the preset clock frequency; since the preset clock frequency is less than or equal to the current clock frequency, based on the technical solution provided by the embodiment of the present invention, since the preset clock frequency is less than the current clock frequency, the generated clock frequency management request can achieve the effect of reducing the current clock frequency of the upstream routing node when the path load situation is that the path is blocked, thereby reducing the transmission of high-frequency information of the upstream routing node and reducing the power consumption of the routing node; at the same time, when the path load situation is that the path is not blocked, a clock frequency management request of the preset clock frequency equal to the current clock frequency can be sent to the upstream routing node, so that the current clock frequency of the upstream routing node can be maintained. It can be seen that this solution can comprehensively consider the path load situation of the downstream routing node to send a clock frequency management request that meets the path load situation (i.e., matches the path load situation) to the upstream routing node, so as to achieve refined control of the power consumption of each routing node, thereby accurately reducing the power consumption of the routing network.

[0105] In order to improve the accuracy of the cache status evaluation result, in one implementation, step S102 may include:

[0106] Obtaining a cache status evaluation result of an input port based on the input information cache amount;

[0107] Determine, using the cache status evaluation result, a path load condition between the input port and an output port of an upstream routing node with which information is exchanged, as indicated by the cache status evaluation result;

[0108] Step S103 may include:

[0109] Under different path load conditions indicated by the cache status evaluation result, determining a corresponding preset clock frequency, and generating a matching clock frequency management request based on the preset clock frequency;

[0110] The generated clock frequency management request is sent to the upstream routing node.

[0111] The input information cache capacity is the amount of input information cached in the cache, so the input information cache capacity can be used to obtain an evaluation result on the path load condition: the cache status evaluation result. Based on the different path load conditions indicated by the cache status evaluation result, the preset clock frequency applicable to each path load condition is determined, so that an accurate and appropriate preset clock frequency can be obtained based on full consideration of the current path load condition of the routing node.

[0112] Based on the above-mentioned embodiment of the routing network, it can be known that an input port of a routing node may include different types of physical channels, so the input information buffer amount can be determined based on the input information transmitted by each type of physical channel. In order to obtain an accurate input information buffer amount, in one embodiment, step S101 may include:

[0113] For each input port:

[0114] The number of cache entries of each type of input information received by the input port is obtained; and the input information cache capacity of the input port is determined based on the number of cache entries of each type of input information.

[0115] Based on the routing network provided by the aforementioned embodiment, it can be known that a routing node includes multiple input ports, and an input port includes multiple types of physical channels, so the input information also includes corresponding types of input information transmitted by different types of physical channels.

[0116] Therefore, when determining the input information cache capacity of an input port, the number of cache entries of various types of input information transmitted by all types of physical channels in an input port may be considered, thereby obtaining an accurate input information cache capacity.

[0117] Since different types of physical channels have different effects on the path load of the input port, in order to ensure the accuracy and rationality of the cache status evaluation result, in one embodiment, obtaining the cache status evaluation result of the input port based on the input information cache amount includes:

[0118] Determine the number of valid cache entries of the input port based on the number of cache entries of each type of input information; the number of valid cache entries is used to represent the comprehensive impact of different types of input information received by the input port on the path load;

[0119] A cache status evaluation result of the input port is determined based on the number of valid cache entries.

[0120] Based on the above content, it can be known that an input port of a routing node may include multiple types of physical channels, so that multiple types of input information can be transmitted, such as input information of data types and input information of command types. Therefore, in order to accurately determine the cache status evaluation result of each input port, the comprehensive impact of various types of input information received by the input port on the path load is considered, and the number of valid cache entries (EntryNum) of the input port is determined. Then, the cache status evaluation result of the input port is determined based on the number of valid cache entries, which can improve the reliability and rationality of the cache status evaluation result.

[0121] In order to comprehensively consider the impact of different types of input information on the path load and determine the accurate number of valid cache entries, in one embodiment, the number of cache entries based on each type of input information determines the number of valid cache entries of the input port, including:

[0122] Based on the path load impact weights corresponding to each type of input information and the number of cache entries corresponding to each type of input information, a weighted comprehensive evaluation is performed on the path load situation of the input port, and the result of the weighted comprehensive evaluation is determined as the number of valid cache entries of the input port.

[0123] Since each input port is composed of multiple physical channels of different types, when a certain input port of a routing node sends a clock frequency management request to the output port of an upstream routing node with which it interacts with information, the final determination of the preset clock frequency is jointly determined by the input information transmitted by multiple types of physical channels. Therefore, each input port of the routing node will monitor the buffer used to buffer the input information transmitted by different types of physical channels (the situation of the corresponding type of input information cached by it) in real time.

[0124] Therefore, when determining the comprehensive impact of various types of input information received by an input port on the path load, the number of cache entries corresponding to each type of input information can be determined first, that is, based on the cache status in the cache connected to each type of physical channel.

[0125] Different types of physical channels have different influences on the path load, so different types of input information cached in the buffer have different influences on the path load. Therefore, different path load influence weights are assigned to the corresponding types of input information cached in each buffer according to the influence of each physical channel.

[0126] Then, a weighted comprehensive evaluation is performed based on the number of cache entries corresponding to each type of input information, and the result of the weighted comprehensive evaluation is determined as the number of valid cache entries.

[0127] To facilitate understanding of the implementation of weighted comprehensive evaluation of different types of input information, the physical channels of an input port of a routing node described above include: request type physical channels, response type physical channels, data type physical channels, and consistency command type physical channels; and the number of cache entries corresponding to the input information transmitted by each type of physical channel is recorded as: Req_EntryNum, Rsp_EntryNum, Data_EntryNum, Probe_EntryNum. The number of valid cache entries is recorded as: Active_EntryNum.

[0128] The calculation formula for weighted comprehensive evaluation of the number of cache entries corresponding to each type of input information can be expressed as:

[0129] Active_EntryNum=K0*Req_EntryNum+K1*Rsp_EntryNum+K2*Data_Entry Num+K3*Probe_EntryNum+B.

[0130] Among them, K0-K3 are the path load impact weights (weight coefficients) of the number of cache entries corresponding to each type of input information, and B represents a bias parameter.

[0131] K0~K3 and B can be determined by C-Model (Cycle-Accurate Model). C-Model is a method used in the field of chip design, mainly used for functional verification and performance evaluation before chip manufacturing, thereby reducing design iterations and improving design efficiency.

[0132] In hardware implementation, software configuration channels can be reserved for parameters K0~K3 and B to facilitate parameter tuning based on post-silicon performance measured models.

[0133] After performing a weighted comprehensive evaluation on various types of input information using the above calculation formula, the number of reliable valid cache entries can be determined, providing a reliable implementation basis for the subsequent determination of cache status evaluation results.

[0134] After obtaining the number of valid cache entries, a cache status evaluation result may be determined. Therefore, in one embodiment, determining the cache status evaluation result of the input port based on the number of valid cache entries includes:

[0135] When determining that the number of valid cache entries indicates a first cache state, determining a cache state evaluation result of the input port is: a path load level at which the number of valid cache entries is located;

[0136] When the number of valid cache entries indicates a second cache state, it is determined that a cache state evaluation result of the input port is an idle state.

[0137] The number of valid cache entries can be divided into two cases based on the cache state they represent. In the first case, the number of valid cache entries represents a first cache state, and the first cache state may be that a certain amount of input information is stored in the cache, that is, the number of valid cache entries is a value greater than 0. At this time, the cache state in the cache that caches various types of input information is non-empty.

[0138] When the number of valid cache entries represents the first cache state, the number of valid cache entries can have multiple numerical values, such as 10, 20, etc., and different numerical values ​​of the number of valid cache entries correspond to different path load conditions. Therefore, based on the specific numerical value of the number of valid cache entries, the path load level can be determined, and the determined path load level can be used as the final cache state evaluation result of the input port.

[0139] The second case corresponds to a second cache state represented by the number of valid cache entries. The second cache state may be that there is no cache input information in the cache, that is, the number of valid cache entries is equal to 0. At this time, the cache status in the cache that caches various types of input information is empty.

[0140] When the number of valid cache entries indicates the second cache state, it can be determined that the cache state evaluation result of the input port at this time is an idle state, that is, there is no transmission, reception, or cache of interactive information at this time.

[0141] Based on the number of valid cache entries with different values, the cache status evaluation result of the input port can be accurately determined, so that the generation of the clock frequency management request of each input port can be accurately achieved.

[0142] To accurately determine the preset clock frequency, in one embodiment, determining the preset clock frequency under different path load conditions indicated by the path load condition indicated by the cache status evaluation result includes:

[0143] When determining that the cache state evaluation result of the input port is: the path load level at which the number of valid cache entries is located, determining the corresponding clock management gear for each path load level based on the path load levels at which different numbers of valid cache entries are located, and each clock management gear corresponds to a clock frequency management strategy; determining a preset clock frequency based on the clock frequency management strategy corresponding to the clock management gear; the clock frequency management strategy is used to indicate the management method of the clock frequency;

[0144] When it is determined that the cache state evaluation result of the input port is an idle state, a working scenario corresponding to the idle state is determined, and a preset clock frequency is determined according to a clock frequency management strategy corresponding to a clock management gear in the working scenario.

[0145] In the case where the number of valid entries represents the first cache state, the number of valid entries can have different numerical values, and the number of valid cache entries with different numerical values ​​can be in different channel load levels, thereby indicating the specific channel load situation of the input port at this time. Therefore, different clock management gears can be set for different channel load levels. Since each clock management gear has a clock frequency management strategy for indicating the management method of the clock frequency, the preset clock frequency applicable to each channel load level can be accurately obtained, so that after the current clock frequency of the upstream routing node meets the preset clock frequency, the channel load situation at the corresponding channel load level can be alleviated.

[0146] When the number of valid cache entries represents the second cache state (the number of valid cache entries is 0), it means that the cache state evaluation result of the input port is an idle state at this time, and the input port can be in an idle state in different working scenarios. Different working scenarios have different requirements for clock frequency. Therefore, based on the specific working scenario, the preset clock frequency can be determined by the clock frequency management strategy corresponding to the clock management gear in the working scenario, which can meet the demand for the preset clock frequency in the idle state.

[0147] When determining that the cache state evaluation result of the input port is: the path load level at which the number of valid cache entries is located, in order to accurately obtain the clock management gears under different path load levels to determine the appropriate preset clock frequency, therefore, in one embodiment, the path load level includes a first level, a second level, a third level and a fourth level at which the path load increases step by step, and the clock management gear includes a first clock management gear, a second clock management gear, a third clock management gear and a fourth clock management gear at which the clock frequency decreases step by step;

[0148] When determining that the cache state evaluation result of the input port is: the path load level at which the number of valid cache entries is located, determining the clock management gear corresponding to each path load level based on the path load levels at which different numbers of valid cache entries are located, includes:

[0149] If the path load level is the first level, determining the corresponding clock management gear is: the first clock management gear or the second clock management gear;

[0150] If the path load level is the second level, determining the corresponding clock management gear is: the second clock management gear or the third clock management gear;

[0151] If the path load level is the third level, determining the corresponding clock management gear is: the third clock management gear or the fourth clock management gear;

[0152] If the path load level is the fourth level, the corresponding clock management gear is determined to be: the first clock management gear or the second clock management gear.

[0153] When the path load level is the first level (Light Traffic Region) where the path load is relatively light (path congestion is relatively light), it means that the number of cached input information in the downstream routing node corresponding to the input port is relatively small, which means that the path between the input port and the output port of the upstream routing node with which it interacts with information is relatively idle, which means that the sender of the information does not have too many information sending requests. If the current clock frequency of the upstream routing node is increased or maintained at this time, it will only lead to a waste of power consumption. Therefore, for this type of situation, a clock management gear with a lower clock frequency can be selected: the first clock management gear (C0) or the second clock management gear (C1), which can not only meet the path load situation at this time, but also reduce the current clock frequency of the upstream routing node and reduce the frequency of the routing network.

[0154] When the path load level is the second level (Moderate Traffic Region) with medium path load, it means that the number of cached input information in the downstream routing node corresponding to the input port is slightly increased, which means that the path between the input port and the output port of the upstream routing node with which the information is interacting is between idle and busy, which means that although the sender of the information has a request to send information, the amount is not very large. If the current clock frequency of the upstream routing node is increased, it will only waste power consumption. Therefore, at this time, the clock frequency can be selected to first manage the lower clock gear: the second clock management gear (C1) or the third clock management gear (C2), which can not only meet the path load situation at this time, but also reduce the current clock frequency of the upstream routing node and reduce the frequency of the routing network.

[0155] When the path load level is the third level (Heavy Traffic Region) with a heavier path load, it means that the number of cached input information in the downstream routing node corresponding to the input port has increased, which means that the path between the input port and the output port of the upstream routing node with which it interacts with information is busy, which means that the sender of the information has sent a large number of information sending requests, but congestion has not yet occurred. However, if the frequency is reduced, it is impossible to transmit such a large amount of traffic. At this time, you can choose to maintain the current clock frequency or slightly reduce the current clock frequency. The clock management gear: the third clock management gear (C2) or the fourth clock management gear (C3) meets the path load situation at this time, and does not increase the current clock frequency of the upstream routing node, and does not increase the power consumption of the upstream routing node.

[0156] When the path load level is the fourth level (Congestion Traffic Region) where the path load is severely blocked, it means that the amount of input information cached in the downstream routing node corresponding to the input port is very large, which means that the path between the input port and the output port of the upstream routing node with which the information is interacting is blocked and cannot interact with the information smoothly. As explained above, if the current clock frequency of the upstream routing node is increased at this time, it will only bring meaningless data flow movement of the upstream routing node, resulting in a waste of power consumption. Therefore, at this time, a clock management gear with a low clock frequency can be selected: the first clock management gear (C0) or the second clock management gear (C1), so as to dredge the blocked path at this time, alleviate the path load situation, and reduce the current clock frequency of the upstream routing node, thereby reducing the frequency of the routing network.

[0157] For the purpose of illustrating the different path load levels corresponding to different numbers of valid entries, please refer to Figure 5 , Figure 5 It is a schematic diagram of the results of different path load levels provided by an embodiment of the present invention.

[0158] like Figure 5 As shown, in the embodiment of the present invention, the path load level is divided into 4 categories, and each path load level includes the number of valid cache entries within a certain value range. Therefore, after completing the weighted comprehensive evaluation of the number of cache entries corresponding to each type of input information, the value range of the valid cache entries is determined based on the specific value of the number of valid cache entries to determine the path load level.

[0159] After determining the clock management gears corresponding to different path load levels, the corresponding preset clock frequencies can be determined. Therefore, in one embodiment, the preset clock frequency is determined based on the clock frequency management strategy corresponding to the clock management gears, including:

[0160] If the determined clock management gear is: the first clock management gear or the second clock management gear, the preset clock frequency determined based on the clock frequency management strategy corresponding to the first clock management gear or the second clock management gear is: 8 divided by the current clock frequency or 4 divided by the current clock frequency;

[0161] If the determined clock management gear is: the second clock management gear or the third clock management gear, the preset clock frequency determined based on the clock frequency management strategy corresponding to the second clock management gear or the third clock management gear is: 4 divided by the current clock frequency or 2 divided by the current clock frequency;

[0162] If the determined clock management gear is: the third clock management gear or the fourth clock management gear, the preset clock frequency determined based on the clock frequency management strategy corresponding to the third clock management gear or the fourth clock management gear is: 2 of the current clock frequency or no frequency division of the current clock frequency;

[0163] If the determined clock management gear is: the first clock management gear or the second clock management gear, the preset clock frequency determined based on the clock frequency management strategy corresponding to the first clock management gear or the second clock management gear is: 8 divided by the current clock frequency or 4 divided by the current clock frequency.

[0164] The embodiment of the present invention adopts a power-of-2 frequency division method when determining whether to switch or maintain the current clock frequency, that is, the management method of the current clock frequency in the clock frequency management strategy. The power-of-2 frequency division method can meet the design of the routing network, can meet the alignment of the clock phase, and can change the speed of the current clock frequency.

[0165] When the clock management gear is: the first clock management gear (C0) or the second clock management gear (C1), since the purpose at this time is to significantly reduce the current clock frequency, the current clock frequency is mainly used, and a power-of-2 division method is adopted: 8 division corresponding to the C0 gear or 4 division corresponding to the C1 gear, to significantly reduce the current clock frequency.

[0166] When the clock management gear is the second clock management gear (C1) or the third clock management gear (C2), since the purpose at this time is to reduce the current clock frequency to a relatively low degree, the current clock frequency is mainly used, and the power-of-2 division method is adopted: 4 division corresponding to the C1 gear or 2 division corresponding to the C2 gear, to reduce the current clock frequency.

[0167] When the clock management gear is: the third clock management gear (C2) or the fourth clock management gear (C3), since the purpose at this time is to maintain the current clock frequency as much as possible, the current clock frequency is mainly used, and the power of 2 division method is adopted: 4 division corresponding to the C2 gear or 0 division corresponding to the C3 gear, that is, the current clock frequency is not divided, so as to maintain the current clock frequency of the upstream routing node as much as possible without increasing the current clock frequency.

[0168] When the clock management gear is the first clock management gear (C0) or the second clock management gear (C1), the purpose at this time is to reduce the current clock frequency to a large extent to alleviate the congestion of the channel. Therefore, the current clock frequency is mainly used, and the power-of-2 frequency division method is adopted: 8 division corresponding to the C0 gear or 4 division corresponding to the C1 gear, to reduce the current clock frequency and reduce the power consumption of the upstream routing node.

[0169] Of course, the above clock management gears and the frequency division methods of the clock frequency management strategy are all examples, and in other implementations, there may be other gear divisions and determination of frequency division methods in the clock frequency management strategy, as long as they can alleviate the path load and do not increase the power consumption of the upstream routing node.

[0170] In other implementations, when it is determined that the cache state evaluation result is an idle state, the clock management gear further includes a fifth clock management gear whose clock frequency is lower than the fourth clock management gear; when it is determined that the cache state evaluation result of the input port is an idle state, based on the working scene corresponding to the idle state, obtaining the clock management gear of the working scene includes:

[0171] If the working scenario corresponding to the idle state is no information interaction, the acquired clock management gear is the fifth clock management gear, and the clock frequency management strategy corresponding to the fifth clock management gear is used to determine the preset clock frequency as: the clock frequency of the first value;

[0172] If the working scenario corresponding to the idle state is information interaction, but in the interval period of information interaction, the clock management gear obtained is the first clock management gear, and the clock frequency management strategy corresponding to the first clock management gear is used to determine the preset clock frequency: 8 divided by the current clock frequency.

[0173] When the cache status evaluation result is idle, the following work scenarios may occur:

[0174] The first working scenario: There is no transmission of input information (packet) between the upstream routing node and the downstream routing node (the routing node where the input port is located);

[0175] The second working scenario: there is transmission of input information between the upstream routing node and the downstream routing node, but the information exchange interval of the input information is currently in progress.

[0176] For the first working scenario: it can include multiple types, such as upstream routing nodes (e.g. Figure 3 The functional module connected to the mounting node of the RUY routing node shown in the figure is an IO device. When the IO device is not enabled, the upstream routing node has no access to any slave, and the current clock frequency of the upstream routing node can be 0 (that is, the first value), that is, the fifth clock management gear can be configured to the C-OFF gear, that is, the current clock frequency of the upstream routing node is turned off.

[0177] For the second working scenario: the downstream routing node can send a clock frequency management request to the upstream routing node to reduce the current clock frequency, and can apply to reduce the current clock frequency of the upstream routing node to the C0 gear to reduce the power consumption (dynamic power consumption) of the upstream routing node.

[0178] Based on the structure of the routing network provided above, the embodiment of the present invention further provides a clock frequency management method for routing nodes, which is used to accurately reduce the power consumption of the routing network.

[0179] Please refer to Figure 6 , Figure 6 1 is another flow chart of a method for managing the clock frequency of a routing node provided by an embodiment of the present invention. The method is applied to each routing node in the routing network described in the above embodiment.

[0180] like Figure 6 As shown, the method comprises the following steps:

[0181] Step S201, obtaining clock frequency management requests received by each output port of the routing node.

[0182] Step S202: determining an executable target clock frequency management request based on the preset clock frequencies in each clock frequency management request.

[0183] Step S203: executing the target clock frequency management request so that the current clock frequency of the routing node complies with the preset clock frequency in the target clock frequency management request.

[0184] The preset clock frequency is less than or equal to the current clock frequency.

[0185] The clock frequency management request is a request sent by an input port of each downstream routing node for information interaction with each output port of the routing node.

[0186] Since each input port of the downstream routing node can generate and send a clock frequency management request, and each clock frequency management request includes a preset clock frequency that meets the path load of the corresponding input port. Therefore, after obtaining the clock frequency management requests received by each output port, the upstream routing node can comprehensively consider the path load of each input port of the downstream routing node and determine an executable target clock frequency management request so that the current clock frequency of the routing node meets the preset clock frequency, thereby satisfying the path load between each routing node in the overall routing network.

[0187] It can be seen that the technical solution provided by the embodiment of the present invention can determine the clock frequency management requests sent by each input port and received by each output port of the routing node when each routing node serves as an upstream routing node. Since the clock frequency management request of each input port is generated based on the path load indicated by the cache status evaluation result; and the cache status evaluation result can represent the path load between the input ports of the downstream routing node connected to the output port, since the path load is proportional to the clock frequency and the power consumption of the routing network, that is, the greater the path load, the greater the power consumption of the routing network, and the higher the clock frequency; therefore, the embodiment of the present invention can receive the clock frequency management requests issued by each input port in response to the path load determined based on the input information cache amount, so as to respond to each clock frequency management request. After the judgment is made, an executable target clock frequency management request is determined, so that the current clock frequency of the upstream routing node meets the preset clock frequency of the executable target clock frequency management request; since the preset clock frequency is less than or equal to the current clock frequency, based on the technical solution provided by the embodiment of the present invention, since the preset clock frequency is less than the current clock frequency, the generated clock frequency management request can achieve the effect of reducing the current clock frequency of the upstream routing node when the path load situation is that the path is blocked, thereby reducing the transmission of high-frequency information of the upstream routing node and reducing the power consumption of the routing node; at the same time, when the path load situation is that the path has not been blocked, a clock frequency management request with a preset clock frequency equal to the current clock frequency can be sent to the upstream routing node, so that the current clock frequency of the upstream routing node can be maintained. It can be seen that this scheme can comprehensively consider the path load conditions of the downstream routing node to send a clock frequency management request that meets the path load conditions (i.e., matches the path load conditions) to the upstream routing node. Then, the upstream routing node can further analyze the clock frequency management requests sent by each downstream routing node to determine an executable target clock frequency management request, so as to achieve refined control of the power consumption of each routing node, thereby accurately reducing the power consumption of the routing network.

[0188] In order to make the current clock frequency conform to the preset clock frequency, the step of determining an executable target clock frequency management request based on the preset clock frequencies in each clock frequency management request includes:

[0189] If the preset clock frequencies in the various clock frequency management requests are the same, determining any one of the various clock frequency management requests as an executable target clock frequency management request;

[0190] If the preset clock frequencies in the various clock frequency management requests are different, the clock frequency management request with the greatest degree of channel load impact is determined as the executable target clock frequency management request based on the degree of channel load impact corresponding to the input port sending each clock frequency management request.

[0191] Since each routing node may have multiple input ports and multiple output ports, when the routing node acts as an upstream routing node, its final clock frequency (the current clock frequency that meets the preset clock frequency) is determined by the clock frequency management requests received by each output port from the input ports of multiple downstream routing nodes.

[0192] For illustration purposes, please refer to Figure 7 , Figure 7 It is a schematic diagram of a process of executing a clock frequency management request provided by an embodiment of the present invention.

[0193] like Figure 7 As shown, routing node 10 is connected to the input ports of downstream routing nodes: routing node 11, routing node 12, routing node 13, and routing node 14 through four output ports. If the clock frequency management request (CLK_req*) received by the Src port connected to routing node 11, routing node 12, routing node 13, and routing node 14 has the same preset clock frequency, then routing node 10 will directly execute the clock frequency management request so that the current clock frequency meets the preset clock frequency.

[0194] If the preset clock frequencies of the clock frequency management request are different, the degree of influence of different input ports on the path load conditions of the routing node 10 can be considered, and an executable target clock frequency management request that can best meet the path load conditions of each path can be determined. The executable target clock frequency management request is executed, and the current clock frequency is adjusted according to the preset clock frequency in the executable target clock frequency management request to make it meet the preset clock frequency.

[0195] In one embodiment, determining the clock frequency management request with the greatest degree of influence of the path load as the executable target clock frequency management request according to the degree of influence of the path load corresponding to the input port sending each clock frequency management request includes:

[0196] Determine the path load impact weight corresponding to each input port according to the impact degree of the path load condition of the input port that sends each clock frequency management request;

[0197] The clock frequency management request with the greatest degree of channel load impact is determined by using the channel load impact weight, and is determined as an executable target clock frequency management request.

[0198] Since the input ports of different downstream routing nodes have different degrees of influence on the path load, the load impact weight of the path allocated to the input port can be referred to, and the final executable target clock frequency management request can be determined through the C-model.

[0199] An embodiment of the present invention provides an electronic device, such as a terminal device, a server device, or other computer device, including a memory and a processor, wherein the memory stores a program, and the processor calls the program stored in the memory to execute the clock frequency management method for a routing node as described in one of the aforementioned embodiments, or executes the clock frequency management method for a routing node as described in any of the aforementioned embodiments.

[0200] An embodiment of the present invention provides a storage medium storing a program, which, when executed, implements the clock frequency management method for a routing node as described in any of the foregoing embodiments, or implements the clock frequency management method for a routing node as described in any of the foregoing embodiments.

[0201] An embodiment of the present invention provides a computer program product, including a computer program, which, when executed by a processor, implements the clock frequency management method for a routing node as described in any of the aforementioned embodiments, or implements the clock frequency management method for a routing node as described in any of the aforementioned embodiments.

[0202] The above describes multiple implementation schemes provided by the embodiments of the present invention. The various optional methods introduced in each implementation scheme can be combined and cross-referenced with each other without conflict, thereby extending a variety of possible implementation schemes, which can all be considered as implementation schemes disclosed and open in the embodiments of the present invention.

[0203] Although the embodiments of the present invention are disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A routing network, characterized in that: include: at least one routing node; Each of the routing nodes comprises: at least one input port and a buffer connected to each input port, each buffer being used to buffer input information received by the correspondingly connected input port; Each routing node is used to: Determine the input information buffer capacity of the buffer corresponding to each input port of the routing node; determine the path load between the input port and the output port of the upstream routing node that interacts with the input port based on the input information buffer capacity; and send a clock frequency management request matching the path load condition to the upstream routing node based on the path load condition, so that the current clock frequency of the upstream routing node meets the preset clock frequency, wherein the preset clock frequency is less than or equal to the current clock frequency; and send the clock frequency management request from each input port to the output port of the corresponding upstream routing node.

2. The routing network according to claim 1, characterized in that The input port includes different types of physical channels, and each type of physical channel is connected to a corresponding buffer; the input information includes corresponding types of input information transmitted by each type of physical channel; the buffer connected to each type of physical channel is used to cache the corresponding types of input information transmitted by the physical channel.

3. The routing network according to claim 2, characterized in that: The various types of input information include: input information of command type transmitted by a physical channel of command type, input information of response type transmitted by a physical channel of response type, and input information of data type transmitted by a physical channel of data type, wherein the input information of command type includes input information of data read or write command type and input information of consistency command type.

4. The routing network according to claim 3, characterized in that: Each routing node also includes: at least one output port; Each routing node is also used to: Acquire clock frequency management requests received by each output port of the routing node; determine executable target clock frequency management requests based on preset clock frequencies in each clock frequency management request; and execute the target clock frequency management request so that the current clock frequency of the routing node meets the preset clock frequency in the target clock frequency management request; The clock frequency management request is a request sent by an input port of each downstream routing node for information interaction with each output port of the routing node.

5. A clock frequency management method for a routing node, characterized in that: Applied to each routing node in the routing network according to any one of claims 1 to 4, the method comprises: Determining the input information buffer capacity of the input port of the routing node; Determine the path load between the input port and the output port of the upstream routing node with which the input port interacts with information based on the input information buffer amount; Based on the path load condition, a clock frequency management request matching the path load condition is sent to the upstream routing node, so that the current clock frequency of the upstream routing node meets the preset clock frequency, wherein the preset clock frequency is less than or equal to the current clock frequency; The clock frequency management request is sent to an output port of a corresponding upstream routing node.

6. The clock frequency management method of a routing node according to claim 5, characterized in that: The determining, based on the input information buffer amount, of a path load between the input port and an output port of an upstream routing node with which information is exchanged comprises: Obtaining a cache status evaluation result of an input port based on the input information cache amount; Determine, using the cache status evaluation result, a path load condition between the input port and an output port of an upstream routing node with which information is exchanged, as indicated by the cache status evaluation result; The sending a clock frequency management request matching the path load condition to the upstream routing node based on the path load condition comprises: Under different path load conditions indicated by the cache status evaluation result, determining a corresponding preset clock frequency, and generating a matching clock frequency management request based on the preset clock frequency; The generated clock frequency management request is sent to the upstream routing node.

7. The clock frequency management method of a routing node according to claim 6, characterized in that: The determining of the input information buffer amount of the input port of the routing node comprises: For each input port: Obtaining the number of cache entries of each type of input information received by the input port; The input information cache capacity of the input port is determined based on the number of cache entries of each type of input information.

8. The clock frequency management method of a routing node according to claim 7, characterized in that: The step of obtaining a cache status evaluation result of an input port based on the input information cache amount includes: Determine the number of valid cache entries of the input port based on the number of cache entries of each type of input information; the number of valid cache entries is used to represent the comprehensive impact of different types of input information received by the input port on the path load; A cache status evaluation result of the input port is determined based on the number of valid cache entries.

9. The clock frequency management method of a routing node according to claim 8, characterized in that: The determining the number of valid cache entries of the input port based on the number of cache entries of each type of input information includes: Based on the path load impact weights corresponding to each type of input information and the number of cache entries corresponding to each type of input information, a weighted comprehensive evaluation is performed on the path load situation of the input port, and the result of the weighted comprehensive evaluation is determined as the number of valid cache entries of the input port.

10. The clock frequency management method of a routing node according to claim 9, characterized in that: The determining of the cache status evaluation result of the input port based on the number of valid cache entries includes: When determining that the number of valid cache entries indicates a first cache state, determining a cache state evaluation result of the input port is: a path load level at which the number of valid cache entries is located; When the number of valid cache entries indicates a second cache state, it is determined that a cache state evaluation result of the input port is an idle state.

11. The clock frequency management method of a routing node according to claim 10, characterized in that: The step of using the cache status evaluation result to determine the path load between the input port and the output port of the upstream routing node with which the input port interacts with the input port includes: When determining that the cache state evaluation result of the input port is: the path load level at which the number of valid cache entries is located, based on the path load levels at which different numbers of valid cache entries are located, determining the clock management gear corresponding to each path load level, each clock management gear corresponding to a clock frequency management strategy; determining the preset clock frequency based on the clock frequency management strategy corresponding to the clock management gear; the clock frequency management strategy is used to indicate the management method of the clock frequency; When it is determined that the cache state evaluation result of the input port is an idle state, a working scenario corresponding to the idle state is determined, and a preset clock frequency is determined according to a clock frequency management strategy corresponding to a clock management gear in the working scenario.

12. The clock frequency management method of a routing node according to claim 11, characterized in that: The channel load levels include a first level, a second level, a third level and a fourth level where the channel load increases step by step, and the clock management gears include a first clock management gear, a second clock management gear, a third clock management gear and a fourth clock management gear where the clock frequency decreases step by step; When the cache status evaluation result of the input port is determined as the path load level at which the number of valid cache entries is located, determining the clock management gear corresponding to each path load level based on the path load levels at which different numbers of valid cache entries are located, includes: If the path load level is the first level, determining the corresponding clock management gear is: the first clock management gear or the second clock management gear; If the path load level is the second level, determining the corresponding clock management gear is: the second clock management gear or the third clock management gear; If the path load level is the third level, determining the corresponding clock management gear is: the third clock management gear or the fourth clock management gear; If the path load level is the fourth level, the corresponding clock management gear is determined to be: the first clock management gear or the second clock management gear.

13. The clock frequency management method of a routing node according to claim 12, characterized in that: The determining the preset clock frequency based on the clock frequency management strategy corresponding to the clock management gear comprises: If the determined clock management gear is: the first clock management gear or the second clock management gear, the preset clock frequency determined based on the clock frequency management strategy corresponding to the first clock management gear or the second clock management gear is: 8 divided by the current clock frequency or 4 divided by the current clock frequency; If the determined clock management gear is: the second clock management gear or the third clock management gear, the preset clock frequency determined based on the clock frequency management strategy corresponding to the second clock management gear or the third clock management gear is: 4 divided by the current clock frequency or 2 divided by the current clock frequency; If the determined clock management gear is: the third clock management gear or the fourth clock management gear, the preset clock frequency determined based on the clock frequency management strategy corresponding to the third clock management gear or the fourth clock management gear is: 2 of the current clock frequency or no frequency division of the current clock frequency; If the determined clock management gear is: the first clock management gear or the second clock management gear, the preset clock frequency determined based on the clock frequency management strategy corresponding to the first clock management gear or the second clock management gear is: 8 divided by the current clock frequency or 4 divided by the current clock frequency.

14. The clock frequency management method of a routing node according to claim 12, characterized in that: The clock management gear further includes a fifth clock management gear whose clock frequency is lower than that of the fourth clock management gear; when the cache state evaluation result of the input port is determined to be an idle state, determining a working scenario corresponding to the idle state, and determining a preset clock frequency according to a clock frequency management strategy corresponding to the clock management gear under the working scenario, including: If the working scenario corresponding to the idle state is no information interaction, the acquired clock management gear is the fifth clock management gear, and the clock frequency management strategy corresponding to the fifth clock management gear is used to determine the preset clock frequency as: the clock frequency of the first value; If the working scenario corresponding to the idle state is information interaction, but in the interval period of information interaction, the clock management gear obtained is the first clock management gear, and the clock frequency management strategy corresponding to the first clock management gear is used to determine the preset clock frequency: 8 divided by the current clock frequency.

15. A method for managing clock frequency of a routing node, characterized in that: Applied to each routing node in the routing network according to any one of claims 1 to 4, the method comprises: Acquire clock frequency management requests received by each output port of the routing node; Determining an executable target clock frequency management request based on the preset clock frequencies in each clock frequency management request; Executing the target clock frequency management request so that the current clock frequency of the routing node meets the preset clock frequency in the target clock frequency management request; the preset clock frequency is less than or equal to the current clock frequency; The clock frequency management request is a request sent by an input port of each downstream routing node for information interaction with each output port of the routing node.

16. The clock frequency management method of a routing node according to claim 15, characterized in that: The routing node where the output port is located determines an executable target clock frequency management request based on the preset clock frequency in each clock frequency management request, including: If the preset clock frequencies in the various clock frequency management requests are the same, determining any one of the various clock frequency management requests as an executable target clock frequency management request; If the preset clock frequencies in the various clock frequency management requests are different, the clock frequency management request with the greatest degree of channel load impact is determined as the executable target clock frequency management request based on the degree of channel load impact corresponding to the input port sending each clock frequency management request.

17. The clock frequency management method of a routing node according to claim 16, characterized in that: When it is determined that the preset clock frequencies in the various clock frequency management requests are different, determining the clock frequency management request with the greatest degree of influence of the path load as the executable target clock frequency management request according to the degree of influence of the path load corresponding to the input port sending each clock frequency management request, includes: Determine the path load impact weight corresponding to each input port according to the impact degree of the path load condition of the input port that sends each clock frequency management request; The clock frequency management request with the greatest degree of channel load impact is determined by using the channel load impact weight, and is determined as an executable target clock frequency management request.

18. An electronic device, characterized in that: It includes a memory and a processor, the memory stores a program, and the processor calls the program stored in the memory to execute the clock frequency management method of the routing node as described in any one of claims 5-14, or executes the clock frequency management method of the routing node as described in any one of claims 15-17.

19. A storage medium, characterized in that: The storage medium stores a program, and when the program is executed, it implements the clock frequency management method of the routing node as described in any one of claims 5-14, or implements the clock frequency management method of the routing node as described in any one of claims 15-17.

20. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the clock frequency management method for a routing node as described in any one of claims 5-14 is implemented, or the clock frequency management method for a routing node as described in any one of claims 15-17 is implemented.

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