Radiation-proof memory logic circuit

Abstract

The invention provides an anti-radiation memory logic circuit, and relates to the field of integrated circuits. The circuit comprises a magnetic tunnel junction / CMOS hybrid logic network, an anti-SEU reading circuit and an anti-SET pulse filter circuit. The magnetic tunnel junction / CMOS hybrid logic network is connected with the anti-SEU reading circuit, and the input end of the filter circuit is connected to the output end of the anti-SEU reading circuit. The magnetic tunnel junction / CMOS hybrid logic network has a reconfigurable function and can realize various Boolean logics (AND logics, OR logics and XOR logics). When radiation particles irradiate a sensitive node of the read circuit, the anti-SEU read circuit is used to correct logic errors caused by SEU. And the filter circuit is used for filtering SET pulses left when the previous-stage reading circuit corrects the SEU. According to the invention, the single event upset resistance of the in-memory logic circuit is effectively improved, and the soft error rate of the circuit is reduced. Meanwhile, compared with a traditional multimode redundancy reinforcing mode, the area overhead and power consumption of the circuit can be effectively reduced.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and in particular to a radiation-resistant in-memory logic circuit. Background Art

[0002] As the basic storage unit of magnetic memory, magnetic tunnel junction is considered to be one of the most promising new memory devices and has been widely studied in recent years. Magnetic tunnel junction has the advantages of high speed, non-volatility, long life, low power consumption, and compatibility with CMOS technology. At the same time, it has good anti-interference, especially good tolerance to radiation environment, so it is widely used in high-radiation application scenarios such as aerospace and military. The in-memory logic circuit based on magnetic tunnel junction has the advantages of high integration, low power consumption and non-volatility. It combines storage and computing functions into magnetic tunnel junction, reduces the data transmission distance, and improves computing efficiency. However, the in-memory logic circuit inherits the characteristics of both memory and logic circuit, and is more sensitive to single-particle events (SEU and SET). In addition, in the in-memory logic circuit based on magnetic tunnel junction, the read circuit generally adopts a latch structure, and the sensitive nodes in the latch structure are vulnerable to high-energy particles, resulting in circuit errors. This error will continue until the state is reset or the next logical operation.

[0003] Single event effect is a major form of high-energy particle attack. It mainly includes single event upset (SEU) effect and single event transient (SET) effect. SEU effect refers to the ionization effect that may occur in semiconductor materials when high-energy particles pass through sensitive nodes of the circuit. High-energy particles collide with atoms in the semiconductor, resulting in the generation of free electrons and holes. When these free charges (electrons and holes) gather at sensitive nodes of the circuit, they may cause the voltage of the node to temporarily deviate from the normal working state. For example, the voltage of a certain storage unit is changed instantly, causing the stored bit value to flip and remain until the next write operation. SET effect refers to a short current pulse or voltage transient caused by high-energy particles passing through semiconductor devices. SET pulses usually disappear in a very short time, but during this time, they may affect the logic circuit. SET pulses may propagate in the circuit and pass through multiple logic gates or nodes. If these pulses are not attenuated or filtered out during the propagation process, they may affect other nodes downstream in the circuit, thereby expanding the scope of the error. At the same time, when the SET pulse propagates to the input of the timing circuit and is sampled at the rising edge of the clock signal, the erroneous signal may be latched, causing erroneous behavior of the entire circuit. In this case, a short pulse may cause a persistent error state. Therefore, radiation-resistant technology is essential to ensure the stable operation of critical systems and avoid functional failures or data errors. It can effectively resist the SEU effect and SET effect caused by high-energy particle radiation, thereby improving the reliability of the system in high-radiation environments such as aerospace, military, and nuclear energy.

[0004] In order to improve the ability of logic circuits to resist radiation, redundant logic structures are mainly used in the prior art, such as triple module redundancy (TMR). That is, multiple modules with the same function are set in the key circuit part. When radiation causes an error in one of the modules, the correct output is determined by majority voting, thereby improving the reliability of the circuit. However, redundant logic structures have the disadvantages of large area overhead, high power consumption, and high cost. Summary of the invention

[0005] Purpose of the invention: To propose an in-memory logic circuit that is resistant to radiation. When a sensitive node of a reading circuit is attacked, an anti-SEU reading circuit and a SET pulse filtering circuit work together to detect and correct errors that may occur in the circuit, thereby ensuring that the logical function of the in-memory logic circuit is accurate and improving the reliability of the circuit, thereby effectively solving the above-mentioned problems raised by the prior art.

[0006] In order to achieve the above technical objectives, the technical solutions adopted by the present invention are as follows: A radiation-resistant in-memory logic circuit structure comprises three modules: a magnetic tunnel junction / CMOS hybrid logic network, an anti-SEU reading circuit, and an anti-SET pulse filtering circuit.

[0007] The connection mode of the three modules in the circuit is: the magnetic tunnel junction / CMOS hybrid logic network is connected to the anti-SEU reading circuit, and the anti-SEU reading circuit is connected to the anti-SET pulse filtering circuit. The output signal of the anti-SEU reading circuit will be input into the anti-SET pulse filtering circuit.

[0008] When the sensitive nodes of the circuit are hit by high-energy particles and produce the SEU effect, causing the output signal to flip, the anti-SEU reading circuit reinforces the reading circuit by setting redundant storage nodes S1 and S2. It can detect errors and correct the output signal. However, when the anti-SEU reading circuit corrects the output signal, it is easy to leave SET pulses on the output waveform. Therefore, an anti-SET pulse filter circuit is used to detect and filter the SET pulse. Avoid the propagation of SET pulses in the logic circuit, ensuring that the logic circuit is not interfered by radiation and operates normally.

[0009] In a further embodiment, the above-mentioned magnetic tunnel junction / CMOS hybrid logic network includes: an NMOS transistor N7, whose drain is connected to the source of N3, whose source is connected to the upper end of the magnetic tunnel junction M1, and whose gate is connected to the input signal C1; an NMOS transistor N8, whose drain is connected to the source of N4, whose source is connected to the upper end of the magnetic tunnel junction M1, and whose gate is connected to the input signal C2; an NMOS transistor N9, whose drain is connected to the source of N3, whose source is connected to the upper end of the magnetic tunnel junction M2, and whose gate is connected to the input signal C2; an NMOS transistor N10, whose source is connected to the source of N4, whose source is connected to the upper end of the magnetic tunnel junction M2, and whose gate is connected to the input signal C3; a magnetic tunnel junction M1, whose upper end is connected to the sources of N7 and N8, and whose lower end is connected to the drain of N11; a magnetic tunnel junction M2, whose upper end is connected to the sources of N9 and N10, and whose lower end is connected to the drain of N11.

[0010] In a further embodiment, the above-mentioned SEU-resistant reading circuit includes: a PMOS transistor P1, whose source is connected to VDD, whose drain is connected to the drain of N3 and sets the node QB, and whose gate is connected to the clock signal CLK; a PMOS transistor P2, whose source is connected to VDD, whose drain is connected to the drain of N4 and sets the node Q, and whose gate is connected to the clock signal CLK; a PMOS transistor P3, whose source is connected to VDD, whose drain is connected to the drain of N1, and whose gate is connected to the node Q; a PMOS transistor P4 , its source is connected to VDD, its drain is connected to the drain of N2, and its gate is connected to the node QB; PMOS transistor P5, its source is connected to VDD, its drain is connected to the source of P7, and its gate is connected to the node Q; PMOS transistor P6, its source is connected to VDD, its drain is connected to the source of P8, and its gate is connected to the node QB; PMOS transistor P7, its source is connected to the drain of P5, its drain is connected to the drain of N5 and a redundant node S1 is set, and its gate is connected to the drain of P8; PMOS transistor P8 , its source is connected to the drain of P6, its drain is connected to the drain of N6 and a redundant node S2 is set, and its gate is connected to the drain of P7; NMOS transistor N1, its drain is connected to the drain of P3, its source is connected to the drain of N3, and its gate is connected to node S1; NMOS transistor N2, its drain is connected to the drain of P4, its source is connected to the drain of N4, and its gate is connected to node S2; NMOS transistor N3, its drain is connected to the source of N1, its source is connected to the drains of N7 and N9, and its gate is connected to node Q ; NMOS transistor N4, whose drain is connected to the source of N2, whose source is connected to the drains of N8 and N10, and whose gate is connected to the node QB; NMOS transistor N5, whose drain is connected to the redundant node S1, whose source is grounded, and whose gate is connected to the node Q; NMOS transistor N6, whose drain is connected to the redundant node S2, whose source is grounded, and whose gate is connected to the node QB; NMOS transistor N11, whose drain is connected to the lower ends of the magnetic tunnel junctions M1 and M2, whose source is grounded, and whose gate is connected to the clock signal CLK.

[0011] In a further embodiment, the above-mentioned anti-SET pulse filter circuit includes: a delay unit, whose input end is connected to the node Q, and whose output end is connected to the gates of P10 and N13 and designed to the node D; a PMOS transistor P9, whose source is connected to VDD, whose drain is connected to the source of P10, and whose gate is connected to the node Q; a PMOS transistor P10, whose source is connected to the drain of P9, whose drain is connected to the drain of N12, and whose gate is connected to the node D; an NMOS transistor N12, whose drain is connected to the drain of P10, whose source is connected to the drain of N13, and whose gate is connected to the node Q; an NMOS transistor N13, whose drain is connected to the source of N12, whose source is grounded, and whose gate is connected to the node D.

[0012] In a further embodiment, the above magnetic tunnel junction / CMOS hybrid logic network has a reconfigurable logic computing function: (1) When the circuit performs AND logic calculations: C1 = '1', C2 = '0', C3 = A, The OUT node outputs the logical result "AB"; (2) When the circuit performs or logical calculation: C1= / A, C2='0', C3 = '1', The OUT node outputs the logical result "A + B"; (3) When the circuit performs an XOR logic calculation: C1 = / A, C2 = A, C3 = / A, The OUT node outputs the logical result "A ⊕ B".

[0013] In addition, the above-mentioned SEU-resistant reading circuit has the ability to read data. When the resistance of the left branch in the logic network is small, the logic values ​​of the storage nodes Q and S2 are '1', and the logic values ​​of the storage nodes QB and S1 are '0'; when the resistance of the right branch in the logic network is small, the logic values ​​of the storage nodes QB and S1 are '1', and the logic values ​​of the storage nodes Q and S2 are '0'.

[0014] In addition, the above-mentioned anti-SEU reading circuit has the ability to resist SEU. The four storage nodes Q, QB, S1, and S2 are mutually constrained. When one of the nodes is attacked by SEU and the logical state changes, the other nodes can remain stable and correct the logical state of the attacked node through the mutual constraint relationship between the nodes.

[0015] In addition, the above-mentioned anti-SET pulse filter circuit has the ability to filter out SET pulses. By using the delay unit, the SET pulse undergoes a certain delay before reaching the sensitive circuit. Then, the C unit (composed of transistors P9, P10, N12, and N13) is used to filter out the SET pulse and enhance the reliability of the system.

[0016] Compared with the prior art, the present invention has the following beneficial effects: The present invention proposes a radiation-resistant in-memory logic circuit. When a sensitive node of the circuit is attacked, the anti-SEU reading circuit and the SET pulse filtering circuit work together to detect and correct errors that may occur in the circuit, thereby ensuring the accuracy of the circuit's logic function. Compared with existing technical solutions, the present invention can effectively reduce area overhead and power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 Schematic diagram of the logic circuit in the radiation-resistant memory.

[0018] Figure 2 This is a functional diagram of the SEU-resistant reading circuit.

[0019] Figure 3 This is a functional diagram of the anti-SET pulse circuit. DETAILED DESCRIPTION

[0020] In the following description, a large number of specific details are provided to provide a more thorough understanding of the present invention. However, it is apparent to those skilled in the art that the present invention can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present invention, some technical features known in the art are not described.

[0021] See also Figure 1 The present invention provides a radiation-resistant memory logic circuit structure, including three modules: a magnetic tunnel junction / CMOS hybrid logic network, an anti-SEU reading circuit, and an anti-SET pulse filtering circuit. The magnetic tunnel junction / CMOS hybrid logic network includes transistors N7~N10 and magnetic tunnel junctions M1~M2; the anti-SEU reading circuit includes transistors P1~P8, N1~N6, and N11; and the anti-SET pulse filtering circuit includes a delay unit, transistors P9~P10, and N12~N13.

[0022] The connection relationship of each device is as follows: The source of P1 is connected to VDD, the drain of P1 is connected to the source of N1, the drain of N3, the gate of P4, the gate of N4, the gate of P6, and the gate of N6, and the gate of P1 is connected to the clock signal CLK; The source of P2 is connected to VDD, the drain of P2 is connected to the source of N2, the drain of N4, the gate of P3, the gate of N3, the gate of P5, the gate of N5, the input end of the delay unit, the gate of P9, and the gate of N12, and the gate of P2 is connected to the clock signal CLK; The source of P3 is connected to VDD, the drain of P3 is connected to the drain of N1, and the gate of P3 is connected to the gate of N3, the gate of P5, the gate of N5, the source of N2, the drain of N4, the drain of P2, the input of the delay unit, the gate of P9, and the gate of N12; The source of P4 is connected to VDD, the drain of P4 is connected to the drain of N2, and the gate of P4 is connected to the gate of N4, the gate of P6, the gate of N6, the source of N1, the drain of N3, and the drain of P1; The source of P5 is connected to VDD, the drain of P5 is connected to the source of P7, and the gate of P5 is connected to the gate of N3, the gate of P5, the gate of N5, the source of N2, the drain of N4, the drain of P2, the input of the delay unit, the gate of P9, and the gate of N12; The source of P6 is connected to VDD, the drain of P6 is connected to the source of P8, and the gate of P6 is connected to the gate of N6, the gate of P4, the gate of N4, the source of N1, the drain of N3, and the drain of P1; The source of P7 is connected to the drain of P5, the drain of P7 is connected to the drain of N5, the gate of P8, and the gate of N1, and the gate of P7 is connected to the drain of P8, the drain of N6, and the gate of N2; The source of P8 is connected to the drain of P6, the drain of P8 is connected to the drain of N6, the gate of P7, and the gate of N2, and the gate of P8 is connected to the drain of P7, the drain of N5, and the gate of N1; The source of P9 is connected to VDD, the drain of P9 is connected to the source of P10, the drain of P9 is connected to the source of P10, and the gate of P9 is connected to the gate of P3, the gate of N3, the gate of P5, the gate of N5, the source of N2, the drain of N4, the drain of P2, the input terminal of the delay unit, and the gate of N12; The source of P10 is connected to the drain of P9, the drain of P10 is connected to the drain of N12, and the gate of P10 is connected to the output end of the delay unit and the gate of N13; The source of N1 is connected to the drain of P1, the drain of N3, the gate of P4, the gate of N4, the gate of P6, and the gate of N6. The drain of N1 is connected to the drain of P3. The gate of N1 is connected to the drain of P7, the drain of N5, and the gate of P8. The source of N2 is connected to the gate of P3, the gate of N3, the gate of P5, the gate of N5, the drain of N4, the drain of P2, the input terminal of the delay unit, the gate of P9, and the gate of N12. The drain of N2 is connected to the drain of P4. The gate of N2 is connected to the drain of P8, the drain of N6, and the gate of P7. The source of N3 is connected to the drain of N7 and the drain of N9, the drain of N3 is connected to the source of N1, the drain of P1, the gate of P4, the gate of N4, the gate of P6, and the gate of N6, and the gate of N3 is connected to the source of N2, the gate of P3, the gate of P5, the gate of N5, the drain of N4, the drain of P2, the input terminal of the delay unit, the gate of P9, and the gate of N12; The source of N4 is connected to the drain of N8 and the drain of N10, the drain of N4 is connected to the gate of N3, the source of N2, the gate of P3, the gate of P5, the gate of N5, the drain of P2, the input terminal of the delay unit, the gate of P9, and the gate of N12, and the gate of N4 is connected to the drain of N3, the source of N1, the drain of P1, the gate of P4, the gate of P6, and the gate of N6; The source of N5 is grounded, the drain of N5 is connected to the gate of N1, the drain of P7, and the gate of P8, and the gate of N5 is connected to the source of N2, the gate of P3, the gate of N3, the gate of P5, the drain of N4, the drain of P2, the input terminal of the delay unit, the gate of P9, and the gate of N12; The source of N6 is grounded, the drain of N6 is connected to the gate of N2, the drain of P8, and the gate of P7, and the gate of N6 is connected to the source of N1, the drain of P1, the drain of N3, the gate of P4, the gate of N4, and the gate of P6; The source of N7 is connected to the source of N8 and the upper end of M1, the drain of N7 is connected to the source of N3 and the drain of N9, and the gate of N7 is connected to the input signal C1; The source of N8 is connected to the source of N7 and the upper end of M1, the drain of N8 is connected to the source of N4 and the drain of N10, and the gate of N8 is connected to the input signal C2; The source of N9 is connected to the source of N10 and the upper end of M2, the drain of N9 is connected to the source of N3 and the drain of N7, and the gate of N9 is connected to the input signal C2; The source of N10 is connected to the source of N9 and the upper end of M2, the drain of N10 is connected to the source of N4 and the drain of N8, and the gate of N9 is connected to the input signal C3; The source of N11 is grounded, the drain of N11 is connected to the lower ends of M1 and M2, and the gate of N11 is connected to the clock signal CLK; The source of N12 is connected to the drain of N13, the drain of N12 is connected to the drain of P10, and the gate of N12 is connected to the drain of P2, the drain of N4, the gate of P3, the gate of N3, the gate of P5, the gate of N5, the input terminal of the delay unit, and the gate of P9; The source of N13 is grounded, the drain of N13 is connected to the source of N12, and the gate of N13 is connected to the gate of P10 and the output of the delay unit; The input end of the delay unit is connected to the drain of P2, the drain of N4, the gate of P3, the gate of N3, the gate of P5, the gate of N5, the gate of P9, and the gate of N12, and the output end of the delay unit is connected to the gate of P10 and the gate of N13.

[0023] It should be noted that there is some duplication in the above connection relationships, but it is retained for ease of understanding.

[0024] Among them, the hybrid magnetic tunnel junction / CMOS hybrid logic network has a reconfigurable function and can perform a variety of Boolean logic operations, as follows: (1) When the circuit performs AND logic calculations: C1 = '1', C2 = '0', C3 = A, The OUT node outputs the logical result "AB"; (2) When the circuit performs or logical calculation: C1= / A,C2='0',C3 = '1', The OUT node outputs the logical result "A + B"; (3) When the circuit performs an XOR logic calculation: C1 = / A, C2 = A, C3 = / A, The OUT node outputs the logical result "A ⊕ B".

[0025] For the SEU-resistant reading circuit, the four storage nodes Q, QB, S1, and S2 have a mutual constraint relationship. When one of the nodes is attacked by SEU and the logical state changes, the other nodes can remain stable and correct the logical state of the attacked node through the relevant constraint relationship between the nodes.

[0026] See also Figure 2 , when the resistance of the left branch in the magnetic tunnel junction / CMOS hybrid logic network is less than the resistance of the right branch, the value of node Q, S2 is '1', and the value of node QB, S1 is '0'. It is known that the reverse biased drain junction of the MOS tube in the cut-off state is a sensitive node of the circuit. In addition, SEU at the drain of PMOS will cause a positive transient pulse (the node logic state may be '0'→'1' or '1'→'1'), while in the case of NMOS, it will cause a negative transient pulse (the node logic state may be '0'→'0' or '1'→'0'). Since the data stored in node QB in this case is '0', its only possible transient state is '0'→'0', and QB will not change the state of the node. Therefore, QB is insensitive. For the assumed case, the three nodes Q, S1 and S2 are sensitive nodes.

[0027] The SEU-resistant read circuit works as follows: The Q node is attacked by SEU: When the node Q flips from '1' to '0', it causes P3 and P5 to turn on, and turns off N3 and N5. At this time, node S2 is not affected, keeping transistor N1 turned on and transistor P7 turned off. Since nodes QB and S1 are not connected to VDD or GND, they enter a high impedance state. The capacitor nodes in a high impedance state will maintain their previous logic values, and nodes QB and S1 will maintain the original logic '0'. According to the above analysis, S1, S2 and QB are all in a stable state. Node S2 will keep N2 turned on, node QB will keep P4 turned on and N4 turned off, and the affected node Q can restore the original logic value '1'.

[0028] The S1 node is attacked by SEU: When the node S1 flips from '0' to '1', P8 is turned off and N1 is turned on. At this time, S1, Q, and QB are all in a high impedance state and maintain their initial logic values. Node S2 will keep P7 off, node Q will keep P5 off and N5 on, and the affected node S1 can restore the original logic value '0'.

[0029] The S2 node is attacked by SEU: When the node S2 flips from '1' to '0', P7 is turned on and N2 is turned off. At this time, S1, Q, and QB are all in a high impedance state and maintain their initial logic values. Node S1 will keep P8 turned on, node QB will keep P6 turned on and N6 turned off, and the affected node S2 can restore the original logic value '1'.

[0030] It should be noted that in another case, when the resistance of the left branch in the magnetic tunnel junction / CMOS hybrid logic network is greater than the resistance of the right branch, the value of the node Q, S2 is '0', and the value of the node QB, S1 is '1'. At this time, the three nodes QB, S1, and S2 are sensitive nodes, and their anti-radiation reinforcement principle is the same as described above.

[0031] In addition, when the charge of the incident particles of SEU is large, although the anti-SEU reading circuit can restore the logic value of the attacked node, the attacked node will also form a SET pulse. The SET pulse will have an adverse effect on the logic circuit. Therefore, we use an anti-SET pulse filter circuit to filter the SET pulse.

[0032] The anti-SET pulse filter circuit includes a delay unit and a C unit (composed of P9, P10, N12, and N13). The logical function of the C unit is as follows: when its two inputs D and Q are the same, the C unit acts as an inverter. When its inputs D and Q are different, the output node OUT presents a high impedance state, and the output voltage will maintain its value until the leakage current decreases.

[0033] See also Figure 3 When the output node Q of the anti-SEU reading circuit is affected by the SET pulse, a short SET pulse appears on its output waveform. After the node Q is input to the delay unit, a short SET pulse will also appear in the output waveform of the delay unit, but there is a time interval of △T between the two SET pulses (△T is the hysteresis time of the delay unit). During the period from the falling edge of the SET pulse at point Q to the rising edge of the SET pulse at point D, the output node of the C unit is in a high-impedance state, and the output remains unchanged during this period, thereby filtering out the SET pulse and reducing its impact on the circuit.

[0034] Although the steps in the present invention are arranged with numbers, they are not used to limit the order of the steps. Unless the order of the steps is clearly stated or the execution of a certain step requires other steps as a basis, the relative order of the steps can be adjusted. It is understood that the term "and / or" used in this article involves and covers any and all possible combinations of one or more of the associated listed items.

[0035] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A radiation-resistant in-memory logic circuit, characterized in that: Including magnetic tunnel junction / CMOS hybrid logic network, anti-SEU reading circuit, and anti-SET pulse filtering circuit; The magnetic tunnel junction / CMOS hybrid logic network is electrically connected to the SEU-resistant reading circuit; The anti-SEU reading circuit is electrically connected to the anti-SET pulse filtering circuit, the output signal of the anti-SEU reading circuit is input into the anti-SET pulse filtering circuit, and the anti-SET pulse filtering circuit outputs a circuit logic result; When the sensitive nodes of the reading circuit are hit by high-energy particles and produce the SEU effect, causing the output signal to flip, the anti-SEU reading circuit detects the current error signal and corrects the output signal, while leaving the SET pulse; the anti-SET pulse filtering circuit is used to detect and filter the SET pulse.

2. The radiation-resistant in-memory logic circuit according to claim 1, characterized in that: The magnetic tunnel junction / CMOS hybrid logic network specifically includes: NMOS transistor N7, whose drain is connected to the source of NMOS transistor N3, whose source is connected to the upper end of magnetic tunnel junction M1, and whose gate is connected to signal C1; NMOS transistor N8, whose drain is connected to the source of NMOS transistor N4, whose source is connected to the upper end of magnetic tunnel junction M1, and whose gate is connected to signal C2; NMOS transistor N9, whose drain is connected to the source of NMOS transistor N3, whose source is connected to the upper end of magnetic tunnel junction M2, and whose gate is connected to signal C2; NMOS transistor N10, whose drain is connected to the source of NMOS transistor N4, whose source is connected to the upper end of magnetic tunnel junction M2, and whose gate is connected to signal C3; A magnetic tunnel junction M1, an upper end of which is connected to the source of the NMOS transistor N7 and the NMOS transistor N8, and a lower end of which is connected to the drain of the NMOS transistor N11; The magnetic tunnel junction M2 has an upper end connected to the sources of the NMOS transistors N9 and N10 , and a lower end connected to the drain of the NMOS transistor N11 .

3. The radiation-resistant in-memory logic circuit according to claim 1, characterized in that: The anti-SEU reading circuit specifically includes: A PMOS transistor P1, whose source is connected to the power supply voltage VDD, whose drain is connected to the drain of the NMOS transistor N3 and sets a node QB, and whose gate is connected to the clock signal CLK; A PMOS transistor P2, whose source is connected to the power supply voltage VDD, whose drain is connected to the drain of the NMOS transistor N4 and sets a node Q, and whose gate is connected to the clock signal CLK; A PMOS transistor P3, whose source is connected to the supply voltage VDD, whose drain is connected to the drain of the NMOS transistor N1, and whose gate is connected to the node Q; A PMOS transistor P4, whose source is connected to the supply voltage VDD, whose drain is connected to the drain of the NMOS transistor N2, and whose gate is connected to the node QB; A PMOS transistor P8, whose source is connected to the supply voltage VDD, whose drain is connected to the source of the PMOS transistor P7, and whose gate is connected to the node Q; A PMOS transistor P6, whose source is connected to the supply voltage VDD, whose drain is connected to the source of the PMOS transistor P8, and whose gate is connected to the node QB; A PMOS transistor P7, whose source is connected to the drain of the PMOS transistor P5, whose drain is connected to the drain of the NMOS transistor N5 and sets a redundant node S1, and whose gate is connected to the drain of the PMOS transistor P8; A PMOS transistor P5, whose source is connected to the drain of the PMOS transistor P6, whose drain is connected to the drain of the NMOS transistor N6 and sets a node redundancy S2, and whose gate is connected to the drain of the PMOS transistor P7; an NMOS transistor N1, whose drain is connected to the drain of the PMOS transistor P3, whose source is connected to the drain of the NMOS transistor N3, and whose gate is connected to the redundant node S1; an NMOS transistor N2, a drain of which is connected to the drain of the PMOS transistor P4, a source of which is connected to the drain of the NMOS transistor N4, and a gate of which is connected to the redundant node S2; an NMOS transistor N3, whose drain is connected to the source of the NMOS transistor N1, whose source is connected to the drains of the NMOS transistors N7 and N9, and whose gate is connected to the node Q; an NMOS transistor N4, whose drain is connected to the source of the NMOS transistor N2, whose source is connected to the drains of the NMOS transistors N8 and N10, and whose gate is connected to the node QB; An NMOS transistor N5, having a drain connected to the node S1, a source connected to the ground, and a gate connected to the node Q; An NMOS transistor N6 having a drain connected to the node S2, a source connected to the ground, and a gate connected to the node QB; The NMOS transistor N11 has a drain connected to the lower ends of the magnetic tunnel junctions M1 and M2, a source grounded, and a gate connected to the clock signal CLK.

4. The radiation-resistant in-memory logic circuit according to claim 1, characterized in that: The anti-SET pulse filter circuit specifically comprises: A delay unit, whose input terminal is connected to the node Q, and whose output terminal is connected to the gates of the PMOS transistor P10 and the NMOS transistor N13 and sets the node D; A PMOS transistor P9, whose source is connected to the supply voltage VDD, whose drain is connected to the source of the PMOS transistor P10, and whose gate is connected to the node Q; A PMOS transistor P10, whose source is connected to the drain of the PMOS transistor P9, whose drain is connected to the drain of the NMOS transistor N12, and whose gate is connected to the node D; an NMOS transistor N12, whose drain is connected to the drain of the PMOS transistor P10, whose source is connected to the drain of the NMOS transistor N12, and whose gate is connected to the node Q; The NMOS transistor N13 has a drain connected to the source of the NMOS transistor N12, a source connected to the ground, and a gate connected to the node D.

5. The radiation-resistant in-memory logic circuit according to claim 2, characterized in that: The volatile data A to be subjected to logical calculation is represented by an external input signal.

6. The radiation-resistant in-memory logic circuit according to claim 2, characterized in that: Non-volatile data B for performing logical calculations is stored in the magnetic tunnel junctions M1 and M2, wherein the magnetic tunnel junction M1 stores a data value of / B, and the magnetic tunnel junction M2 stores a data value of B; If the state of the magnetic tunnel junction is a parallel state, the stored logic value is '1'; if the state of the magnetic tunnel junction is an anti-parallel state, the stored logic value is '0'.

7. The radiation-resistant in-memory logic circuit according to claim 2, characterized in that: The magnetic tunnel junction / CMOS hybrid logic network performs AND logic calculations in the following manner: Input signal C1 = '1', C2 = '0', C3 = A; The OUT node outputs the logical result "AB".

8. The radiation-resistant in-memory logic circuit according to claim 2, characterized in that: The magnetic tunnel junction / CMOS hybrid logic network performs OR logic calculation in the following manner: Input signal C1 = / A, C2 = '0', C3 = '1'; The OUT node outputs the logical result "A + B".

9. The radiation-resistant in-memory logic circuit according to claim 2, characterized in that: The magnetic tunnel junction / CMOS hybrid logic network performs XOR logic calculation in the following manner: Input signal C1 = / A, C2 = A, C3 = / A; The OUT node outputs the logical result "A ⊕ B".

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