A radiation-resistant in-memory logic circuit

Abstract

This invention provides a radiation-resistant in-memory logic circuit, relating to the field of integrated circuits. The circuit comprises three parts: a magnetic tunnel junction / CMOS hybrid logic network, an anti-SEU readout circuit, and an anti-SET pulse filter circuit. The magnetic tunnel junction / CMOS hybrid logic network is connected to the anti-SEU readout circuit, while the input of the filter circuit is connected to the output of the anti-SEU readout circuit. The magnetic tunnel junction / CMOS hybrid logic network is reconfigurable and can implement various Boolean logic operations (AND, OR, XOR). When a radiated particle irradiates a sensitive node of the readout circuit, the anti-SEU readout circuit corrects logic errors caused by the SEU. The filter circuit filters out SET pulses left over from the previous readout circuit's SEU correction. This invention effectively improves the resistance to single-event upsets (SOME) in-memory logic circuits and reduces the soft error rate. Furthermore, compared to traditional multi-mode redundancy hardening methods, this invention effectively reduces circuit area overhead and power consumption.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and more particularly to a radiation-resistant in-memory logic circuit. Background Technology

[0002] Magnetic tunnel junctions (MTJs), as the basic storage unit of magnetic memories, are considered one of the most promising new memory devices and have been extensively studied in recent years. MTJs possess advantages such as high speed, non-volatility, long lifespan, low power consumption, and compatibility with CMOS technology. They also exhibit good anti-interference capabilities, particularly good tolerance to radiation environments, making them widely used in high-radiation applications such as aerospace and military. MTJ-based in-memory logic circuits offer advantages such as high integration, low power consumption, and non-volatility. They combine storage and computation functions within the MTJ, reducing data transmission distance and improving computational efficiency. However, in-memory logic circuits inherit characteristics from both memory and logic circuits, making them more sensitive to single-event events (SEU and SET). Furthermore, in MTJ-based in-memory logic circuits, the read circuit typically employs a latch structure. Sensitive nodes in the latch structure are susceptible to attacks from high-energy particles, leading to circuit errors. These errors persist until the state is reset or the next logic operation occurs.

[0003] Single-event effects are a major form of high-energy particle attack. They primarily include single-event upset (SEU) and single-event transient (SET) effects. The SEU effect refers to the ionization effect that can occur in semiconductor materials when high-energy particles pass through sensitive nodes in a circuit. High-energy particles collide with atoms in the semiconductor, resulting in the generation of free electrons and holes. When these free charges (electrons and holes) accumulate at sensitive nodes in the circuit, they can cause the voltage of that node to temporarily deviate from its normal operating state. For example, a sudden change in the voltage of a memory cell can cause the stored bit value to flip and remain so until the next write operation. The SET effect refers to the brief current pulse or voltage transient caused when high-energy particles pass through a semiconductor device. SET pulses usually disappear within a very short time, but during this period, they can affect logic circuits. SET pulses can propagate through the circuit and pass through multiple logic gates or nodes. If these pulses are not attenuated or filtered out during propagation, they can affect other downstream nodes in the circuit, thus expanding the scope of the error. Meanwhile, when the SET pulse propagates to the input of a sequential circuit and is sampled precisely at the rising edge of the clock signal, this erroneous signal may be latched, causing erroneous behavior throughout the circuit. In this case, a brief pulse can lead to a persistent erroneous state. Therefore, radiation-hardened technology is crucial for ensuring the stable operation of critical systems and preventing functional failures or data errors. It can effectively resist the SEU and SET effects induced by high-energy particle radiation, thereby improving the reliability of systems in high-radiation environments such as aerospace, military, and nuclear energy.

[0004] To improve the radiation resistance of logic circuits, existing technologies mainly employ redundant logic structures, such as triple modular redundancy (TMR). This involves placing multiple modules with the same function in critical circuit sections. When radiation causes one module to malfunction, the correct output is determined through majority voting or other methods, thereby improving circuit reliability. However, redundant logic structures suffer from drawbacks such as large area overhead, high power consumption, and high cost. Summary of the Invention

[0005] Purpose of the invention: To propose a radiation-resistant in-memory logic circuit that, when a sensitive node of the read circuit is attacked, utilizes an anti-SEU read circuit and a SET pulse filter circuit to detect and correct possible errors in the circuit, ensuring the accuracy of the logic function of the in-memory logic circuit and improving the reliability of the circuit, thereby effectively solving the aforementioned problems proposed in the prior art.

[0006] To achieve the above-mentioned technical objectives, the technical solution adopted by the present invention is as follows:

[0007] An irradiation-resistant in-memory logic circuit structure includes three modules: a magnetic tunnel junction / CMOS hybrid logic network, an anti-SEU readout circuit, and an anti-SET pulse filter circuit.

[0008] The three modules in the circuit are connected as follows: the magnetic tunnel junction / CMOS hybrid logic network is connected to the anti-SEU read circuit, and the anti-SEU read circuit is connected to the anti-SET pulse filter circuit. The output signal of the anti-SEU read circuit is input to the anti-SET pulse filter circuit.

[0009] When a sensitive node in the circuit is struck by a high-energy particle, causing a SEU effect that leads to a flipping of the output signal, the anti-SEU read circuit strengthens the read circuit by setting redundant storage nodes S1 and S2. It can detect errors and correct the output signal. However, when correcting the output signal, the anti-SEU read circuit is prone to leaving SET pulses on the output waveform. Therefore, an anti-SET pulse filter circuit is used to detect and filter out SET pulses. This prevents SET pulses from propagating in the logic circuit, ensuring that the logic circuit is not affected by radiation interference and operates normally.

[0010] In a further embodiment, the above-mentioned magnetic tunnel junction / CMOS hybrid logic network includes: an NMOS transistor N7, whose drain is connected to the source of N3, whose source is connected to the upper end of the magnetic tunnel junction M1, and whose gate is connected to the input signal C1; an NMOS transistor N8, whose drain is connected to the source of N4, whose source is connected to the upper end of the magnetic tunnel junction M1, and whose gate is connected to the input signal C2; an NMOS transistor N9, whose drain is connected to the source of N3, whose source is connected to the upper end of the magnetic tunnel junction M2, and whose gate is connected to the input signal C2; an NMOS transistor N10, whose source is connected to the source of N4, whose source is connected to the upper end of the magnetic tunnel junction M2, and whose gate is connected to the input signal C3; a magnetic tunnel junction M1, whose upper end is connected to the sources of N7 and N8, and whose lower end is connected to the drain of N11; and a magnetic tunnel junction M2, whose upper end is connected to the sources of N9 and N10, and whose lower end is connected to the drain of N11.

[0011] In a further embodiment, the aforementioned anti-SEU readout circuit includes: a PMOS transistor P1, whose source is connected to VDD, whose drain is connected to the drain of N3 and forms node QB, and whose gate is connected to the clock signal CLK; a PMOS transistor P2, whose source is connected to VDD, whose drain is connected to the drain of N4 and forms node Q, and whose gate is connected to the clock signal CLK; a PMOS transistor P3, whose source is connected to VDD, whose drain is connected to the drain of N1, and whose gate is connected to node Q; and a PMOS transistor P4. PMOS transistor P5 has its source connected to VDD, its drain connected to the drain of N2, and its gate connected to node QB; PMOS transistor P6 has its source connected to VDD, its drain connected to the source of P8, and its gate connected to node QB; PMOS transistor P7 has its source connected to the drain of P5, its drain connected to the drain of N5 and a redundant node S1 is provided, and its gate connected to the drain of P8; PMOS transistor P8... Its source is connected to the drain of P6, its drain is connected to the drain of N6 and a redundant node S2 is set, and its gate is connected to the drain of P7; NMOS transistor N1 has its drain connected to the drain of P3, its source connected to the drain of N3, and its gate connected to node S1; NMOS transistor N2 has its drain connected to the drain of P4, its source connected to the drain of N4, and its gate connected to node S2; NMOS transistor N3 has its drain connected to the source of N1, its source connected to the drains of N7 and N9, and its gate connected to node Q. NMOS transistor N4 has its drain connected to the source of N2, its source connected to the drains of N8 and N10, and its gate connected to node QB; NMOS transistor N5 has its drain connected to redundant node S1, its source grounded, and its gate connected to node Q; NMOS transistor N6 has its drain connected to redundant node S2, its source grounded, and its gate connected to node QB; NMOS transistor N11 has its drain connected to the lower end of magnetic tunnel junctions M1 and M2, its source grounded, and its gate clock signal CLK.

[0012] In a further embodiment, the above-mentioned anti-SET pulse filter circuit includes: a delay unit, the input of which is connected to node Q, and the output of which is connected to the gates of P10 and N13 and connected to node D; a PMOS transistor P9, the source of which is connected to VDD, the drain of which is connected to the source of P10, and the gate of which is connected to node Q; a PMOS transistor P10, the source of which is connected to the drain of P9, the drain of which is connected to the drain of N12, and the gate of which is connected to node D; an NMOS transistor N12, the drain of which is connected to the drain of P10, the source of which is connected to the drain of N13, and the gate of which is connected to node Q; and an NMOS transistor N13, the drain of which is connected to the source of N12, the source of which is grounded, and the gate of which is connected to node D.

[0013] In a further embodiment, the aforementioned magnetic tunnel junction / CMOS hybrid logic network has reconfigurable logic computing capabilities:

[0014] (1) When the circuit performs AND logic calculations:

[0015] C1 = '1', C2 = '0', C3 = A,

[0016] The OUT node outputs the logical result "AB";

[0017] (2) When the circuit performs or performs logic calculations:

[0018] C1= / A, C2='0', C3 = '1',

[0019] The OUT node outputs the logical result "A + B";

[0020] (3) When the circuit performs an XOR logic calculation:

[0021] C1 = / A, C2 = A, C3 = / A,

[0022] The OUT node outputs the logical result "A ⊕ B".

[0023] Furthermore, the aforementioned anti-SEU readout circuit has the capability to read data. When the resistance of the left branch in the logic network is small, the logic values ​​of storage nodes Q and S2 are '1', and the logic values ​​of storage nodes QB and S1 are '0'; when the resistance of the right branch in the logic network is small, the logic values ​​of storage nodes QB and S1 are '1', and the logic values ​​of storage nodes Q and S2 are '0'.

[0024] Furthermore, the aforementioned anti-SEU read circuit is capable of resisting SEU attacks. The four storage nodes Q, QB, S1, and S2 are mutually constrained. When one node receives an SEU attack and its logic state changes, the other nodes can remain stable and correct the logic state of the attacked node through the mutual constraints between nodes.

[0025] Furthermore, the aforementioned anti-SET pulse filter circuit has the ability to filter out SET pulses. A delay unit is used to ensure the SET pulse experiences a certain delay before reaching the sensitive circuit. Then, the C unit (composed of transistors P9, P10, N12, and N13) is used to filter out the SET pulse, enhancing the system's reliability.

[0026] Compared with the prior art, the present invention has the following beneficial effects:

[0027] This invention proposes a radiation-resistant in-memory logic circuit. When a sensitive node of the circuit is attacked, an anti-SEU readout circuit and a SET pulse filter circuit work together to detect and correct potential errors in the circuit, ensuring the accuracy of the circuit's logic function. Compared with existing technical solutions, this invention can effectively reduce area overhead and power consumption. Attached Figure Description

[0028] Figure 1 This is a schematic diagram of the internal logic circuit for radiation protection.

[0029] Figure 2 This is a schematic diagram of the anti-SEU readout circuit.

[0030] Figure 3 This is a functional diagram of the anti-SET pulse circuit. Detailed Implementation

[0031] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention can be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described in order to avoid obscuring the invention.

[0032] See Figure 1 This invention provides a radiation-resistant in-memory logic circuit structure, comprising three modules: a magnetic tunnel junction / CMOS hybrid logic network, an anti-SEU readout circuit, and an anti-SET pulse filter circuit. The magnetic tunnel junction / CMOS hybrid logic network includes transistors N7-N10 and magnetic tunnel junctions M1-M2; the anti-SEU readout circuit includes transistors P1-P8, N1-N6, and N11; and the anti-SET pulse filter circuit includes a delay unit and transistors P9-P10 and N12-N13.

[0033] The connection relationships of each component are as follows:

[0034] The source of P1 is connected to VDD, and the drain of P1 is connected to the source of N1, the drain of N3, the gate of P4, the gate of N4, the gate of P6, and the gate of N6. The gate of P1 is connected to the clock signal CLK.

[0035] The source of P2 is connected to VDD. The drain of P2 is connected to the source of N2, the drain of N4, the gate of P3, the gate of N3, the gate of P5, the gate of N5, the input of the delay unit, the gate of P9, and the gate of N12. The gate of P2 is connected to the clock signal CLK.

[0036] The source of P3 is connected to VDD, the drain of P3 is connected to the drain of N1, and the gate of P3 is connected to the gate of N3, the gate of P5, the gate of N5, the source of N2, the drain of N4, the drain of P2, the input of the delay unit, the gate of P9, and the gate of N12.

[0037] The source of P4 is connected to VDD, the drain of P4 is connected to the drain of N2, and the gate of P4 is connected to the gate of N4, the gate of P6, the gate of N6, the source of N1, the drain of N3, and the drain of P1.

[0038] The source of P5 is connected to VDD, the drain of P5 is connected to the source of P7, and the gate of P5 is connected to the gate of N3, the gate of P5, the gate of N5, the source of N2, the drain of N4, the drain of P2, the input of the delay unit, the gate of P9, and the gate of N12.

[0039] The source of P6 is connected to VDD, the drain of P6 is connected to the source of P8, and the gate of P6 is connected to the gate of N6, the gate of P4, the gate of N4, the source of N1, the drain of N3, and the drain of P1.

[0040] The source of P7 is connected to the drain of P5, the drain of P7 is connected to the drain of N5, the gate of P8, and the gate of N1, and the gate of P7 is connected to the drain of P8, the drain of N6, and the gate of N2.

[0041] The source of P8 is connected to the drain of P6, the drain of P8 is connected to the drain of N6, the gate of P7, and the gate of N2, and the gate of P8 is connected to the drain of P7, the drain of N5, and the gate of N1.

[0042] The source of P9 is connected to VDD, the drain of P9 is connected to the source of P10, the drain of P9 is connected to the source of P10, and the gate of P9 is connected to the gate of P3, the gate of N3, the gate of P5, the gate of N5, the source of N2, the drain of N4, the drain of P2, the input of the delay unit, and the gate of N12.

[0043] The source of P10 is connected to the drain of P9, the drain of P10 is connected to the drain of N12, and the gate of P10 is connected to the output of the delay unit and the gate of N13.

[0044] The source of N1 is connected to the drain of P1, the drain of N3, the gate of P4, the gate of N4, the gate of P6, and the gate of N6. The drain of N1 is connected to the drain of P3. The gate of N1 is connected to the drain of P7, the drain of N5, and the gate of P8.

[0045] The source of N2 is connected to the gates of P3, N3, P5, N5, N4, P2, the input of the delay unit, the gate of P9, and the gate of N12. The drain of N2 is connected to the drain of P4. The gate of N2 is connected to the drains of P8, N6, and P7.

[0046] The source of N3 is connected to the drain of N7 and the drain of N9. The drain of N3 is connected to the source of N1, the drain of P1, the gate of P4, the gate of N4, the gate of P6, and the gate of N6. The gate of N3 is connected to the source of N2, the gate of P3, the gate of P5, the gate of N5, the drain of N4, the drain of P2, the input of the delay unit, the gate of P9, and the gate of N12.

[0047] The source of N4 is connected to the drain of N8 and the drain of N10. The drain of N4 is connected to the gate of N3, the source of N2, the gate of P3, the gate of P5, the gate of N5, the drain of P2, the input of the delay unit, the gate of P9, and the gate of N12. The gate of N4 is connected to the drain of N3, the source of N1, the drain of P1, the gate of P4, the gate of P6, and the gate of N6.

[0048] The source of N5 is grounded, and the drain of N5 is connected to the gate of N1, the drain of P7, and the gate of P8. The gate of N5 is connected to the source of N2, the gate of P3, the gate of N3, the gate of P5, the drain of N4, the drain of P2, the input of the delay unit, the gate of P9, and the gate of N12.

[0049] The source of N6 is grounded, the drain of N6 is connected to the gate of N2, the drain of P8, and the gate of P7, and the gate of N6 is connected to the source of N1, the drain of P1, the drain of N3, the gate of P4, the gate of N4, and the gate of P6.

[0050] The source of N7 is connected to the source of N8 and the upper end of M1. The drain of N7 is connected to the source of N3 and the drain of N9. The gate of N7 is connected to the input signal C1.

[0051] The source of N8 is connected to the source of N7 and the upper end of M1. The drain of N8 is connected to the source of N4 and the drain of N10. The gate of N8 is connected to the input signal C2.

[0052] The source of N9 is connected to the source of N10 and the upper end of M2. The drain of N9 is connected to the source of N3 and the drain of N7. The gate of N9 is connected to the input signal C2.

[0053] The source of N10 is connected to the source of N9 and the upper end of M2. The drain of N10 is connected to the source of N4 and the drain of N8. The gate of N9 is connected to the input signal C3.

[0054] The source of N11 is grounded, the drain of N11 is connected to the lower end of M1 and M2, and the gate of N11 is connected to the clock signal CLK.

[0055] The source of N12 is connected to the drain of N13, the drain of N12 is connected to the drain of P10, and the gate of N12 is connected to the drain of P2, the drain of N4, the gate of P3, the gate of N3, the gate of P5, the gate of N5, the input of the delay unit, and the gate of P9.

[0056] The source of N13 is grounded, the drain of N13 is connected to the source of N12, and the gate of N13 is connected to the gate of P10 and the output of the delay unit.

[0057] The input terminal of the delay unit is connected to the drain of P2, the drain of N4, the gate of P3, the gate of N3, the gate of P5, the gate of N5, the gate of P9, and the gate of N12. The output terminal of the delay unit is connected to the gate of P10 and the gate of N13.

[0058] It should be noted that there is some repetition in the above connections, but this has been retained for ease of understanding.

[0059] Among them, the hybrid magnetic tunnel junction / CMOS hybrid logic network has reconfigurability and can perform various Boolean logic operations, as follows:

[0060] (1) When the circuit performs AND logic calculations:

[0061] C1 = '1', C2 = '0', C3 = A,

[0062] The OUT node outputs the logical result "AB";

[0063] (2) When the circuit performs or performs logic calculations:

[0064] C1 = / A, C2 = '0', C3 = '1',

[0065] The OUT node outputs the logical result "A + B";

[0066] (3) When the circuit performs an XOR logic calculation:

[0067] C1 = / A, C2 = A, C3 = / A,

[0068] The OUT node outputs the logical result "A ⊕ B".

[0069] For the anti-SEU read circuit, the four memory nodes Q, QB, S1, and S2 are mutually constrained. When one node is attacked by an SEU and its logic state changes, the other nodes can remain stable and correct the logic state of the attacked node through the relevant constraints between the nodes.

[0070] See Figure 2 In a magnetic tunnel junction / CMOS hybrid logic network, when the resistance of the left branch is less than the resistance of the right branch, the values ​​of nodes Q and S2 are '1', and the values ​​of nodes QB and S1 are '0'. It is known that the reverse-biased drain junction of a MOS transistor in the off state is a sensitive node in the circuit. Furthermore, the SEU at the drain of a PMOS transistor causes a positive transient pulse (the node logic state may be '0'→'1' or '1'→'1'), while in the case of an NMOS transistor, it causes a negative transient pulse (the node logic state may be '0'→'0' or '1'→'0'). Since node QB stores '0' in this case, its only possible transient is '0'→'0', and QB will not change the node state. Therefore, QB is not sensitive. In the hypothetical case, nodes Q, S1, and S2 are sensitive nodes.

[0071] The anti-SEU readout circuit works as follows:

[0072] Node Q is subjected to an SEU attack: When node Q flips from '1' to '0', P3 and P5 turn on, and N3 and N5 turn off. At this time, node S2 is unaffected, keeping transistor N1 on and transistor P7 off. Since nodes QB and S1 are not connected to VDD or GND, they enter a high-impedance state. Capacitor nodes in a high-impedance state retain their previous logic values, while nodes QB and S1 retain their original logic '0'. Based on the above analysis, S1, S2, and QB are all in a stable state. Node S2 keeps N2 on, node QB keeps P4 on and N4 off, and the affected node Q can recover its original logic value '1'.

[0073] Node S1 is subjected to an SEU attack: When node S1 flips from '0' to '1', it causes P8 to turn off and N1 to turn on. At this time, S1, Q, and QB are all in a high-impedance state, maintaining their initial logic values. Node S2 will keep P7 off, node Q will keep P5 off and N5 on, and the affected node S1 can recover its original logic value of '0'.

[0074] Node S2 is subjected to an SEU attack: When node S2 flips from '1' to '0', P7 is turned on and N2 is turned off. At this time, S1, Q, and QB are all in a high-impedance state, maintaining their initial logic values. Node S1 will keep P8 on, node QB will keep P6 on and N6 off, and the affected node S2 can recover its original logic value '1'.

[0075] It should be noted that in another scenario, when the resistance of the left branch in the magnetic tunnel junction / CMOS hybrid logic network is greater than the resistance of the right branch, the values ​​of nodes Q and S2 are '0', and the values ​​of nodes QB and S1 are '1'. In this case, nodes QB, S1, and S2 are sensitive nodes, and their radiation hardening principle is the same as described above.

[0076] Furthermore, when the incident particle charge of the SEU is large, although the anti-SEU readout circuit can recover the logic value of the attacked node, the attacked node will also generate a SET pulse. SET pulses can adversely affect the logic circuit. Therefore, we use an anti-SET pulse filter circuit to filter out SET pulses.

[0077] The anti-SET pulse filter circuit includes a delay unit and a C unit (composed of P9, P10, N12, and N13). The logic function of the C unit is as follows: when its two inputs D and Q are the same, the C unit acts as an inverter. When its inputs D and Q are different, the output node OUT presents a high impedance state, and the output voltage will maintain its value until the leakage current decreases.

[0078] See Figure 3 When the output node Q of the anti-SEU readout circuit is affected by a SET pulse, a brief SET pulse appears on its output waveform. After node Q is input to the delay unit, a brief SET pulse also appears in the output waveform of the delay unit, but there is a time interval ΔT between the two SET pulses (ΔT is the hysteresis time of the delay unit). During the time from the falling edge of the SET pulse at point Q to the rising edge of the SET pulse at point D, the output node of unit C is in a high-impedance state, and the output remains unchanged during this period. This filters out the SET pulse and reduces its impact on the circuit.

[0079] Although the steps in this invention are arranged by reference numerals, this is not intended to limit the order of the steps. Unless the order of the steps is explicitly stated or the execution of a step requires other steps as a basis, the relative order of the steps can be adjusted. It is understood that the term "and / or" as used herein refers to and covers any and all possible combinations of one or more of the associated listed items.

[0080] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A radiation-resistant in-memory logic circuit, characterized in that, This includes a magnetic tunnel junction / CMOS hybrid logic network, an anti-SEU readout circuit, and an anti-SET pulse filter circuit; The magnetic tunnel junction / CMOS hybrid logic network is electrically connected to the anti-SEU read circuit; The magnetic tunnel junction / CMOS hybrid logic network specifically includes: NMOS transistor N7 has its drain connected to the source of NMOS transistor N3, its source connected to the upper end of magnetic tunnel junction M1, and its gate connected to signal C1. NMOS transistor N8 has its drain connected to the source of NMOS transistor N4, its source connected to the upper end of magnetic tunnel junction M1, and its gate connected to signal C2. NMOS transistor N9 has its drain connected to the source of NMOS transistor N3, its source connected to the upper end of magnetic tunnel junction M2, and its gate connected to signal C2. NMOS transistor N10 has its drain connected to the source of NMOS transistor N4, its source connected to the upper end of magnetic tunnel junction M2, and its gate connected to signal C3. The magnetic tunnel junction M1 is connected at its upper end to the source of NMOS transistors N7 and N8, and at its lower end to the drain of NMOS transistor N11. The magnetic tunnel junction M2 is connected at its upper end to the source of NMOS transistors N9 and NMOS transistor N10, and at its lower end to the drain of NMOS transistor N11. The anti-SEU reading circuit and the anti-SET pulse filter circuit are electrically connected. The output signal of the anti-SEU reading circuit is input to the anti-SET pulse filter circuit, and the anti-SET pulse filter circuit outputs the circuit logic result. When the sensitive node of the read circuit is struck by a high-energy particle, causing the SEU effect and the output signal to flip, the anti-SEU read circuit detects the current error signal and corrects the output signal, while leaving the SET pulse; the anti-SET pulse filter circuit is used to detect and filter out the SET pulse.

2. The radiation-resistant in-memory logic circuit according to claim 1, characterized in that, The anti-SEU readout circuit specifically includes: PMOS transistor P1 has its source connected to the supply voltage VDD, its drain connected to the drain of NMOS transistor N3 and node QB set, and its gate connected to the clock signal CLK. PMOS transistor P2 has its source connected to the supply voltage VDD, its drain connected to the drain of NMOS transistor N4 and set to node Q, and its gate connected to the clock signal CLK. PMOS transistor P3 has its source connected to the supply voltage VDD, its drain connected to the drain of NMOS transistor N1, and its gate connected to node Q. PMOS transistor P4 has its source connected to the supply voltage VDD, its drain connected to the drain of NMOS transistor N2, and its gate connected to node QB. PMOS transistor P8 has its source connected to the supply voltage VDD, its drain connected to the source of PMOS transistor P7, and its gate connected to node Q. PMOS transistor P6 has its source connected to the supply voltage VDD, its drain connected to the source of PMOS transistor P8, and its gate connected to node QB. PMOS transistor P7 has its source connected to the drain of PMOS transistor P5, its drain connected to the drain of NMOS transistor N5 and a redundant node S1 is provided, and its gate is connected to the drain of PMOS transistor P8. PMOS transistor P5 has its source connected to the drain of PMOS transistor P6, its drain connected to the drain of NMOS transistor N6 and node redundancy S2 is set, and its gate is connected to the drain of PMOS transistor P7. NMOS transistor N1 has its drain connected to the drain of PMOS transistor P3, its source connected to the drain of NMOS transistor N3, and its gate connected to redundant node S1. NMOS transistor N2 has its drain connected to the drain of PMOS transistor P4, its source connected to the drain of NMOS transistor N4, and its gate connected to redundant node S2. NMOS transistor N3 has its drain connected to the source of NMOS transistor N1, its source connected to the drain of NMOS transistors N7 and N9, and its gate connected to node Q. NMOS transistor N4 has its drain connected to the source of NMOS transistor N2, its source connected to the drain of NMOS transistors N8 and N10, and its gate connected to node QB. NMOS transistor N5 has its drain connected to node S1, its source grounded, and its gate connected to node Q. NMOS transistor N6 has its drain connected to node S2, its source grounded, and its gate connected to node QB. The NMOS transistor N11 has its drain connected to the lower end of the magnetic tunnel junctions M1 and M2, its source grounded, and its gate clock signal CLK.

3. The radiation-resistant in-memory logic circuit according to claim 1, characterized in that, The anti-SET pulse filter circuit specifically includes: The delay unit has its input connected to node Q and its output connected to the gates of PMOS transistor P10 and NMOS transistor N13, and is configured to node D. PMOS transistor P9 has its source connected to the supply voltage VDD, its drain connected to the source of PMOS transistor P10, and its gate connected to node Q. PMOS transistor P10 has its source connected to the drain of PMOS transistor P9, its drain connected to the drain of NMOS transistor N12, and its gate connected to node D. NMOS transistor N12 has its drain connected to the drain of PMOS transistor P10, its source connected to the drain of NMOS transistor N12, and its gate connected to node Q. NMOS transistor N13 has its drain connected to the source of NMOS transistor N12, its source is grounded, and its gate is connected to node D.

4. The radiation-resistant in-memory logic circuit according to claim 1, characterized in that: The volatile data A used for logical calculations is represented by an external input signal.

5. The radiation-resistant in-memory logic circuit according to claim 1, characterized in that: The non-volatile data B used for logical calculations is stored in the magnetic tunnel junctions M1 and M2, wherein the magnetic tunnel junction M1 stores the data value / B and the magnetic tunnel junction M2 stores the data value B. If the magnetic tunnel junction is in a parallel state, the stored logic value is '1'; if the magnetic tunnel junction is in an antiparallel state, the stored logic value is '0'.

6. The radiation-resistant in-memory logic circuit according to claim 1, characterized in that, The magnetic tunnel junction / CMOS hybrid logic network performs logical computation in the following manner: Input signals C1 = '1', C2 = '0', C3 = A; The OUT node outputs the logical result "AB".

7. The radiation-resistant in-memory logic circuit according to claim 1, characterized in that, The magnetic tunnel junction / CMOS hybrid logic network performs OR logic computation in the following manner: Input signals C1 = / A, C2 = '0', C3 = '1'; The OUT node outputs the logical result "A + B".

8. The radiation-resistant in-memory logic circuit according to claim 1, characterized in that, The magnetic tunnel junction / CMOS hybrid logic network performs XOR logic computation in the following manner: Input signals C1 = / A, C2 = A, C3 = / A; The OUT node outputs the logical result "A ⊕ B".

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