Quality determination method of component interconnection structure and related equipment

Abstract

According to the quality determination method of the component interconnection structure and the related equipment provided by the invention, the failure mode and the reason can be quickly and accurately identified through the pre-constructed failure mode model and the fault tree analysis algorithm, and tedious test and verification links are not needed, so that the quality determination period is greatly shortened. Meanwhile, stress simulation based on shape parameters and environmental load parameters can accurately predict the stress intensity of the interconnection structure of the component in practical application, and in combination with a quality analysis algorithm, the quality of the target interconnection structure can be comprehensively evaluated, so that the reliability of the interconnection structure of the component is ensured, and the quality determination cost of the interconnection structure is remarkably reduced.

Description

Technical Field

[0001] The present application relates to the technical field of quality management, and in particular to a method for determining the quality of a component interconnection structure and related equipment. Background Art

[0002] The interconnection structure of components can not only realize the transmission of electrical signals, but also improve the integration of circuits, reduce circuit delays and power consumption, and improve the working efficiency and performance of components. Therefore, the quality of the interconnection structure of components is crucial.

[0003] Based on the above situation, the quality determination method of the component interconnection structure in the prior art has the problems of high cost and long cycle. Summary of the invention

[0004] In view of this, the purpose of the present application is to propose a method for determining the quality of a component interconnection structure and related equipment to solve the above technical problems.

[0005] Based on the above objectives, the first aspect of the present application provides a method for determining the quality of a component interconnection structure, comprising:

[0006] Obtaining attribute parameters and shape parameters of a target interconnect structure of components;

[0007] Performing failure analysis processing based on the attribute parameters through a pre-built failure mode model to obtain a failure mode analysis result;

[0008] According to the failure mode analysis result, the failure cause processing is performed by using a fault tree analysis algorithm to determine the failure cause processing result;

[0009] Based on the shape parameters, a stress simulation is performed on the target interconnection structure of the component according to preset environmental load parameters to obtain a stress intensity simulation result;

[0010] The stress intensity simulation result and the failure cause processing result are processed by a quality analysis algorithm to obtain a quality determination result of the target interconnection structure of the component.

[0011] Optionally, the failure mode model includes a database having failure modes corresponding to different attribute parameters;

[0012] The failure analysis process is performed based on the attribute parameters through a pre-built failure mode model to obtain a failure mode analysis result, including:

[0013] Based on the attribute parameters, the failure mode corresponding to the attribute parameters is searched from the database, and the failure mode corresponding to the attribute parameters is used as the failure mode analysis result.

[0014] Optionally, the failure mode model includes a pre-trained convolutional neural network model, wherein the convolutional neural network model includes a convolution layer, an activation function layer, a pooling layer, and a fully connected layer;

[0015] The failure analysis process is performed based on the attribute parameters through a pre-built failure mode model to obtain a failure mode analysis result, including:

[0016] Using the convolution layer to perform convolution feature extraction on the attribute parameters to obtain convolution feature data;

[0017] Performing nonlinear transformation processing on the convolution feature data through the activation function layer to obtain feature data after nonlinear transformation;

[0018] Downsampling the feature data after nonlinear transformation through the pooling layer to obtain downsampled feature data;

[0019] A failure mode classification result is determined using a fully connected layer based on the downsampled feature data and a preset weight matrix, and the failure mode classification result is used as a failure mode analysis result.

[0020] Optionally, performing failure cause processing by using a fault tree analysis algorithm according to the failure mode analysis result to determine the failure cause processing result includes:

[0021] Determining a top event of a target interconnect structure of the component based on a failure mode analysis result;

[0022] Determine the cause of the next layer event that causes the top event at the current layer, and determine the bottom events that cause the cause of the next layer event layer by layer, and determine the logical relationship between the top event, each of the next layer event causes and the bottom events;

[0023] The occurrence probability of the minimum cut set of the top event is determined by using a descending tree algorithm, a target bottom event is determined from each bottom event based on the occurrence probability of each bottom event, and the target bottom event is used as a failure cause processing result.

[0024] Optionally, the failure model analysis results include multiple types of failure modes;

[0025] The step of determining the top event of the target interconnect structure of the component based on the failure mode analysis result comprises:

[0026] Determine the occurrence frequency data, impact degree data and detection degree data of each type of failure mode under the attribute parameters;

[0027] The occurrence frequency data, impact degree data and detection degree data of various types of failure modes are multiplied to obtain the risk priority numbers of various types of failure modes;

[0028] The failure mode of the type with the largest risk priority number is determined from the risk priority numbers corresponding to the multiple types of failure modes, and the failure mode of the type with the largest risk priority number is used as the top event of the target interconnection structure of the component.

[0029] Optionally, performing stress simulation on the target interconnect structure of the component based on the shape parameter according to preset environmental load parameters to obtain a stress intensity simulation result includes:

[0030] Constructing a geometric model of a target interconnection structure of the component based on the shape parameters;

[0031] Mesh the geometric model according to the preset mesh density to generate the finite element mesh;

[0032] Preset environmental load parameters are applied to the finite element mesh, and stress simulation is performed on the finite element mesh using a simulation program to obtain a stress intensity simulation result, wherein the simulation program is a software program for stress simulation of a target interconnection structure of components.

[0033] Optionally, the stress strength simulation result includes a stress-strain distribution diagram and a fatigue strength distribution diagram;

[0034] The step of processing the stress intensity simulation result and the failure cause processing result by a quality analysis algorithm to obtain a quality determination result of a target interconnect structure of the component includes:

[0035] Determine the stress concentration area and strain abnormal point position of the target interconnection structure of the component by using the stress-strain distribution diagram;

[0036] Determining a fatigue strength region having a fatigue strength lower than a preset fatigue strength threshold value based on the fatigue strength distribution map;

[0037] According to the failure cause processing result, the failure mechanism of the target interconnection structure of the component is determined, and the stress concentration area, the strain abnormal point position, the fatigue strength area and the failure mechanism are combined and processed to obtain the quality determination result of the target interconnection structure of the component.

[0038] Based on the same inventive concept, the second aspect of the present application provides a device for determining the quality of a component interconnection structure, comprising:

[0039] A parameter acquisition module is configured to acquire attribute parameters and shape parameters of a target interconnection structure of components;

[0040] A failure mode analysis module is configured to perform failure analysis processing based on the attribute parameters through a pre-built failure mode model to obtain a failure mode analysis result;

[0041] A failure cause processing module is configured to perform failure cause processing according to the failure mode analysis result by using a fault tree analysis algorithm to determine a failure cause processing result;

[0042] A stress simulation module is configured to perform stress simulation on a target interconnection structure of the component based on the shape parameters according to preset environmental load parameters to obtain a stress intensity simulation result;

[0043] The quality analysis module is configured to process the stress intensity simulation result and the failure cause processing result through a quality analysis algorithm to obtain a quality determination result of the target interconnection structure of the component.

[0044] Based on the same inventive concept, the third aspect of the present application provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and running on the processor, wherein the processor implements the method described in the first aspect above when executing the computer program.

[0045] Based on the same inventive concept, the fourth aspect of the present application provides a non-transitory computer-readable storage medium, which stores computer instructions, and the computer instructions are used to enable a computer to execute the method described in the first aspect above.

[0046] From the above, it can be seen that the quality determination method and related equipment of the interconnection structure of components provided by the present application can quickly and accurately identify failure modes and causes through pre-built failure mode models and fault tree analysis algorithms, without the need for cumbersome testing and verification links, thereby greatly shortening the quality determination cycle. At the same time, based on the stress simulation of shape parameters and environmental load parameters, the stress intensity of the interconnection structure of components in actual applications can be accurately predicted. Combined with the quality analysis algorithm, the quality of the target interconnection structure can be comprehensively evaluated, ensuring the reliability of the interconnection structure of components and significantly reducing the quality determination cost of the interconnection structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the technical solutions in the present application or related technologies, the drawings required for use in the embodiments or related technical descriptions are briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0048] Figure 1A flow chart of a method for determining the quality of a component interconnection structure according to an embodiment of the present application;

[0049] Figure 2 A schematic diagram of a quality determination process of a component interconnection structure according to an embodiment of the present application;

[0050] Figure 3 A schematic diagram of the fault tree analysis algorithm flow of an embodiment of the present application;

[0051] Figure 4 A schematic diagram of the stress simulation process of an embodiment of the present application;

[0052] Figure 5 A structural block diagram of a device for determining the quality of a component interconnection structure according to an embodiment of the present application;

[0053] Figure 6 A schematic diagram of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0054] In order to make the objectives, technical solutions and advantages of the present application more clearly understood, the present application is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0055] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present application should be the usual meanings understood by people with ordinary skills in the field to which the present application belongs. The "first", "second" and similar words used in the embodiments of the present application do not represent any order, quantity or importance, but are only used to distinguish different components. "Including" or "comprising" and similar words mean that the elements or objects appearing in front of the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0056] It is understandable that before using the technical solutions of each embodiment of the present application, the type, scope of use, usage scenarios, etc. of the personal information involved will be informed to the user in an appropriate manner, and the user's authorization will be obtained.

[0057] For example, in response to receiving an active request from a user, a prompt message is sent to the user to clearly remind the user that the operation requested to be performed will require obtaining and using the user's personal information. Thus, the user can independently choose whether to provide personal information to the electronic device, application, server, storage medium or other software or hardware that performs the operation of the technical solution of the present application according to the prompt message.

[0058] As an optional but non-limiting implementation, in response to receiving the user's active request, the prompt information may be sent to the user in the form of a pop-up window, in which the prompt information may be presented in text form. In addition, the pop-up window may also carry a selection control for the user to choose "agree" or "disagree" to provide personal information to the electronic device.

[0059] It is understandable that the above notification and the process of obtaining user authorization are merely illustrative and do not constitute a limitation on the implementation method of this application. Other methods that meet relevant laws and regulations may also be applied to the implementation method of this application.

[0060] The interconnection structure of components can not only realize the transmission of electrical signals, but also improve the integration of circuits, reduce circuit delays and power consumption, and improve the working efficiency and performance of components. The complexity of the application environment has put forward higher requirements on the reliability of components, so the quality of the interconnection structure of components is crucial.

[0061] Based on the above situation, the quality determination method of the component interconnection structure in the prior art has the problems of high cost and long cycle.

[0062] In order to solve the problems of high cost and long cycle brought about by the traditional method of determining the quality of component interconnection structure, it is urgent to establish a set of efficient methods for determining the quality of component interconnection structure to provide support for subsequent device interconnection structure process improvements while ensuring its high reliability application.

[0063] The embodiment of the present application provides a method for determining the quality of the interconnection structure of components. Through the pre-built failure mode model and fault tree analysis algorithm, the failure mode and cause can be quickly and accurately identified without tedious testing and verification steps, thereby greatly shortening the quality determination cycle. At the same time, based on the stress simulation of shape parameters and environmental load parameters, the stress intensity of the interconnection structure of components in actual applications can be accurately predicted. Combined with the quality analysis algorithm, the quality of the target interconnection structure can be comprehensively evaluated, ensuring the reliability of the interconnection structure of components and significantly reducing the quality determination cost of the interconnection structure.

[0064] like Figure 1 As shown, the method of this embodiment includes:

[0065] Step 101: Acquire attribute parameters and shape parameters of a target interconnection structure of components.

[0066] In this step, components include but are not limited to integrated circuits, electronic components, mechanical parts, etc.

[0067] The interconnection structure of components includes but is not limited to solder joints, pins, leads, through silicon vias (TSV), etc. The target interconnection structure refers to any interconnection structure that requires quality assessment.

[0068] Interconnection technologies include but are not limited to wire bonding (WB), tape-automated bonding (TAB), flip chip (FC), wafer-level package (WLP) and through silicon via (TSV).

[0069] The key processes of the interconnect structure include but are not limited to bonding, reverse soldering, capping and ball planting.

[0070] The property parameters of the target interconnect structure refer to the specific properties or performance parameters of the structure (such as metal wires, welding points, etc.) used to connect different devices or modules in electronic components or integrated circuits, for example, structural characteristic parameters, manufacturing process parameters, or material parameters.

[0071] The shape parameters of the target interconnect structure refer to the characteristic parameters of the interconnect structure in terms of physical form, which determine the layout, size, shape, etc. of the interconnect structure. For example, the shape parameters include:

[0072] Length: The length of the interconnect structure affects the transmission delay and attenuation of the signal.

[0073] Width: The width of an interconnect determines its ability to carry current and the contact area with other structures.

[0074] Thickness: For some types of interconnect structures (such as metal lines), their thickness will also affect the signal transmission performance and mechanical strength.

[0075] Shape: The shape of the interconnect structure can be a straight line, a curve, a broken line, etc. Different shapes will affect the signal transmission path and interference.

[0076] Step 102 : performing failure analysis processing based on the attribute parameters through a pre-built failure mode model to obtain a failure mode analysis result.

[0077] In this step, the pre-built failure mode model is used to predict or analyze the failure modes that may occur in the interconnection structure of the components under different conditions (such as property parameters).

[0078] Failure mode refers to the situation where the interconnection structure of components cannot work as expected. It may be caused by design defects, material aging, improper operation, environmental factors and other reasons. It can be used to assist in identifying potential risk points.

[0079] The failure mode analysis results provide key information about the failure mode, failure probability, potential impact, etc. of the interconnection structure of components under different conditions. It can be used to guide decisions in design optimization, material selection, manufacturing process control, maintenance strategy formulation, etc. to improve the reliability and safety of components.

[0080] Step 103: performing failure cause processing by using a fault tree analysis algorithm according to the failure mode analysis result to determine a failure cause processing result.

[0081] In this step, the Fault Tree Analysis (FTA) algorithm is a logical diagram method used to analyze the causes of unwanted top events (ie, fault or failure events) in the system.

[0082] In FTA, the top event is at the top of the tree, and then a series of basic events (i.e., the direct causes of the top event) are connected through logic gates (such as AND gates and OR gates).

[0083] The result of FTA is a fault tree that clearly shows the logical path from the top event to the basic event (i.e., the cause of the failure).

[0084] After completing the Failure Modes and Effects Analysis (FMEA), the key failure modes and their causes (i.e., the failure mode analysis results) are identified. Next, the FTA algorithm is used to construct a fault tree for these key failure modes.

[0085] By analyzing the fault tree, all possible cause paths leading to the top event (i.e. the key failure mode identified in FMEA) can be found.

[0086] Next, for each cause path, preventive or corrective actions can be developed to reduce or eliminate the occurrence of these causes.

[0087] After implementing the above preventive or corrective measures, the results need to be verified and evaluated, which may include re-conducting FMEA to confirm whether the risk has been reduced, and monitoring the performance of the interconnection structure of components to confirm whether the failure events have been reduced or eliminated.

[0088] Ultimately, it can be determined whether the failure cause treatment was successful and whether further improvements are needed, thereby improving the reliability and safety of the interconnection structure of components.

[0089] The failure cause treatment results refer to the results of analyzing and treating the failure causes of the interconnection structure of components, including the evaluation of various potential failure modes, such as fatigue, corrosion, fracture, etc., and the possible causes of these failure modes.

[0090] Step 104 , performing stress simulation on the target interconnection structure of the component based on the shape parameters according to preset environmental load parameters to obtain a stress intensity simulation result.

[0091] In this step, the environmental load parameters describe the various external forces or conditions that components may encounter in the actual working environment, such as temperature changes, mechanical vibrations, electromagnetic fields, pressure, etc. These environmental loads will cause stress on the components, thus affecting their performance and life.

[0092] Based on shape parameters and environmental load parameters, computer simulation technology is used to simulate the stress distribution and strength of components under specific environmental loads. This simulation can help predict the performance of components in actual working environments.

[0093] Stress intensity simulation results refer to the results of stress intensity simulation of the interconnection structure of components, which are used to evaluate the stress level of the interconnection structure under specific conditions (such as temperature change, mechanical load, etc.). These results help to identify potential weaknesses or high-risk areas in the structure and optimize the design accordingly.

[0094] Step 105 , performing processing by a quality analysis algorithm according to the stress intensity simulation result and the failure cause processing result, to obtain a quality determination result of the target interconnection structure of the component.

[0095] In this step, the quality analysis algorithm is used to process and analyze the simulation results and the algorithm for processing the results mentioned above. The purpose of this algorithm is to combine these two aspects of information to evaluate the quality of the interconnection structure of the components. It involves the integration, analysis, comparison and interpretation of data to draw comprehensive conclusions about the quality of the structure.

[0096] The quality determination result of the target interconnect structure may be a qualitative evaluation (such as "qualified", "unqualified", "needs further optimization" or "weak links and failure mechanisms of the interconnect structure") or a quantitative score. It reflects the ability of the interconnect structure to meet the design requirements and usage requirements under given conditions.

[0097] Aims to ensure that the interconnection structure of components meets the expected quality standards during design, manufacturing and use.

[0098] Through the above scheme, through the pre-built failure mode model and fault tree analysis algorithm, the failure mode and cause can be quickly and accurately identified without tedious testing and verification, thus greatly shortening the quality determination cycle. At the same time, based on the stress simulation of shape parameters and environmental load parameters, the stress intensity of the interconnection structure of components in actual applications can be accurately predicted. Combined with the quality analysis algorithm, the quality of the target interconnection structure can be comprehensively evaluated, ensuring the reliability of the interconnection structure of components and significantly reducing the quality determination cost of the interconnection structure.

[0099] In some embodiments, the failure mode model includes a database having failure modes corresponding to different attribute parameters.

[0100] Step 102 includes:

[0101] Based on the attribute parameters, the failure mode corresponding to the attribute parameters is searched from the database, and the failure mode corresponding to the attribute parameters is used as the failure mode analysis result.

[0102] In the above scheme, based on the given attribute parameters, the database is searched for matching or related failure mode information. This process may involve data retrieval, matching and screening to ensure that the most relevant or accurate failure mode with the specific attribute parameters is found.

[0103] The failure mode analysis results are the failure modes corresponding to the given property parameters. This analysis result can be used for various purposes, such as risk assessment, fault prevention, design improvement, etc. Understanding the possible failure modes helps to take measures in advance to reduce or avoid the occurrence of these failures, thereby improving the reliability and safety of the interconnection structure of components.

[0104] In some embodiments, the failure mode model includes a pre-trained convolutional neural network model, and the convolutional neural network model includes a convolution layer, an activation function layer, a pooling layer, and a fully connected layer.

[0105] Step 102 includes:

[0106] Step A1, using the convolution layer to perform convolution feature extraction on the attribute parameters to obtain convolution feature data.

[0107] Step A2, performing nonlinear transformation processing on the convolution feature data through the activation function layer to obtain feature data after nonlinear transformation.

[0108] Step A3, downsampling the feature data after nonlinear transformation through the pooling layer to obtain downsampled feature data.

[0109] Step A4: Determine a failure mode classification result using a fully connected layer based on the downsampled feature data and a preset weight matrix, and use the failure mode classification result as a failure mode analysis result.

[0110] In the above scheme, a convolution layer is used to perform a convolution operation on the input attribute parameters. The convolution layer consists of multiple convolution kernels (or filters), each of which slides on the input data and calculates the dot product to extract local features.

[0111] The result of the convolution operation is a set of convolution feature data, which reflects the feature representation of the input data under different convolution kernels.

[0112] The convolution operation is linear. In order to introduce nonlinear characteristics, the convolution feature data is nonlinearly transformed through the activation function layer.

[0113] Commonly used activation functions include Rectified Linear Unit (ReLU), Sigmoid, and Tanh, etc. These functions can increase the expressive power of the model, allowing the model to learn and simulate more complex nonlinear relationships.

[0114] The feature data that has undergone nonlinear transformation is downsampled through the pooling layer. Pooling operations usually include maximum pooling and average pooling, which reduce the dimension and amount of calculation of the data by selecting the maximum value or average value in the local area.

[0115] The purpose of downsampling is to retain important features while reducing the complexity of the data and improving the robustness and generalization ability of the model.

[0116] The downsampled feature data is passed to the fully connected layer. Each neuron in the fully connected layer is connected to all neurons in the previous layer, and the output is generated by calculating the weighted sum and applying the activation function.

[0117] The fully connected layer determines the failure mode classification result based on the downsampled feature data and the preset weight matrix. The weight matrix is ​​learned through the training process and contains information that maps features to failure mode classification labels.

[0118] Finally, the output of the fully connected layer is interpreted as the classification result of the failure mode, which is output as the result of the failure mode analysis.

[0119] Combining the advantages of convolution operations, nonlinear transformations, downsampling, and fully connected layers, it can efficiently process complex input data and output accurate classification results. In failure mode analysis, it can automatically learn the characteristics of failure modes from a large amount of data and accurately identify new failure modes, thereby improving the reliability and safety of the interconnection structure of components.

[0120] In some embodiments, step 103 includes:

[0121] Step B1, determining a top event of a target interconnect structure of the component based on a failure mode analysis result.

[0122] Step B2, determine the cause of the next layer event that causes the top event in the current layer, and determine the bottom event that causes the cause of the next layer event layer by layer, and determine the logical relationship between the top event, each next layer event cause and the bottom event.

[0123] Step B3, using a descending tree algorithm to determine the occurrence probability of the minimum cut set of the top event, determining a target bottom event from each bottom event based on the occurrence probability of each bottom event, and using the target bottom event as a failure cause processing result.

[0124] In the above scheme, the top event (i.e., top event) in the component interconnection structure that may cause system failure is identified through failure mode analysis. This top event is usually a general description of the system or component not working as expected, such as "interconnection structure failure."

[0125] Next, analyze the direct causes of the top event (i.e., the next level of events). These causes may be design defects, material problems, manufacturing errors, etc.

[0126] Then, continue to analyze downward to identify the deeper causes (i.e., bottom events) that led to these next-level events. This process may involve multiple layers of analysis until the most basic cause is found.

[0127] During the analysis process, it is necessary to clarify the logical relationship between the various events, such as whether it is an "and" (all conditions must be met) or an "or" (any condition can be met) relationship. This helps to understand the cause-effect chain between events.

[0128] The descending tree algorithm is a technique used in fault tree analysis (FTA), which can help identify the minimum cut set that leads to the top event (i.e., the lowest level set of basic events that lead to the top event).

[0129] By calculating the probability of each bottom event and considering the logical relationship between them, the probability of the top event can be calculated.

[0130] Finally, based on the probability of occurrence of the bottom events, the bottom events that are most likely to cause the top events (i.e., target bottom events) are identified. These events are the root causes of system or component failures and should be treated as a priority.

[0131] Once the target events are identified, appropriate measures can be taken to prevent or mitigate the impact of these events, thereby improving the reliability and safety of the system.

[0132] In some embodiments, the failure model analysis results include multiple types of failure modes.

[0133] Step B1 comprises:

[0134] Step C1, determining the occurrence frequency data, impact degree data and detection degree data of each type of failure mode under the attribute parameters.

[0135] Step C2: multiplying the occurrence frequency data, impact degree data and detection degree data of various types of failure modes to obtain risk priority numbers of various types of failure modes.

[0136] Step C3, determining a failure mode of the type with the largest risk priority number from the risk priority numbers corresponding to the multiple types of failure modes, and using the failure mode of the type with the largest risk priority number as the top event of the target interconnection structure of the component.

[0137] In the above scheme, the occurrence frequency data refers to the probability or frequency of a certain failure mode occurring under specific conditions. This is usually determined based on historical data or test data.

[0138] Impact data describes the impact of a failure mode on system performance, safety, reliability, etc. This is usually quantified by assessing the severity of the consequences of the failure.

[0139] Detection data refers to the difficulty of discovering the failure mode through detection methods before or after the failure occurs. The higher the detection, the easier it is to discover and take measures before or at the early stage of failure.

[0140] The Risk Priority Number (RPN) is the product of three parameters: frequency of occurrence data, impact degree data, and detection degree data. The calculation formula is usually: RPN = frequency of occurrence data impact degree data × detection degree data.

[0141] The Risk Priority Number is used to measure the risk level of each failure mode. The higher the RPN value, the greater the risk of the failure mode.

[0142] Among all the failure modes considered, compare their risk priority numbers and find the failure mode with the largest RPN value.

[0143] This failure mode is considered to be the most critical in the interconnection structure of components, the so-called "top event". The top event is a high-risk item that requires special attention in system analysis because it has a significant impact on the overall performance and safety of the system.

[0144] Through this process, potential high-risk failure modes in the component interconnection structure can be systematically identified, thereby guiding subsequent design improvements, test strategies or maintenance plans to improve system reliability and safety.

[0145] In some embodiments, step 104 includes:

[0146] Step D1, constructing a geometric model of a target interconnection structure of the component based on the shape parameters.

[0147] Step D2, meshing the geometric model according to a preset mesh density to generate a finite element mesh.

[0148] Step D3, applying preset environmental load parameters to the finite element mesh, and performing stress simulation on the finite element mesh using a simulation program to obtain a stress intensity simulation result, wherein the simulation program is a software program for stress simulation of a target interconnection structure of components.

[0149] In the above scheme, an accurate geometric model is constructed based on the shape parameters of the target interconnect structure of the components (such as size, shape, material properties, etc.). This geometric model is the basis for subsequent analysis and simulation, and it should accurately reflect the shape and characteristics of the actual structure.

[0150] Finite element analysis (FEA) is a structural analysis method that simplifies the analysis process by dividing complex structures into small, interconnected units (i.e., finite elements). In this step, the previously constructed geometric model needs to be divided according to the preset mesh density to generate a finite element mesh. The choice of mesh density (i.e., the size of each unit) has an important impact on the accuracy of the simulation results and the computational efficiency.

[0151] Apply preset environmental load parameters such as temperature, pressure, gravity, etc. to the finite element mesh according to actual conditions. These load parameters will be used as input conditions for subsequent stress simulation analysis.

[0152] Specialized simulation programs (such as ANSYS Workbench, Abaqus, etc.) are used to perform stress simulation on the previously generated finite element mesh, aiming to predict and analyze the stress state and strength performance of the target interconnection structure of components under specific environmental conditions through computer simulation.

[0153] These simulation programs usually contain complex algorithms and mathematical models that can simulate the stress distribution and strength of the structure under given load conditions. By running the simulation program, stress strength simulation results can be obtained, which can be used to evaluate the strength and durability of the structure and predict potential failure modes.

[0154] In some embodiments, the stress strength simulation results include a stress-strain distribution diagram and a fatigue strength distribution diagram.

[0155] Step 105 includes:

[0156] Step E1, using the stress-strain distribution diagram to determine the stress concentration area and the position of the strain abnormality point of the target interconnection structure of the component.

[0157] Step E2: determining a fatigue strength region having a fatigue strength lower than a preset fatigue strength threshold value based on the fatigue strength distribution map.

[0158] Step E3, determining the failure mechanism of the target interconnection structure of the component according to the failure cause processing result, and combining the stress concentration area, the strain abnormal point position, the fatigue strength area and the failure mechanism to obtain the quality determination result of the target interconnection structure of the component.

[0159] In the above scheme, the stress-strain distribution diagram is a visualization tool that shows the distribution of the target interconnect structure of the component under different stress or strain conditions.

[0160] By analyzing this graph, it is possible to identify areas that experience excessive stress concentrations (i.e., stress values ​​much higher than surrounding areas), as well as strain anomalies (i.e., points where strain values ​​differ significantly from expected or surrounding areas). These areas and points may indicate weaknesses or potential failure points in the structure.

[0161] Next, use the fatigue strength distribution diagram. This diagram shows the fatigue strength of the target interconnect structure of the component at different locations, that is, the ability of the structure to resist fatigue failure under repeated stress or strain.

[0162] By comparing with the preset fatigue strength threshold, it is possible to determine which areas have insufficient fatigue strength, that is, these areas are more likely to suffer fatigue failure due to long-term stress or strain.

[0163] The conclusion drawn after fault analysis or testing of the target interconnect structure of components based on the failure cause processing results is the failure mechanism.

[0164] Failure mechanism refers to the specific physical or chemical process that causes structural failure, such as fracture, corrosion, wear, etc.

[0165] Determining the failure mechanism helps to understand why the structure fails and provides direction for subsequent quality improvements.

[0166] Finally, the stress concentration areas, strain anomaly locations, fatigue strength below threshold areas, and failure mechanisms determined in the above process are combined and processed. The final quality determination result may be a comprehensive score, a risk level, or a series of improvement suggestions to guide subsequent design optimization, production control, or maintenance strategies.

[0167] In some embodiments, first, an analysis of the interconnection structure and process characteristics of components is carried out, and reliability issues such as inherent reliability, process quality, and potential hidden dangers of the interconnection structure are evaluated from the aspects of structure, process, and materials; then, failure cases of interconnection structures of components in the aerospace field and other fields are collected, and a fault tree model of typical failure modes is established in combination with the structural and process characteristics to analyze the causes of failure; finally, based on the structural, process, and material characteristics, a finite element simulation model of the interconnection structure is established to analyze the stress and strain distribution of the interconnection structure under environmental loads, as well as its potential failure modes and failure mechanisms, to form a reliability evaluation method for the interconnection structure. The flow chart of the reliability evaluation (i.e., quality determination) method of the interconnection structure of components proposed in this application is as follows: Figure 2 As shown:

[0168] Step 201, structural and process analysis;

[0169] Step 202: Fault tree analysis;

[0170] Step 203: Finite element simulation.

[0171] Among them, step 201 specifically includes: structural characteristics analysis, manufacturing process analysis and material characteristics analysis; step 202 specifically includes: failure case analysis and fault tree analysis; step 203 specifically includes: three-dimensional model establishment, finite element model establishment and simulation analysis.

[0172] (1) Component interconnection structure and process analysis

[0173] The design, development, and process of typical component interconnection structures are analyzed, and their structural characteristics and manufacturing processes are analyzed. The inherent reliability, process quality, and potential hidden dangers of the interconnection structure are evaluated from the aspects of structure, process, and materials, and the interconnection structure and process analysis methods are formed. Typical interconnection structures include solder joints, pins, leads, TSV, etc. Typical interconnection technologies include wire bonding (Wire Bonding, WB), tape-automated bonding (Tape-automated Bonding, TAB), flip chip (Flip Chip, FC), wafer-level package (Wafer-Level Package, WLP), and through silicon via (Through Silicon Via, TSV). The main key processes of the interconnection structure are analyzed, including the processes and methods of bonding, flip chip welding, capping, and ball planting.

[0174] (2) Fault tree analysis of component interconnection structure

[0175] Collect failure cases of interconnection structures of components used in aerospace and other fields, summarize the stress environment and failure mode of each mission profile during the entire life cycle, and related failure analysis reports and other analysis contents. Combined with the device structure characteristics and process characteristics, analyze the weak links of the interconnection structure, and conduct failure mode and failure mechanism analysis, sort out the logical relationship between the bottom event and the top event, establish a fault tree model of typical failure mode, and conduct failure cause analysis.

[0176] The interconnection structure fault tree reflects the possible failure modes and the causes of these failure modes. The flowchart of establishing the fault tree is as follows: Figure 3 As shown, it includes system analysis, clear top events, establishment of fault tree and qualitative analysis of minimum cut set. First, conduct system analysis, carry out analysis of the design principle, structural performance, application environment and other conditions of the interconnection structure, and conduct extensive research and analysis of its fault diagnosis information; then, select the fault mode with the greatest impact on the interconnection structure as the top event, and find out all the event causes that may cause the top event; then, find out the next layer of event causes that cause each sub-event layer by layer, until the bottom layer event cause (i.e. bottom event) is found; finally, use the fault tree for qualitative analysis to clarify the logical relationship between these events and the top event (if any of cause 1 and cause 2 occurs, it will cause the occurrence of the upper layer event, connected by "or"; if cause 1 and cause 2 occur at the same time, it will cause the occurrence of the upper layer event, connected by "and" logical or gate), determine to build a logical structure diagram that connects events and events, form a structural function, use the descending method to solve the minimum cut set of the fault tree, and clarify the factors that have a greater impact on the reliability of the interconnection structure.

[0177] (3) Reliability simulation of component interconnection structure

[0178] Components contain multi-layer material structures and connection methods. In order to avoid the problem of non-convergence or unnecessary complexity of the model caused by relatively unimportant refined structures in mesh division and simulation calculations, it is necessary to simplify and make assumptions about the geometric model of the components to be evaluated according to the actual situation of the selected components, mainly: ignoring the structure that has a small impact on the model results; ideal connection between materials, no voids or impurities; all materials are isotropic, etc. Then, based on the geometric parameters, a three-dimensional model is established using three-dimensional drawing software (Solidworks).

[0179] The established three-dimensional model is imported into the simulation program (Ansys Workbench) to define material properties and unit properties, mesh division is performed according to analysis requirements, the mesh of the interconnected structure is refined, and mesh quality inspection and independence verification are performed.

[0180] Select the environmental load type and analysis module according to the requirements, apply constraints and environmental loads to the model, calculate the stress-strain distribution and fatigue strength distribution, and the finite element simulation process is as follows: Figure 4 As shown:

[0181] Step 401: Establish a three-dimensional model;

[0182] Step 402: Establish a finite element model;

[0183] Step 403, setting simulation conditions;

[0184] Step 404: solving and post-processing.

[0185] Among them, step 401 specifically includes: structural simplification, setting geometric parameters and establishing a model; step 402 specifically includes: defining material properties and unit types, meshing and independence verification; step 403 specifically includes: selecting load type and analysis module, applying constraints and load conditions; step 404 specifically includes: simulation calculation and outputting calculation results.

[0186] By analyzing the simulation results, the weak links and failure mechanisms of the interconnection structure under the required environmental conditions are analyzed, and a reliability evaluation method for the interconnection structure of components is formed.

[0187] Among them, (1) corresponds to - component interconnection structure and process analysis

[0188] The first step is to select a typical component interconnection structure (which can be a solder joint, lead, pin or TSV, etc.), obtain the structural characteristics and process characteristics of the component interconnection structure (evaluation object), and obtain the geometric parameters, material properties and other data of the evaluation object;

[0189] (2) Corresponding - Component interconnection structure fault tree analysis (qualitative analysis)

[0190] The second step is to summarize the stress environment and failure mode of each mission profile in the whole life cycle according to the failure cases for the selected evaluation objects;

[0191] The third step is to analyze the weak links of the interconnect structure in combination with the structural characteristics and process characteristics, and to carry out failure mode and failure mechanism analysis;

[0192] The fourth step is to determine the top event based on the analysis results of the second and third steps, find out the intermediate events and bottom events layer by layer, determine the logical relationship between the connection events and events, establish a fault tree model of typical failure modes, form a structural function, use the downward method to solve the minimum cut set of the fault tree, identify the factors that have a greater impact on the reliability of the interconnection structure, and obtain the cause of failure;

[0193] (3) Corresponding - Component interconnection structure reliability simulation (simulation analysis)

[0194] The fifth step is to simplify and assume the evaluation object using structural characteristics, and to build a three-dimensional model of the evaluation object using three-dimensional drawing software (Solidworks) based on the geometric parameters obtained in the first step;

[0195] Step 6: Import the three-dimensional model established in step 5 into the simulation program (Ansys Workbench) software, define the material properties and unit properties, divide the mesh according to the analysis requirements, refine the mesh of the interconnected structure, and perform mesh quality inspection and independence verification to obtain the finite element model;

[0196] Step 7. According to the requirements [section stress analyzed in step 2], select the environmental load type and analysis module (temperature load corresponds to thermal analysis module, random vibration load corresponds to random vibration analysis module, mechanical impact load corresponds to structural analysis module), apply constraints and environmental loads to the model established in step 4 (random vibration and mechanical impact must be analyzed modally before this), and calculate the stress-strain distribution and fatigue strength distribution results;

[0197] In the eighth step, the calculation results of the seventh step are analyzed and processed to obtain the weak links and failure mechanisms of the evaluation object, and form the evaluation results of the interconnection structure of the components (ie, the quality determination results of the target interconnection structure of the components).

[0198] In addition, in the first step, a typical component interconnection structure (which can be a solder joint, lead, pin or TSV, etc.) is selected to obtain the structural characteristics and process characteristics of the component interconnection structure (evaluation object) [providing a basis for the failure mode and failure mechanism analysis in the second step and the model simplification in the fifth step], and obtain the geometric parameters, material properties and other data of the evaluation object [input geometric parameters for the establishment of a three-dimensional model in the fifth step, and input material properties for the establishment of a finite element model in the sixth step];

[0199] In the second step, for the selected evaluation object, the stress environment and failure mode of each mission profile throughout the life cycle are summarized based on failure cases [providing input for the selection of environmental loads in the seventh step].

[0200] It should be noted that the method of the embodiment of the present application can be performed by a single device, such as a computer or server. The method of this embodiment can also be applied to a distributed scenario and completed by multiple devices cooperating with each other. In the case of such a distributed scenario, one of the multiple devices can only perform one or more steps in the method of the embodiment of the present application, and the multiple devices will interact with each other to complete the described method.

[0201] It should be noted that the above describes some embodiments of the present application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the above embodiments and still achieve the desired results. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0202] Based on the same inventive concept, corresponding to any of the above-mentioned embodiments and methods, the present application also provides a device for determining the quality of a component interconnection structure.

[0203] refer to Figure 5 , the device for determining the quality of the component interconnection structure comprises:

[0204] The parameter acquisition module 501 is configured to acquire the property parameters and shape parameters of the target interconnection structure of the component;

[0205] The failure mode analysis module 502 is configured to perform failure analysis processing based on the attribute parameters through a pre-built failure mode model to obtain a failure mode analysis result;

[0206] The failure cause processing module 503 is configured to process the failure cause by using a fault tree analysis algorithm according to the failure mode analysis result and determine the failure cause processing result;

[0207] A stress simulation module 504 is configured to perform stress simulation on a target interconnection structure of the component based on the shape parameters according to preset environmental load parameters to obtain a stress intensity simulation result;

[0208] The quality analysis module 505 is configured to process the stress intensity simulation result and the failure cause processing result through a quality analysis algorithm to obtain a quality determination result of the target interconnection structure of the component.

[0209] In some embodiments, the failure mode model includes a database having failure modes corresponding to different attribute parameters;

[0210] The failure mode analysis module 502 is specifically configured as follows:

[0211] Based on the attribute parameters, the failure mode corresponding to the attribute parameters is searched from the database, and the failure mode corresponding to the attribute parameters is used as the failure mode analysis result.

[0212] In some embodiments, the failure mode model includes a pre-trained convolutional neural network model, wherein the convolutional neural network model includes a convolution layer, an activation function layer, a pooling layer, and a fully connected layer;

[0213] The failure mode analysis module 502 is specifically configured as follows:

[0214] Using the convolution layer to perform convolution feature extraction on the attribute parameters to obtain convolution feature data;

[0215] Performing nonlinear transformation processing on the convolution feature data through the activation function layer to obtain feature data after nonlinear transformation;

[0216] Downsampling the feature data after nonlinear transformation through the pooling layer to obtain downsampled feature data;

[0217] A failure mode classification result is determined using a fully connected layer based on the downsampled feature data and a preset weight matrix, and the failure mode classification result is used as a failure mode analysis result.

[0218] In some embodiments, the failure cause processing module 503 includes:

[0219] A top event determination unit, configured to determine a top event of a target interconnect structure of the component based on a failure mode analysis result;

[0220] A logic relationship determination unit is configured to determine the cause of the next layer event that causes the top event at the current layer, and to determine the bottom events that cause the cause of the next layer event layer by layer, and to determine the logic relationship between the top event, each of the next layer event causes and the bottom events;

[0221] The failure cause determination unit is configured to determine the occurrence probability of the minimum cut set of the top event using a descending tree algorithm, determine a target bottom event from each bottom event based on the occurrence probability of each bottom event, and use the target bottom event as a failure cause processing result.

[0222] In some embodiments, the failure model analysis results include multiple types of failure modes;

[0223] The top event determination unit is specifically configured to:

[0224] Determine the occurrence frequency data, impact degree data and detection degree data of each type of failure mode under the attribute parameters;

[0225] The occurrence frequency data, impact degree data and detection degree data of various types of failure modes are multiplied to obtain the risk priority numbers of various types of failure modes;

[0226] The failure mode of the type with the largest risk priority number is determined from the risk priority numbers corresponding to the multiple types of failure modes, and the failure mode of the type with the largest risk priority number is used as the top event of the target interconnection structure of the component.

[0227] In some embodiments, the stress simulation module 504 is specifically configured to:

[0228] Constructing a geometric model of a target interconnection structure of the component based on the shape parameters;

[0229] Mesh the geometric model according to the preset mesh density to generate the finite element mesh;

[0230] Preset environmental load parameters are applied to the finite element mesh, and stress simulation is performed on the finite element mesh using a simulation program to obtain a stress intensity simulation result, wherein the simulation program is a software program for stress simulation of a target interconnection structure of components.

[0231] In some embodiments, the stress strength simulation results include a stress-strain distribution diagram and a fatigue strength distribution diagram;

[0232] The quality analysis module 505 is specifically configured as follows:

[0233] Determine the stress concentration area and strain abnormal point position of the target interconnection structure of the component by using the stress-strain distribution diagram;

[0234] Determining a fatigue strength region having a fatigue strength lower than a preset fatigue strength threshold value based on the fatigue strength distribution map;

[0235] According to the failure cause processing result, the failure mechanism of the target interconnection structure of the component is determined, and the stress concentration area, the strain abnormal point position, the fatigue strength area and the failure mechanism are combined and processed to obtain the quality determination result of the target interconnection structure of the component.

[0236] For the convenience of description, the above device is described in terms of functions divided into various modules. Of course, when implementing the present application, the functions of each module can be implemented in the same or multiple software and / or hardware.

[0237] The device of the above embodiment is used to implement the quality determination method of the corresponding component interconnection structure in any of the above embodiments, and has the beneficial effects of the corresponding method embodiment, which will not be repeated here.

[0238] Based on the same inventive concept, corresponding to any of the above-mentioned embodiments and methods, the present application also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the method for determining the quality of the component interconnection structure described in any of the above embodiments is implemented.

[0239] Figure 6 A more specific schematic diagram of the hardware structure of an electronic device provided in this embodiment is shown, and the device may include: a processor 601, a memory 602, an input / output interface 603, a communication interface 604, and a bus 605. The processor 601, the memory 602, the input / output interface 603, and the communication interface 604 are connected to each other in communication within the device through the bus 605.

[0240] The processor 601 can be implemented by a general-purpose CPU (Central Processing Unit), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of this specification.

[0241] The memory 602 can be implemented in the form of ROM (Read Only Memory), RAM (Random Access Memory), static storage device, dynamic storage device, etc. The memory 602 can store an operating system and other application programs. When the technical solutions provided in the embodiments of this specification are implemented by software or firmware, the relevant program codes are stored in the memory 602 and called and executed by the processor 601.

[0242] The input / output interface 603 is used to connect the input / output module to realize information input and output. The input / output module can be configured in the device as a component (not shown in the figure), or it can be externally connected to the device to provide corresponding functions. The input device can include a keyboard, a mouse, a touch screen, a microphone, various sensors, etc., and the output device can include a display, a speaker, a vibrator, an indicator light, etc.

[0243] The communication interface 604 is used to connect a communication module (not shown) to realize communication interaction between the device and other devices. The communication module can realize communication through a wired mode (such as USB, network cable, etc.) or a wireless mode (such as mobile network, WIFI, Bluetooth, etc.).

[0244] The bus 605 includes a path for transmitting information between various components of the device (eg, the processor 601 , the memory 602 , the input / output interface 603 , and the communication interface 604 ).

[0245] It should be noted that, although the above device only shows the processor 601, the memory 602, the input / output interface 603, the communication interface 604 and the bus 605, in the specific implementation process, the device may also include other components necessary for normal operation. In addition, it can be understood by those skilled in the art that the above device may also only include the components necessary for implementing the embodiments of the present specification, and does not necessarily include all the components shown in the figure.

[0246] The electronic device of the above embodiment is used to implement the quality determination method of the corresponding component interconnection structure in any of the above embodiments, and has the beneficial effects of the corresponding method embodiment, which will not be described in detail here.

[0247] Based on the same inventive concept, corresponding to any of the above-mentioned embodiment methods, the present application also provides a non-transitory computer-readable storage medium, wherein the non-transitory computer-readable storage medium stores computer instructions, and the computer instructions are used to enable the computer to execute the quality determination method of the component interconnection structure as described in any of the above embodiments.

[0248] The computer-readable medium of this embodiment includes permanent and non-permanent, removable and non-removable media, and information storage can be implemented by any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, read-only compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device.

[0249] The computer instructions stored in the storage medium of the above embodiment are used to enable the computer to execute the quality determination method of the component interconnection structure as described in any of the above embodiments, and have the beneficial effects of the corresponding method embodiments, which will not be repeated here.

[0250] A person skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of the present application is limited to these examples. In line with the concept of the present application, the technical features in the above embodiments or different embodiments may be combined, the steps may be implemented in any order, and there are many other variations of the different aspects of the embodiments of the present application as described above, which are not provided in detail for the sake of simplicity.

[0251] In addition, to simplify the description and discussion, and in order not to make the embodiments of the present application difficult to understand, the known power supply / ground connection with the integrated circuit (IC) chip and other components may or may not be shown in the provided drawings. In addition, the device can be shown in the form of a block diagram to avoid making the embodiments of the present application difficult to understand, and this also takes into account the fact that the details of the implementation of these block diagram devices are highly dependent on the platform to be implemented in the embodiments of the present application (that is, these details should be fully within the scope of understanding of those skilled in the art). In the case of elaborating specific details (e.g., circuits) to describe exemplary embodiments of the present application, it is obvious to those skilled in the art that the embodiments of the present application can be implemented without these specific details or when these specific details are changed. Therefore, these descriptions should be considered to be illustrative rather than restrictive.

[0252] Although the present application has been described in conjunction with specific embodiments of the present application, many replacements, modifications and variations of these embodiments will be apparent to those skilled in the art from the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may use the embodiments discussed.

[0253] The embodiments of the present application are intended to cover all such substitutions, modifications and variations that fall within the broad scope of the present application. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present application should be included in the protection scope of the present application.

Claims

1. A method for determining the quality of a component interconnection structure, characterized in that: include: Obtaining attribute parameters and shape parameters of a target interconnect structure of components; Performing failure analysis processing based on the attribute parameters through a pre-built failure mode model to obtain a failure mode analysis result; According to the failure mode analysis result, the failure cause processing is performed by using a fault tree analysis algorithm to determine the failure cause processing result; Based on the shape parameters, a stress simulation is performed on the target interconnection structure of the component according to preset environmental load parameters to obtain a stress intensity simulation result; The stress intensity simulation result and the failure cause processing result are processed by a quality analysis algorithm to obtain a quality determination result of the target interconnection structure of the component.

2. The method according to claim 1, characterized in that The failure mode model includes a database having failure modes corresponding to different attribute parameters; The failure analysis process is performed based on the attribute parameters through a pre-built failure mode model to obtain a failure mode analysis result, including: Based on the attribute parameters, the failure mode corresponding to the attribute parameters is searched from the database, and the failure mode corresponding to the attribute parameters is used as the failure mode analysis result.

3. The method according to claim 1, characterized in that The failure mode model includes a pre-trained convolutional neural network model, wherein the convolutional neural network model includes a convolution layer, an activation function layer, a pooling layer, and a fully connected layer; The failure analysis process is performed based on the attribute parameters through a pre-built failure mode model to obtain a failure mode analysis result, including: Using the convolution layer to perform convolution feature extraction on the attribute parameters to obtain convolution feature data; Performing nonlinear transformation processing on the convolution feature data through the activation function layer to obtain feature data after nonlinear transformation; Downsampling the feature data after nonlinear transformation through the pooling layer to obtain downsampled feature data; A failure mode classification result is determined using a fully connected layer based on the downsampled feature data and a preset weight matrix, and the failure mode classification result is used as a failure mode analysis result.

4. The method according to claim 1, characterized in that: The method of performing failure cause processing by using a fault tree analysis algorithm according to the failure mode analysis result to determine the failure cause processing result includes: Determining a top event of a target interconnect structure of the component based on a failure mode analysis result; Determine the cause of the next layer event that causes the top event at the current layer, and determine the bottom events that cause the cause of the next layer event layer by layer, and determine the logical relationship between the top event, each of the next layer event causes and the bottom events; The occurrence probability of the minimum cut set of the top event is determined by using a descending tree algorithm, a target bottom event is determined from each bottom event based on the occurrence probability of each bottom event, and the target bottom event is used as a failure cause processing result.

5. The method according to claim 4, characterized in that The failure model analysis results include multiple types of failure modes; The step of determining the top event of the target interconnect structure of the component based on the failure mode analysis result comprises: Determine the occurrence frequency data, impact degree data and detection degree data of each type of failure mode under the attribute parameters; The occurrence frequency data, impact degree data and detection degree data of various types of failure modes are multiplied to obtain the risk priority numbers of various types of failure modes; The failure mode of the type with the largest risk priority number is determined from the risk priority numbers corresponding to the multiple types of failure modes, and the failure mode of the type with the largest risk priority number is used as the top event of the target interconnection structure of the component.

6. The method according to claim 1, characterized in that The step of performing stress simulation on the target interconnect structure of the component based on the shape parameter according to the preset environmental load parameter to obtain the stress intensity simulation result includes: Constructing a geometric model of a target interconnection structure of the component based on the shape parameters; Mesh the geometric model according to the preset mesh density to generate the finite element mesh; Preset environmental load parameters are applied to the finite element mesh, and stress simulation is performed on the finite element mesh using a simulation program to obtain a stress intensity simulation result, wherein the simulation program is a software program for stress simulation of a target interconnection structure of components.

7. The method according to claim 1, characterized in that The stress strength simulation results include a stress-strain distribution diagram and a fatigue strength distribution diagram; The step of processing the stress intensity simulation result and the failure cause processing result by a quality analysis algorithm to obtain a quality determination result of a target interconnect structure of the component includes: Determine the stress concentration area and strain abnormal point position of the target interconnection structure of the component by using the stress-strain distribution diagram; Determining a fatigue strength region having a fatigue strength lower than a preset fatigue strength threshold value based on the fatigue strength distribution map; According to the failure cause processing result, the failure mechanism of the target interconnection structure of the component is determined, and the stress concentration area, the strain abnormal point position, the fatigue strength area and the failure mechanism are combined and processed to obtain the quality determination result of the target interconnection structure of the component.

8. A device for determining the quality of a component interconnection structure, characterized in that: include: A parameter acquisition module is configured to acquire attribute parameters and shape parameters of a target interconnection structure of components; A failure mode analysis module is configured to perform failure analysis processing based on the attribute parameters through a pre-built failure mode model to obtain a failure mode analysis result; A failure cause processing module is configured to perform failure cause processing according to the failure mode analysis result by using a fault tree analysis algorithm to determine a failure cause processing result; A stress simulation module is configured to perform stress simulation on a target interconnection structure of the component based on the shape parameters according to preset environmental load parameters to obtain a stress intensity simulation result; The quality analysis module is configured to process the stress intensity simulation result and the failure cause processing result through a quality analysis algorithm to obtain a quality determination result of the target interconnection structure of the component.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and running on the processor, characterized in that: When the processor executes the program, the method according to any one of claims 1 to 7 is implemented.

10. A non-transitory computer-readable storage medium storing computer instructions, characterized in that: The computer instructions are used to enable a computer to execute the method according to any one of claims 1 to 7.

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