Monitor rapid generation system for verification environment

Abstract

The invention relates to the technical field of chip verification, in particular to a monitor rapid generation system for verifying an environment, and the system adds first identification information in an initial monitor component, so that the first identification information and the second interface information of a target interface can be obtained according to the second identification information and the second interface information of the target interface. According to the embodiment of the invention, the initial monitor component is instantiated into the target monitor component corresponding to the target interface, and the monitor components corresponding to the plurality of interfaces can be generated in batches without independently developing the corresponding target monitor component for each interface in an application scene with a large number of interfaces, so that the efficiency of generating the monitor components is improved, and the user experience is improved. In addition, according to the second interface information and the module information, the binding file is generated in a script mode, the efficiency of applying the generated target monitor to the simulation process can be effectively improved, and the chip verification efficiency is also improved.

Description

Technical Field

[0001] The present invention relates to the technical field of chip verification, and in particular to a monitor rapid generation system for a verification environment. Background Art

[0002] In the chip verification scenario, it is necessary to perform white-box inspection on the modules in the chip design. The white-box inspection includes checking whether the output of each interface is the same as the reference value by inputting preset stimuli. In the existing method, the verification personnel are usually required to develop a corresponding monitor component for each interface to sample the output of the corresponding interface.

[0003] However, since module design may involve a large number of interfaces, developing corresponding monitor components for sampling for each interface will bring a huge workload, and the development process of verifiers is prone to errors, resulting in low chip verification efficiency. In addition, monitor components are often difficult to reuse to multiple interfaces, and the inheritance of monitor components is poor.

[0004] Therefore, how to quickly generate monitor components to improve the efficiency of chip verification has become an urgent problem to be solved. Summary of the invention

[0005] In view of the above technical problems, the technical solution adopted by the present invention is: A monitor rapid generation system for verifying an environment, the system comprising: a processor and a memory storing a computer program, when the computer program is executed by the processor, the following steps are implemented: S101, constructing an initial monitor component, wherein the initial monitor component includes N first identification information and first interface information respectively corresponding to the N first identification information, where N is a positive integer.

[0006] S102: Acquire a target interface and second identification information and second interface information corresponding to the target interface.

[0007] S103: instantiate the initial monitor component according to the second identification information and the second interface information to obtain a target monitor component.

[0008] S104, based on the second interface information and the module information of the target module corresponding to the target interface, a binding file corresponding to the target interface is generated using a preset script, and the target monitor component and the binding file are included in the verification environment to support checking of the target interface in the simulation process.

[0009] Compared with the prior art, the present invention has obvious beneficial effects. By means of the above technical solution, the present invention provides a system for quickly generating a monitor for verifying an environment, which can achieve considerable technical advancement and practicality, and has wide industrial utilization value. It has at least the following beneficial effects: The present invention provides a monitor rapid generation system for a verification environment, the system comprising: a processor and a memory storing a computer program, when the computer program is executed by the processor, the following steps are implemented: S101, constructing an initial monitor component, the initial monitor component comprising N first identification information and first interface information respectively corresponding to the N first identification information, N being a positive integer, S102, acquiring a target interface and second identification information and second interface information corresponding to the target interface, S103, instantiating the initial monitor component according to the second identification information and the second interface information to obtain a target monitor component, S104, generating a binding file corresponding to the target interface using a preset script according to the second interface information and module information of a target module corresponding to the target interface, the target monitor component and the binding file being included in a verification environment to support checking the target interface in a simulation process.

[0010] It can be seen that by adding the first identification information to the initial monitor component, the initial monitor component can be instantiated as a target monitor component corresponding to the target interface according to the second identification information and the second interface information of the target interface. In application scenarios with a large number of interfaces, there is no need to develop a corresponding target monitor component for each interface separately, and monitor components corresponding to multiple interfaces can be generated in batches, thereby improving the efficiency of monitor component generation, and then improving the efficiency of chip verification. Moreover, according to the second interface information and module information, the binding file is generated by scripting, which can effectively improve the efficiency of the generated target monitor in the simulation process and also improve the efficiency of chip verification. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0012] Figure 1 A flowchart of a computer program being executed by a processor in a monitor rapid generation system for a verification environment provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0013] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0014] This embodiment provides a system for quickly generating a monitor for verifying an environment. Figure 1 , is a flow chart of a computer program executed by a processor in a monitor rapid generation system for verification environment provided by an embodiment of the present invention, the system comprising: a processor and a memory storing the computer program, when the computer program is executed by the processor, the following steps are implemented: S101, constructing an initial monitor component, wherein the initial monitor component includes N first identification information and first interface information respectively corresponding to the N first identification information, where N is a positive integer; S102, obtaining a target interface and second identification information and second interface information corresponding to the target interface; S103, instantiating the initial monitor component according to the second identification information and the second interface information to obtain a target monitor component; S104, based on the second interface information and the module information of the target module corresponding to the target interface, a binding file corresponding to the target interface is generated using a preset script, and the target monitor component and the binding file are included in the verification environment to support checking of the target interface in the simulation process.

[0015] The verification environment may refer to a comprehensive test system built to ensure the correctness of the chip design, which is designed to verify whether the chip can work according to the expected functional and performance requirements through various stimulus and inspection mechanisms. The verification environment includes a monitor component.

[0016] The initial monitor component can be used to declare virtual interfaces, define queues, define component communications, add monitoring logic, etc. In the present embodiment, the above contents of declaring virtual interfaces, defining queues, defining component communications, and adding monitoring logic can be included in the first interface information, and each first interface information has its corresponding first identification information. The first identification information can be used to distinguish the first interface information of different interfaces, and the first interface information corresponding to different first identification information are usually different.

[0017] The target interface may refer to an interface that needs to be sampled during chip testing. The second identification information may be used to identify the target interface, and the second interface information may be used to point to an actual physical interface.

[0018] In this embodiment, instantiation may refer to creating an instance of a corresponding target monitor component, and a binding file may be used to describe a binding relationship between an instance of a corresponding target interface and its corresponding target module.

[0019] Specifically, the instantiation process of the target monitor component may include defining a monitor class and instantiating the target monitor component in an agent class. In this embodiment, defining the monitor class may correspond to the initial monitor component, including declaring a virtual interface, and instantiating the target monitor component in the agent class includes connecting the virtual interface defined by the monitor class and the virtual interface defined by the agent class, and assigning the target interface to the virtual interface defined by the agent class.

[0020] In a specific implementation, the first identification information includes type information.

[0021] The type information may be used to identify a specific transaction type, event or signal in a verification environment corresponding to the interface.

[0022] In a specific implementation, the first identification information also includes numbering information.

[0023] The number information can be used to distinguish different interfaces under the same type of information.

[0024] In a specific implementation manner, instantiating the initial monitor component according to the second identification information and the second interface information to obtain a target monitor component includes: determining, in the initial monitor component, first identification information corresponding to the second identification information according to the second identification information; The initial monitor component is instantiated according to the first interface information and the second interface information corresponding to the first identification information to obtain the target monitor component.

[0025] The first identification information corresponding to the second identification information may refer to the first identification information that is the same as the second identification information.

[0026] Specifically, the second interface information is assigned to the virtual interface defined by the agent class, and the virtual interface defined by the monitor class corresponding to the first interface information is connected to the target interface, thereby obtaining an instance of the target monitor component.

[0027] In a specific implementation, the preset script uses a perf script.

[0028] The perf script may refer to a script related to the perf tool in the Linux system.

[0029] In a specific implementation, the preset script is included in the simulation process.

[0030] The simulation process may refer to a process of simulating and verifying a target module.

[0031] In a specific implementation, when executing the simulation process, the preset script is called to generate a reference file, and the reference file includes a binding file corresponding to the target interface.

[0032] Among them, when executing the simulation process, calling the preset script can generate a reference file, which can include binding files between various interfaces and corresponding modules. It can be known that the reference file includes the binding file corresponding to the target interface.

[0033] In a specific implementation, the checking the target interface includes: Inputting a preset stimulus into the target module, and obtaining the real value output by the target interface through the target monitor component; The true value is compared with a preset reference value. When the true value is consistent with the reference value, the target interface check is passed; otherwise, the target interface check is failed.

[0034] Among them, the target monitor component can be used to sample the output of the target interface after the preset stimulus is input into the target module, so as to observe the signal changes of the corresponding interface and obtain the true value of the target interface output. The preset stimulus corresponds to the reference value that the target interface should output. Therefore, by comparing the true value and the reference value, the inspection result of the target interface can be determined.

[0035] It can be seen that this embodiment adds the first identification information to the initial monitor component, so that the initial monitor component can be instantiated as a target monitor component corresponding to the target interface according to the second identification information and the second interface information of the target interface. In the application scenario with a large number of interfaces, there is no need to develop a corresponding target monitor component for each interface separately, and monitor components corresponding to multiple interfaces can be generated in batches, thereby improving the efficiency of monitor component generation, and then improving the efficiency of chip verification. Moreover, according to the second interface information and module information, the binding file is generated by scripting, which can effectively improve the efficiency of the generated target monitor in the simulation process and also improve the efficiency of chip verification.

[0036] Although some specific embodiments of the present invention have been described in detail by way of example, it should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present invention. It should also be understood by those skilled in the art that various modifications may be made to the embodiments without departing from the scope and spirit of the present invention. The scope of the present invention is defined by the appended claims.

Claims

1. A monitor rapid generation system for verification environment, characterized in that: The system comprises: a processor and a memory storing a computer program, and when the computer program is executed by the processor, the following steps are implemented: S101, constructing an initial monitor component, wherein the initial monitor component includes N first identification information and first interface information respectively corresponding to the N first identification information, where N is a positive integer; S102, obtaining a target interface and second identification information and second interface information corresponding to the target interface; S103, instantiating the initial monitor component according to the second identification information and the second interface information to obtain a target monitor component; S104, based on the second interface information and the module information of the target module corresponding to the target interface, a binding file corresponding to the target interface is generated using a preset script, and the target monitor component and the binding file are included in the verification environment to support checking of the target interface in the simulation process.

2. The monitor rapid generation system for verification environment according to claim 1, characterized in that: The first identification information includes type information.

3. The monitor rapid generation system for verification environment according to claim 2, characterized in that: The first identification information also includes number information.

4. The monitor rapid generation system for verification environment according to claim 1, characterized in that: The instantiating the initial monitor component according to the second identification information and the second interface information to obtain a target monitor component includes: determining, in the initial monitor component, first identification information corresponding to the second identification information according to the second identification information; The initial monitor component is instantiated according to the first interface information and the second interface information corresponding to the first identification information to obtain the target monitor component.

5. The monitor rapid generation system for verification environment according to claim 1, characterized in that: The preset script adopts the perf script.

6. The monitor rapid generation system for verification environment according to claim 1, characterized in that: The preset script is included in the simulation process.

7. The monitor rapid generation system for verification environment according to claim 6, characterized in that: When executing the simulation process, the preset script is called to generate a reference file, and the reference file includes a binding file corresponding to the target interface.

8. The monitor rapid generation system for verification environment according to claim 1, characterized in that: The checking of the target interface includes: Inputting a preset stimulus into the target module, and obtaining the real value output by the target interface through the target monitor component; The true value is compared with a preset reference value. When the true value is consistent with the reference value, the target interface check is passed; otherwise, the target interface check is failed.

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