Verification method and device of network-on-chip design file, equipment and storage medium

Abstract

In the embodiment of the invention, the excitation component is sent to the reference model unit from the excitation generation unit through the compatible interface, so that the excitation generation unit can interact with the reference model unit through the compatible interface, send the excitation component to the reference model unit, and store the excitation component in a memory area allocated by the reference model unit in the excitation component; the reference model unit does not need to read a pre-written input source file from a hard disk, interaction of the hard disk is reduced, the problem of resource shortage in the development process is relieved, meanwhile, the excitation assembly is sent to the verification unit, and an actual measurement result obtained by the verification unit is compared with a reference result obtained by the reference model unit. According to the network-on-chip design file verification method and device, interaction between the excitation generation unit and the reference model is achieved through the compatible interface, it is avoided that the reference model unit reads data from a hard disk, the problem of resource shortage is solved, and the system performance is improved.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a verification method, device, electronic device and computer-readable storage medium for an on-chip network design file. Background Art

[0002] When verifying multiple components in a Network On Chip (NOC), the routing subsystem in the NOC needs to be verified first.

[0003] The pre-written input source file is read through the reference model unit, and the output reference result is stored. After the actual measured result is obtained by testing the unit to be verified, the reference result is read for offline comparison to finally obtain the comparison result.

[0004] During offline comparison, a large amount of offline file data will be generated, and reading this offline file data during development will cause resource shortage. Summary of the invention

[0005] The embodiments of the present application provide a method, device, electronic device and computer-readable storage medium for verifying an on-chip network design file to solve the problems in the related art.

[0006] In a first aspect, an embodiment of the present application provides a method for verifying an on-chip network design file, the method comprising: In the process of verifying the on-chip network design file by the verification platform, the stimulus component generated by the stimulus generating unit is sent to the verification unit, and the stimulus component is sent to the reference model unit through a compatible interface; the compatible interface is used to realize the data interaction between the stimulus generating unit and the reference model unit; after the stimulus component is transmitted to the reference model unit, it is stored in the memory area allocated for the reference model unit in the memory; Compile and run the stimulus component and the on-chip network design file by the verification unit to obtain a measured result; Compile and run the stimulus component in the memory slice through the reference model unit to obtain a reference result; The measured result is compared with the reference result to obtain a verification result of the on-chip network design file.

[0007] In a second aspect, an embodiment of the present application provides a verification device for an on-chip network design file, the device comprising: The stimulus generation module is used to send the stimulus component generated by the stimulus generation unit to the verification unit during the verification of the on-chip network design file by the verification platform, and send the stimulus component to the reference model unit through a compatible interface; the compatible interface is used to realize the data interaction between the stimulus generation unit and the reference model unit; after the stimulus component is transmitted to the reference model unit, it is stored in the memory area allocated to the reference model unit in the memory; A measurement module, used to compile and run the stimulus component and the on-chip network design file through the verification unit to obtain a measurement result; A reference module, used for compiling and running the stimulus component in the memory slice through the reference model unit to obtain a reference result; The comparison module is used to compare the measured result with the reference result to obtain the verification result of the on-chip network design file.

[0008] In a third aspect, an embodiment of the present application provides an electronic device, comprising a processor and a memory, wherein the memory stores programs or instructions that can be run on the processor, and when the programs or instructions are executed by the processor, the steps of one or more methods described in the embodiments of the present application are implemented.

[0009] In a fourth aspect, an embodiment of the present application provides a readable storage medium. When instructions in the readable storage medium are executed by a processor of an electronic device, the electronic device can execute one or more methods described in the embodiments of the present application.

[0010] In an embodiment of the present application, the stimulus component is sent from the stimulus generating unit to the reference model unit through a compatible interface, so that the stimulus generating unit can interact with the reference model unit through the compatible interface, and the stimulus component is sent to the reference model unit, and the stimulus component is stored in the memory area allocated to the reference model unit, so that the reference model unit does not need to read the pre-written input source file from the hard disk, thereby reducing the interaction of the hard disk and alleviating the problem of resource shortage in the development process. At the same time, the stimulus component is sent to the verification unit, and the actual measured results obtained by the verification unit are compared with the reference results obtained by the reference model unit to obtain the verification results of the on-chip network design file. The present application realizes the interaction between the stimulus generating unit and the reference model through a compatible interface, avoids the reference model unit from reading data from the hard disk, alleviates the problem of resource shortage, enables data to be processed faster, and improves system performance.

[0011] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0013] Figure 1 It is a flowchart of the steps of a method for verifying an on-chip network design file provided in an embodiment of the present application; Figure 2 is a flowchart of the steps of another method for verifying an on-chip network design file provided by an embodiment of the present application; Figure 3 It is a specific step flow chart of an on-chip network design file provided by an embodiment of the present application; Figure 4 is a compatible channel structure diagram provided in an embodiment of the present application; Figure 5 is a schematic diagram of a comparison target field provided in an embodiment of the present application; Figure 6 It is a specific step flow chart of another on-chip network design file provided by an embodiment of the present application; Figure 7 It is a block diagram of a verification device for a network-on-chip design file provided in an embodiment of the present application; Figure 8 is a block diagram of an electronic device provided in an embodiment of the present application; Fig. 9 It is a block diagram of another electronic device according to another embodiment of the present application. DETAILED DESCRIPTION

[0014] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0015] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally a class, and the number of objects is not limited. For example, the first object can be one or more. In addition, the term "and / or" in the specification and claims is used to describe the association relationship of associated objects, indicating that three kinds of relationships can exist, for example, A and / or B can be represented: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the front and back associated objects are a kind of "or" relationship. In the embodiment of the present application, the term "multiple" refers to two or more, and other quantifiers are similar.

[0016] Network on Chip (NoC) is a communication architecture for System on Chip (SoC) that has emerged with the development of integrated circuit technology and the increase in system complexity. It aims to solve the communication problems that arise with the increasing scale of integrated circuits. By drawing on the ideas of traditional computer networks, each functional module on the chip (such as processor core, memory, peripherals, etc.) is used as a network node and connected to an on-chip communication network based on packet switching or circuit switching through a network interface to achieve efficient data transmission between modules. The NoC has the advantages of strong scalability, high communication parallelism, and good flexibility, and can meet the needs of modern complex SoCs for high-performance communication.

[0017] The on-chip network is mainly divided into the routing subsystem, the interface bridge subsystem and the consistency subsystem. For the routing subsystem, routing verification is crucial. It is the key link to ensure the accurate and efficient transmission of data within the on-chip network. Through verification, it can ensure that the routing algorithm operates correctly under different network conditions, allowing data packets to accurately and accurately reach the destination node from the source node, avoiding data loss, mistransmission and excessive transmission delay, thereby ensuring the stable operation and performance of the entire on-chip system.

[0018] In some related technologies, route verification is performed by offline file comparison, and the reference model required for route verification is designed. After determining the routing algorithm, network topology and constraints, the model is established and then debugged and verified to finally obtain a reference model. All input sources are written to a file, and then the written file is read through the reference model to obtain a reference result, which is compared offline with the actual measured result generated by the unit under test to finally obtain a verification result. In the offline comparison process, generating and reading the written file requires frequent interaction with the hard disk, resulting in resource constraints during the development process, and it is difficult to guarantee the timeliness of the reference results and the actual measured results generated in the offline comparison process, making it difficult to ensure the consistency of the network status information of the two results during the generation process, so that the comparison of the execution time required to complete the task is not accurate enough, and routing delay prediction cannot be performed.

[0019] Figure 1 is a flowchart of a method for verifying an on-chip network design file provided by an embodiment of the present application, such as Figure 1 As shown, the method may include: Step 101 , during the process of verifying the on-chip network design file by the verification platform, the stimulus component generated by the stimulus generating unit is sent to the verification unit, and the stimulus component is sent to the reference model unit through the compatible interface.

[0020] Among them, the verification platform is an environment for comprehensive verification of the on-chip network design. It can simulate the operation of the chip in various actual scenarios, check whether the design meets the expected functional and performance requirements, and discover and solve potential problems before the chip is manufactured. The on-chip network design file is a series of documents and codes that describe the on-chip network design. It records the architecture, functions, interfaces, timing and other information of the on-chip network in detail. The on-chip network design file includes the design file for the routing subsystem. The stimulus component is to simulate the actual application scenario. It is used for a series of input signals and data on the on-chip network design file. These input signals and data will cause the verification unit to produce actual measured results. By comparing with the reference results output by the reference model unit, it can be judged whether the verification unit can work normally.

[0021] In some embodiments, the chip verification of the verification platform adopts the Universal Verification Methodology (UVM) framework. UVM is built on the SystemVerilog language, which is a hardware description and verification language for chip design and verification. It combines multiple functions such as hardware description, verification and test platform construction, and is widely used in the field of integrated circuit design and verification. The reference model unit is usually developed using software description languages ​​such as C language or Python language for design flexibility and scalability. Therefore, it is difficult for the stimulus generation unit and the reference model unit of the verification platform using different languages ​​to exchange data.

[0022] In an embodiment of the present application, the stimulus component is sent from the stimulus generating unit to the verification unit, and at the same time, the stimulus generating unit is enabled to interact with the reference model unit through a compatible interface, so that the reference model unit receives the stimulus component sent by the stimulus generating unit without reading the input source file written in advance in the hard disk. After the reference model unit receives the stimulus component, the stimulus component is stored in the memory area allocated to the reference model in the memory, thereby reducing the frequent interaction of the reference model unit with the hard disk and alleviating the problem of resource shortage in the development process.

[0023] For example, the stimulus generation unit is constructed in SystemVerilog language, while the reference model unit is developed in Python language. In order to realize the interaction between the stimulus generation unit and the reference model unit, SystemVerilog can call C or C++ functions through the compatible interface. At the same time, the compatible interface also has an interface that encapsulates Python code into a C or C++ callable form, thereby realizing indirect interaction between SystemVerilog and Python.

[0024] In some embodiments, when sending the stimulus component to the reference model unit and the verification unit, the data of the stimulus component is also bit-packed to integrate multiple independent binary bits into a larger data unit. For example, when performing complex on-chip network design file verification, the single-bit information of multiple stimulus components can be packaged into a byte or word to reduce the resources required for storage and transmission.

[0025] Step 102: compile and run the stimulus component and the on-chip network design file through the verification unit to obtain a measured result.

[0026] The on-chip network design file is a design file designed by determining the on-chip network functions and performances based on information such as usage requirements and application scenarios.

[0027] In the embodiment of the present application, the stimulus component is sent to the verification unit through the stimulus generation unit, and the stimulus component and the on-chip network design file are compiled and run through the verification unit, wherein the stimulus generation unit and the verification unit are developed using the same hardware description language, so data interaction can be completed without a compatible interface, and after the operation is completed, the measured result is generated. By comparing the measured result with the reference result, it is determined whether the verification unit can work normally, and the correctness and reliability of the function of the on-chip network are guaranteed.

[0028] For example, the verification unit includes a 2×2-dimensional on-chip network routing module, whose main function is to determine the direction to which the data packet is forwarded based on the input data packet destination address. The forwarding directions include: east, west, south, and north. The stimulus generation unit generates stimulus components that simulate various data packet destination addresses and sends them to the verification unit. The verification unit executes the stimulus components, and finally obtains the actual measurement result of the verification unit on which direction the data packet is forwarded.

[0029] Step 103: compile and run the stimulus component in the memory slice through the reference model unit to obtain a reference result.

[0030] In an embodiment of the present application, the reference model unit is based on the routing design file, determines the routing algorithm, network topology and constraints, and then establishes the model and debugs and verifies it, so as to ensure the correctness of the reference model unit generation result when the reference model unit is obtained.

[0031] In addition, the reference model unit reads the stimulus components in the memory slice for execution. The memory slice is an area for fast data storage and reading, with extremely high read and write speeds. The reference model unit can directly obtain the stimulus components from here, making this process faster. If the reference model unit needs to read the source file pre-written in the hard disk, it will be a relatively cumbersome and time-consuming process. The read and write speed of the hard disk is much lower than that of the memory. Reading data from the hard disk requires multiple steps such as seek and rotation delay, which will consume a lot of time. Moreover, the I / O operation of the hard disk will also occupy a lot of system resources, resulting in reduced operating efficiency of the entire development environment. During the development process, especially when conducting large-scale on-chip network verification, the hard disk I / O often becomes a performance bottleneck, making system resources extremely tight. The reference model unit directly reads the stimulus components in the memory slice, reducing unnecessary interactions between the reference model unit and the hard disk, allowing the hard disk to use more resources for other important tasks, such as data storage and backup. At the same time, the efficient use of memory also enables the reference model unit to obtain the required stimulus components more quickly, speeding up the execution of the verification process. This approach effectively alleviates the problem of resource shortage during the development process, allowing the entire development system to run more stably and efficiently, and providing a strong guarantee for the smooth implementation of on-chip network verification work.

[0032] Step 104 , comparing the measured result with the reference result to obtain a verification result of the on-chip network design file.

[0033] In an embodiment of the present application, the excitation component is used to apply a series of excitation signals simulating actual application scenarios to the actual circuit corresponding to the on-chip network design file. In this process, various data related to the operation of the on-chip network are collected by monitoring the output port of the verification unit, such as the transmission time, routing path, data content, etc. of the data packet. These measured results truly reflect the behavior of the on-chip network in the actual operating environment, and the reference results are based on a deep understanding of the on-chip network design specifications, using algorithm models or simplified logic to implement the construction of the reference model. The reference results it generates represent the operating status and output data that the on-chip network should present under ideal circumstances. By comparing the measured results and the reference results, the verification results of the on-chip network design file are obtained.

[0034] In some embodiments, the comparison between the measured results and the reference results is completed through the scoreboard, an important verification component. The scoreboard will compare the measured results and the data in the reference results one by one according to pre-defined rules and strategies. The comparison includes not only the consistency of the data values, but also the format, sequence of the data, and the time when the transaction occurs. During the comparison process, the scoreboard will record the differences in detail and mark the possible errors. Finally, based on the comparison results of the scoreboard, the verification of the on-chip network design file is comprehensively judged. If the measured results and the reference results are highly consistent in all key aspects and no obvious differences or errors are found, it can be considered that the on-chip network design file has passed this verification, and its functions and performance basically meet the design requirements. On the contrary, if there are significant differences or a large number of error records, this indicates that the on-chip network design file may have design defects or logical errors, and the design file needs to be thoroughly checked and modified, and then re-verified until the verification results meet expectations.

[0035] In summary, in an embodiment of the present application, the stimulus component is sent from the stimulus generating unit to the reference model unit through a compatible interface, so that the stimulus generating unit can interact with the reference model unit through the compatible interface, and the stimulus component is sent to the reference model unit, and the stimulus component is stored in the memory area allocated to the reference model unit, so that the reference model unit does not need to read the pre-written input source file from the hard disk, thereby reducing the interaction of the hard disk and alleviating the problem of resource shortage in the development process. At the same time, the stimulus component is sent to the verification unit, and the actual measured results obtained by the verification unit are compared with the reference results obtained by the reference model unit to obtain the verification results of the on-chip network design file. The present application realizes the interaction between the stimulus generating unit and the reference model through a compatible interface, avoids the reference model unit from reading data from the hard disk, alleviates the problem of resource shortage, enables data to be processed faster, and improves system performance.

[0036] Figure 2 , is a flowchart of the specific steps of a verification method for an on-chip network design file provided in an embodiment of the present application, such as Figure 2 As shown, the method may include: Step 201 , during the process of the verification platform verifying the on-chip network design file, the stimulus component generated by the stimulus generating unit is sent to the verification unit, and the stimulus component is sent to the reference model unit through a compatible interface.

[0037] This step may specifically refer to the above step 101, which will not be described in detail here.

[0038] Optionally, the compatible interface includes an interactive interface and a compatible channel, and step 201 may specifically include: Sub-step 2011, converting the stimulus component into a target data format matching the compatible channel by calling the interaction interface when sending the stimulus component.

[0039] Sub-step 2012: sending the converted excitation component to the reference model unit via the compatible channel; the compatible channel is used to transmit the data in the target data format to the reference model unit.

[0040] For sub-steps 2011-2012, the stimulus generation unit is constructed using the SystemVerilog language, while the reference model unit is constructed using C or Python. Data interaction between the stimulus generation unit and the reference model unit needs to be achieved through a compatible interface. The compatible interface includes an interactive interface and a compatible channel. Through the interactive interface, the stimulus component is converted into a target data format that matches the compatible channel, and then the converted stimulus component is sent to the reference model unit through the compatible channel to achieve data interaction between the stimulus generation unit and the reference model unit, so that the reference model unit reads the stimulus component received and stored in the memory area, reduces interaction with the hard disk, and alleviates resource pressure in the development process.

[0041] In some embodiments, a direct programming interface (DPI) is used as an interaction interface. DPI is an interface mechanism defined in the SystemVerilog standard, which can realize interaction with external programming languages ​​such as C and C++. By importing and exporting functions and defining data mapping rules, SystemVerilog and external languages ​​can perform function calls and data transfer. The compatible channel is developed in C language, so that the DPI can be used to convert the stimulus component into a target data format that matches the compatible channel.

[0042] In some embodiments, in order to enable data interaction between the stimulus generating unit and the reference model unit, Socket can be used. As a key interface for network programming, Socket can effectively realize the interaction between C and Python programs. Whether it is the TCP (Transmission Control Protocol) protocol that requires a reliable connection, or the UDP (User Datagram Protocol) protocol that pursues efficient transmission, it can use its standard interface to realize data exchange between programs in different languages, meet diverse network communication needs, and play an important role in distributed systems, network services and other fields.

[0043] It should be noted that when the reference model unit is developed using C or C++, data interaction between the stimulus generating unit and the reference model unit can be achieved using only the interaction interface without using a transmission channel to achieve interaction.

[0044] like Figure 3 As shown in the figure, in the chip verification process, the stimulus generation unit is responsible for generating stimulus components for verifying chip functions. In order to ensure that these stimulus components can be accurately received and processed by the reference model unit, the stimulus generation unit will use the interactive interface to adjust the format of the original stimulus components according to the characteristics and requirements of the compatible channel, and convert them into stimulus components in the target data format that is compatible with the compatible channel. After completing the format conversion, the stimulus generation unit will efficiently and stably send the converted stimulus components to the reference model unit through the compatible channel.

[0045] Optionally, sub-step 2012 may specifically include: Sub-step 20121, when the compatible channel receives the converted excitation component, the converted excitation component is stored in an excitation component queue; the excitation component queue is an unbounded queue.

[0046] Sub-step 20122, sending the stimulus component with the highest task order in the stimulus component queue to the reference model unit through the compatible channel.

[0047] For sub-steps 20121-20122, if Figure 4 The figure shows the data processing diagram of the compatible channel. When the compatible channel receives the converted stimulus component, it stores the stimulus component in an unbounded queue. The compatible channel will prioritize the stimulus components in the queue according to the established rules. After the sorting is completed, the stimulus component with the highest task ranking in the queue is accurately and efficiently sent to the reference model unit to ensure the smooth progress of the verification process. By storing the stimulus components that need to interact in an unbounded queue, there is no need to pre-set the maximum capacity of the queue. Elements can be added dynamically according to actual needs. It is highly flexible when storing stimulus components. At the same time, since there is no need to consider the problem of queue being full, it is also simpler in implementation.

[0048] In some embodiments, when the compatible channel receives the converted stimulus component, the stimulus component can be stored in a bounded queue, the maximum capacity of the queue is explicitly limited, and the resource exhaustion problem caused by the unlimited growth of the queue is avoided. At the same time, when the queue is full, the generation or processing of data can be effectively controlled. For example, when the queue is full, the generation of data can be suspended, or the number of processing threads can be increased to ensure the stability of the system.

[0049] Step 202: compile and run the stimulus component and the on-chip network design file through the verification unit to obtain a measured result.

[0050] This step may be specifically referred to as the above step 102, which will not be described in detail here.

[0051] Step 203: compile and run the stimulus component in the memory slice through the reference model unit to obtain a reference result.

[0052] This step may be specifically referred to as the above step 103, which will not be described in detail here.

[0053] Optionally, the routing channel includes a request channel, a response channel, a listening channel, and a transmission channel. Each channel included in the routing channel is allocated with a corresponding memory slice. Step 203 may specifically include: Sub-step 2031, determining the task type of the stimulus component compiled and run by the reference model unit.

[0054] Sub-step 2032, storing the reference result obtained by the reference model unit in one of the request channel, the response channel, the listening channel and the transmission channel according to the task type.

[0055] For sub-steps 2031 and 2032, Figure 3 As shown, the routing channel includes a request channel, a response channel, a listening channel and a transmission channel. Each channel is allocated a corresponding memory slice. When the reference model unit generates a reference result, the task type is determined according to the execution task corresponding to the stimulus component during execution. The task type includes a request type, a response type, a listening type and a transmission type. The reference result is then stored in the memory slice of one of the four channels included in the routing channel according to the task type. It does not need to be stored in the hard disk, which reduces unnecessary interactions between the reference model unit and the hard disk. The efficient use of memory also enables the reference model unit to store reference results more quickly, speeding up the execution speed of the verification process and alleviating the problem of resource shortage during the development process.

[0056] Optionally, the reference result includes a unique comparison target field of the reference result, and sub-step 2032 may specifically include: Sub-step 20321, obtaining the comparison target field and the corresponding task type in the reference result to be stored.

[0057] Sub-step 20322, when no data having the comparison target field is stored in the routing channel matching the task type, a duplicate check pass result is obtained.

[0058] Sub-step 20323, when data having the comparison field is stored in a routing channel matching the task type, canceling the storage of the reference result to be stored.

[0059] Sub-step 20324, in response to the duplicate check passing result, storing the reference result in a routing channel matching the task type.

[0060] For sub-steps 20231 to 20234, the reference results include a comparison target field that indicates that each reference result is unique, such as Figure 5 As shown in the figure, a reference result includes many fields, for example, field 3:0 represents field 0-3. Field 10:4 stores the source ID of the route, field 17:11 stores the target ID of the route, and field 35:18 stores other address information required for the route. Among them, the unique comparison target field is composed of field 3:0, field 10:4 and field 35:18.

[0061] Among them, by obtaining the comparison target field and the corresponding task type, it is possible to find out whether the current comparison target field has been stored in the routing channel of the corresponding task type. Since the comparison target field is unique, the comparison target field can be searched in the current routing channel. When the routing channel stores data with the comparison field, the storage of the reference result to be stored is cancelled. When the routing channel does not store data with the comparison target field, it indicates that the duplicate check has passed, and the reference result is stored in the routing channel matching the task type. The storage of duplicate data in the memory area of ​​the routing channel is avoided, effectively reducing the storage space occupied. Because there is no need to process a large amount of duplicate data, the storage and reading and writing of data can be carried out more efficiently.

[0062] For example, a reference result has a max_width:0 field, and the reference result's source point ID 10:4 field, target ID 17:11 field, and other address information 35:18 fields required for routing are combined to form a unique comparison target field. Reference results with the same comparison target field as the reference result belong to the execution results of the same stimulus component. Therefore, the uniqueness of the stored reference results can be ensured by checking for duplication in the comparison target field and then storing it in the storage channel.

[0063] Step 204: Obtain a comparison target field of the measured result.

[0064] In an embodiment of the present application, the comparison target field of the measured results is composed of three specific parts, namely the 10:4 field, the 17:11 field and the 35:18 field. These fields undertake important data storage functions, which store key information related to routing. Routing information plays a vital role in the network communication and data transmission of the entire chip, and its accuracy directly affects the performance and function of the chip. During the verification process, the reference results are carefully compared with the comparison target fields of the measured results. When the two are exactly the same, the design of the on-chip network achieves the expected effect in terms of routing function.

[0065] Step 205 : According to the routing channel stored corresponding to the type of completed task represented by the reference result, a comparison target field in the reference result in the corresponding stored routing channel is obtained.

[0066] Among them, the task types include request type, response type, listening type and transmission type, and each task type corresponds to a unique routing channel.

[0067] In an embodiment of the present application, by storing the reference results in the memory area of ​​the corresponding routing channel, the interaction between the reference model and the hard disk when storing the reference results is reduced, thereby alleviating the pressure of frequent interaction with the hard disk during the development process. By storing the reference results in the memory area of ​​the routing channel, the reference results are stored more quickly and are easier to read, so that the storage and reading and writing of the reference results can be carried out more efficiently.

[0068] Step 206: When the comparison target field of the reference result contains the comparison target field of the measured result, a comparison success result is obtained.

[0069] In some embodiments, the reference result and the measured result are compared by a comparison unit, such as Figure 3 As shown, the comparison unit obtains the measured result sent by the verification unit, and at the same time obtains the reference result in the corresponding routing channel of the completed task type represented by the reference result, and compares the comparison target fields of the reference result and the measured result, and obtains a successful comparison result when they are consistent.

[0070] It should be noted that when the comparison unit performs a comparison, the 10:4 field representing the source point ID in the comparison target field is replaced with the node ID of the current comparison unit. For example, if the current acquisition node is 0_1_P0, the data content of the original 10:4 field is replaced according to the node ID of 0_1_P0, so that the 10:4 field representing the source ID of the comparison target field of the reference result and the measured result is the source ID of the current comparison unit.

[0071] like Figure 6 The figure shows the flow chart of network-on-chip design file verification, in which the excitation component is sent to the reference model unit and the verification unit at the same time through the excitation sound unit, wherein the excitation component sent to the reference model unit realizes data transmission through a compatible interface, and the reference model unit stores the reference result in the memory area after generating the reference result, and at the same time, after the verification unit generates the measured result, it samples the measured result and sends it to the comparison unit, which compares the sampled measured result through the comparison unit and searches in the memory area where the reference result is stored, and finally obtains the comparison result.

[0072] Optionally, the method further includes: Step 207 : when the measured result is obtained, calculating the first execution time consumed by the verification unit to compile and run the stimulus component and the on-chip network design file.

[0073] In an embodiment of the present application, by calculating the first execution time consumed by the verification unit to compile and run the stimulus component and the on-chip network design file, the actual execution time of the verification unit can be calculated, and since the stimulus generation unit sends the stimulus component to the reference model unit and the verification unit at the same time, the network status of the verification unit when compiling and running the stimulus component and the on-chip network design file is the same as that of the reference model unit, thereby ensuring the timeliness of the first execution time, reducing the impact of external factors on the results when performing routing delay prediction, and improving the accuracy of routing delay prediction.

[0074] Optionally, step 207 may specifically include: Sub-step 2071, recording the first starting time when the verification unit starts to compile and run, and calculating the first execution duration according to the first ending time when the running is completed and the first starting time.

[0075] In the embodiments of the present application, Figure 4 As shown, the first starting time can be recorded on the reference measured result, that is, the max_width+32:max_width+1 field of the measured result, and only the first starting time needs to be recorded. When the first execution duration is needed, the first end time can be obtained by reading the current time, thereby calculating the first execution duration.

[0076] Step 208: When the reference result is obtained, a second execution time consumed by the reference model unit to compile and run the stimulus component is calculated.

[0077] In an embodiment of the present application, the actual execution time of the reference model unit is calculated by calculating the second execution time consumed by the reference model unit to compile and run the stimulus component. Since the stimulus generation unit sends the stimulus components to the reference model unit and the verification unit at the same time, the real-time bandwidth, node load, and link congestion level of the network are similar when the reference result and the measured result are generated, thereby ensuring the timeliness of the reference result and the measured result during comparison, making the network status information of the two results consistent during the generation process, improving the accuracy of the comparison, and obtaining a more accurate routing delay prediction result.

[0078] Optionally, step 208 may specifically include: Sub-step 2081, recording the second starting time when the reference model unit starts to compile and run; and calculating the second execution duration based on the second ending time when the running is completed and the second starting time.

[0079] In an embodiment of the present application, similar to the actual measured results, the second starting time of the reference result can be recorded in the high-order field of the reference result, that is, recorded in the max_width+32:max_width+1 field of the reference result. Similarly, it is only necessary to record the second actual time. When calculating the second execution duration, the second execution duration can be obtained by reading the current time as the second end time.

[0080] Step 209 : when the verification result of the network on chip design file indicates that the verification is successful, the first execution time and the second execution time are compared to obtain a routing delay result.

[0081] In an embodiment of the present application, by comparing the first execution time and the second execution time, the difference in the time spent on running the verification unit and the reference model unit can be obtained, and the routing delay result can be obtained, prompting the tester to find out the cause of the routing delay, thereby ensuring efficient and stable operation of the network.

[0082] For example, in a certain verification, 1,000 stimulus components were sent to the reference model unit and the verification unit at the same time. The reference model unit took 50 milliseconds to run. However, due to the influence of hardware processing speed, network bandwidth limitation and real-time traffic, the verification unit took 80 milliseconds to complete the same task. The difference of 30 milliseconds between the two running times is the delay of this routing task. This delay may be caused by many factors, such as insufficient hardware performance of the verification unit, network congestion, insufficient optimization of routing algorithm, etc. By analyzing this delay, testers can make targeted optimizations, such as upgrading the hardware of the verification unit, adjusting the routing algorithm or optimizing the network topology, so as to improve the routing performance of the network and ensure that data can be transmitted quickly and accurately.

[0083] In summary, in the embodiment of the present application, the stimulus component is sent from the stimulus generation unit to the reference model unit through a compatible interface, so that the stimulus generation unit can interact with the reference model unit through a compatible interface, the stimulus component is sent to the reference model unit, and the stimulus component is stored in the memory area allocated to the reference model unit, so that the reference model unit does not need to read the pre-written input source file from the hard disk, thereby reducing the interaction of the hard disk and alleviating the resource shortage problem in the development process. At the same time, the stimulus component is sent to the verification unit to ensure that the network environment of the reference model unit and the verification unit are consistent when running, and the actual measurement result obtained by the verification unit and the first execution time are consistent with the reference model unit. The result is compared with the second execution time to obtain the verification result of the on-chip network design file and the routing delay result. The routing delay result is used to characterize the cause of the routing delay, and the routing is optimized in a targeted manner to improve the routing performance of the network, ensuring that data can be transmitted quickly and accurately. This application implements the interaction between the stimulus generation unit and the reference model through a compatible interface, avoids the reference model unit from reading data from the hard disk, alleviates the problem of resource shortage, enables data to be processed faster, and improves system performance. In addition, since the stimulus components are sent at the same time, the timeliness of the reference results and the measured results is guaranteed, making the routing delay results more accurate, which is conducive to troubleshooting the causes of routing delays and optimizing them, thereby improving routing quality.

[0084] Figure 7 : is a block diagram of a verification device for an on-chip network design file provided in an embodiment of the present application, the device comprising: The stimulus generation module 301 is used to send the stimulus component generated by the stimulus generation unit to the verification unit during the process of verifying the on-chip network design file on the verification platform, and send the stimulus component to the reference model unit through a compatible interface; the compatible interface is used to realize data interaction between the stimulus generation unit and the reference model unit; after the stimulus component is transmitted to the reference model unit, it is stored in the memory area allocated to the reference model unit in the memory.

[0085] The actual measurement module 302 is used to compile and run the stimulus component and the on-chip network design file through the verification unit to obtain the actual measurement result.

[0086] The reference module 303 is used to compile and run the stimulus component in the memory slice through the reference model unit to obtain a reference result.

[0087] The comparison module 304 is used to compare the measured result with the reference result to obtain a verification result of the on-chip network design file.

[0088] Optionally, the stimulus generation module 301 may specifically include: The interaction submodule is used to convert the stimulus component into a target data format matching the compatible channel by calling the interaction interface when sending the stimulus component.

[0089] The compatible submodule is used to send the converted excitation component to the reference model unit through the compatible channel; the compatible channel is used to transmit the data in the target data format to the reference model unit.

[0090] Optionally, the reference module 303 may specifically include: The identification submodule is used to determine the task type of the stimulus component compiled and run by the reference model unit, and the task type includes a request type, a response type, a listening type and a transmission type.

[0091] The storage submodule is used to store the reference result obtained by the reference model unit in one of the request channel, response channel, listening channel and transmission channel according to the task type; the reference result is stored in the memory area of ​​the corresponding channel.

[0092] Optionally, the storage submodule may specifically include: The acquisition unit is used to obtain the comparison target field and the corresponding task type in the reference result to be stored.

[0093] The duplicate checking unit is used to obtain a duplicate checking pass result when no data having the comparison target field is stored in a routing channel matching the task type.

[0094] A deduplication unit is used to cancel the storage of the reference result to be stored when data with the comparison field is stored in a routing channel matching the task type.

[0095] A storage unit is used to store the reference result in a routing channel matching the task type in response to the duplication check passing result.

[0096] Optionally, the comparison module 304 may specifically include: The measured submodule is used to obtain the comparison target field of the measured result.

[0097] The reference submodule is used to obtain the comparison target field in the reference result in the corresponding stored routing channel according to the routing channel corresponding to the completed task type represented by the reference result; the task type includes request type, response type, listening type and transmission type.

[0098] The comparison submodule is used to obtain a comparison success result when the comparison target field of the reference result contains the comparison target field of the measured result.

[0099] Optionally, the device may further include: The measured duration module is used to calculate the first execution duration consumed by the verification unit to compile and run the stimulus component and the on-chip network design file when the measured result is obtained.

[0100] The reference duration module is used to calculate the second execution duration consumed by the reference model unit to compile and run the stimulus component when the reference result is obtained.

[0101] The delay module is used to compare the first execution time with the second execution time when the verification result of the on-chip network design file indicates that the verification is successful, so as to obtain a routing delay result, wherein the routing delay result is used to reflect the difference in execution time between the measured result and the reference result.

[0102] Optionally, the actual measurement duration module may specifically include: The measured duration submodule records the first starting time when the verification unit starts to compile and run, and calculates the first execution duration based on the first ending time when the running is completed and the first starting time.

[0103] Optionally, the reference duration module may specifically include: The reference duration submodule is used to record the second starting time when the reference model unit starts to compile and run; and calculate the second execution duration based on the second end time when the running is completed and the second starting time.

[0104] Optionally, the compatible submodules may specifically include: The queue unit is used for storing the converted stimulus component in an stimulus component queue when the compatible channel receives the converted stimulus component; the stimulus component queue is an unbounded queue.

[0105] The sending unit is used to send the stimulus component with the highest task order in the stimulus component queue to the reference model unit through the compatible channel.

[0106] In summary, in an embodiment of the present application, the stimulus component is sent from the stimulus generating unit to the reference model unit through a compatible interface, so that the stimulus generating unit can interact with the reference model unit through the compatible interface, and the stimulus component is sent to the reference model unit, and the stimulus component is stored in the memory area allocated to the reference model unit, so that the reference model unit does not need to read the pre-written input source file from the hard disk, thereby reducing the interaction of the hard disk and alleviating the problem of resource shortage in the development process. At the same time, the stimulus component is sent to the verification unit, and the actual measured results obtained by the verification unit are compared with the reference results obtained by the reference model unit to obtain the verification results of the on-chip network design file. The present application realizes the interaction between the stimulus generating unit and the reference model through a compatible interface, avoids the reference model unit from reading data from the hard disk, alleviates the problem of resource shortage, enables data to be processed faster, and improves system performance.

[0107] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0108] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0109] Regarding the device in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0110] An embodiment of the present application provides a data row protection device for a dynamic random access memory, comprising a memory and one or more programs, wherein the one or more programs are stored in the memory and are configured to be executed by one or more processors to include methods for performing one or more of the methods described in the above-mentioned embodiments.

[0111] Figure 8 is a block diagram of an electronic device 600 according to an exemplary embodiment. For example, the electronic device 600 may be a mobile phone, a computer, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, etc.

[0112] Reference Figure 8 , the electronic device 600 may include one or more of the following components: a processing component 602 , a memory 604 , a power component 606 , a multimedia component 608 , an audio component 610 , an input / output (I / O) interface 612 , a sensor component 614 , and a communication component 616 .

[0113] The processing component 602 generally controls the overall operation of the electronic device 600, such as operations associated with display, phone calls, data communications, camera operations, and recording operations. The processing component 602 may include one or more processors 620 to execute instructions to complete all or part of the steps of the above-mentioned method. In addition, the processing component 602 may include one or more modules to facilitate the interaction between the processing component 602 and other components. For example, the processing component 602 may include a multimedia module to facilitate the interaction between the multimedia component 608 and the processing component 602.

[0114] The memory 604 is used to store various types of data to support the operation of the electronic device 600. Examples of such data include instructions for any application or method operating on the electronic device 600, contact data, phone book data, messages, pictures, multimedia, etc. The memory 604 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk.

[0115] The power supply component 606 provides power to the various components of the electronic device 600. The power supply component 606 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to the electronic device 600.

[0116] The multimedia component 608 includes a screen that provides an output interface between the electronic device 600 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touch, slide, and gestures on the touch panel. The touch sensor may not only sense the boundaries of the touch or slide action, but also detect the duration and pressure associated with the touch or slide operation. In some embodiments, the multimedia component 608 includes a front camera and / or a rear camera. When the electronic device 600 is in an operating mode, such as a shooting mode or a multimedia mode, the front camera and / or the rear camera may receive external multimedia data. Each front camera and rear camera may be a fixed optical lens system or have a focal length and optical zoom capability.

[0117] The audio component 610 is used to output and / or input audio signals. For example, the audio component 610 includes a microphone (MIC), and when the electronic device 600 is in an operation mode, such as a call mode, a recording mode, and a voice recognition mode, the microphone is used to receive an external audio signal. The received audio signal can be further stored in the memory 604 or sent via the communication component 616. In some embodiments, the audio component 610 also includes a speaker for outputting audio signals.

[0118] I / O interface 612 provides an interface between processing component 602 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include but are not limited to: a home button, a volume button, a start button, and a lock button.

[0119] The sensor assembly 614 includes one or more sensors for providing various aspects of status assessment for the electronic device 600. For example, the sensor assembly 614 can detect the open / closed state of the electronic device 600, the relative positioning of the components, such as the display and keypad of the electronic device 600, and the sensor assembly 614 can also detect the position change of the electronic device 600 or a component of the electronic device 600, the presence or absence of contact between the user and the electronic device 600, the orientation or acceleration / deceleration of the electronic device 600, and the temperature change of the electronic device 600. The sensor assembly 614 may include a proximity sensor configured to detect the presence of a nearby object without any physical contact. The sensor assembly 614 may also include an optical sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 614 may also include an acceleration sensor, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

[0120] The communication component 616 is used to facilitate wired or wireless communication between the electronic device 600 and other devices. The electronic device 600 can access a wireless network based on a communication standard, such as WiFi, a carrier network (such as 2G, 3G, 4G or 5G), or a combination thereof. In an exemplary embodiment, the communication component 616 receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 616 also includes a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology and other technologies.

[0121] In an exemplary embodiment, the electronic device 600 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to implement the methods provided in the embodiments of the present application.

[0122] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 604 including instructions, and the instructions can be executed by a processor 620 of an electronic device 600 to perform the above method. For example, the non-transitory storage medium can be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, etc.

[0123] Fig. 9 is a block diagram of an electronic device 700 according to an exemplary embodiment. For example, the electronic device 700 may be provided as a server. Fig. 9 The electronic device 700 includes a processing component 722, which further includes one or more processors, and a memory resource represented by a memory 732 for storing instructions that can be executed by the processing component 722, such as an application. The application stored in the memory 732 may include one or more modules, each corresponding to a set of instructions. In addition, the processing component 722 is configured to execute instructions to perform the method provided in the embodiment of the present application.

[0124] The electronic device 700 may also include a power supply component 726 configured to perform power management of the electronic device 700, a wired or wireless network interface 750 configured to connect the electronic device 700 to a network, and an input / output (I / O) interface 758. The electronic device 700 may operate based on an operating system stored in the memory 732, such as Windows Server TM, Mac OS X TM, Unix TM, Linux TM, FreeBSD TM or the like.

[0125] An embodiment of the present application further provides a computer program product, including a computer program, which implements the method described in the above embodiment when executed by a processor.

[0126] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the application disclosed herein. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0127] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A verification method for a network-on-chip design file, characterized in that: The method comprises: In the process of verifying the on-chip network design file by the verification platform, the stimulus component generated by the stimulus generating unit is sent to the verification unit, and the stimulus component is sent to the reference model unit through a compatible interface; the compatible interface is used to realize the data interaction between the stimulus generating unit and the reference model unit; after the stimulus component is transmitted to the reference model unit, it is stored in the memory area allocated for the reference model unit in the memory; Compile and run the stimulus component and the on-chip network design file by the verification unit to obtain a measured result; Compile and run the stimulus component in the memory slice through the reference model unit to obtain a reference result; The measured result is compared with the reference result to obtain a verification result of the on-chip network design file.

2. The method according to claim 1, characterized in that: The compatible interface includes an interactive interface and a compatible channel, and sending the excitation component to the reference model unit through the compatible interface includes: By calling the interaction interface when sending the stimulus component, the stimulus component is converted into a target data format that matches the compatible channel; The converted excitation component is sent to the reference model unit through the compatible channel; the compatible channel is used to transmit the data in the target data format to the reference model unit.

3. The method according to claim 1, characterized in that: The routing channels of the network on chip include a request channel, a response channel, a listening channel and a transmission channel, and each channel included in the routing channel is allocated with a corresponding memory slice area; The step of compiling and running the stimulus component in the memory slice area through the reference model unit to obtain a reference result includes: Determine the task type of the stimulus component compiled and run by the reference model unit, wherein the task type includes a request type, a response type, a listening type, and a transmission type; According to the task type, the reference result obtained by the reference model unit is stored in one of the request channel, the response channel, the listening channel and the transmission channel; the reference result is stored in the memory area of ​​the corresponding channel.

4. The method according to claim 3, characterized in that The reference result includes a unique comparison target field of the reference result, and storing the reference result obtained by the reference model unit according to the task type in one of the request channel, the response channel, the listening channel and the transmission channel includes: Obtaining a comparison target field and a corresponding task type in the reference result to be stored; When no data having the comparison target field is stored in the routing channel matching the task type, a duplicate check pass result is obtained; When data having the comparison target field is stored in a routing channel matching the task type, canceling the storage of the reference result to be stored; In response to the duplication check passing result, the reference result is stored in a routing channel matching the task type.

5. The method according to claim 1, characterized in that The reference result and the measured result include their own corresponding unique comparison target fields, the routing channel of the on-chip network includes a request channel, a response channel, a listening channel and a transmission channel, and the comparison of the measured result and the reference result to obtain the verification result of the on-chip network design file includes: Obtaining a comparison target field of the measured result; According to the routing channel stored corresponding to the completed task type represented by the reference result, obtaining the comparison target field in the reference result in the corresponding stored routing channel; the task type includes request type, response type, listening type and transmission type; When the comparison target field of the reference result contains the comparison target field of the measured result, a comparison success result is obtained.

6. The method according to claim 1, characterized in that The method further comprises: When the measured result is obtained, calculating a first execution time consumed by the verification unit to compile and run the stimulus component and the on-chip network design file; When the reference result is obtained, calculating a second execution time consumed by the reference model unit to compile and run the stimulus component; When the verification result of the on-chip network design file indicates that the verification is successful, the first execution time and the second execution time are compared to obtain a routing delay result, and the routing delay result is used to reflect the difference in execution time between the measured result and the reference result.

7. The method according to claim 6, characterized in that The calculating a first execution time consumed by the verification unit to compile and run the stimulus component and the on-chip network design file includes: Recording a first starting time when the verification unit starts to compile and run, and calculating the first execution duration according to a first ending time when the running is completed and the first starting time; When the reference result is obtained, calculating the second execution time consumed by the reference model unit to compile and run the stimulus component includes: Record the second starting time when the reference model unit starts to compile and run; and calculate the second execution duration according to the second ending time when the running is completed and the second starting time.

8. The method according to claim 2, characterized in that: The step of sending the converted stimulus component to the reference model unit through the compatible channel includes: When the compatible channel receives the converted stimulus component, the converted stimulus component is stored in an stimulus component queue; the stimulus component queue is an unbounded queue; The excitation component with the highest task order in the excitation component queue is sent to the reference model unit through the compatible channel.

9. A verification device for a network-on-chip design file, characterized in that: The device comprises: The stimulus generation module is used to send the stimulus component generated by the stimulus generation unit to the verification unit during the verification of the on-chip network design file by the verification platform, and send the stimulus component to the reference model unit through a compatible interface; the compatible interface is used to realize the data interaction between the stimulus generation unit and the reference model unit; after the stimulus component is transmitted to the reference model unit, it is stored in the memory area allocated for the reference model unit in the memory; A measurement module, used to compile and run the stimulus component and the on-chip network design file through the verification unit to obtain a measurement result; A reference module, used to compile and run the stimulus component in the memory slice through the reference model unit to obtain a reference result; The comparison module is used to compare the measured result with the reference result to obtain the verification result of the on-chip network design file.

10. An electronic device, characterized in that: The method comprises a processor and a memory, wherein the memory stores a program or instruction that can be run on the processor, and when the program or instruction is executed by the processor, the steps of the method according to any one of claims 1 to 8 are implemented.

11. A readable storage medium, characterized in that: When the instructions in the readable storage medium are executed by a processor of an electronic device, the electronic device is enabled to perform the method as claimed in any one of method claims 1 to 8.

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