Data processing method and device and data processing chip

Abstract

The invention discloses a data processing method and device and a data processing chip, and the method comprises the steps: obtaining at least one first target data object containing first target data; the first target data in each first target data object at least comprises all valid data in each first data object corresponding to the target data processing channel; acquiring a second data object corresponding to the first target data object from a second data object set corresponding to the target data processing channel; performing data processing on each piece of first target data in the at least one first target data object and the corresponding second data object; wherein the number of the first target data objects is smaller than the number of the first data objects corresponding to the target data processing channel.

Description

Technical Field

[0001] The present application belongs to the field of artificial intelligence technology, and in particular, relates to a data processing method, device and data processing chip. Background Art

[0002] Neural Networks (NN) are complex network systems formed by a large number of simple processing units (called neurons) that are widely interconnected. At present, in data processing based on neural network models, there are problems such as low computing performance, high resource requirements and low resource utilization. How to solve at least some of these problems has become a technical difficulty in this field. Summary of the invention

[0003] To this end, this application discloses the following technical solutions:

[0004] A data processing method, comprising:

[0005] Acquire at least one first target data object including first target data; the first target data in each first target data object at least includes all valid data in each first data object corresponding to the target data processing channel;

[0006] Acquire a second data object corresponding to the first target data object from a second data object set corresponding to the target data processing channel;

[0007] Performing data processing on each first target data and the corresponding second data object in the at least one first target data object;

[0008] The number of the first target data objects is less than the number of first data objects corresponding to the target data processing channel.

[0009] Optionally, the sparsity of each first target data object is less than a first threshold; the sparsity is used to characterize the proportion of invalid data in the first target data object.

[0010] Optionally, the valid data in the first data object is valid bit data in a binary sequence of the first data object;

[0011] The method for forming the first target data object includes:

[0012] Obtaining a first data object set corresponding to a target data processing channel in the model;

[0013] Based on the same bit positions in the binary sequences of different first data objects, move the valid bit data of the corresponding first data object in the first data object set to the position where the invalid bit data of other first data objects are located, so as to reduce the number of first data objects containing valid bit data;

[0014] The at least one first target data object includes a first data object obtained after the move is completed and at least contains valid bit data; and the other first data objects are first data objects other than the corresponding first data object in the first data object set.

[0015] Optionally, each first target data corresponds to corresponding position information, which is used to indicate the position of a second data object corresponding to the first data object to which the first target data belongs;

[0016] Acquiring a second data object corresponding to the first target data object from a second data object set corresponding to the target data processing channel includes:

[0017] For each first target data in the first target data objects, a second data object in a second data object set corresponding to a corresponding target data processing channel and located at a target position is obtained to obtain a second data object corresponding to the first target data; the second data object corresponding to the first target data object includes the second data object corresponding to each first target data in the first target data object;

[0018] The corresponding target data processing channel and the target position are respectively the data processing channel indicated by the position information of the first target data and the indicated position within the indicated data processing channel.

[0019] Optionally, the performing data processing on each first target data and the corresponding second data object in the at least one first target data object includes:

[0020] According to the number of available hardware processing channels that can be processed in parallel, a corresponding number of first target data objects are allocated to the available hardware processing channels, and the available hardware processing channels are used to perform data processing on the first target data and the corresponding second data objects in each allocated first target data object;

[0021] The first target data at corresponding positions between different first target data objects on the available hardware processing channels are processed in parallel.

[0022] Optionally, the data processing includes multiplication and accumulation operations; the valid data in the first data object is valid bit data in the binary sequence of the first data object;

[0023] The performing data processing on the first target data and the corresponding second data object in each allocated first target data object includes:

[0024] Acquire data at preset starting positions in respective binary sequences corresponding to respective first target data objects assigned as respective current data to be processed; the preset starting positions in the binary sequences corresponding to different first target data objects are the same;

[0025] Obtaining a second data object corresponding to each data to be processed;

[0026] Accumulate the multiplication results of each of the to-be-processed data and the corresponding second data object to obtain a first addition result;

[0027] Shifting the historical accumulation result by one bit to a higher bit, adding the shift result and the first addition result to obtain a second addition result, and updating the historical accumulation result by using the second addition result;

[0028] Obtaining the next bit of the current data to be processed in the binary sequence of each first target data object in a descending manner, updating the current corresponding data to be processed based on the next bit of data, and looping to the step of obtaining the second data object corresponding to each data to be processed until the processing of the data in each binary sequence is completed, and using the latest historical accumulation operation result obtained as the operation result of each assigned first target data object;

[0029] The historical accumulation operation results corresponding to each first target data object allocated each time are initially zero or empty.

[0030] Optionally, the sparsity of the first data object in the first data object set corresponding to the target data processing channel is less than a second threshold; the sparsity is used to characterize the proportion of invalid data in the first data object.

[0031] A data processing device, comprising:

[0032] A first acquisition module is used to acquire at least one first target data object containing first target data; the first target data in each first target data object at least includes all valid data in each first data object corresponding to the target data processing channel;

[0033] A second acquisition module is used to acquire a second data object corresponding to the first target data object from the second data object set corresponding to the target data processing channel.

[0034] A data processing module, used for performing data processing on each first target data and the corresponding second data object in the at least one first target data object;

[0035] The number of the first target data objects is less than the number of first data objects corresponding to the target data processing channel.

[0036] A data processing chip, comprising:

[0037] A data acquisition component is used to acquire data at a preset starting position in each binary sequence corresponding to each allocated first target data object as each current data to be processed; and to acquire a second data object corresponding to each data to be processed; the preset starting positions in the binary sequences corresponding to different first target data objects are the same;

[0038] A first operation component, used for accumulating the multiplication results of each of the to-be-processed data and the corresponding second data object to obtain a first addition result;

[0039] A second operation component is used to shift the historical accumulation operation result by one bit to a higher bit, add the shift result and the first addition operation result to obtain a second addition operation result, and use the second addition operation result to update the historical accumulation operation result;

[0040] Storage component, used to store historical accumulation operation results;

[0041] The data acquisition component is also used to obtain the next bit of the current data to be processed in the binary sequence of each first target data object in a descending manner, update the current corresponding data to be processed based on the next bit of data, and loop to obtain the processing of the second data object corresponding to each data to be processed, until the various components based on the data processing chip complete the processing of the data in the various binary sequences, and use the latest historical cumulative operation results obtained as the operation results of the assigned various first target data objects.

[0042] Optionally, in the data processing chip:

[0043] The first operation component comprises a first addition operation unit for accumulating a multiplication result of each of the to-be-processed data and the corresponding second data object to obtain a first addition operation result;

[0044] The second operation component includes a shift unit for shifting the historical accumulated operation result to a higher position by one bit, and a second addition operation unit for accumulating the shift result of the shifter with the corresponding first addition operation result to obtain a second addition operation result;

[0045] The storage component includes a register unit for storing historical accumulation operation results;

[0046] The number of the first adding unit, the second adding unit, the shifting unit and the registering unit is one respectively.

[0047] It can be seen from the above scheme that the present application discloses a data processing method, an apparatus and a data processing chip, wherein the data processing method includes: obtaining at least one first target data object containing first target data; the first target data in each first target data object includes at least all valid data in each first data object corresponding to the target data processing channel; obtaining the second data object corresponding to the first target data object from the second data object set corresponding to the target data processing channel; performing data processing on each first target data and the corresponding second data object in the at least one first target data object; wherein the number of the first target data objects is less than the number of the first data objects corresponding to the target data processing channel. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are merely embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0049] Figure 1 It is a system architecture diagram of a two-way hardware module parallel system provided by this application;

[0050] Figure 2 It is a schematic diagram of the binary sequence corresponding to each weight in the 3*3 weight matrix provided in this application;

[0051] Figure 3 It is a flowchart of the data processing method provided by this application;

[0052] Figure 4(a)-Figure 4(b) This is an example diagram of performing effective bit data shift aggregation between weights included in a weight matrix corresponding to an input channel provided by the present application;

[0053] Figure 5 This is an example diagram of the relevant information of the target weight obtained after the move is completed provided by this application;

[0054] Figure 6 It is a composition structure diagram of a multi-channel parallel system in the known technology;

[0055] Figure 7 It is a composition structure diagram of the multi-channel parallel system provided by this application;

[0056] Figure 8It is a structural diagram of the left-shift one bit shifter provided by the present application;

[0057] Fig. 9 It is a structural diagram of the data processing device provided by the present application;

[0058] Fig.10 It is a composition structure diagram of the data processing chip provided by this application. DETAILED DESCRIPTION

[0059] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0060] In data processing based on neural network models, known technologies have problems such as low computing performance, high resource requirements and low resource utilization.

[0061] In order to solve at least some of the technical problems in the known technologies, the embodiments of the present application disclose a data processing method, an apparatus and a data processing chip. The disclosed data processing method can be applied to but not limited to electronic devices such as personal computers or servers.

[0062] In the neural network model, the network channels of the model network layer include input channels and output channels. One output channel corresponds to multiple input channels, and each input channel corresponds to a corresponding convolution kernel weight matrix, referred to as the "weight matrix". Accumulating the calculation results of the weight matrices on each input channel corresponding to the same output channel and the corresponding eigenvalues ​​in the corresponding input feature map will generate an output eigenvalue of the output channel, and each output eigenvalue forms the output feature map of the output channel.

[0063] In neural network models such as deep neural networks, due to pruning and quantization operations, some bits in the weights of the model network layer Kernel will be 0, or even the entire weight will be 0 (specifically, some bits in the binary sequence of the weights will be 0, or even all bits in the entire binary sequence will be 0). According to statistics, the proportion of 0-valued bits in weights in mainstream networks can reach more than 70%. However, the applicant found that the main operations in the neural network model are multiplication and addition operations, and the value of 0 does not contribute to either multiplication or addition operations. Therefore, the 0-valued bit of the weight is an invalid bit that does not contribute to the operation. Based on this, the embodiment of the present application improves the resource utilization and computing efficiency of the system by converting the weights into a binary sequence and discarding at least some of the 0-valued bits, i.e., invalid bits, in the binary sequence of the weights.

[0064] The network layer of the neural network model needs to perform multiplication and accumulation operations on the weights in the weight matrix on each input channel corresponding to the output channel and the corresponding eigenvalues ​​in the corresponding input feature map to generate the output eigenvalue of the output channel, and then form the corresponding output feature map based on the generated output eigenvalues.

[0065] In practical applications, the multiplication operation between weights and eigenvalues ​​can be converted into a shift operation based on the bit value in the weight binary sequence to shift the eigenvalue. Figure 1 The two-way hardware module parallel system shown in the figure has two or more shift modules to process multiple weights in parallel. Correspondingly, a multi-way parallel architecture formed by multiple shift modules can be used to perform shift-based multiplication operations on different weights and corresponding eigenvalues ​​in parallel, and accumulate the operation results of each path. The applicant found that when the 0-valued bits, i.e., invalid bits, in the binary sequence of weights are discarded and each weight is processed in parallel based on a parallel system, the amount of data processed by each parallel shift module is often different due to the different number of valid bits of different weights. The weight with the most valid bits will become the critical path of the system. In actual applications, there is often a situation where the critical path length is much longer than the other path lengths, and due to the limitation of the parallel capability of the parallel system, multiple rounds of processing are often required for each weight, resulting in low utilization of system resources and low processing efficiency.

[0066] See also Figure 2 The example specifically provides the binary sequence corresponding to each weight in the 3*3 weight matrix. In this example, each weight is 8-bit data. The specific situation of valid bits and invalid bits in the binary sequence of each weight is as follows Figure 2 As shown, in the use of Figure 1 When the two-way hardware module parallel system shown in the figure processes it, the 9 weights in the 3*3 weight matrix are distributed to the two hardware modules for processing in multiple rounds in a fixed order. Two weights are processed in each round, and the 9 weights are processed in five rounds. The total processing time of the system is the sum of the processing time of each round: 3+3+6+5+5=22. The number of valid bits in the binary sequence of different weights is different. In some rounds of processing, the critical path length is much larger than the length of other paths, resulting in low resource utilization of the two hardware modules and a large number of execution rounds, which further affects the processing efficiency.

[0067] In order to address the problem of low hardware resource utilization and low computing efficiency caused by the different numbers of valid bits between bit-sparse network weights, the embodiment of the present application proposes a technical idea of ​​reducing the number of weights by shifting and clustering the valid bits of different weights in the input channel weight matrix to compress and eliminate the invalid bits, thereby improving the hardware resource utilization and the system computing efficiency accordingly.

[0068] See also Figure 3 The data processing method flow chart shown in the figure, the data processing method provided by the embodiment of the present application includes the following processing steps:

[0069] Step 301: Acquire at least one first target data object containing first target data; the first target data in each first target data object at least includes all valid data in each first data object corresponding to a target data processing channel.

[0070] The method provided in this application can be applied to, but is not limited to, various fields such as natural language processing, image processing, video processing, speech recognition, industrial detection (such as equipment defect detection), etc.

[0071] The embodiments of the present application mainly take the data processing of a neural network model (such as a deep neural network model) as an example to illustrate the solution.

[0072] The target data processing channel may include but is not limited to one or more input channels of the network layer of the neural network model. For example, for image processing based on the neural network model, the target data processing channel may specifically include any one or more input channels of the R, G, and B primary color input channels of the model convolution layer and the texture input channel and semantic input channel.

[0073] When the target data processing channel includes multiple input channels, the multiple input channels included are specifically multiple input channels corresponding to the same output channel in the model network layer.

[0074] The valid data in the first data object refers to the data contained in the first data object that has contribution value to the data processing of the first data object, while the data contained in the first data object that does not have contribution value to the data processing can be regarded as non-valid data or invalid data of the first data object.

[0075] For the data processing scenario of the neural network model, the first data object can specifically be the weight in the convolution kernel weight matrix corresponding to the corresponding input channel of the network layer of the neural network model. The valid data in the first data object can be the valid bit data in the binary sequence of the weight, that is, the valid bit data "1", and the invalid bit data "0" in the binary sequence of the weight corresponds to the invalid data in the first data object.

[0076] The number of first target data objects is less than the number of first data objects corresponding to the target data processing channel. Optionally, the sparsity of each first target data object is less than a first threshold; the sparsity is used to characterize the proportion of invalid data in the first target data object.

[0077] For the data processing scenario of the neural network model, the first target data object is the above-mentioned technical idea of ​​shifting and aggregating valid bit data (valid bit) proposed in this application, by shifting and aggregating the valid bit data of different weights in the weight matrix of the input channel, and compressing and reducing the invalid bit data (invalid bit), and obtaining the weights that have completed compression and contain at least valid bit data. Among them, the shift aggregation performed refers to shifting the valid bit data in the weight, that is, the valid bit, across the weight, and specifically shifting the valid bit data from its source weight across the weight to the corresponding invalid bit data in the binary sequence of the corresponding destination weight, so that the valid bit data in each weight is aggregated and at least part of the invalid bit data is compressed, thereby achieving the effect of reducing the number of valid weights containing valid bit data.

[0078] In practical applications, the shifting and aggregation of valid bit data can be performed between the weights included in the weight matrix corresponding to one input channel, or between the weights included in multiple weight matrices corresponding to multiple input channels. There is no limitation on this, and it can be determined according to actual needs. The multiple input channels are multiple input channels corresponding to the same output channel.

[0079] See also Figure 4(a)-Figure 4(b) , provides an example of shifting and aggregating valid bit data between each weight contained in the weight matrix corresponding to an input channel. In this example, the binary sequences corresponding to the 9 weights in the 3*3 weight matrix are shown in Figure 4(a). After the binary sequences of each weight in Figure 4(a) are shifted and aggregating valid bits across weights, the number of weights is reduced from 9 to 4 (because all bits in the corresponding binary sequence are 0 weights, they do not contribute to data operations, so they can be regarded as invalid weights and discarded). It is easy to understand that in this example, the first data object is the weight represented by each binary sequence in Figure 4(a), and the number of first data objects is 9. The first target data object is the weight represented by each binary sequence that contains at least a valid bit in Figure 4(b). The embodiment of the present application refers to it as the target weight, and its number is 4. The data of each bit in the first target data object is the first target data, which may be valid bit data "1" or invalid bit data "0".

[0080] When the effective bit data is shifted across weights, the bit positions corresponding to the effective bit data in the binary sequence of the weights before and after the shift can be the same or different, without limitation. For example, for a certain effective bit "1", the corresponding bit positions in the binary sequence of the weights before and after the shift are both 3 (assuming that the positions of each bit in the 8-bit binary sequence are 8, 7, 6, ..., 1 from high to low), or the corresponding bit positions in the binary sequence of the weights before and after the shift are 3 and 5.

[0081] Step 302: Acquire a second data object corresponding to the first target data object from a second data object set corresponding to the target data processing channel.

[0082] Each first target data corresponds to corresponding position information, which is used to indicate the position of the second data object corresponding to the first data object to which the first target data belongs.

[0083] In this step, for each first target data in the first target data object, the second data object at the target position in the second data object set corresponding to the corresponding target data processing channel can be specifically obtained to obtain the second data object corresponding to the first target data; the second data object corresponding to the first target data object includes the second data objects corresponding to each first target data in the first target data object.

[0084] The corresponding target data processing channel and the target position are respectively the data processing channel indicated by the position information of the first target data and the indicated position within the indicated data processing channel.

[0085] Furthermore, the location information corresponding to each first target data may include the object identifier of the first data object to which the first target data belongs and the channel identifier of the target data processing channel corresponding to the first data object. Optionally, if the target data processing channel includes only one input channel, that is, only the shift aggregation of valid bit data is performed between the weights included in the weight matrix corresponding to the one input channel, the channel identifier in the location information corresponding to the first target data may be empty, or the information item of the channel identifier may not be set, and the target data processing channel corresponding to the first data object to which the first target data belongs is assumed to be the one input channel that participates in the data shift aggregation.

[0086] Therefore, the corresponding target data processing channel mentioned above is specifically the data processing channel indicated by the channel identifier in the location information of the first target data, or the corresponding data processing channel that participates in the data movement aggregation by default; the target position is specifically the position indicated by the object identifier in the location information corresponding to the first target data in the corresponding target data processing channel.

[0087] Exemplarily, still taking the data processing scenario of the neural network model as an example, the second data object set corresponding to the target data processing channel is specifically the feature map corresponding to the input channel, and the second data object is the feature value in the feature map corresponding to the input channel.

[0088] After shifting and clustering the valid bit data in the weight, optionally, the present application simultaneously records the corresponding position information for each bit (first target data) in the obtained target weight (first target data object), and the position information includes a weight ID (Weight ID) and a channel ID, which are respectively used to indicate the position of the original weight to which the bit belongs in the weight matrix (such as the position in the 3*3 weight matrix), and the input channel corresponding to the original weight. Thus, for each bit in the target weight, the feature value corresponding to the weight ID in the position information of the bit in the feature map of the channel (input channel) indicated by the channel ID in its position information can be obtained as the second data object corresponding to the bit.

[0089] It is worth noting that if the bit positions corresponding to the valid bit data in the respective weights change before and after the valid bit data is shifted across weights, it is also necessary to record the bit position information corresponding to the first data object (such as the original weight) in the binary sequence of the valid bit data that has been shifted in the first target data contained in the first target data object, so that when the shift-based multiplication operation is performed on the valid bit data and its corresponding eigenvalue in the subsequent process, the shift processing can be performed correctly based on the recorded bit position information. For the first target data that has not been moved in the first target data object, the corresponding bit position information can be recorded or not. In the case of not recording, the subsequent shift-based multiplication operation is directly performed according to the corresponding bit position in the binary sequence of the first target data object.

[0090] Among them, the feature map can be but not limited to various types of data such as images and voices. The neural network model can specifically perform one-dimensional convolution, two-dimensional convolution or three-dimensional convolution on the feature map, without limitation, depending on actual needs. For example, for a one-dimensional convolution kernel of size 1*3, a one-dimensional convolution can be performed on a 1*3 feature map based on a 1*3 weight matrix, and for a two-dimensional convolution kernel of size 3*3, a two-dimensional convolution can be performed on a 3*3 feature map based on a 3*3 weight matrix.

[0091] Step 303: Perform data processing on each first target data and the corresponding second data object in the at least one first target data object.

[0092] After obtaining the second data object corresponding to the first target data in the first target data object, optionally, a multi-channel hardware module parallel system can be used to perform data processing on each first target data and the corresponding second data object in the at least one first target data object in a parallel manner. Each hardware module in the multi-channel hardware module parallel system can be regarded as a hardware processing channel of the parallel system, such as Figure 1The two-way hardware module parallel system includes two hardware processing channels.

[0093] In this step, the corresponding number of first target data objects can be allocated to the available hardware processing channels according to the number of available hardware processing channels that can be processed in parallel in the above parallel system, and the first target data and the corresponding second data objects in each allocated first target data object can be processed using the available hardware processing channels. Optionally, the data processing performed can include multiplication and accumulation processing, that is, firstly performing a shift-based multiplication operation on each first target data and its corresponding second data object, and then accumulating the multiplication operation results corresponding to each first target data, but it is not limited to this. In actual applications, the data processing performed can be determined according to the actual application requirements.

[0094] The first target data at corresponding positions between different first target data objects on the available hardware processing channels are processed in parallel.

[0095] For example, for the four target weights (i.e., four first target data objects) in FIG4(b), assuming that Figure 1 The two-way hardware module parallel system shown in the figure processes it. Since the system has two available hardware processing channels for parallel processing, the compressed four target weights are processed in two rounds, and two target weights are assigned to the parallel system in each round. The processing time of the first round is 8, the processing time of the second round is 7, and the total processing time is 15. Compared with the uncompressed aggregation method, the system processing time is reduced from 22 to 15, thereby improving the hardware utilization of the system, reducing the processing time, and improving the processing efficiency.

[0096] In the neural network model, the weight information corresponding to the input channel of each network layer is known after the network training is completed. In practical applications, software can be used to perform the effective bit shifting and aggregation processing proposed in the embodiment of the present application on the weights of the input channels of each network layer of the model through software, so as to squeeze out at least part of the invalid bits in each weight and reduce the number of effective weights.

[0097] To summarize, the embodiment of the present application moves and aggregates the valid data in each first data object corresponding to the target data processing channel to form at least one first target data object, thereby achieving data compression of the first data object, discarding at least part of the invalid data contained therein, and reducing the number of first data objects containing valid data (such as valid weights), thereby reducing the workload of data processing, reducing the storage space and transmission bandwidth requirements, improving system resource utilization, and improving the data processing efficiency of the system.

[0098] In an optional embodiment, when the first target data object is formed by the shift aggregation method proposed in the present application, the method for forming the first target data object can be specifically implemented as the following processing process:

[0099] 11) Obtain a first data object set corresponding to a target data processing channel in the model.

[0100] Optionally, the model may specifically be a neural network model.

[0101] For the data processing scenario of the neural network model, the convolution kernel weight matrix corresponding to one or more input channels of the model network layer can be obtained as the first data object set corresponding to the target data processing channel. Each weight in the weight matrix is ​​regarded as a first data object.

[0102] 12) based on the same bit positions in the binary sequences of different first data objects, move the valid bit data of the corresponding first data object in the first data object set to the position where the invalid bit data of other first data objects are located, so as to reduce the number of first data objects containing valid bit data;

[0103] The at least one first target data object includes a first data object obtained after the move is completed and at least contains valid bit data; and the other first data objects are first data objects other than the corresponding first data object in the first data object set.

[0104] In this embodiment, each first data object is represented as a corresponding binary sequence, and preferably, the valid bit data is moved and aggregated across the first data objects (such as across weights) without changing the bit position corresponding to the valid bit data in the binary sequence. Taking the moving aggregation of the valid bits in the weights as an example, the valid bit with bit position 3 will only move between the 3rd bit positions of different weights.

[0105] Since the moving and aggregation of valid bit data does not change the bit position of the valid bit data in the binary sequence, there is no need to store the bit position information of the first target data in the first target data object obtained after compression. It is only necessary to store the object identifier and channel identifier corresponding to the first target data in each first target data object to indicate the first data object to which each first target data belongs, and the data processing channel corresponding to the first data object. Optionally, if the valid bit data is moved only between the first data objects corresponding to a target data processing channel (such as the weights corresponding to an input channel), the channel identifier can be empty, that is, the channel identifier is not recorded, and the data processing channel corresponding to the first data object to which each first target data in the first target data object belongs is assumed to be the one target data processing channel currently participating in the data moving and aggregation.

[0106] Figure 4(a)-Figure 4(b) The example of can also be used as an example of moving and gathering valid bit data without changing the bit position corresponding to the valid bit data in this embodiment, wherein the arrow symbol represents the move operation on the bit data, the bit corresponding to the tail position of the arrow of the symbol is the bit to be moved, and the position indicated by the arrow is the target position to which the bit to be moved is to be moved. According to 4(a)-Figure 4(b), each valid bit in the binary sequence corresponding to weights 7-9 is moved to the same bit position of the binary sequence of the corresponding weight in weights 1-5 based on the method of this embodiment. For example: the valid bit data at the 8th bit position in the binary sequence of weight 8 is moved to the 8th bit position in the binary sequence of weight 2; the valid bit data at the 1st bit position in the binary sequence of weight 9 is moved to the 1st bit position in the binary sequence of weight 4.

[0107] Accordingly, since the moving aggregation of valid bit data does not change the bit position of the valid bit data in the binary sequence, there is no need to store the bit position information in the target weight (first target data object) obtained after compression. It is only necessary to store the weight ID and channel ID corresponding to each bit data in each target weight after compression, so as to indicate the original weight to which each bit data belongs, and the input channel corresponding to the original weight. Optionally, if the bit data is moved only between the weights of the weight matrix corresponding to one input channel, the channel ID can be empty, and the input channel corresponding to the original weight to which each bit data in the target weight belongs is the input channel currently participating in the data moving aggregation.

[0108] In addition, in practical applications, the number of valid bits contained in each target weight can also be stored, see Figure 5 The example provides the number of valid bits respectively contained in the target weight 2 and the target weight 3 obtained after the move, the valid bits in the corresponding binary sequences, and the weight ID (Weight ID) corresponding to each valid bit.

[0109] This embodiment achieves data compression of the first data object by moving and aggregating the valid data in each first data object corresponding to the target data processing channel, thereby improving the utilization rate of system resources and the data processing efficiency of the system. At the same time, this embodiment moves and aggregates the valid bit data across the first data object without changing the bit position corresponding to the valid bit data, which can facilitate the subsequent direct multiplication operation based on the shift on the first target data and its corresponding second data object based on the bit position of the first target data in the first target data object.

[0110] In an optional embodiment, data processing is performed on the first target data and the corresponding second data object in each allocated first target data object on the corresponding available hardware processing channel, which may be further implemented as follows:

[0111] 21) Acquire data at preset starting positions in respective binary sequences corresponding to respective first target data objects allocated as respective current data to be processed; the preset starting positions in the binary sequences corresponding to different first target data objects are the same.

[0112] Optionally, the data at the preset starting position in each binary sequence corresponding to each first target data object may be the highest-order data in each binary sequence corresponding to each first target data object, that is, the first-order data in the bit sequence from high to low.

[0113] However, the data at the preset starting position in each binary sequence corresponding to each first target data object may also be the data at the position where valid bit data first appears in the bit sequence from high to low in each binary sequence corresponding to each first target data object, that is, the most significant bit. For example, assuming that there are two first target data objects, for the bit sequence from high to low, the binary sequence of the first first target data object begins to appear valid bits from the third bit, and the binary sequence of the second first target data object begins to appear valid bits from the second bit, then the preset starting position may be the second bit position in the bit sequence from high to low of each binary sequence of the two first target data objects. In this embodiment, the processing of the data before the starting position in the binary sequence of each first target data object is skipped. Since the skipped data is invalid bit data, it does not affect the final processing result of each first target data object, and the correctness of the final processing result can be guaranteed.

[0114] In this embodiment, for each allocated first target data object, starting from the preset starting position, the data in each binary sequence corresponding to each first target data object is read in descending order (from high to low order), and each data read each time is the data of the same bit position in different binary sequences corresponding to each first target data object, which is specifically 0 or 1, depending on the actual value of each first target data object. For example, starting from the highest bit, the bit data in the binary sequence of each target weight obtained after compression is read in sequence, and for each target weight, the data read at the same time is the data of the same bit position in different binary sequences corresponding to each target weight, and the read data is used as the current data to be processed.

[0115] 22) Obtain the second data object corresponding to each data to be processed.

[0116] Among them, the second data object corresponding to the data to be processed can be read according to the position information corresponding to each data to be processed. For example, for each bit of data read as the current data to be processed, according to its corresponding WeightID, the feature value corresponding to the Weight ID is read from the feature map corresponding to the current input channel (assuming that there is only one target data processing channel, namely the current input channel) as the feature value corresponding to the bit of data.

[0117] In practical applications, a multi-channel parallel system can determine the second data object corresponding to the data to be processed based on the position information corresponding to the data to be processed so as to read it; or it can be based on software, using software to determine the second data object corresponding to the data to be processed in advance based on the position information corresponding to the data to be processed, and store it to a specified location, and the available hardware processing channels in the subsequent parallel system can directly read the required second data object from the specified location.

[0118] Since each data to be processed is 0 or 1, the multiplication result of 1 and its corresponding second data object (such as the corresponding eigenvalue) is the second data object, and the multiplication result of 0 and its corresponding second data object is 0. Therefore, for the data to be processed with a value of 1, the corresponding second data object can be directly read as the multiplication result corresponding to the data to be processed. For the data to be processed with a value of 0, the reading of the corresponding second data object can be omitted, and 0 can be directly used as the multiplication result corresponding to the data to be processed without actually performing the corresponding multiplication operation.

[0119] 23) Accumulate the multiplication results of each of the to-be-processed data and the corresponding second data object to obtain a first addition result.

[0120] This step may use an adder, which may directly read the second data object corresponding to each data to be processed or 0 as the multiplication result of the data to be processed and its corresponding second data object according to the value of the data to be processed (0 or 1), and perform an addition operation in the adder to obtain the first addition operation result.

[0121] In the prior art, for each channel of data to be processed in a multi-channel parallel system (each channel of data to be processed can be regarded as one channel), a corresponding shifter is used to perform shift processing on the data to be processed and its corresponding second data object, so as to complete the multiplication operation of the two based on the shift. For an n-channel parallel system, n shifters are required accordingly, see Figure 6, is the structure of the parallel system in the known technology. For a two-way parallel system, two shifters are required. After shifting the multi-way data in parallel, an adder ( Figure 6 The 16-bit Adder in the ... Figure 6 The 17-bit Adder in the process adds the current multiplication-accumulation result of each data channel with the historical multiplication-accumulation result of each data channel to obtain the multiplication-accumulation result of all processed data in the binary sequence of each first target data object. This iterative process is carried out until the data in the binary sequence of each first target data object is processed, and the processing result of each first target data object is obtained. Figure 6 In the figure, Flop represents a register, which is used to store the multiplication and accumulation result data generated by the 17-bit Adder during the iteration process.

[0122] The embodiment of the present application further optimizes the hardware of the parallel system. Figure 6 The parallel system architecture shown is improved to Figure 7 The architecture shown in FIG. 1 is a structure in which n shifters corresponding to n channels of data to be processed are adjusted to an adder. For a two-channel parallel architecture and a binary sequence length of an 8-bit first target data object, the adder can be a 9-bit adder, that is, Figure 7 The 9-bit Adder in the 9-bit Adder. The second data object or 0 corresponding to each data to be processed can be directly read, and the addition operation is performed in the adder to obtain the first addition operation result. The setting of the shifter can be omitted in this link.

[0123] 24) Shift the historical cumulative operation result one bit to a higher position, add the shift result and the first addition operation result to obtain a second addition operation result, and use the second addition operation result to update the historical cumulative operation result.

[0124] The historical accumulation operation result is the multiplication and accumulation operation result of all processed data so far obtained in the process of performing multiple rounds of iterative processing on different bit data in the binary sequence of each first target data object based on the iterative method. It is easy to understand that the historical accumulation operation result corresponding to each first target data object allocated each time is zero or empty at the beginning.

[0125] In this step, a shifter can be used to shift the historical accumulation operation result one bit to the higher bit, that is, to shift it to the left by one bit. The shifter used can be called a left-shift one-bit shifter. Figure 7Specifically represented as Left shift 1, and using another adder to add the shift result and the first addition result to obtain a second addition result. On this basis, the second addition result is used to update the historical accumulation result, thus completing the processing of each current data to be processed. Figure 7 In the example of the two-way parallel architecture, the adder for accumulating the shift result and the first addition result may be a 17-bit adder, that is, Figure 7 17bit Adder in Figure 7 In the example, Flop also represents a register, which is used to store the historical accumulation operation results generated during the iteration process.

[0126] Optionally, the left shift one bit shifter, combined with reference to Figure 8 The structure shown can directly implement its function through fixed wiring, that is, the lowest bit of the original data is filled with 0 through fixed wiring, and the highest bit is discarded without consuming logic resources.

[0127] Figure 7 and Figure 8 The MSB in the bit is the most significant bit, which means the most significant bit.

[0128] 25) Obtain the next bit of the current data to be processed in the binary sequence of each first target data object in descending order, update the current corresponding data to be processed based on the next bit of data, and loop to the step of obtaining the second data object corresponding to each data to be processed until the processing of the data in each binary sequence is completed, and use the latest historical cumulative operation result as the operation result of the assigned each first target data object.

[0129] After completing the processing of each current data to be processed, based on the iterative idea, the next bit of data of the current data to be processed can be obtained from the binary sequence of each first target data object in a decreasing manner, and each next bit of data obtained can be used as a new data to be processed to trigger a new round of data processing on the data to be processed, until the available hardware processing channels in the parallel architecture complete the data processing of each allocated first data object, and the latest historical accumulation operation result is used as the operation result of each currently allocated first target data object, and the accumulator (such as Figure 7 The Accumulator in the parallel system accumulates the calculation result with the calculation results of each first target data object in other paths of the parallel system. For example, the calculation results of each compressed target weight currently assigned are accumulated with the calculation results corresponding to each target weight in other paths to obtain the corresponding output feature value.

[0130] The following is for Figure 7 The parallel system architecture of provides an application example of the above process.

[0131] Assume that the currently assigned two weights (compressed target weights) are: weightl = 13 = (1101) 2 , weight2 = 11 = (1011) 2 , the processing process is:

[0132] 31) The first beat starts from the most significant bit (the fourth bit), and the two paths select the corresponding feature values ​​in the corresponding feature map according to the weight ID, and then send them to the 9-bit adder for addition and then store them in flop.

[0133] 32) The second beat processes the third bits of the two weights. The third bit of weight1 is 1, and the corresponding eigenvalue is taken out according to the weight ID. The third bit of the other weight2 is 0, and the result is 0 (indicating that the multiplication result of the third bit and its corresponding eigenvalue is 0). The result stored in the flop of the previous beat is shifted left by one bit and added to the eigenvalue of weight1 at the 17-bit adder, and the result is stored in flop.

[0134] 33) The third beat processes the second bits of the two weights. If the second bit of Weight1 is 0, the result is 0; if the second bit of Weight2 is 1, the corresponding eigenvalue is taken out, the result in the previous beat stored in the flop is shifted left by one bit, and then added to the eigenvalue of Weight2 at the 17-bit adder, and the result is stored in the flop.

[0135] 34) The fourth beat processes the first bit of the two weights. If the first bit of the two weights is 1, the eigenvalues ​​corresponding to the first bit of the two weights are taken out respectively, and added at the 9-bit adder. Then, the result in the flop of the previous beat is shifted left by one bit and added to the output result of the 9-bit adder at the 17-bit adder, and the result is stored in the flop. In the next beat, the result in the flop is sent to the downstream accumulator to be added with the data of other paths.

[0136] Based on the above processing method, this embodiment can optimize the hardware architecture in the parallel system and simplify the circuit of the parallel system. At the same time, after simplifying the circuit of the parallel system, the clock frequency can be increased and the system performance can be further improved.

[0137] In an optional embodiment, the sparsity of the first data object in the first data object set corresponding to the target data processing channel is less than a second threshold; the sparsity is used to characterize the proportion of invalid data in the first data object.

[0138] Optionally, constraints may be added during the model training process of the neural network model to control the sparsity of the first data objects in the generated first data object set to be less than the second threshold.

[0139] There may still be some empty bits (invalid bit data) in the first target data object such as the target weight obtained after shifting and clustering the valid bit data. The processing of the invalid bit data will affect the system performance. In response to this situation, this embodiment adds constraints when quantizing the model training to obtain the weights of the model network layer, and sets an upper limit on the proportion of empty bits. When the upper limit is exceeded, the model is re-quantized to reduce the proportion of empty bits in the weights of the model network layer, thereby further achieving the effect of reducing the proportion of empty bits in the target weights obtained after subsequent shifting and clustering, so as to further improve the data processing efficiency of the system.

[0140] Corresponding to the above method, the embodiment of the present application also provides a data processing device, whose composition structure is as follows: Fig. 9 As shown, including:

[0141] A first acquisition module 901 is used to acquire at least one first target data object containing first target data; the first target data in each first target data object at least includes all valid data in each first data object corresponding to the target data processing channel;

[0142] A second acquisition module 902, configured to acquire a second data object corresponding to the first target data object from a second data object set corresponding to the target data processing channel;

[0143] A data processing module 903 is used to perform data processing on each first target data and the corresponding second data object in the at least one first target data object;

[0144] The number of the first target data objects is less than the number of first data objects corresponding to the target data processing channel.

[0145] In an optional implementation manner, the sparsity of each first target data object is less than a first threshold; the sparsity is used to characterize the proportion of invalid data in the first target data object.

[0146] In an optional implementation manner, the valid data in the first data object is valid bit data in a binary sequence of the first data object;

[0147] The above-mentioned device also includes a construction module for constructing the first target data object. When constructing the first target data object, the construction module is specifically used to:

[0148] Obtaining a first data object set corresponding to a target data processing channel in the model;

[0149] Based on the same bit positions in the binary sequences of different first data objects, move the valid bit data of the corresponding first data object in the first data object set to the position where the invalid bit data of other first data objects are located, so as to reduce the number of first data objects containing valid bit data;

[0150] The at least one first target data object includes a first data object obtained after the move is completed and at least contains valid bit data; and the other first data objects are first data objects other than the corresponding first data object in the first data object set.

[0151] In an optional implementation manner, each first target data corresponds to corresponding position information, which is used to indicate the position of the second data object corresponding to the first data object to which the first target data belongs;

[0152] The second acquisition module 902 is specifically configured to: for each first target data in the first target data objects, acquire a second data object in a second data object set corresponding to a corresponding target data processing channel and located at a target position, to obtain a second data object corresponding to the first target data; the second data object corresponding to the first target data object includes the second data object corresponding to each first target data in the first target data object;

[0153] The corresponding target data processing channel and the target position are respectively the data processing channel indicated by the position information of the first target data and the indicated position within the indicated data processing channel.

[0154] In an optional implementation manner, the data processing module 903 is specifically used to: allocate a corresponding number of first target data objects to the available hardware processing channels according to the number of available hardware processing channels that can be processed in parallel, and use the available hardware processing channels to perform data processing on the first target data and the corresponding second data objects in each allocated first target data object;

[0155] The first target data at corresponding positions between different first target data objects on the available hardware processing channels are processed in parallel.

[0156] In an optional implementation manner, the data processing includes multiplication-accumulation operations; the valid data in the first data object is valid bit data in a binary sequence of the first data object;

[0157] The data processing module 903, when performing data processing on the first target data and the corresponding second data object in each allocated first target data object, is specifically used to:

[0158] Acquire data at preset starting positions in respective binary sequences corresponding to respective first target data objects assigned as respective current data to be processed; the preset starting positions in the binary sequences corresponding to different first target data objects are the same;

[0159] Obtaining a second data object corresponding to each data to be processed;

[0160] Accumulate the multiplication results of each of the to-be-processed data and the corresponding second data object to obtain a first addition result;

[0161] Shifting the historical accumulation result by one bit to a higher bit, adding the shift result and the first addition result to obtain a second addition result, and updating the historical accumulation result by using the second addition result;

[0162] Obtaining the next bit of the current data to be processed in the binary sequence of each first target data object in a descending manner, updating the current corresponding data to be processed based on the next bit of data, and looping to the step of obtaining the second data object corresponding to each data to be processed until the processing of the data in each binary sequence is completed, and using the latest historical accumulation operation result obtained as the operation result of each assigned first target data object;

[0163] The historical accumulation operation results corresponding to each first target data object allocated each time are initially zero or empty.

[0164] In an optional implementation, the sparsity of the first data object in the first data object set corresponding to the target data processing channel is less than a second threshold; the sparsity is used to characterize the proportion of invalid data in the first data object.

[0165] As for the data processing device provided in the embodiment of the present application, since it corresponds to the data processing method provided in the above method embodiment, the description is relatively simple. For the relevant similarities, please refer to the description of the above method embodiment, which will not be described in detail here.

[0166] In addition, the present application also provides a data processing chip, the composition structure of which is as follows: Fig.10 As shown, including:

[0167] The data acquisition component 10 is used to acquire data at a preset starting position in each binary sequence corresponding to each allocated first target data object as each current data to be processed; and to acquire a second data object corresponding to each data to be processed; the preset starting positions in the binary sequences corresponding to different first target data objects are the same;

[0168] A first operation component 20, configured to accumulate a multiplication result of each of the to-be-processed data and the corresponding second data object to obtain a first addition result;

[0169] The second operation component 30 is used to shift the historical accumulation operation result by one bit to a higher bit, add the shift result and the first addition operation result to obtain a second addition operation result, and use the second addition operation result to update the historical accumulation operation result;

[0170] Storage component 40, used to store historical accumulation operation results;

[0171] The data acquisition component is also used to obtain the next bit of the current data to be processed in the binary sequence of each first target data object in a descending manner, update the current corresponding data to be processed based on the next bit of data, and loop to obtain the processing of the second data object corresponding to each data to be processed, until the various components based on the data processing chip complete the processing of the data in the various binary sequences, and use the latest historical cumulative operation results obtained as the operation results of the assigned various first target data objects.

[0172] Optionally, the first operation component 20 includes a first addition operation unit for accumulating a multiplication result of each of the to-be-processed data and the corresponding second data object to obtain a first addition operation result;

[0173] The second operation component 30 includes a shift unit for shifting the historical accumulated operation result to a higher position by one bit, and a second addition operation unit for accumulating the shift result of the shifter with the corresponding first addition operation result to obtain a second addition operation result;

[0174] The storage component 40 includes a register unit for storing historical accumulation operation results;

[0175] The number of the first adding unit, the second adding unit, the shift unit and the register unit is one respectively. The first adding unit and the second adding unit can be adders respectively, the shift unit can be a shifter, and the register unit can be a register.

[0176] The cooperative relationship between the components in the data processing chip and the corresponding more detailed processing flows can be found in the above description of the embodiment for implementing data processing based on a parallel system, which will not be repeated here.

[0177] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0178] For the convenience of description, the above system or device is described by dividing it into various modules or units according to its functions. Of course, when implementing the present application, the functions of each unit can be implemented in the same or multiple software and / or hardware.

[0179] It can be known from the description of the above implementation methods that those skilled in the art can clearly understand that the present application can be implemented by means of software plus a necessary general hardware platform. Based on such an understanding, the technical solution of the present application can be essentially or partly contributed to the prior art in the form of a software product, which can be stored in a storage medium such as ROM / RAM, a magnetic disk, an optical disk, etc., and includes several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in the various embodiments of the present application or certain parts of the embodiments.

[0180] Finally, it should be noted that, in this article, relational terms such as first, second, third and fourth are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements includes not only those elements, but also includes other elements not clearly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of more restrictions, the elements limited by the statement "comprise a..." do not exclude the existence of other identical elements in the process, method, article or equipment including the elements.

[0181] The above is only a preferred implementation of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A data processing method, comprising: Acquire at least one first target data object including first target data; The first target data in each first target data object at least includes all valid data in each first data object corresponding to the target data processing channel; Acquire a second data object corresponding to the first target data object from a second data object set corresponding to the target data processing channel; Performing data processing on each first target data and the corresponding second data object in the at least one first target data object; The number of the first target data objects is less than the number of first data objects corresponding to the target data processing channel.

2. According to the method of claim 1, the sparsity of each first target data object is less than a first threshold; the sparsity is used to characterize the proportion of invalid data in the first target data object.

3. The method according to claim 1, wherein the valid data in the first data object is valid bit data in a binary sequence of the first data object; The method for forming the first target data object includes: Obtaining a first data object set corresponding to a target data processing channel in the model; Based on the same bit positions in the binary sequences of different first data objects, move the valid bit data of the corresponding first data object in the first data object set to the position where the invalid bit data of other first data objects are located, so as to reduce the number of first data objects containing valid bit data; The at least one first target data object includes a first data object obtained after the move is completed and at least contains valid bit data; and the other first data objects are first data objects other than the corresponding first data object in the first data object set.

4. The method according to claim 1, each first target data corresponds to corresponding position information, which is used to indicate the position of the second data object corresponding to the first data object to which the first target data belongs; Acquiring a second data object corresponding to the first target data object from a second data object set corresponding to the target data processing channel includes: For each first target data in the first target data objects, a second data object in a second data object set corresponding to a corresponding target data processing channel and located at a target position is obtained to obtain a second data object corresponding to the first target data; the second data object corresponding to the first target data object includes the second data object corresponding to each first target data in the first target data object; The corresponding target data processing channel and the target position are respectively the data processing channel indicated by the position information of the first target data and the indicated position within the indicated data processing channel.

5. The method according to claim 1, wherein the step of performing data processing on each first target data and the corresponding second data object in the at least one first target data object comprises: According to the number of available hardware processing channels that can be processed in parallel, a corresponding number of first target data objects are allocated to the available hardware processing channels, and the available hardware processing channels are used to perform data processing on the first target data and the corresponding second data objects in each allocated first target data object; The first target data at corresponding positions between different first target data objects on the available hardware processing channels are processed in parallel.

6. The method according to claim 5, wherein the data processing comprises a multiplication-accumulation operation; the valid data in the first data object is valid bit data in a binary sequence of the first data object; The performing data processing on the first target data and the corresponding second data object in each allocated first target data object comprises: Acquire data at preset starting positions in respective binary sequences corresponding to respective first target data objects assigned as respective current data to be processed; the preset starting positions in the binary sequences corresponding to different first target data objects are the same; Obtaining a second data object corresponding to each data to be processed; Accumulate the multiplication results of each of the to-be-processed data and the corresponding second data object to obtain a first addition result; Shifting the historical accumulation result by one bit to a higher bit, adding the shift result and the first addition result to obtain a second addition result, and updating the historical accumulation result by using the second addition result; Obtaining the next bit of the current data to be processed in the binary sequence of each first target data object in a descending manner, updating the current corresponding data to be processed based on the next bit of data, and looping to the step of obtaining the second data object corresponding to each data to be processed until the processing of the data in each binary sequence is completed, and using the latest historical accumulation operation result obtained as the operation result of each assigned first target data object; The historical accumulation operation results corresponding to each first target data object allocated each time are initially zero or empty.

7. According to the method of claim 3, the sparsity of the first data object in the first data object set corresponding to the target data processing channel is less than a second threshold; the sparsity is used to characterize the proportion of invalid data in the first data object.

8. A data processing device, comprising: A first acquisition module, used to acquire at least one first target data object containing first target data; The first target data in each first target data object at least includes all valid data in each first data object corresponding to the target data processing channel; A second acquisition module, configured to acquire a second data object corresponding to the first target data object from a second data object set corresponding to the target data processing channel; A data processing module, used for performing data processing on each first target data and the corresponding second data object in the at least one first target data object; The number of the first target data objects is less than the number of first data objects corresponding to the target data processing channel.

9. A data processing chip, comprising: A data acquisition component, used to acquire data at a preset starting position in each binary sequence corresponding to each allocated first target data object as each current data to be processed; and obtaining a second data object corresponding to each data to be processed; The preset starting positions in the binary sequences corresponding to different first target data objects are the same; A first operation component, used for accumulating the multiplication results of each of the to-be-processed data and the corresponding second data object to obtain a first addition result; A second operation component is used to shift the historical accumulation operation result by one bit to a higher bit, add the shift result and the first addition operation result to obtain a second addition operation result, and use the second addition operation result to update the historical accumulation operation result; Storage component, used to store historical accumulation operation results; The data acquisition component is also used to obtain the next bit of the current data to be processed in the binary sequence of each first target data object in a descending manner, update the current corresponding data to be processed based on the next bit of data, and loop to obtain the processing of the second data object corresponding to each data to be processed, until the various components based on the data processing chip complete the processing of the data in the various binary sequences, and use the latest historical cumulative operation results obtained as the operation results of the assigned various first target data objects.

10. The data processing chip according to claim 9, wherein: The first operation component comprises a first addition operation unit for accumulating a multiplication result of each of the to-be-processed data and the corresponding second data object to obtain a first addition operation result; The second operation component includes a shift unit for shifting the historical accumulated operation result to a higher position by one bit, and a second addition operation unit for accumulating the shift result of the shifter with the corresponding first addition operation result to obtain a second addition operation result; The storage component includes a register unit for storing historical accumulation operation results; The number of the first adding unit, the second adding unit, the shifting unit and the registering unit is one respectively.

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