Circuit for transmitting signals by using T + FLY-BY topological structure

Abstract

The invention provides a circuit for transmitting signals by using a T + FLY-BY topological structure. The circuit comprises a DRAM (Dynamic Random Access Memory) controller, a first group of DRAMs and a first branch point which are arranged on a PCB (Printed Circuit Board), the first group of DRAM comprises a plurality of DRAM particles; a CA port of the DRAM controller is connected with the first branch point through a signal line, and the first branch point is connected with the first DRAM particle and / or the second DRAM particle through a signal line; the CA signal line arranged between the first DRAM particle and the at least one third DRAM particle is of an FLY-BY topological structure, and the CA signal line arranged between the second DRAM particle and the at least one fourth DRAM particle is of an FLY-BY topological structure; the first DRAM particle, the second DRAM particle, the third DRAM particle and the fourth DRAM particle form a first group of DRAMs. The time required for signal transmission can be reduced, and it is ensured that signal transmission meets the time sequence requirement.

Description

Technical Field

[0001] The present application relates to the field of storage technology, and in particular to a circuit for transmitting signals using a T+FLY-BY topology structure. Background Art

[0002] As the performance requirements of electronic devices increase, the DRAM controller needs to couple more DRAM particles. For example, the DRAM controller couples 18 DRAM particles. The signal group transmitted between the DRAM controller and the DRAM particles includes CA (command / address), CK (clock signal), DQ (data signal), and DQS (data selection signal). The 18 DRAMs are laid out on the two surfaces (front and back) of the PCB (Printed Circuit Board), with 9 DRAMs on each side. For example, DRAM1 to DRAM9 (9 DRAMs) are laid out on the front, and DRAM1' to DRAM9' (9 DRAMs) are laid out on the back. See Figure 1 , which is a schematic diagram of laying out multiple DRAMs on two surfaces of a PCB board, and the dotted line indicates laying out DRAMs on the back side of the PCB board.

[0003] 18 DRAMs can be divided into 2 groups, for example, 9 DRAMs on the front side as one group, and 9 DRAMs on the back side as another group; or 5 DRAMs on the front side and 4 DRAMs on the back side as one group, and 4 DRAMs on the front side and 5 DRAMs on the back side as another group. Each group of DRAMs corresponds to a CK signal, such as a DRAM controller includes two CK signal ports, CK0 and CK1, which are used to provide CK signals to the two groups of DRAMs respectively. The two groups of DRAMs share DQ, CA, and DQS signals. For example, the DRAM controller includes a CA port and a DQS port, and provides CA signals to the two groups of DRAMs through the CA port, and provides DQS signals to the two groups of DRAMs through the DQS port; the number of DQ ports is the same as the number of DRAM particles supported by each group. For example, the DRAM controller includes nine DQ ports, DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, DQ7, and DQ8, to provide DQ signals to each group of 9 DRAMs respectively. See. Figure 2A and Figure 2B As shown, the 9 DRAMs on the front side of the PCB board are grouped as one group, and the 9 DRAMs on the back side of the PCB board are grouped as another group. The DRAM controller is deployed on the front side of the PCB board. The group on the front side corresponds to the CK0 signal, and the group on the back side corresponds to the CK1 signal. The two groups of DRAMs share DQ, CA, and DQS signals.

[0004] The PCB board has multiple layers, and multiple DRAMs are arranged on both sides of the PCB board. The DRAM particles arranged on the front and back sides correspond to each other one by one (one-to-one relative arrangement). The same pins of the DRAM particles arranged oppositely on the front and back sides can be connected through through holes. The through holes penetrate the multiple layers of the PCB board from the front to the back, so that the signals of each port of the DRAM controller arranged on the front side can be transmitted to the DRAM particles arranged on the front side through the through holes, and can also be transmitted to the DRAM particles arranged on the back side. For example, the DQ, CA or DQS signal on the DRAM particle on the front side is transmitted to the corresponding DRAM particle on the back side through the through hole. For example, the DQ pin of the DRAM1 particle receives the DQ signal, and the DQ signal received by the DRAM1 particle is transmitted to the DQ pin of the DRAM1' particle through the through hole coupled with the DQ pin of the DRAM1 particle.

[0005] At present, when transmitting CA and CK signals to DRAM chips, the routing usually adopts FLY-BY topology or T-type structure, and the routing of DQ and DQS signals usually adopts point-to-point method. Figure 3A As shown in FIG. 1 , the signal routing for transmitting CA and CK signals adopts a FLY-BY topology structure, and the signal routing for transmitting DQ and DQS signals adopts a point-to-point method; see Figure 3B FIG. 4 is another schematic diagram of a signal routing for transmitting a CA signal using a FLY-BY topology structure.

[0006] In the FLY-BY topology, for example, the CA signal line is extended to each DRAM chip in turn in a single routing form, and the CA signal line is connected to the CA port of each DRAM chip through a short connection line. In order to improve the signal quality, a termination resistor VTT is also set at the end of the CA signal line to compensate for the capacitive load. Summary of the invention

[0007] When the DRAM controller transmits signals such as CA, CK, DQ or DQS to DRAM particles, it is required that the time deviation between CK and DQS cannot exceed a specified threshold (for example, 1 clock cycle). When multiple DRAMs (such as 9) in each group of DRAMs use the FLY-BY topology to transmit CA / CK signals, since each group of DRAMs contains a large number of DRAM particles, affected by other components on the circuit board, the number of DRAM particles to be placed, the position of the port on the DRAM controller that accesses the DRAM particles, etc., the CA and CK signal lines use the FLY-BY topology, so that the shape of the CA and CK signal lines will be affected. In order to meet the wiring requirements of the FLY-BY topology, the CA and CK signal lines may be too long. Since the time required to transmit the CA and CK signals is proportional to the length of the CA and CK signal lines, the excessively long connection will cause the time deviation between CK and DQS to exceed the specified threshold, and the timing requirements cannot be met. The present application hopes to provide a solution to solve the above technical problems.

[0008] The embodiment of the present application provides a circuit, comprising: a DRAM controller, a first group of DRAMs, and a first branch point arranged on a PCB board;

[0009] The first group of DRAMs includes a plurality of DRAM chips;

[0010] The CA port of the DRAM controller is connected to the first branch point through a signal line, and the first branch point is connected to the first DRAM particle and / or the second DRAM particle in the first group of DRAMs through a signal line;

[0011] The signal line for transmitting CA signals arranged between the first DRAM particle and at least one third DRAM particle adopts a FLY-BY topology structure, and the signal line for transmitting CA signals arranged between the second DRAM particle and at least one fourth DRAM particle adopts a FLY-BY topology structure;

[0012] The first DRAM particle, the second DRAM particle, the at least one third DRAM particle and the at least one fourth DRAM particle are different DRAM particles in the first group of DRAMs, and together constitute the first group of DRAMs.

[0013] Optionally, the circuit further comprises: a second branch point;

[0014] The first CK port of the DRAM controller is connected to the second branch point through a signal line, and the second branch point is connected to the first DRAM particle and / or the second DRAM particle in the first group of DRAM through a signal line;

[0015] The signal line for transmitting the CK signal arranged between the first DRAM particle and the at least one third DRAM particle adopts a FLY-BY topology structure, and the signal line for transmitting the CK signal arranged between the second DRAM particle and the at least one fourth DRAM particle adopts a FLY-BY topology structure.

[0016] Optionally, a difference between a length of a signal line arranged between the first DRAM chip and the at least one third DRAM chip and a length of a signal line arranged between the second DRAM chip and the at least one fourth DRAM chip is within a first preset range.

[0017] Optionally, the length of a signal line connecting the first branch point or the second branch point and corresponding pins on the first DRAM chip and the second DRAM chip is within a second preset range.

[0018] Optionally, a length of a signal line between two adjacent DRAM particles in the first group of DRAMs is within a preset third range.

[0019] Optionally, the first branch point and the second branch point are through holes provided on the PCB board.

[0020] Optionally, the first branch point and / or the second branch point are both dedicated through holes set on the PCB board for realizing the branch point function; or, the first branch point is a through hole corresponding to the CA pin of the DRAM particle on the PCB board, and the second branch point is a through hole corresponding to the CK pin of the DRAM particle in the first group of DRAM.

[0021] Optionally, the first branch point and / or the second branch point is the dedicated through hole, and the first branch point and / or the second branch point is connected to the first DRAM particle and the second DRAM particle through a signal line.

[0022] Optionally, a through hole corresponding to the CA pin of the first DRAM particle serves as the first branch point, and the first branch point is connected to a pin corresponding to the second DRAM particle through a signal line; or

[0023] The through hole corresponding to the CA pin of the second DRAM particle serves as the first branch point, and the first branch point is connected to the pin corresponding to the first DRAM particle through a signal line.

[0024] Optionally, a through hole corresponding to a CK pin of the first DRAM particle serves as the second branch point, and the second branch point is connected to a pin corresponding to the second DRAM particle through a signal line; or

[0025] The through hole corresponding to the CK pin of the second DRAM particle serves as the second branch point, and the second branch point is connected to the pin corresponding to the first DRAM particle through a signal line.

[0026] Optionally, the CA port of the DRAM controller is connected to the CA port of the first DRAM particle or the second DRAM particle through a signal line;

[0027] The first CK port of the DRAM controller is connected to the CK port of the first DRAM particle or the second DRAM particle through a signal line.

[0028] Optionally, the CA port of the DRAM controller is connected to the first branch point via a signal line, and the first branch point is connected to the CA port of the first DRAM particle and / or the second DRAM particle via a signal line;

[0029] The first CK port of the DRAM controller is connected to the second branch point through a signal line, and the second branch point is connected to the CK port of the first DRAM particle and / or the second DRAM particle through a signal line.

[0030] Optionally, the circuit further comprises: a second group of DRAM;

[0031] The CA port of the DRAM controller is connected to the first branch point through a signal line, and the first branch point is connected to the fifth DRAM particle and / or the sixth DRAM particle in the second group of DRAM through a signal line;

[0032] The signal line for transmitting the CA signal arranged between the fifth DRAM chip and at least one seventh DRAM chip adopts a FLY-BY topology structure, and the signal line for transmitting the CA signal arranged between the sixth DRAM chip and at least one eighth DRAM chip adopts a FLY-BY topology structure;

[0033] Among them, the fifth DRAM particle, the sixth DRAM particle, the at least one seventh DRAM particle and the at least one eighth DRAM particle are different DRAM particles in the second group of DRAMs, and together constitute the second group of DRAMs.

[0034] Optionally, the first branch point is a dedicated through hole, and the first branch point is connected to the CA pins of the fifth DRAM particle and the sixth DRAM particle respectively through a signal line.

[0035] Optionally, when the through hole corresponding to the CA pin of the first DRAM particle is used as the first branch point, the CA pin of the fifth DRAM particle or the sixth DRAM particle is connected to the CA pin of the first DRAM particle through the through hole corresponding to the CA pin of the first DRAM particle, and the CA signal is transmitted to the CA pin of the fifth DRAM particle or the sixth DRAM particle through the through hole of the CA pin of the first DRAM particle.

[0036] Optionally, the circuit further includes a third branch point and the DRAM controller further includes a second CK port;

[0037] The second CK port of the DRAM controller is connected to the third branch point through a signal line, and the third branch point is connected to the fifth DRAM particle and / or the sixth DRAM particle in the second group of DRAM through a signal line;

[0038] The signal line for transmitting the CK signal arranged between the fifth DRAM particle and at least one seventh DRAM particle adopts a FLY-BY topology structure, and the signal line for transmitting the CK signal arranged between the sixth DRAM particle and at least one eighth DRAM particle adopts a FLY-BY topology structure.

[0039] Optionally, the second CK port and the first CK port are different CK ports on the DRAM controller;

[0040] The first branch point, the second branch point and the third branch point are different branch points.

[0041] Optionally, the third branch point is a dedicated through hole provided on the PCB board that is different from the first branch point and the second branch point; or, the third branch point is a through hole corresponding to a CK pin of a DRAM particle in the second group of DRAMs.

[0042] Optionally, the third branch point is a dedicated through hole, and the third branch point is connected to the CK pins of the fifth DRAM particle and the sixth DRAM particle respectively through a signal line.

[0043] Optionally, when the through hole corresponding to the CK pin of the fifth DRAM particle is used as the third branch point, the second CK port of the DRAM controller is connected to the CK pin of the fifth DRAM particle through a signal line;

[0044] The CK pins of the sixth DRAM particle are connected to the through holes corresponding to the CK pins of the fifth DRAM particle through signal lines, and the CK signal is transmitted to the CK pins of the sixth DRAM particle through the through holes of the CK pins of the fifth DRAM particle.

[0045] Optionally, when the third branch point is a through hole corresponding to the CK pin of the sixth DRAM particle, the second CK port of the DRAM controller is connected to the CK pin of the sixth DRAM particle through a signal line;

[0046] The CK pin of the fifth DRAM particle is connected to a through hole corresponding to the CK pin of the sixth DRAM particle through a signal line, and a CK signal is transmitted to the CK pin of the fifth DRAM particle through the through hole of the CK pin of the sixth DRAM particle.

[0047] Optionally, the first group of DRAMs and the second group of DRAMs are located on different end surfaces of the PCB board, or the first group of DRAMs and the second group of DRAMs both include DRAM particles from two end surfaces arranged on the PCB board.

[0048] Optionally, both the first group of DRAM and the second group of DRAM include DRAM particles from two end surfaces arranged on the PCB board, and the first branch point is a through hole corresponding to the CA pin of the first DRAM particle, the CA pin of the fifth DRAM particle or the sixth DRAM particle is connected to the through hole corresponding to the CA pin of the first DRAM particle through a signal line, and the CA pin of the second DRAM particle is connected to the through hole of the CA pin of the first DRAM particle through a signal line;

[0049] The CA signal is transmitted to the CA pin of the second DRAM particle and to the CA pin of the fifth DRAM particle or the CA pin of the sixth DRAM particle through the through hole of the CA pin of the first DRAM particle.

[0050] Optionally, if the CA signal is transmitted to the CA pin of the fifth DRAM particle through the through hole of the CA pin corresponding to the first DRAM particle, the CA pin of the sixth DRAM particle is connected to the through hole of the CA pin of the fifth DRAM particle through a signal line, and the CA signal is transmitted to the CA pin of the sixth DRAM particle through the CA pin of the fifth DRAM particle.

[0051] Optionally, if the CA signal is transmitted to the CA pin of the sixth DRAM particle through the through hole of the CA pin corresponding to the first DRAM particle, the CA pin of the fifth DRAM particle is connected to the through hole of the CA pin of the sixth DRAM particle through a signal line, and the CA signal is transmitted to the CA pin of the fifth DRAM particle through the CA pin of the sixth DRAM particle.

[0052] According to an embodiment of the present application, DRAM particles within a DRAM group are divided by using branch points, and multiple DRAM particles corresponding to each divided part of the DRAM use a FLY-BY topology structure to transmit CA or CK signals. The CA or CK signals are transmitted in parallel between the DRAM particles in the DRAM group through their respective corresponding FLY-BY topology structures, thereby reducing the time required to transmit the CA or CK signals between the DRAM particles in the group and ensuring that the transmission of the CA or CK signals meets the timing requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] Figure 1 A schematic diagram showing the layout of DRAM on two surfaces of a PCB board;

[0054] Figure 2A A schematic diagram showing that the DRAM controller provides DQ, CA, DQS, and CK signals to the DRAM on the front side of the PCB board;

[0055] Figure 2B A schematic diagram showing that the DRAM controller provides DQ, CA, DQS, and CK signals to the DRAM on the back of the PCB;

[0056] Figure 3A A schematic diagram showing that the routing for transmitting CA and CK signals adopts a FLY-BY structure, and the routing for transmitting DQ and DQS signals adopts a point-to-point structure;

[0057] Figure 3B A schematic diagram showing that the routing for transmitting CA signals adopts a FLY-BY topology;

[0058] Figure 4 A schematic diagram showing a method of transmitting CA and / or CK signals using a T+FLY-BY topology structure and transmitting DQ and / or DQS signals in a point-to-point manner provided in an embodiment of the present application;

[0059] Figure 5A One of the schematic diagrams showing that the DRAMs at both end surfaces of the PCB board provided in the embodiment of the present application adopt the T+FLY-BY topology structure to transmit CA signals;

[0060] Figure 5B One of the schematic diagrams showing that the DRAM on the front side of the PCB board provided in the embodiment of the present application adopts the T+FLY-BY topology structure to transmit the CA signal;

[0061] Figure 5C One of the schematic diagrams showing that the DRAM on the back of the PCB board provided in the embodiment of the present application adopts the T+FLY-BY topology structure to transmit the CA signal;

[0062] Figure 6One of the schematic diagrams showing the DRAMs at both end surfaces of the PCB board provided by the embodiment of the present application, and implementing the T+FLY-BY topology structure based on the transmission of CA signals through the through holes corresponding to the CA pins;

[0063] Figure 7 The second schematic diagram shows that the DRAMs at both end surfaces of the PCB board provided in the embodiment of the present application adopt the T+FLY-BY topology structure to transmit CA signals;

[0064] Fig. 8A A schematic diagram showing a group of DRAMs located on the front side of a PCB board provided by an embodiment of the present application providing a CK0 signal through a CK0 port of a DRAM controller;

[0065] Figure 8B A schematic diagram showing a group of DRAMs located on the back of a PCB board provided by an embodiment of the present application providing a CK1 signal through a CK1 port of a DRAM controller;

[0066] Fig.9A A schematic diagram showing two groups of DRAMs sharing DQ signals provided in an embodiment of the present application;

[0067] Fig. 9B A schematic diagram showing point-to-point transmission of DQ signals between corresponding DRAMs provided in an embodiment of the present application;

[0068] Fig. 10A The third schematic diagram shows that the DRAMs at both end surfaces of the PCB board provided in the embodiment of the present application adopt the T+FLY-BY topology structure to transmit CA signals;

[0069] Fig. 10B The second schematic diagram shows that the DRAM on the front side of the PCB board provided in the embodiment of the present application adopts the T+FLY-BY topology structure to transmit the CA signal;

[0070] Fig. 10C The second schematic diagram shows that the DRAM on the back of the PCB board provided in the embodiment of the present application adopts the T+FLY-BY topology structure to transmit the CA signal;

[0071] Fig. 10D The second schematic diagram shows the DRAM at both end surfaces of the PCB board provided by the embodiment of the present application, and the T+FLY-BY topology structure is realized by transmitting CA signals based on the through holes corresponding to the CA pins;

[0072] Fig.10E A schematic diagram showing a PCB board layout of a DRAM, an NVM chip, and a DRAM controller provided in an embodiment of the present application, wherein the DRAM adopts a T+FLY-BY topology structure to transmit a CK signal;

[0073] Fig.11AA schematic diagram showing a T+FLY-BY topology structure achieved by providing through holes on a PCB board specifically used as branch points;

[0074] Fig. 11B A schematic diagram showing a topological structure of T+FLY-BY using through holes corresponding to DRAM pins as branch points;

[0075] Fig. 12A One of the schematic diagrams of pre-comprehensive simulation results of realizing a T+FLY-BY topology structure by setting through holes dedicated to branch points on a PCB board;

[0076] Fig. 12B One of the schematic diagrams of pre-synthesis simulation results of realizing the T+FLY-BY topology structure using the through holes corresponding to the DRAM pins as branch points;

[0077] Fig. 12C The second schematic diagram of the pre-comprehensive simulation results of realizing the T+FLY-BY topology structure by setting through holes dedicated to branch points on the PCB board;

[0078] Fig.12D The second schematic diagram of pre-synthesis simulation results of the topological structure of T+FLY-BY using the through holes corresponding to the DRAM pins as branch points;

[0079] Fig.13A A schematic diagram showing the simulation results after synthesis of the first pair of DRAMs in the FLY-BY structure 1 in which a through hole dedicated to a branch point is provided on a PCB board;

[0080] Fig. 13B A schematic diagram showing the simulation results after synthesis of the first pair of DRAMs in the FLY-BY structure 1 in a manner of using the through holes corresponding to the DRAM pins as branch points;

[0081] Fig. 13C A schematic diagram showing the simulation results after synthesis of the first pair of DRAMs in the FLY-BY structure 2 in which a through hole dedicated to a branch point is provided on a PCB board;

[0082] Fig.13D A schematic diagram showing the post-synthesis simulation results of the first pair of DRAMs in the FLY-BY structure 2 using the through holes corresponding to the DRAM pins as branch points. DETAILED DESCRIPTION

[0083] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0084] In the embodiment of the present application, in order to meet the timing requirements, the DRAM topology adopts the T+FLY-BY topology structure, and the signal is transmitted through the T+FLY-BY topology structure. For example, when transmitting a CA signal or a CK signal, the signal line routing that transmits the CA signal or the CK signal adopts the T+FLY-BY topology structure. In order to realize the T+FLY-BY topology structure, a T point (branch point) is set on the PCB board. For example, each group of DRAM is divided into two parts, and each part includes a plurality of DRAM particles (hereinafter collectively referred to as DRAM). The CA or CK signal routing connected from the CA or CK port of the DRAM controller is divided into two paths through the T point, and each path provides a CA or CK signal for each part of the DRAM in each group of DRAM. A FLY-BY topology is used to transmit CA or CK signals for multiple DRAMs in each part. CA or CK signals are transmitted in parallel between two parts of DRAM in each group of DRAMs through their respective corresponding FLY-BY topologies, thereby reducing the time required to transmit CA or CK signals between multiple DRAMs in the group, ensuring that the transmission of CA or CK signals meets the timing requirements, and thereby ensuring that the time deviation between CK and DQS meets the requirements.

[0085] For example, see Figure 4 As shown, a group of DRAMs includes 9 DRAMs (DRAM1, DRAM2, DRAM3, DRAM4, DRAM5, DRAM6, DRAM7, DRAM8, and DRAM9), which are divided into two parts using a T-type topology structure (DRAM1 to DRAM5 as one part, and DRAM6 to DRAM9 as the other part). The CA and / or CK signal routing of multiple DRAMs in each part adopts a FLY-BY topology structure. For example, the FLY-BY topology structure for transmitting CA or CK signals for DRAM1 to DRAM5 is FLY-BY structure 1, and the FLY-BY topology structure for transmitting CA or CK signals for DRAM6 to DRAM9 is FLY-BY structure 2. FLY-BY1 and FLY-BY2 can transmit CA and / or CK signals for the group of DRAMs DRAM1 to DRAM9 in parallel, thereby reducing the time required to transmit CA and / or CK signals between multiple DRAMs in the group to meet the timing requirements.

[0086] As an example, the branch point can be a through hole on the PCB board. For example, the through hole used as a branch point can be a through hole specially set on the PCB board for use as a branch point, and it can also be a through hole corresponding to a specified pin itself on the DRAM. For example, if the through hole corresponding to the DRAM pin itself is used as a branch point, it is necessary to select a group of DRAMs, select a DRAM from the multiple DRAMs in the group, and use the through hole corresponding to the specified pin itself on the selected DRAM as the branch point. For example, for the CA signal, the through hole corresponding to the CA pin itself of the selected DRAM is used as the branch point; or for the CK signal, the through hole corresponding to the CK pin itself of the selected DRAM is used as the branch point. For another example, if a through hole is specially set on the PCB board as a branch point, it is necessary to select a position on the PCB board to set the through hole. Optionally, for a group of DRAMs, the position of the through hole serving as a branch point on the PCB board can be determined in the following manner: the determined T point (branch point) makes the trace lengths corresponding to the two parts of the FLY-BY topology structure as close as possible; the trace length between the T point (branch point) and the pin corresponding to the specified DRAM (such as CA or CK) is within a set range, for example, the set range is between 100 and 200 mils, where mil is a unit of length, representing one thousandth of an inch. The specified DRAM is the first DRAM corresponding to each part, and the first DRAM is the DRAM that is closest to the T point in each part on the PCB board. Figure 4 DRAM5 and DRAM6 are the first DRAMs corresponding to the two parts. The process of transmitting CA signals based on the T+FLY-BY topology structure is introduced below.

[0087] For example, see Figure 5A and Figure 5B As shown, taking a group of DRAMs including 9 DRAMs all located on the front side of the PCB board and a DRAM controller also arranged on the front side of the PCB board as an example, a through hole (such as Figure 5A and Figure 5B The through hole 1 shown in the figure is used as a branch point. On the front of the PCB board, the CA port on the DRAM controller is connected to the through hole 1 through a signal line, and the through hole 1 is respectively connected to the CA ports of DRAM5 and DRAM6 on the front of the PCB board through a signal line, and the CA signal is transmitted to DRAM5 and DRAM6 in a T-type topology. Both DRAM5 and DRAM6 serve as the first DRAM to receive the CA signal. The 9 DRAMs (DRAM1 to DRAM9) on the front are divided into two parts (Part A and Part B) through the through hole 1; Part A includes DRAM5, DRAM4, DRAM3, DRAM2, and DRAM1; Part B includes DRAM6, DRAM7, DRAM8, and DRAM9.

[0088] For example, for part A, DRAM5 is used as the first DRAM, and the FLY-BY topology is used to transmit the CA signal between DRAM5 and DRAM1 in the order of DRAM5->DRAM4->DRAM3->DRAM2->DRAM1. For part B, DRAM6 is used as the first DRAM, and the FLY-BY topology is used to transmit the CA signal between DRAM6 and DRAM9 in the order of DRAM6->DRAM7->DRAM8->DRAM9. In this way, the CA signal can be transmitted between the 9 DRAMs in the group according to the T+FLY-BY topology, see Figure 5A as well as Figure 5B The solid line in FIG.

[0089] Since the DRAM is arranged on both sides of the PCB, 9 DRAMs are also arranged on the back side of the PCB. When the CA signal of the CA port on the DRAM controller is transmitted to through-hole 1 through the signal line, the CA signal is transmitted from the front side of the PCB to the back side of the PCB through through-hole 1, and then the CA signal is transmitted to the DRAM on the back side of the PCB through the signal line between the DRAM on the back side of the PCB and through-hole 1, so that the 9 DRAMs on the back side transmit CA signals in a similar way to the 9 DRAMs on the front side (T+FLY-BY topology), see Figure 5A as well as Figure 5C As shown in the dotted line routing in . For example, through hole 1 is connected to the CA ports of DRAM5' and DRAM6' on the back of the PCB board through a signal line, and the CA signal is transmitted to DRAM5' and DRAM6' in a T-type topology. DRAM5' and DRAM6' are both the first DRAMs in a group of DRAMs on the back to receive the CA signal. The 9 DRAMs on the back (DRAM1' to DRAM9') are divided into two parts (Part C and Part D) through through hole 1; wherein Part C includes DRAM5', DRAM4', DRAM3', DRAM2', and DRAM1'; and Part D includes DRAM6', DRAM7', DRAM8', and DRAM9'. ​​The CA signal is transmitted in Part C and Part D in a FLY-BY topology. For another example, for Part C, it can transmit the received CA signal in a FLY-BY topology of DRAM5'->DRAM4'->DRAM3'->DRAM2'->DRAM1'. For the D part, the received CA signal may be transmitted according to the FLY-BY topology structure of DRAM6'->DRAM7'->DRAM8'->DRAM9'.

[0090] For example, see Figure 6As shown, the CA pin of DRAM5 corresponds to the through hole Via_5, DRAM5 and DRAM5' are arranged on the front and back of the PCB board relatively, and DRAM5 and DRAM5' can transmit CA signals through through hole Via_5; the CA pin of DRAM6 corresponds to the through hole Via_6, DRAM6 and DRAM6' are arranged on the front and back of the PCB board relatively, and DRAM6 and DRAM6' can transmit CA signals through through hole Via_6. Through hole Via_5 and through hole Via_6 can be coupled with through hole 1 through signal lines.

[0091] The CA signal sent by the CA port of the DRAM controller is transmitted to the through hole Via_5 through the through hole 1. Since the CA pin in the front DRAM5 and the CA pin in the back DRAM5' can be coupled with the through hole Via_5, the CA pin in the front DRAM5 and the CA pin in the back DRAM5' can receive the CA signal sent by the CA port of the DRAM controller. For DRAM5, it can transmit the received CA signal according to the FLY-BY topology structure of DRAM5->DRAM4->DRAM3->DRAM2->DRAM1; for DRAM5', it can transmit the received CA signal according to the FLY-BY topology structure of DRAM5'->DRAM4'->DRAM3'->DRAM2'->DRAM1'.

[0092] The CA signal sent by the CA port of the DRAM controller is transmitted to the via Via_6 through the via 1. Since the CA pin in the front DRAM6 and the CA pin in the back DRAM6' can be coupled with the via Via_6, the CA pin in the front DRAM6 and the CA pin in the back DRAM6' can receive the CA signal sent by the CA port of the DRAM controller. For DRAM6, it can transmit the received CA signal according to the FLY-BY topology structure of DRAM6->DRAM7->DRAM8->DRAM9; for DRAM6', it can transmit the received CA signal according to the following FLY-BY topology structure: DRAM6'->DRAM7'->DRAM8'->DRAM9'. ​​It should be understood that for part A, part B, part C and part D, the shape of the CA signal routing of the FLY-BY topology structure should be based on the position of the DRAM on the PCB board. The signal routing of the FLY-BY topology structure is laid out near the DRAM, and then the CA signal routing is connected to the CA port of the DRAM through the signal line to realize the transmission of the signal from the DRAM controller to the DRAM.

[0093] The following is an example of a group of DRAMs including DRAMs located at two end surfaces of a PCB board. Figure 7As shown, DRAM 1, DRAM 2, DRAM 3, DRAM 4, DRAM 5 corresponding to the front of the PCB board and DRAM 1', DRAM 2', DRAM 3', DRAM 4' corresponding to the back of the PCB board constitute a group of DRAMs, and DRAM 6, DRAM 7, DRAM 8, DRAM 9 corresponding to the front of the PCB board and DRAM 5', DRAM 6', DRAM 7', DRAM 8', DRAM 9' corresponding to the back of the PCB board constitute another group of DRAMs. The CA port on the DRAM controller is connected to the through hole 1 through a signal line, and the through hole 1 is connected to the CA ports of DRAM 5 on the front of the PCB board and DRAM 4' on the back of the PCB board through a signal line.

[0094] For example, based on the connection between the through hole 1 and the CA port of DRAM 5 and DRAM 4' through the signal line, the CA signal is transmitted to DRAM5 and DRAM4' in a T-type topology. Both DRAM5 and DRAM4' are the first DRAMs to receive the CA signal. The group of DRAMs is divided into two parts (part A' and part B') by the through hole 1. Part A' includes DRAM1, DRAM2, DRAM3, DRAM4, and DRAM5, and part B' includes DRAM1', DRAM2', DRAM3', and DRAM4'. The CA signal is transmitted in the A' part and the B' part in a FLY-BY topology. For example, for the A' part, it can transmit the received CA signal between DRAM5 and DRAM1 according to the FLY-BY topology of DRAM5->DRAM4->DRAM3->DRAM2->DRAM1. For the B' part, it can transmit the received CA signal between DRAM4' and DRAM1' according to the FLY-BY topology of DRAM4'->DRAM3'->DRAM2'->DRAM1'.

[0095] For example, the connection length between through hole 1 and DRAM5 and DRAM 4' is within the set range; accordingly, the total length of the T+FLY-BY topology structure routing corresponding to through hole 1 to DRAM1 (the total length of the routing corresponding to through hole 1->DRAM5->DRAM4->DRAM3->DRAM2->DRAM1) and the total length of the T+FLY-BY topology structure routing corresponding to through hole 1 to DRAM 1' (the total length of the routing corresponding to through hole 1->DRAM4'->DRAM3'->DRAM2'->DRAM1') are close.

[0096] Each pin of the DRAM has a corresponding through hole. For example, the CA pin in DRAM5 corresponds to the through hole Via_5. DRAM5 and DRAM5' are relatively arranged on the front and back of the PCB board. DRAM5 and DRAM5' can transmit CA signals through the through hole Via_5. Although DRAM5 and DRAM5' correspond to different groups, since DRAMs in different groups share the CA signal, DRAM5' can receive the signal transmitted by DRAM5.

[0097] For another group of DRAMs, the through hole 1 is connected to the CA ports of DRAM 6 on the front of the PCB board and DRAM 5' on the back of the PCB board through a signal line. Based on the connection with the CA ports of DRAM 6 and DRAM 5', the CA signal is transmitted to DRAM6 and DRAM 5' in a T-type topology. DRAM6 and DRAM 5' are both the first DRAMs to receive the CA signal. The group of DRAMs is divided into two parts (C' part and D' part) by the through hole 1. The C' part includes DRAM 6, DRAM 7, DRAM 8, and DRAM 9, and the D' part includes DRAM 5', DRAM 6', DRAM 7', DRAM 8', and DRAM 9'. In the C' part and the D' part, the CA signal is transmitted in a FLY-BY topology. Among them, for the C' part, it can transmit the received CA signal between the corresponding DRAMs (DRAM6 to DRAM9) according to the FLY-BY topology of DRAM6->DRAM7->DRAM8->DRAM9. As for the D' part, it can transmit the received CA signal between DRAM5' to DRAM9' according to the FLY-BY topology structure of DRAM5'->DRAM6'->DRAM7'->DRAM8'->DRAM9'.

[0098] The following is an introduction to the CK signal.

[0099] As an example, the CK signal can also be transmitted using the T+FLY-BY topology. In order to use the T+FLY-BY topology to transmit the CK signal, a through hole dedicated to a branch point can also be set on the PCB board, and the T-type topology corresponding to the CK signal is realized based on the set through hole. Optionally, the CA signal and the CK signal can use different through holes to respectively realize the T+FLY-BY topology.

[0100] As another example, when multiple DRAMs arranged on the front and back of the PCB are divided into multiple groups, the CK signals corresponding to different groups of DRAMs are different. For example, when multiple DRAMs arranged on the front and back of the PCB are divided into two groups, the DRAM controller includes two CK ports, namely, a CK0 port and a CK1 port. The CK0 port provides a CK signal for one group of DRAMs, and the CK1 port provides a CK signal for another group of DRAMs. The CK signal provided by the CK0 port is CK0, and the CK signal provided by the CK1 port is CK1. For example, see Fig. 8A As shown, the DRAM controller is arranged on the front side of the PCB board, and a group of DRAMs located on the front side of the PCB board provide a CK0 signal through the CK0 port of the DRAM controller, see Figure 8B As shown in the figure, a group of DRAMs located on the back of the PCB board provides the CK1 signal through the CK1 port of the DRAM controller. Fig. 8A As shown, in order to enable the CK0 signal to be transmitted in a group of DRAMs on the front side of the PCB board according to the T+FLY-BY topology, a through hole (through hole 2) dedicated to serving as a branch point can be set on the PCB board.

[0101] exist Fig. 8A In the case shown, the CK0 signal provided by the CK0 port of the DRAM controller is divided into two paths through the through hole 2 to form a T-type topology structure, and the CK0 signal is transmitted to DRAM5 and DRAM6 in the T-type topology structure, and DRAM5 and DRAM6 are the first DRAMs to receive the CK0 signal. The 9 DRAMs (DRAM1 to DRAM9) on the front are divided into two parts (Part A and Part B) through the through hole 2; Part A includes DRAM5, DRAM4, DRAM3, DRAM2, and DRAM1; Part B includes DRAM6, DRAM7, DRAM8, and DRAM9. For example, for Part A, DRAM5 is used as the first DRAM, and the CK0 signal is transmitted between DRAM5 and DRAM1 according to the FLY-BY topology structure of DRAM5->DRAM4->DRAM3->DRAM2->DRAM1. For Part B, DRAM6 is used as the first DRAM, and the CK0 signal is transmitted between DRAM6 and DRAM9 according to the FLY-BY topology structure of DRAM6->DRAM7->DRAM8->DRAM9. Furthermore, the CK0 signal between the 9 DRAMs in the group can be transmitted according to the T+FLY-BY topology.

[0102] like Figure 8BAs shown, in order to enable the CK1 signal to be transmitted in a group of DRAMs on the back of the PCB board according to the T+FLY-BY topology, a through hole (through hole 3) dedicated to serving as a branch point can be set on the PCB board. For example, through hole 3 and through hole 2 are different through holes. Through hole 3 set on the PCB board divides a group of DRAMs on the back of the PCB board into two parts, and a T-type topology corresponding to the CK1 signal is realized based on the through hole. Since the DRAM controller is set on the front of the PCB board, the CK1 port on the DRAM controller is connected to the through hole 3 through a signal line. Since the through hole 3 runs through the PCB board, the through hole 3 connects the corresponding two DRAMs in a group of DRAMs on the back of the PCB board through a signal line, and transmits the CK1 signal to the back of the PCB board. A group of DRAMs located on the back of the PCB board is divided into two parts (part C and part D) based on the T-type topology; part C includes DRAM5', DRAM4', DRAM3', DRAM2', DRAM1'; part D includes DRAM6', DRAM7', DRAM8', DRAM9'. ​​The CK1 signal is transmitted in part C and part D respectively in the FLY-BY topology.

[0103] exist Figure 8B In the situation shown, the CK1 signal provided by the CK1 port of the DRAM controller is transmitted to DRAM5' and DRAM6' through the through hole 3. DRAM5', as the first DRAM of part C, implements the transmission of the CK1 signal along the direction of DRAM 5', DRAM 4', DRAM 3', DRAM 2', and DRAM 1' according to the FLY-BY topology structure of DRAM5'->DRAM4'->DRAM3'->DRAM2'->DRAM1'. As for DRAM6', as the first DRAM of part D, implements the transmission of the CK1 signal along the direction of DRAM 6', DRAM 7', DRAM 8', and DRAM 9' according to the FLY-BY topology structure of DRAM6'->DRAM7'->DRAM8'->DRAM9'.

[0104] As an example, for the case where two parts corresponding to a group of DRAMs are located on different end surfaces of the PCB board. For any group of DRAMs, since the corresponding DRAMs are distributed on the two end surfaces of the PCB board, when the group of DRAMs corresponds to the CK1 signal, the CK1 signal provided by the CK1 port of the DRAM controller is transmitted to the DRAMs distributed on the two end surfaces of the PCB board through the through hole. For example, the 9 DRAMs corresponding to the group of DRAMs include: DRAM5, DRAM4, DRAM3, DRAM2, DRAM1 distributed on one end surface of the PCB board, and DRAM4', DRAM3', DRAM2', DRAM1' distributed on the other end surface of the PCB board; the CK1 signal provided by the DRAM controller distributed on one end surface of the PCB board is transmitted to DRAM5, DRAM4, DRAM3, DRAM2, DRAM1, and the CK1 signal is transmitted to DRAM4', DRAM3', DRAM2', DRAM1' through the through hole. The CK0 port provides the CK0 signal to another group of DRAMs, which is similar to the CK1 port providing the CK1 signal to a group of DRAMs, and will not be repeated here. In addition, the specific transmission of the CK0 signal or the CK1 signal in each group of DRAMs with the T+FLY-BY topology structure is similar to the transmission of the aforementioned CA signal in each group of DRAMs with the T+FLY-BY topology structure, which will not be repeated here.

[0105] In addition to providing CA and CK signals to the DRAM, the DRAM controller also provides DQ and DQS signals to the DRAM. As another example, the DRAM controller provides the DQ or DQS signals to the DRAM using a point-to-point topology. For example, see Fig.9A and Fig. 9B As shown, the number of DQ ports is the same as the number of DRAMs supported by one set of DRAMs, and the two sets of DRAMs share the same set of DQ signals. For example, each DRAM on the front side is connected to the DQ pin of the corresponding DRAM on the back side through a through hole, and the two DRAMs arranged opposite to each other share the same DQ signal. For example, the DQ pin in the front DRAM1 is connected to the through hole corresponding to the DQ pin in the back DRAM1', so that the two DRAMs share the same DQ signal.

[0106] The following is an introduction to a solution for forming a T+FLY-BY topology structure using the through holes corresponding to the DRAM pins themselves.

[0107] For a PCB board with double-sided DRAM, CA signals, DQ signals, DQS signals, etc. are shared between the double-sided DRAMs. In order to share signals between the DRAM on the front side of the PCB board and the DRAM on the back side of the PCB board, corresponding through holes are set for the pins of the DRAM on the front side of the PCB board and the DRAM on the back side of the PCB board, and signals (such as CA signals, DQ signals, DQS signals, etc.) are transmitted between the pins of the two DRAMs on the front side and the back side of the PCB board through the through holes. For example, the DQS pin in the DRAM1 on the front side of the PCB board is connected to the through hole corresponding to the DQS pin in the DRAM1' on the back side. When the DRAM controller is set on the front side of the PCB board, the DQS port of the DRAM controller is connected to the DQS pin in DRAM1 on the front side of the PCB board through a signal line to send a DQS signal to DRAM1 on the front side of the PCB board; when the DQS pin of DRAM1 on the front side of the PCB board receives the DQS signal sent by the DRAM controller, the DQS signal is transmitted to the DQS pin in DRAM1' through the through hole corresponding to the DQS pin in DRAM1 and the DQS pin in DRAM1' on the back side, thereby allowing the two DRAMs to share the same DQS signal.

[0108] As an example, the through holes corresponding to the CA pins in a DRAM can be used as branch points to realize the division of a group of DRAMs, so that the CA signals can be transmitted in a group of DRAMs according to the T+FLY-BY topology structure through the division. As another example, the through holes corresponding to the CK pins in a DRAM can be used as branch points to realize the division of a group of DRAMs, so that the CK signals can be transmitted in a T+FLY-BY topology structure through the division.

[0109] As another example, for the CA signal, since different groups of DRAMs can share the CA signal, only one DRAM can be selected, and the through hole corresponding to the CA pin of the selected DRAM is used as a branch point. The CA port on the DRAM controller is connected to the corresponding through hole (the through hole corresponding to the CA pin of the selected DRAM) through a signal line, and the through hole connects the two groups of DRAMs through the signal line.

[0110] For example, two groups of DRAM are distributed on two end surfaces of the PCB board, each end surface corresponds to a group of DRAM, and each group of DRAM includes 9 DRAMs. Fig. 10A as well as Fig. 10BAs shown, the through hole corresponding to the CA pin of DRAM5 among the 9 DRAMs on the front is used as the branch point (point T). For a group of DRAMs on the front of the PCB board, the CA signal is transmitted between the above DRAMs according to the FLY-BY topology of DRAM5->DRAM6->DRAM7->DRAM8->DRAM9, and the CA signal is transmitted according to the FLY-BY topology of DRAM5->DRAM4->DRAM3->DRAM2->DRAM1, thereby realizing the transmission of CA signals among the 9 DRAMs according to the T+FLY-BY topology. Fig. 10A as well as Fig. 10C As shown, for a group of DRAMs on the back of the PCB board, since DRAM5 and DRAM5' are two DRAMs arranged opposite to each other on the front and back of the PCB board, CA signal transmission can be achieved between them based on the through holes corresponding to the CA pins themselves. When the CA pin of DRAM5 receives the CA signal provided by the CA port of the DRAM controller, the CA signal can be transmitted to DRAM5' through the through holes corresponding to the CA pin of DRAM5, and DRAM5' can transmit the CA signal to DRAM6' and DRAM4' through the CA pin, thereby enabling another group of DRAMs on the PCB board to transmit CA signals between DRAM5' and DRAM9' according to a FLY-BY topology structure of, for example, DRAM5'->DRAM6'->DRAM7'->DRAM8'->DRAM9', and to transmit CA signals between DRAM5' and DRAM1' according to a FLY-BY topology structure of DRAM5'->DRAM4'->DRAM3'->DRAM2'->DRAM1', thereby achieving transmission of CA signals between the group of DRAMs according to a T+FLY-BY topology structure.

[0111] Fig. 10D This is an example of CA signal transmission between the DRAM on the front and the DRAM on the back of the PCB board based on the through hole corresponding to the CA pin. The CA signal provided by the CA port of the DRAM controller set on the front of the PCB board is transmitted to the CA pin of DRAM5, and the CA signal is transmitted to DRAM5' through the through hole corresponding to the CA pin of DRAM5, so as to realize the transmission of CA signal on the back of the PCB board; and a T+FLY-BY topology structure is formed on both the front and back of the PCB board to transmit the CA signal based on the T+FLY-BY topology structure.

[0112] As an example, a case where a group of DRAMs includes DRAMs located at two end surfaces of a PCB board is introduced. For example, DRAM 1, DRAM 2, DRAM 3, DRAM 4, DRAM 5 corresponding to the front side of the PCB board and DRAM 1', DRAM2', DRAM 3', DRAM 4', DRAM 5' corresponding to the back side of the PCB board constitute a group of DRAMs, and DRAM 6, DRAM 7, DRAM 8, DRAM9 corresponding to the front side of the PCB board and DRAM 6', DRAM 7', DRAM 8', DRAM 9' corresponding to the back side of the PCB board constitute another group of DRAMs. With the through hole corresponding to the CA pin of DRAM5 itself as a branch point, one of the group of DRAMs transmits CA signals according to the FLY-BY topology structure of DRAM5'->DRAM4'->DRAM3'->DRAM2'->DRAM1', and transmits CA signals according to the FLY-BY topology structure of DRAM5->DRAM4->DRAM3->DRAM2->DRAM1. Since the CA signal can be shared by different DRAM groups, the CA signal can be transmitted from DRAM5' to DRAM 6' according to the FLY-BY topology structure of DRAM6'->DRAM7'->DRAM8'->DRAM9'. ​​DRAM 6' can transmit the CA signal to DRAM 6 through the through hole corresponding to the CA pin, according to the FLY-BY topology structure of DRAM6->DRAM7->DRAM8->DRAM9.

[0113] As another example, the DRAM controller includes a CK0 port and a CK1 port, the CK0 port corresponds to one group of DRAMs, and the CK1 port corresponds to another group of DRAMs. Since each group of DRAMs corresponds to a CK signal, one DRAM can be selected from each group of DRAMs. For example, for one group of DRAMs (group 1), the group of DRAMs is divided into two parts through a through hole (a through hole corresponding to the CK pin of the DRAM selected in group 1) to realize a T-type topology structure corresponding to the CK0 signal; for another group of DRAMs (group 2), the group of DRAMs is divided into two parts through another through hole (a through hole corresponding to the CK pin of the DRAM selected in group 2) to realize a T-type topology structure corresponding to the CK1 signal.

[0114] The DRAM corresponding to the CK0 signal and the DRAM corresponding to the CK1 signal are different DRAMs, and the selected DRAM corresponding to the CK signal (CK1 signal or CK0 signal) and the DRAM corresponding to the CA signal may be the same DRAM.

[0115] As an example, two groups of DRAM are distributed on the two end surfaces of the PCB board, each end surface corresponds to a group of DRAM, each group of DRAM includes 9 DRAMs, the front group of DRAM corresponds to the CK0 signal, and the back group of DRAM corresponds to the CK1 signal. The through hole corresponding to the CK pin of the DRAM5 particle in the 9 front DRAMs is used as the branch point of the group of DRAMs on the front of the PCB board. For the front group of DRAMs, the CK0 signal is transmitted between the above-mentioned DRAMs according to the FLY-BY topology of DRAM5->DRAM6->DRAM7->DRAM8->DRAM9, and the CK0 signal is transmitted according to the FLY-BY topology of DRAM5->DRAM4->DRAM3->DRAM2->DRAM1, thereby realizing the transmission of the CK0 signal between the 9 DRAMs according to the T+FLY-BY topology. For a group of DRAMs on the back of the PCB board, since DRAM6 and DRAM6' are two DRAMs arranged opposite to each other on the front and back of the PCB board, the transmission of CK signals between them can be realized based on the through holes corresponding to the CK pins themselves. The CK1 port of the DRAM controller located on the front of the PCB board is connected to the CK pin through hole corresponding to DRAM6 (located on the front of the PCB board) through a signal line. Since the CK pin through hole runs through the PCB board, the CK1 signal can be transmitted to DRAM6' on the back of the PCB board. The CK pin through hole of DRAM6' serves as a branch point for a group of DRAMs on the back of the PCB board. For the DRAMs on the back, the CK1 signal is transmitted between the above-mentioned DRAMs according to the FLY-BY topology structure of DRAM6'->DRAM5'->DRAM4'->DRAM3'->DRAM2'->DRAM1', and the CK1 signal is transmitted according to the FLY-BY topology structure of DRAM6'->DRAM7'->DRAM8'->DRAM9', thereby realizing the transmission of CK1 signals between the 9 DRAMs according to the T+FLY-BY topology structure.

[0116] It should be noted that in addition to DRAM, other chips, such as NVM chips, are also placed on the PCB. Fig.10E As described above, a plurality of DRAMs and a plurality of NVM chips are arranged around the DRAM controller, and the DRAMs are arranged closer to the DRAM controller than the NVM chips. Fig.10EThe PCB board structure layout shown is an example of laying out the DRAM controller, DRAM and NVM chips on the front of the PCB board. The DRAM controller is in the middle of the left side of the PCB board, DRAM1-DRAM 4 are above the DRAM controller in a layout of 2 rows and 2 columns, DRAM5-DRAM 7 are on the right side of the DRAM controller, arranged vertically in a column layout, and DRAM8-DRAM 9 are below the DRAM controller in a row; the above layout of DRAM is to ensure that the connection length of the CK0 signal to each DRAM is not too long. The branch point is set between DRAM5 and DRAM4, and the routing form of the FLY-BY topology structure formed by DRAM4 to DRAM1 is: go around upward to VTT, and the routing form of the FLY-BY topology structure formed by DRAM5 to DRAM9 is: go down and turn left to VTT. For the FLY-BY topology structure, it includes a main line and a branch, Fig.10E The main line in the FPGA is a single line, and the branches are the lines connecting the main line and the DRAM.

[0117] In another implementation, for the case where two parts corresponding to a group of DRAMs are located on different end surfaces of a PCB board. For any group of DRAMs, since the corresponding DRAMs are distributed on the two end surfaces of the PCB board, the CK signal provided by the CK port of the DRAM controller needs to be transmitted to the DRAMs distributed on the two end surfaces of the PCB board through a through hole. For example, the 9 DRAMs corresponding to a group of DRAMs include: DRAM4, DRAM3, DRAM2, DRAM1 distributed on the front of the PCB board, and DRAM5', DRAM4', DRAM3', DRAM2', DRAM1' distributed on the back of the PCB board; the 9 DRAMs corresponding to another group of DRAMs include: DRAM5, DRAM6, DRAM7, DRAM8, DRAM9 distributed on the front of the PCB board, and DRAM6', DRAM7', DRAM8', DRAM9' distributed on the back of the PCB board. The through hole corresponding to the CK pin of DRAM4 on the front of the PCB board is used as the T point (e.g., the second branch point). The CK0 port of the DRAM controller located on the front of the PCB board is connected to the CK pin through hole corresponding to DRAM4 through a signal line. The CK pin through hole is connected to the DRAM on the front of the PCB board through the signal line. Since the CK pin through hole runs through the PCB board, the CK0 signal can be transmitted to the back of the PCB board. Based on the second branch point, a group of DRAMs is divided into two parts, one part includes DRAM 4, DRAM 3, DRAM 2, and DRAM1, and the other part includes DRAM5', DRAM4', DRAM3', DRAM2', and DRAM1'. Both parts transmit the CK0 signal, so that the CK0 signal provided by the DRAM controller is transmitted on the front and back of the PCB board.

[0118] The through hole corresponding to the CK pin of DRAM6 on the front of the PCB board is used as the T point (e.g., the third branch point). The CK1 port of the DRAM controller located on the front of the PCB board is connected to the CK pin through hole corresponding to DRAM6 through a signal line. The CK pin through hole is connected to the DRAM on the front of the PCB board through the signal line. Since the CK pin through hole runs through the PCB board, the CK1 signal can be transmitted to the back of the PCB board. Based on the third branch point, a group of DRAMs is divided into two parts, one part includes DRAM6', DRAM 7', DRAM 8', DRAM9', and the other part includes DRAM5, DRAM6, DRAM7, DRAM8, and DRAM9. Both parts transmit the CK1 signal, so that the CK1 signal provided by the DRAM controller is transmitted on the front and back of the PCB board.

[0119] It should be noted that the CA pin and CK pin determined as branch points, and their corresponding DRAM positions in the entire DRAM layout need to meet restriction conditions. For example, the routing lengths corresponding to the two parts of the FLY-BY topology structures determined based on the branch point are as close as possible; and the routing length between the branch point and the first DRAM in the two parts is within a set range.

[0120] In the embodiment of the present application, by setting or selecting through holes on the PCB board and using the through holes as branch points of the T-type topology structure, the CA signal and / or CK signal are transmitted using the T+FLY-BY topology structure, thereby reducing the time required for transmitting the CA and / or CK signals between multiple DRAMs and ensuring that the transmission of the CA and / or CK signals meets the timing requirements.

[0121] The effects of the embodiments of the present application are explained below through simulation results.

[0122] Fig.11A It means that the T+FLY-BY topology is realized by setting a through hole dedicated to the branch point on the PCB board; Fig.11A In the figure, FLY-BY structure one includes DRAM5' and DRAM5 (the first pair of DRAMs), DRAM4' and DRAM4 (the second pair of DRAMs), DRAM3' and DRAM3 (the third pair of DRAMs), DRAM2' and DRAM2 (the fourth pair of DRAMs), DRAM1' and DRAM1 (the fifth pair of DRAMs), and FLY-BY structure two includes DRAM6' and DRAM6 (the first pair of DRAMs), DRAM7' and DRAM7 (the second pair of DRAMs), DRAM8' and DRAM8 (the third pair of DRAMs), DRAM9' and DRAM9 (the fourth pair of DRAMs). Fig. 11BIndicates that the through holes corresponding to the DRAM pins are used as branch points to implement the T+FLY-BY topology; Fig. 11B In the figure, FLY-BY structure one includes DRAM5' and DRAM5 (the first pair of DRAMs), DRAM4' and DRAM4 (the second pair of DRAMs), DRAM3' and DRAM3 (the third pair of DRAMs), DRAM2' and DRAM2 (the fourth pair of DRAMs), DRAM1' and DRAM1 (the fifth pair of DRAMs), and FLY-BY structure two includes DRAM6' and DRAM6 (the first pair of DRAMs), DRAM7' and DRAM7 (the second pair of DRAMs), DRAM8' and DRAM8 (the third pair of DRAMs), DRAM9' and DRAM9 (the fourth pair of DRAMs).

[0123] The pre-integration simulation and post-integration simulation were performed for the DRAM topology structure provided in the embodiment of the present application, and the specific simulation results are as follows:

[0124] 1. Pre-Synthesis Simulation

[0125] In the early stage of design, it is not known which method to use to realize the T+FLY-BY topology, where the through-holes are located as branch points, and what length of the connection line between DRAM and the routing (CA or CK signal line) will make the DRAM performance better. Therefore, a lossy transmission line and through-hole model is established based on the DRAM stacking structure, medium parameters, and path layer switching information, and pre-synthesis simulation is performed based on the model. Fig. 12A , Fig. 12C Comprehensive pre-simulation results for implementing T+FLY-BY topology by setting up dedicated through holes as branch points on the PCB board; Fig. 12B and Fig.12D Pre-synthesis simulation results for implementing the T+FLY-BY topology using the vias corresponding to the DRAM pins as branch points.

[0126] Figures 12A to 12D It indicates the eye diagram obtained by pre-synthesis simulation of part of the DRAM laid out on the PCB board before the PCB board design is completed. The eye diagram is a graph displayed by accumulating a series of signals on an oscilloscope. How to judge the quality of the simulation results needs to be determined based on the "eye" of the eye diagram. For example, the performance of the corresponding circuit can be evaluated based on indicators such as the width, height, and opening of the "eye". Fig. 12A For Fig.11A Pre-synthesis simulation results of the first pair of DRAMs in FLY-BY structure 1; Fig. 12B For Fig. 11B Pre-synthesis simulation results of the first pair of DRAMs in FLY-BY structure 1; Fig. 12CFor Fig.11A Pre-synthesis simulation results of the first pair of DRAMs in FLY-BY structure II; Fig.12D For Fig. 11B Pre-synthesis simulation results of the first pair of DRAMs in FLY-BY structure 2.

[0127] In the case of using the through holes corresponding to the DRAM pins to implement the T+FLY-BY topology, the reflection of the link is more complicated because it first reaches the first pair of DRAM pins in FLY-BY structure one and then reaches FLY-BY structure two through the common through hole. Fig. 12B There is an overshoot phenomenon in the first pair of DRAM simulation results of FLY-BY structure 1. The overshoot phenomenon is reflected in the reflection occurring before the saturation of the rising edge of the signal, causing the "eye" in the eye diagram to press the eye diagram template (such as Fig. 12B (marked by the oval in the middle). Fig.12D ,The overshoot phenomenon is manifested at the first pair of DRAMs in FLY-BY structure 2, resulting in the eye diagram pressing the eye diagram template.

[0128] Since the T+FLY-BY topology is realized by specially set through holes, the T routing is relatively symmetrical. Fig. 12A and Fig. 12C The reflection phenomenon is not obvious, and the phenomenon of the "eye" in the eye diagram pressing the eye diagram template is relatively weak.

[0129] In summary, the eye diagram results of the pre-synthesis simulation using specially set through-holes to implement the T+FLY-BY topology structure are better than using through-holes corresponding to DRAM pins to implement the T+FLY-BY topology structure.

[0130] Through similar experiments, simulation results show Fig.11A In the corresponding T+FLY-BY topological structure, it is preferred that the distance between the through hole serving as the branch point and the first pair of DRAMs in FLY-BY structure one and FLY-BY2 structure two is selected to be 100 to 200 mils, and the branch length between the first pair of DRAMs and the second pair of DRAMs, the branch length between the second pair of DRAMs and the third pair of DRAMs, the branch length between the third pair of DRAMs and the fourth pair of DRAMs, and the branch length between the fourth pair of DRAMs and the fifth pair of DRAMs are 800 to 850 mils.

[0131] 2. Post-Synthesis Simulation

[0132] Figures 13A to 13D It represents the eye diagram obtained by simulating and synthesizing some DRAMs laid out on the PCB board after the PCB board design is completed. Fig.13A For Fig.11APost-synthesis simulation results of the first pair of DRAMs in FLY-BY structure 1; Fig. 13B For Fig. 11B Post-synthesis simulation results of the first pair of DRAMs in FLY-BY structure 1; Fig. 13C For Fig.11A Post-synthesis simulation results of the first pair of DRAMs in FLY-BY structure 2; Fig.13D For Fig. 11B Post-synthesis simulation results of the first pair of DRAMs in FLY-BY structure 2.

[0133] Fig. 13B and Fig.13A compared to, Fig. 13B The part of the waveform in the middle frame has touched the eye diagram mask area. Fig. 13B The corresponding eye diagram does not have Fig.13A The simulation results of the corresponding eye diagram are good. Fig.13D and Fig. 13C compared to, Fig.13D The part of the waveform in the middle frame has touched the eye diagram mask area. Fig.13D The corresponding eye diagram does not have Fig. 13C The simulation results of the corresponding eye diagram are good.

[0134] Fig.13A and Fig. 13C Corresponding Fig.11A The topology scheme uses a dedicated through hole as a branch point to realize the T+FLY-BY topology structure. Fig. 13B and Fig.13D Corresponding Fig. 11B The topology scheme uses DRAM pin through holes as branch points to implement the T+FLY-BY topology of DRAM. Fig. 13B No effect Fig.13A Good, Fig.13D There is no effect Fig. 13C This means that the effect of using DRAM pin through-holes as branch points to implement the T+FLY-BY topology of DRAM is not as good as that of using dedicated through-holes as branch points to implement the T+FLY-BY topology. In addition to DRAM, other devices (such as NVM chips) can also be laid out on the PCB. Therefore, the actual situation needs to be considered when laying out DRAM and routing on the PCB. Based on this, the routing length between the branch point and each DRAM in the actual PCB layout is slightly different from the simulation result. As an example, in Fig.11AIn the example shown, the length of the main line from the DRAM controller to point T is 812.4 mil; in FLY-BY structure one, the length between point T and the first pair of DRAMs is 250 mil, and the branch lengths from the first pair of DRAMs to the second pair of DRAMs, the branch lengths from the second pair of DRAMs to the third pair of DRAMs, the branch lengths from the third pair of DRAMs to the fourth pair of DRAMs, and the branch lengths from the fourth pair of DRAMs to the fifth pair of DRAMs are 774 mil; in FLY-BY structure two, the length from point T to the first pair of DRAMs is 240 mil, and the branch lengths from the first pair of DRAMs to the second pair of DRAMs, the branch lengths from the second pair of DRAMs to the third pair of DRAMs, and the branch lengths from the third pair of DRAMs to the fourth pair of DRAMs are 771 mil.

[0135] exist Fig. 11B In the example shown, the main line length from the DRAM controller to point T is 1059 mil; for FLY-BY structure two, the length between point T and the first pair of DRAMs is 766 mil, and the branch lengths from the first pair of DRAMs to the second pair of DRAMs, the branch lengths from the second pair of DRAMs to the third pair of DRAMs, the branch lengths from the third pair of DRAMs to the fourth pair of DRAMs, and the branch lengths from the fourth pair of DRAMs to the fourth pair of DRAMs are 771 mil; for FLY-BY structure one, the branch lengths from the first pair of DRAMs to the second pair of DRAMs, the branch lengths from the second pair of DRAMs to the third pair of DRAMs, and the branch lengths from the third pair of DRAMs to the fourth pair of DRAMs are 774 mil.

[0136] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they are aware of the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present application. Obviously, those skilled in the art may make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A circuit, characterized in that: include: A DRAM controller, a first group of DRAMs, and a first branch point are arranged on the PCB board; The first group of DRAMs includes a plurality of DRAM chips; The CA port of the DRAM controller is connected to the first branch point through a signal line, and the first branch point is connected to the first DRAM particle and / or the second DRAM particle in the first group of DRAMs through a signal line; The signal line for transmitting CA signals arranged between the first DRAM particle and at least one third DRAM particle adopts a FLY-BY topology structure, and the signal line for transmitting CA signals arranged between the second DRAM particle and at least one fourth DRAM particle adopts a FLY-BY topology structure; The first DRAM particle, the second DRAM particle, the at least one third DRAM particle and the at least one fourth DRAM particle are different DRAM particles in the first group of DRAMs, and together constitute the first group of DRAMs.

2. The circuit according to claim 1, characterized in that Also includes: Second branch point; The first CK port of the DRAM controller is connected to the second branch point through a signal line, and the second branch point is connected to the first DRAM particle and / or the second DRAM particle in the first group of DRAM through a signal line; The signal line for transmitting the CK signal arranged between the first DRAM particle and the at least one third DRAM particle adopts a FLY-BY topology structure, and the signal line for transmitting the CK signal arranged between the second DRAM particle and the at least one fourth DRAM particle adopts a FLY-BY topology structure.

3. The circuit according to claim 1 or 2, characterized in that: A difference between a length of a signal line arranged between the first DRAM chip and the at least one third DRAM chip and a length of a signal line arranged between the second DRAM chip and the at least one fourth DRAM chip is within a first preset range.

4. The circuit according to claim 2, characterized in that The length of the signal line connecting the first branch point or the second branch point and the corresponding pins on the first DRAM chip and the second DRAM chip is within a second preset range.

5. The circuit according to claim 2 or 4, characterized in that: The first branch point and / or the second branch point are both dedicated through holes set on the PCB board for realizing the branch point function; or, the first branch point is a through hole corresponding to the CA pin of the DRAM particle on the PCB board, and the second branch point is a through hole corresponding to the CK pin of the DRAM particle in the first group of DRAMs.

6. The circuit according to any one of claims 1 to 5, characterized in that: Also includes: The second set of DRAM; The CA port of the DRAM controller is connected to the first branch point through a signal line, and the first branch point is connected to the fifth DRAM particle and / or the sixth DRAM particle in the second group of DRAM through a signal line; The signal line for transmitting the CA signal arranged between the fifth DRAM chip and at least one seventh DRAM chip adopts a FLY-BY topology structure, and the signal line for transmitting the CA signal arranged between the sixth DRAM chip and at least one eighth DRAM chip adopts a FLY-BY topology structure; Among them, the fifth DRAM particle, the sixth DRAM particle, the at least one seventh DRAM particle and the at least one eighth DRAM particle are different DRAM particles in the second group of DRAMs, and together constitute the second group of DRAMs.

7. The circuit according to claim 6, characterized in that Also includes a third branch point and the DRAM controller also includes a second CK port; The second CK port of the DRAM controller is connected to the third branch point through a signal line, and the third branch point is connected to the fifth DRAM particle and / or the sixth DRAM particle in the second group of DRAM through a signal line; The signal line for transmitting the CK signal arranged between the fifth DRAM particle and at least one seventh DRAM particle adopts a FLY-BY topology structure, and the signal line for transmitting the CK signal arranged between the sixth DRAM particle and at least one eighth DRAM particle adopts a FLY-BY topology structure.

8. The circuit according to claim 7, characterized in that The second CK port and the first CK port are different CK ports on the DRAM controller; The first branch point, the second branch point and the third branch point are different branch points.

9. The circuit according to claim 7 or 8, characterized in that In the case where the through hole corresponding to the CK pin of the fifth DRAM particle is used as the third branch point, the second CK port of the DRAM controller is connected to the CK pin of the fifth DRAM particle through a signal line; The CK pins of the sixth DRAM particle are connected to the through holes corresponding to the CK pins of the fifth DRAM particle through signal lines, and the CK signal is transmitted to the CK pins of the sixth DRAM particle through the through holes of the CK pins of the fifth DRAM particle.

10. The circuit according to any one of claims 6 to 9, characterized in that The first group of DRAMs and the second group of DRAMs are located on different end surfaces of the PCB board, or the first group of DRAMs and the second group of DRAMs both include DRAM particles from two end surfaces arranged on the PCB board.

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